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authorVinod Koul <vinod.koul@linux.intel.com>2011-11-17 04:24:38 -0500
committerVinod Koul <vinod.koul@linux.intel.com>2011-11-17 04:24:57 -0500
commite0d23ef29ed637dc6bd739f590985746d9ad9caa (patch)
treec5b5856dc88582697997bb10ccacad6fc2535465 /drivers/dma
parentca7fe2db892dcf91b2c72ee352eda4ff867903a7 (diff)
parent55ba4e5ed4ac57b60fe56acfd324f6a87123cc34 (diff)
Merge branch 'dma_slave_direction' into next_test_dirn
resolved conflicts: drivers/media/video/mx3_camera.c
Diffstat (limited to 'drivers/dma')
-rw-r--r--drivers/dma/amba-pl08x.c24
-rw-r--r--drivers/dma/at_hdmac.c22
-rw-r--r--drivers/dma/coh901318.c12
-rw-r--r--drivers/dma/coh901318_lli.c23
-rw-r--r--drivers/dma/coh901318_lli.h4
-rw-r--r--drivers/dma/dw_dmac.c14
-rw-r--r--drivers/dma/ep93xx_dma.c22
-rw-r--r--drivers/dma/fsldma.c4
-rw-r--r--drivers/dma/imx-dma.c10
-rw-r--r--drivers/dma/imx-sdma.c10
-rw-r--r--drivers/dma/intel_mid_dma.c14
-rw-r--r--drivers/dma/intel_mid_dma_regs.h2
-rw-r--r--drivers/dma/ipu/ipu_idmac.c4
-rw-r--r--drivers/dma/mxs-dma.c8
-rw-r--r--drivers/dma/pch_dma.c12
-rw-r--r--drivers/dma/pl330.c18
-rw-r--r--drivers/dma/shdma.c25
-rw-r--r--drivers/dma/ste_dma40.c26
-rw-r--r--drivers/dma/timb_dma.c18
-rw-r--r--drivers/dma/txx9dmac.c12
20 files changed, 141 insertions, 143 deletions
diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index b7cbd1ab1db1..41c62fd0680d 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -882,9 +882,9 @@ static int prep_phy_channel(struct pl08x_dma_chan *plchan,
882 ch->signal = ret; 882 ch->signal = ret;
883 883
884 /* Assign the flow control signal to this channel */ 884 /* Assign the flow control signal to this channel */
885 if (txd->direction == DMA_TO_DEVICE) 885 if (txd->direction == DMA_MEM_TO_DEV)
886 txd->ccfg |= ch->signal << PL080_CONFIG_DST_SEL_SHIFT; 886 txd->ccfg |= ch->signal << PL080_CONFIG_DST_SEL_SHIFT;
887 else if (txd->direction == DMA_FROM_DEVICE) 887 else if (txd->direction == DMA_DEV_TO_MEM)
888 txd->ccfg |= ch->signal << PL080_CONFIG_SRC_SEL_SHIFT; 888 txd->ccfg |= ch->signal << PL080_CONFIG_SRC_SEL_SHIFT;
889 } 889 }
890 890
@@ -1102,10 +1102,10 @@ static int dma_set_runtime_config(struct dma_chan *chan,
1102 1102
1103 /* Transfer direction */ 1103 /* Transfer direction */
1104 plchan->runtime_direction = config->direction; 1104 plchan->runtime_direction = config->direction;
1105 if (config->direction == DMA_TO_DEVICE) { 1105 if (config->direction == DMA_MEM_TO_DEV) {
1106 addr_width = config->dst_addr_width; 1106 addr_width = config->dst_addr_width;
1107 maxburst = config->dst_maxburst; 1107 maxburst = config->dst_maxburst;
1108 } else if (config->direction == DMA_FROM_DEVICE) { 1108 } else if (config->direction == DMA_DEV_TO_MEM) {
1109 addr_width = config->src_addr_width; 1109 addr_width = config->src_addr_width;
1110 maxburst = config->src_maxburst; 1110 maxburst = config->src_maxburst;
1111 } else { 1111 } else {
@@ -1136,7 +1136,7 @@ static int dma_set_runtime_config(struct dma_chan *chan,
1136 cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT; 1136 cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT;
1137 cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT; 1137 cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT;
1138 1138
1139 if (plchan->runtime_direction == DMA_FROM_DEVICE) { 1139 if (plchan->runtime_direction == DMA_DEV_TO_MEM) {
1140 plchan->src_addr = config->src_addr; 1140 plchan->src_addr = config->src_addr;
1141 plchan->src_cctl = pl08x_cctl(cctl) | PL080_CONTROL_DST_INCR | 1141 plchan->src_cctl = pl08x_cctl(cctl) | PL080_CONTROL_DST_INCR |
1142 pl08x_select_bus(plchan->cd->periph_buses, 1142 pl08x_select_bus(plchan->cd->periph_buses,
@@ -1152,7 +1152,7 @@ static int dma_set_runtime_config(struct dma_chan *chan,
1152 "configured channel %s (%s) for %s, data width %d, " 1152 "configured channel %s (%s) for %s, data width %d, "
1153 "maxburst %d words, LE, CCTL=0x%08x\n", 1153 "maxburst %d words, LE, CCTL=0x%08x\n",
1154 dma_chan_name(chan), plchan->name, 1154 dma_chan_name(chan), plchan->name,
1155 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX", 1155 (config->direction == DMA_DEV_TO_MEM) ? "RX" : "TX",
1156 addr_width, 1156 addr_width,
1157 maxburst, 1157 maxburst,
1158 cctl); 1158 cctl);
@@ -1322,7 +1322,7 @@ static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
1322 1322
1323static struct dma_async_tx_descriptor *pl08x_prep_slave_sg( 1323static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1324 struct dma_chan *chan, struct scatterlist *sgl, 1324 struct dma_chan *chan, struct scatterlist *sgl,
1325 unsigned int sg_len, enum dma_data_direction direction, 1325 unsigned int sg_len, enum dma_transfer_direction direction,
1326 unsigned long flags) 1326 unsigned long flags)
1327{ 1327{
1328 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); 1328 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
@@ -1354,10 +1354,10 @@ static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1354 */ 1354 */
1355 txd->direction = direction; 1355 txd->direction = direction;
1356 1356
1357 if (direction == DMA_TO_DEVICE) { 1357 if (direction == DMA_MEM_TO_DEV) {
1358 txd->cctl = plchan->dst_cctl; 1358 txd->cctl = plchan->dst_cctl;
1359 slave_addr = plchan->dst_addr; 1359 slave_addr = plchan->dst_addr;
1360 } else if (direction == DMA_FROM_DEVICE) { 1360 } else if (direction == DMA_DEV_TO_MEM) {
1361 txd->cctl = plchan->src_cctl; 1361 txd->cctl = plchan->src_cctl;
1362 slave_addr = plchan->src_addr; 1362 slave_addr = plchan->src_addr;
1363 } else { 1363 } else {
@@ -1368,10 +1368,10 @@ static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1368 } 1368 }
1369 1369
1370 if (plchan->cd->device_fc) 1370 if (plchan->cd->device_fc)
1371 tmp = (direction == DMA_TO_DEVICE) ? PL080_FLOW_MEM2PER_PER : 1371 tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER_PER :
1372 PL080_FLOW_PER2MEM_PER; 1372 PL080_FLOW_PER2MEM_PER;
1373 else 1373 else
1374 tmp = (direction == DMA_TO_DEVICE) ? PL080_FLOW_MEM2PER : 1374 tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER :
1375 PL080_FLOW_PER2MEM; 1375 PL080_FLOW_PER2MEM;
1376 1376
1377 txd->ccfg |= tmp << PL080_CONFIG_FLOW_CONTROL_SHIFT; 1377 txd->ccfg |= tmp << PL080_CONFIG_FLOW_CONTROL_SHIFT;
@@ -1387,7 +1387,7 @@ static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1387 list_add_tail(&dsg->node, &txd->dsg_list); 1387 list_add_tail(&dsg->node, &txd->dsg_list);
1388 1388
1389 dsg->len = sg_dma_len(sg); 1389 dsg->len = sg_dma_len(sg);
1390 if (direction == DMA_TO_DEVICE) { 1390 if (direction == DMA_MEM_TO_DEV) {
1391 dsg->src_addr = sg_phys(sg); 1391 dsg->src_addr = sg_phys(sg);
1392 dsg->dst_addr = slave_addr; 1392 dsg->dst_addr = slave_addr;
1393 } else { 1393 } else {
diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
index f3cb4a009e7d..3b0c28ff4ad6 100644
--- a/drivers/dma/at_hdmac.c
+++ b/drivers/dma/at_hdmac.c
@@ -662,7 +662,7 @@ err_desc_get:
662 */ 662 */
663static struct dma_async_tx_descriptor * 663static struct dma_async_tx_descriptor *
664atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 664atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
665 unsigned int sg_len, enum dma_data_direction direction, 665 unsigned int sg_len, enum dma_transfer_direction direction,
666 unsigned long flags) 666 unsigned long flags)
667{ 667{
668 struct at_dma_chan *atchan = to_at_dma_chan(chan); 668 struct at_dma_chan *atchan = to_at_dma_chan(chan);
@@ -680,7 +680,7 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
680 680
681 dev_vdbg(chan2dev(chan), "prep_slave_sg (%d): %s f0x%lx\n", 681 dev_vdbg(chan2dev(chan), "prep_slave_sg (%d): %s f0x%lx\n",
682 sg_len, 682 sg_len,
683 direction == DMA_TO_DEVICE ? "TO DEVICE" : "FROM DEVICE", 683 direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE",
684 flags); 684 flags);
685 685
686 if (unlikely(!atslave || !sg_len)) { 686 if (unlikely(!atslave || !sg_len)) {
@@ -694,7 +694,7 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
694 ctrlb = ATC_IEN; 694 ctrlb = ATC_IEN;
695 695
696 switch (direction) { 696 switch (direction) {
697 case DMA_TO_DEVICE: 697 case DMA_MEM_TO_DEV:
698 ctrla |= ATC_DST_WIDTH(reg_width); 698 ctrla |= ATC_DST_WIDTH(reg_width);
699 ctrlb |= ATC_DST_ADDR_MODE_FIXED 699 ctrlb |= ATC_DST_ADDR_MODE_FIXED
700 | ATC_SRC_ADDR_MODE_INCR 700 | ATC_SRC_ADDR_MODE_INCR
@@ -727,7 +727,7 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
727 total_len += len; 727 total_len += len;
728 } 728 }
729 break; 729 break;
730 case DMA_FROM_DEVICE: 730 case DMA_DEV_TO_MEM:
731 ctrla |= ATC_SRC_WIDTH(reg_width); 731 ctrla |= ATC_SRC_WIDTH(reg_width);
732 ctrlb |= ATC_DST_ADDR_MODE_INCR 732 ctrlb |= ATC_DST_ADDR_MODE_INCR
733 | ATC_SRC_ADDR_MODE_FIXED 733 | ATC_SRC_ADDR_MODE_FIXED
@@ -789,7 +789,7 @@ err_desc_get:
789 */ 789 */
790static int 790static int
791atc_dma_cyclic_check_values(unsigned int reg_width, dma_addr_t buf_addr, 791atc_dma_cyclic_check_values(unsigned int reg_width, dma_addr_t buf_addr,
792 size_t period_len, enum dma_data_direction direction) 792 size_t period_len, enum dma_transfer_direction direction)
793{ 793{
794 if (period_len > (ATC_BTSIZE_MAX << reg_width)) 794 if (period_len > (ATC_BTSIZE_MAX << reg_width))
795 goto err_out; 795 goto err_out;
@@ -797,7 +797,7 @@ atc_dma_cyclic_check_values(unsigned int reg_width, dma_addr_t buf_addr,
797 goto err_out; 797 goto err_out;
798 if (unlikely(buf_addr & ((1 << reg_width) - 1))) 798 if (unlikely(buf_addr & ((1 << reg_width) - 1)))
799 goto err_out; 799 goto err_out;
800 if (unlikely(!(direction & (DMA_TO_DEVICE | DMA_FROM_DEVICE)))) 800 if (unlikely(!(direction & (DMA_DEV_TO_MEM | DMA_MEM_TO_DEV))))
801 goto err_out; 801 goto err_out;
802 802
803 return 0; 803 return 0;
@@ -812,7 +812,7 @@ err_out:
812static int 812static int
813atc_dma_cyclic_fill_desc(struct at_dma_slave *atslave, struct at_desc *desc, 813atc_dma_cyclic_fill_desc(struct at_dma_slave *atslave, struct at_desc *desc,
814 unsigned int period_index, dma_addr_t buf_addr, 814 unsigned int period_index, dma_addr_t buf_addr,
815 size_t period_len, enum dma_data_direction direction) 815 size_t period_len, enum dma_transfer_direction direction)
816{ 816{
817 u32 ctrla; 817 u32 ctrla;
818 unsigned int reg_width = atslave->reg_width; 818 unsigned int reg_width = atslave->reg_width;
@@ -824,7 +824,7 @@ atc_dma_cyclic_fill_desc(struct at_dma_slave *atslave, struct at_desc *desc,
824 | period_len >> reg_width; 824 | period_len >> reg_width;
825 825
826 switch (direction) { 826 switch (direction) {
827 case DMA_TO_DEVICE: 827 case DMA_MEM_TO_DEV:
828 desc->lli.saddr = buf_addr + (period_len * period_index); 828 desc->lli.saddr = buf_addr + (period_len * period_index);
829 desc->lli.daddr = atslave->tx_reg; 829 desc->lli.daddr = atslave->tx_reg;
830 desc->lli.ctrla = ctrla; 830 desc->lli.ctrla = ctrla;
@@ -835,7 +835,7 @@ atc_dma_cyclic_fill_desc(struct at_dma_slave *atslave, struct at_desc *desc,
835 | ATC_DIF(AT_DMA_PER_IF); 835 | ATC_DIF(AT_DMA_PER_IF);
836 break; 836 break;
837 837
838 case DMA_FROM_DEVICE: 838 case DMA_DEV_TO_MEM:
839 desc->lli.saddr = atslave->rx_reg; 839 desc->lli.saddr = atslave->rx_reg;
840 desc->lli.daddr = buf_addr + (period_len * period_index); 840 desc->lli.daddr = buf_addr + (period_len * period_index);
841 desc->lli.ctrla = ctrla; 841 desc->lli.ctrla = ctrla;
@@ -863,7 +863,7 @@ atc_dma_cyclic_fill_desc(struct at_dma_slave *atslave, struct at_desc *desc,
863 */ 863 */
864static struct dma_async_tx_descriptor * 864static struct dma_async_tx_descriptor *
865atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, 865atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
866 size_t period_len, enum dma_data_direction direction) 866 size_t period_len, enum dma_transfer_direction direction)
867{ 867{
868 struct at_dma_chan *atchan = to_at_dma_chan(chan); 868 struct at_dma_chan *atchan = to_at_dma_chan(chan);
869 struct at_dma_slave *atslave = chan->private; 869 struct at_dma_slave *atslave = chan->private;
@@ -874,7 +874,7 @@ atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
874 unsigned int i; 874 unsigned int i;
875 875
876 dev_vdbg(chan2dev(chan), "prep_dma_cyclic: %s buf@0x%08x - %d (%d/%d)\n", 876 dev_vdbg(chan2dev(chan), "prep_dma_cyclic: %s buf@0x%08x - %d (%d/%d)\n",
877 direction == DMA_TO_DEVICE ? "TO DEVICE" : "FROM DEVICE", 877 direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE",
878 buf_addr, 878 buf_addr,
879 periods, buf_len, period_len); 879 periods, buf_len, period_len);
880 880
diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c
index 4234f416ef11..d65a718c0f9b 100644
--- a/drivers/dma/coh901318.c
+++ b/drivers/dma/coh901318.c
@@ -39,7 +39,7 @@ struct coh901318_desc {
39 struct scatterlist *sg; 39 struct scatterlist *sg;
40 unsigned int sg_len; 40 unsigned int sg_len;
41 struct coh901318_lli *lli; 41 struct coh901318_lli *lli;
42 enum dma_data_direction dir; 42 enum dma_transfer_direction dir;
43 unsigned long flags; 43 unsigned long flags;
44 u32 head_config; 44 u32 head_config;
45 u32 head_ctrl; 45 u32 head_ctrl;
@@ -1034,7 +1034,7 @@ coh901318_prep_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1034 1034
1035static struct dma_async_tx_descriptor * 1035static struct dma_async_tx_descriptor *
1036coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 1036coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
1037 unsigned int sg_len, enum dma_data_direction direction, 1037 unsigned int sg_len, enum dma_transfer_direction direction,
1038 unsigned long flags) 1038 unsigned long flags)
1039{ 1039{
1040 struct coh901318_chan *cohc = to_coh901318_chan(chan); 1040 struct coh901318_chan *cohc = to_coh901318_chan(chan);
@@ -1077,7 +1077,7 @@ coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
1077 ctrl_last |= cohc->runtime_ctrl; 1077 ctrl_last |= cohc->runtime_ctrl;
1078 ctrl |= cohc->runtime_ctrl; 1078 ctrl |= cohc->runtime_ctrl;
1079 1079
1080 if (direction == DMA_TO_DEVICE) { 1080 if (direction == DMA_MEM_TO_DEV) {
1081 u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE | 1081 u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE |
1082 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE; 1082 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE;
1083 1083
@@ -1085,7 +1085,7 @@ coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
1085 ctrl_chained |= tx_flags; 1085 ctrl_chained |= tx_flags;
1086 ctrl_last |= tx_flags; 1086 ctrl_last |= tx_flags;
1087 ctrl |= tx_flags; 1087 ctrl |= tx_flags;
1088 } else if (direction == DMA_FROM_DEVICE) { 1088 } else if (direction == DMA_DEV_TO_MEM) {
1089 u32 rx_flags = COH901318_CX_CTRL_PRDD_DEST | 1089 u32 rx_flags = COH901318_CX_CTRL_PRDD_DEST |
1090 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE; 1090 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE;
1091 1091
@@ -1274,11 +1274,11 @@ static void coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
1274 int i = 0; 1274 int i = 0;
1275 1275
1276 /* We only support mem to per or per to mem transfers */ 1276 /* We only support mem to per or per to mem transfers */
1277 if (config->direction == DMA_FROM_DEVICE) { 1277 if (config->direction == DMA_DEV_TO_MEM) {
1278 addr = config->src_addr; 1278 addr = config->src_addr;
1279 addr_width = config->src_addr_width; 1279 addr_width = config->src_addr_width;
1280 maxburst = config->src_maxburst; 1280 maxburst = config->src_maxburst;
1281 } else if (config->direction == DMA_TO_DEVICE) { 1281 } else if (config->direction == DMA_MEM_TO_DEV) {
1282 addr = config->dst_addr; 1282 addr = config->dst_addr;
1283 addr_width = config->dst_addr_width; 1283 addr_width = config->dst_addr_width;
1284 maxburst = config->dst_maxburst; 1284 maxburst = config->dst_maxburst;
diff --git a/drivers/dma/coh901318_lli.c b/drivers/dma/coh901318_lli.c
index 9f7e0e6a7eea..6c0e2d4c6682 100644
--- a/drivers/dma/coh901318_lli.c
+++ b/drivers/dma/coh901318_lli.c
@@ -7,11 +7,10 @@
7 * Author: Per Friden <per.friden@stericsson.com> 7 * Author: Per Friden <per.friden@stericsson.com>
8 */ 8 */
9 9
10#include <linux/dma-mapping.h>
11#include <linux/spinlock.h> 10#include <linux/spinlock.h>
12#include <linux/dmapool.h>
13#include <linux/memory.h> 11#include <linux/memory.h>
14#include <linux/gfp.h> 12#include <linux/gfp.h>
13#include <linux/dmapool.h>
15#include <mach/coh901318.h> 14#include <mach/coh901318.h>
16 15
17#include "coh901318_lli.h" 16#include "coh901318_lli.h"
@@ -177,18 +176,18 @@ coh901318_lli_fill_single(struct coh901318_pool *pool,
177 struct coh901318_lli *lli, 176 struct coh901318_lli *lli,
178 dma_addr_t buf, unsigned int size, 177 dma_addr_t buf, unsigned int size,
179 dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl_eom, 178 dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl_eom,
180 enum dma_data_direction dir) 179 enum dma_transfer_direction dir)
181{ 180{
182 int s = size; 181 int s = size;
183 dma_addr_t src; 182 dma_addr_t src;
184 dma_addr_t dst; 183 dma_addr_t dst;
185 184
186 185
187 if (dir == DMA_TO_DEVICE) { 186 if (dir == DMA_MEM_TO_DEV) {
188 src = buf; 187 src = buf;
189 dst = dev_addr; 188 dst = dev_addr;
190 189
191 } else if (dir == DMA_FROM_DEVICE) { 190 } else if (dir == DMA_DEV_TO_MEM) {
192 191
193 src = dev_addr; 192 src = dev_addr;
194 dst = buf; 193 dst = buf;
@@ -215,9 +214,9 @@ coh901318_lli_fill_single(struct coh901318_pool *pool,
215 214
216 lli = coh901318_lli_next(lli); 215 lli = coh901318_lli_next(lli);
217 216
218 if (dir == DMA_TO_DEVICE) 217 if (dir == DMA_MEM_TO_DEV)
219 src += block_size; 218 src += block_size;
220 else if (dir == DMA_FROM_DEVICE) 219 else if (dir == DMA_DEV_TO_MEM)
221 dst += block_size; 220 dst += block_size;
222 } 221 }
223 222
@@ -234,7 +233,7 @@ coh901318_lli_fill_sg(struct coh901318_pool *pool,
234 struct scatterlist *sgl, unsigned int nents, 233 struct scatterlist *sgl, unsigned int nents,
235 dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl, 234 dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl,
236 u32 ctrl_last, 235 u32 ctrl_last,
237 enum dma_data_direction dir, u32 ctrl_irq_mask) 236 enum dma_transfer_direction dir, u32 ctrl_irq_mask)
238{ 237{
239 int i; 238 int i;
240 struct scatterlist *sg; 239 struct scatterlist *sg;
@@ -249,9 +248,9 @@ coh901318_lli_fill_sg(struct coh901318_pool *pool,
249 248
250 spin_lock(&pool->lock); 249 spin_lock(&pool->lock);
251 250
252 if (dir == DMA_TO_DEVICE) 251 if (dir == DMA_MEM_TO_DEV)
253 dst = dev_addr; 252 dst = dev_addr;
254 else if (dir == DMA_FROM_DEVICE) 253 else if (dir == DMA_DEV_TO_MEM)
255 src = dev_addr; 254 src = dev_addr;
256 else 255 else
257 goto err; 256 goto err;
@@ -269,7 +268,7 @@ coh901318_lli_fill_sg(struct coh901318_pool *pool,
269 ctrl_sg = ctrl ? ctrl : ctrl_last; 268 ctrl_sg = ctrl ? ctrl : ctrl_last;
270 269
271 270
272 if (dir == DMA_TO_DEVICE) 271 if (dir == DMA_MEM_TO_DEV)
273 /* increment source address */ 272 /* increment source address */
274 src = sg_phys(sg); 273 src = sg_phys(sg);
275 else 274 else
@@ -293,7 +292,7 @@ coh901318_lli_fill_sg(struct coh901318_pool *pool,
293 lli->src_addr = src; 292 lli->src_addr = src;
294 lli->dst_addr = dst; 293 lli->dst_addr = dst;
295 294
296 if (dir == DMA_FROM_DEVICE) 295 if (dir == DMA_DEV_TO_MEM)
297 dst += elem_size; 296 dst += elem_size;
298 else 297 else
299 src += elem_size; 298 src += elem_size;
diff --git a/drivers/dma/coh901318_lli.h b/drivers/dma/coh901318_lli.h
index 7a5c80990e9e..abff3714fdda 100644
--- a/drivers/dma/coh901318_lli.h
+++ b/drivers/dma/coh901318_lli.h
@@ -97,7 +97,7 @@ coh901318_lli_fill_single(struct coh901318_pool *pool,
97 struct coh901318_lli *lli, 97 struct coh901318_lli *lli,
98 dma_addr_t buf, unsigned int size, 98 dma_addr_t buf, unsigned int size,
99 dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl_last, 99 dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl_last,
100 enum dma_data_direction dir); 100 enum dma_transfer_direction dir);
101 101
102/** 102/**
103 * coh901318_lli_fill_single() - Prepares the lli:s for dma scatter list transfer 103 * coh901318_lli_fill_single() - Prepares the lli:s for dma scatter list transfer
@@ -119,6 +119,6 @@ coh901318_lli_fill_sg(struct coh901318_pool *pool,
119 struct scatterlist *sg, unsigned int nents, 119 struct scatterlist *sg, unsigned int nents,
120 dma_addr_t dev_addr, u32 ctrl_chained, 120 dma_addr_t dev_addr, u32 ctrl_chained,
121 u32 ctrl, u32 ctrl_last, 121 u32 ctrl, u32 ctrl_last,
122 enum dma_data_direction dir, u32 ctrl_irq_mask); 122 enum dma_transfer_direction dir, u32 ctrl_irq_mask);
123 123
124#endif /* COH901318_LLI_H */ 124#endif /* COH901318_LLI_H */
diff --git a/drivers/dma/dw_dmac.c b/drivers/dma/dw_dmac.c
index 9bfd6d360718..decca1c3c83d 100644
--- a/drivers/dma/dw_dmac.c
+++ b/drivers/dma/dw_dmac.c
@@ -696,7 +696,7 @@ err_desc_get:
696 696
697static struct dma_async_tx_descriptor * 697static struct dma_async_tx_descriptor *
698dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 698dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
699 unsigned int sg_len, enum dma_data_direction direction, 699 unsigned int sg_len, enum dma_transfer_direction direction,
700 unsigned long flags) 700 unsigned long flags)
701{ 701{
702 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 702 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
@@ -720,7 +720,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
720 prev = first = NULL; 720 prev = first = NULL;
721 721
722 switch (direction) { 722 switch (direction) {
723 case DMA_TO_DEVICE: 723 case DMA_MEM_TO_DEV:
724 ctllo = (DWC_DEFAULT_CTLLO(chan->private) 724 ctllo = (DWC_DEFAULT_CTLLO(chan->private)
725 | DWC_CTLL_DST_WIDTH(reg_width) 725 | DWC_CTLL_DST_WIDTH(reg_width)
726 | DWC_CTLL_DST_FIX 726 | DWC_CTLL_DST_FIX
@@ -777,7 +777,7 @@ slave_sg_todev_fill_desc:
777 goto slave_sg_todev_fill_desc; 777 goto slave_sg_todev_fill_desc;
778 } 778 }
779 break; 779 break;
780 case DMA_FROM_DEVICE: 780 case DMA_DEV_TO_MEM:
781 ctllo = (DWC_DEFAULT_CTLLO(chan->private) 781 ctllo = (DWC_DEFAULT_CTLLO(chan->private)
782 | DWC_CTLL_SRC_WIDTH(reg_width) 782 | DWC_CTLL_SRC_WIDTH(reg_width)
783 | DWC_CTLL_DST_INC 783 | DWC_CTLL_DST_INC
@@ -1165,7 +1165,7 @@ EXPORT_SYMBOL(dw_dma_cyclic_stop);
1165 */ 1165 */
1166struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, 1166struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1167 dma_addr_t buf_addr, size_t buf_len, size_t period_len, 1167 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1168 enum dma_data_direction direction) 1168 enum dma_transfer_direction direction)
1169{ 1169{
1170 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1170 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1171 struct dw_cyclic_desc *cdesc; 1171 struct dw_cyclic_desc *cdesc;
@@ -1206,7 +1206,7 @@ struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1206 goto out_err; 1206 goto out_err;
1207 if (unlikely(buf_addr & ((1 << reg_width) - 1))) 1207 if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1208 goto out_err; 1208 goto out_err;
1209 if (unlikely(!(direction & (DMA_TO_DEVICE | DMA_FROM_DEVICE)))) 1209 if (unlikely(!(direction & (DMA_MEM_TO_DEV | DMA_DEV_TO_MEM))))
1210 goto out_err; 1210 goto out_err;
1211 1211
1212 retval = ERR_PTR(-ENOMEM); 1212 retval = ERR_PTR(-ENOMEM);
@@ -1228,7 +1228,7 @@ struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1228 goto out_err_desc_get; 1228 goto out_err_desc_get;
1229 1229
1230 switch (direction) { 1230 switch (direction) {
1231 case DMA_TO_DEVICE: 1231 case DMA_MEM_TO_DEV:
1232 desc->lli.dar = dws->tx_reg; 1232 desc->lli.dar = dws->tx_reg;
1233 desc->lli.sar = buf_addr + (period_len * i); 1233 desc->lli.sar = buf_addr + (period_len * i);
1234 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan->private) 1234 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan->private)
@@ -1239,7 +1239,7 @@ struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1239 | DWC_CTLL_FC(dws->fc) 1239 | DWC_CTLL_FC(dws->fc)
1240 | DWC_CTLL_INT_EN); 1240 | DWC_CTLL_INT_EN);
1241 break; 1241 break;
1242 case DMA_FROM_DEVICE: 1242 case DMA_DEV_TO_MEM:
1243 desc->lli.dar = buf_addr + (period_len * i); 1243 desc->lli.dar = buf_addr + (period_len * i);
1244 desc->lli.sar = dws->rx_reg; 1244 desc->lli.sar = dws->rx_reg;
1245 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan->private) 1245 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan->private)
diff --git a/drivers/dma/ep93xx_dma.c b/drivers/dma/ep93xx_dma.c
index b47e2b803faf..009851b2aeea 100644
--- a/drivers/dma/ep93xx_dma.c
+++ b/drivers/dma/ep93xx_dma.c
@@ -330,7 +330,7 @@ static void m2p_fill_desc(struct ep93xx_dma_chan *edmac)
330 struct ep93xx_dma_desc *desc = ep93xx_dma_get_active(edmac); 330 struct ep93xx_dma_desc *desc = ep93xx_dma_get_active(edmac);
331 u32 bus_addr; 331 u32 bus_addr;
332 332
333 if (ep93xx_dma_chan_direction(&edmac->chan) == DMA_TO_DEVICE) 333 if (ep93xx_dma_chan_direction(&edmac->chan) == DMA_MEM_TO_DEV)
334 bus_addr = desc->src_addr; 334 bus_addr = desc->src_addr;
335 else 335 else
336 bus_addr = desc->dst_addr; 336 bus_addr = desc->dst_addr;
@@ -443,7 +443,7 @@ static int m2m_hw_setup(struct ep93xx_dma_chan *edmac)
443 control = (5 << M2M_CONTROL_PWSC_SHIFT); 443 control = (5 << M2M_CONTROL_PWSC_SHIFT);
444 control |= M2M_CONTROL_NO_HDSK; 444 control |= M2M_CONTROL_NO_HDSK;
445 445
446 if (data->direction == DMA_TO_DEVICE) { 446 if (data->direction == DMA_MEM_TO_DEV) {
447 control |= M2M_CONTROL_DAH; 447 control |= M2M_CONTROL_DAH;
448 control |= M2M_CONTROL_TM_TX; 448 control |= M2M_CONTROL_TM_TX;
449 control |= M2M_CONTROL_RSS_SSPTX; 449 control |= M2M_CONTROL_RSS_SSPTX;
@@ -463,7 +463,7 @@ static int m2m_hw_setup(struct ep93xx_dma_chan *edmac)
463 control |= M2M_CONTROL_RSS_IDE; 463 control |= M2M_CONTROL_RSS_IDE;
464 control |= M2M_CONTROL_PW_16; 464 control |= M2M_CONTROL_PW_16;
465 465
466 if (data->direction == DMA_TO_DEVICE) { 466 if (data->direction == DMA_MEM_TO_DEV) {
467 /* Worst case from the UG */ 467 /* Worst case from the UG */
468 control = (3 << M2M_CONTROL_PWSC_SHIFT); 468 control = (3 << M2M_CONTROL_PWSC_SHIFT);
469 control |= M2M_CONTROL_DAH; 469 control |= M2M_CONTROL_DAH;
@@ -803,8 +803,8 @@ static int ep93xx_dma_alloc_chan_resources(struct dma_chan *chan)
803 switch (data->port) { 803 switch (data->port) {
804 case EP93XX_DMA_SSP: 804 case EP93XX_DMA_SSP:
805 case EP93XX_DMA_IDE: 805 case EP93XX_DMA_IDE:
806 if (data->direction != DMA_TO_DEVICE && 806 if (data->direction != DMA_MEM_TO_DEV &&
807 data->direction != DMA_FROM_DEVICE) 807 data->direction != DMA_DEV_TO_MEM)
808 return -EINVAL; 808 return -EINVAL;
809 break; 809 break;
810 default: 810 default:
@@ -952,7 +952,7 @@ fail:
952 */ 952 */
953static struct dma_async_tx_descriptor * 953static struct dma_async_tx_descriptor *
954ep93xx_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 954ep93xx_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
955 unsigned int sg_len, enum dma_data_direction dir, 955 unsigned int sg_len, enum dma_transfer_direction dir,
956 unsigned long flags) 956 unsigned long flags)
957{ 957{
958 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan); 958 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
@@ -988,7 +988,7 @@ ep93xx_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
988 goto fail; 988 goto fail;
989 } 989 }
990 990
991 if (dir == DMA_TO_DEVICE) { 991 if (dir == DMA_MEM_TO_DEV) {
992 desc->src_addr = sg_dma_address(sg); 992 desc->src_addr = sg_dma_address(sg);
993 desc->dst_addr = edmac->runtime_addr; 993 desc->dst_addr = edmac->runtime_addr;
994 } else { 994 } else {
@@ -1032,7 +1032,7 @@ fail:
1032static struct dma_async_tx_descriptor * 1032static struct dma_async_tx_descriptor *
1033ep93xx_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr, 1033ep93xx_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,
1034 size_t buf_len, size_t period_len, 1034 size_t buf_len, size_t period_len,
1035 enum dma_data_direction dir) 1035 enum dma_transfer_direction dir)
1036{ 1036{
1037 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan); 1037 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
1038 struct ep93xx_dma_desc *desc, *first; 1038 struct ep93xx_dma_desc *desc, *first;
@@ -1065,7 +1065,7 @@ ep93xx_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,
1065 goto fail; 1065 goto fail;
1066 } 1066 }
1067 1067
1068 if (dir == DMA_TO_DEVICE) { 1068 if (dir == DMA_MEM_TO_DEV) {
1069 desc->src_addr = dma_addr + offset; 1069 desc->src_addr = dma_addr + offset;
1070 desc->dst_addr = edmac->runtime_addr; 1070 desc->dst_addr = edmac->runtime_addr;
1071 } else { 1071 } else {
@@ -1133,12 +1133,12 @@ static int ep93xx_dma_slave_config(struct ep93xx_dma_chan *edmac,
1133 return -EINVAL; 1133 return -EINVAL;
1134 1134
1135 switch (config->direction) { 1135 switch (config->direction) {
1136 case DMA_FROM_DEVICE: 1136 case DMA_DEV_TO_MEM:
1137 width = config->src_addr_width; 1137 width = config->src_addr_width;
1138 addr = config->src_addr; 1138 addr = config->src_addr;
1139 break; 1139 break;
1140 1140
1141 case DMA_TO_DEVICE: 1141 case DMA_MEM_TO_DEV:
1142 width = config->dst_addr_width; 1142 width = config->dst_addr_width;
1143 addr = config->dst_addr; 1143 addr = config->dst_addr;
1144 break; 1144 break;
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 8a781540590c..b98070c33ca9 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -772,7 +772,7 @@ fail:
772 */ 772 */
773static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg( 773static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg(
774 struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len, 774 struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len,
775 enum dma_data_direction direction, unsigned long flags) 775 enum dma_transfer_direction direction, unsigned long flags)
776{ 776{
777 /* 777 /*
778 * This operation is not supported on the Freescale DMA controller 778 * This operation is not supported on the Freescale DMA controller
@@ -819,7 +819,7 @@ static int fsl_dma_device_control(struct dma_chan *dchan,
819 return -ENXIO; 819 return -ENXIO;
820 820
821 /* we set the controller burst size depending on direction */ 821 /* we set the controller burst size depending on direction */
822 if (config->direction == DMA_TO_DEVICE) 822 if (config->direction == DMA_MEM_TO_DEV)
823 size = config->dst_addr_width * config->dst_maxburst; 823 size = config->dst_addr_width * config->dst_maxburst;
824 else 824 else
825 size = config->src_addr_width * config->src_maxburst; 825 size = config->src_addr_width * config->src_maxburst;
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 4be55f9bb6c1..e4383ee2c9ac 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -107,7 +107,7 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
107 imx_dma_disable(imxdmac->imxdma_channel); 107 imx_dma_disable(imxdmac->imxdma_channel);
108 return 0; 108 return 0;
109 case DMA_SLAVE_CONFIG: 109 case DMA_SLAVE_CONFIG:
110 if (dmaengine_cfg->direction == DMA_FROM_DEVICE) { 110 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
111 imxdmac->per_address = dmaengine_cfg->src_addr; 111 imxdmac->per_address = dmaengine_cfg->src_addr;
112 imxdmac->watermark_level = dmaengine_cfg->src_maxburst; 112 imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
113 imxdmac->word_size = dmaengine_cfg->src_addr_width; 113 imxdmac->word_size = dmaengine_cfg->src_addr_width;
@@ -224,7 +224,7 @@ static void imxdma_free_chan_resources(struct dma_chan *chan)
224 224
225static struct dma_async_tx_descriptor *imxdma_prep_slave_sg( 225static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
226 struct dma_chan *chan, struct scatterlist *sgl, 226 struct dma_chan *chan, struct scatterlist *sgl,
227 unsigned int sg_len, enum dma_data_direction direction, 227 unsigned int sg_len, enum dma_transfer_direction direction,
228 unsigned long flags) 228 unsigned long flags)
229{ 229{
230 struct imxdma_channel *imxdmac = to_imxdma_chan(chan); 230 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
@@ -241,7 +241,7 @@ static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
241 dma_length += sg->length; 241 dma_length += sg->length;
242 } 242 }
243 243
244 if (direction == DMA_FROM_DEVICE) 244 if (direction == DMA_DEV_TO_MEM)
245 dmamode = DMA_MODE_READ; 245 dmamode = DMA_MODE_READ;
246 else 246 else
247 dmamode = DMA_MODE_WRITE; 247 dmamode = DMA_MODE_WRITE;
@@ -271,7 +271,7 @@ static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
271 271
272static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic( 272static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
273 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 273 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
274 size_t period_len, enum dma_data_direction direction) 274 size_t period_len, enum dma_transfer_direction direction)
275{ 275{
276 struct imxdma_channel *imxdmac = to_imxdma_chan(chan); 276 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
277 struct imxdma_engine *imxdma = imxdmac->imxdma; 277 struct imxdma_engine *imxdma = imxdmac->imxdma;
@@ -317,7 +317,7 @@ static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
317 imxdmac->sg_list[periods].page_link = 317 imxdmac->sg_list[periods].page_link =
318 ((unsigned long)imxdmac->sg_list | 0x01) & ~0x02; 318 ((unsigned long)imxdmac->sg_list | 0x01) & ~0x02;
319 319
320 if (direction == DMA_FROM_DEVICE) 320 if (direction == DMA_DEV_TO_MEM)
321 dmamode = DMA_MODE_READ; 321 dmamode = DMA_MODE_READ;
322 else 322 else
323 dmamode = DMA_MODE_WRITE; 323 dmamode = DMA_MODE_WRITE;
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index f993955a640c..2e0357178d19 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -247,7 +247,7 @@ struct sdma_engine;
247struct sdma_channel { 247struct sdma_channel {
248 struct sdma_engine *sdma; 248 struct sdma_engine *sdma;
249 unsigned int channel; 249 unsigned int channel;
250 enum dma_data_direction direction; 250 enum dma_transfer_direction direction;
251 enum sdma_peripheral_type peripheral_type; 251 enum sdma_peripheral_type peripheral_type;
252 unsigned int event_id0; 252 unsigned int event_id0;
253 unsigned int event_id1; 253 unsigned int event_id1;
@@ -650,7 +650,7 @@ static int sdma_load_context(struct sdma_channel *sdmac)
650 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd; 650 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
651 int ret; 651 int ret;
652 652
653 if (sdmac->direction == DMA_FROM_DEVICE) { 653 if (sdmac->direction == DMA_DEV_TO_MEM) {
654 load_address = sdmac->pc_from_device; 654 load_address = sdmac->pc_from_device;
655 } else { 655 } else {
656 load_address = sdmac->pc_to_device; 656 load_address = sdmac->pc_to_device;
@@ -911,7 +911,7 @@ static void sdma_free_chan_resources(struct dma_chan *chan)
911 911
912static struct dma_async_tx_descriptor *sdma_prep_slave_sg( 912static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
913 struct dma_chan *chan, struct scatterlist *sgl, 913 struct dma_chan *chan, struct scatterlist *sgl,
914 unsigned int sg_len, enum dma_data_direction direction, 914 unsigned int sg_len, enum dma_transfer_direction direction,
915 unsigned long flags) 915 unsigned long flags)
916{ 916{
917 struct sdma_channel *sdmac = to_sdma_chan(chan); 917 struct sdma_channel *sdmac = to_sdma_chan(chan);
@@ -1008,7 +1008,7 @@ err_out:
1008 1008
1009static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic( 1009static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1010 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 1010 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1011 size_t period_len, enum dma_data_direction direction) 1011 size_t period_len, enum dma_transfer_direction direction)
1012{ 1012{
1013 struct sdma_channel *sdmac = to_sdma_chan(chan); 1013 struct sdma_channel *sdmac = to_sdma_chan(chan);
1014 struct sdma_engine *sdma = sdmac->sdma; 1014 struct sdma_engine *sdma = sdmac->sdma;
@@ -1093,7 +1093,7 @@ static int sdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1093 sdma_disable_channel(sdmac); 1093 sdma_disable_channel(sdmac);
1094 return 0; 1094 return 0;
1095 case DMA_SLAVE_CONFIG: 1095 case DMA_SLAVE_CONFIG:
1096 if (dmaengine_cfg->direction == DMA_FROM_DEVICE) { 1096 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
1097 sdmac->per_address = dmaengine_cfg->src_addr; 1097 sdmac->per_address = dmaengine_cfg->src_addr;
1098 sdmac->watermark_level = dmaengine_cfg->src_maxburst; 1098 sdmac->watermark_level = dmaengine_cfg->src_maxburst;
1099 sdmac->word_size = dmaengine_cfg->src_addr_width; 1099 sdmac->word_size = dmaengine_cfg->src_addr_width;
diff --git a/drivers/dma/intel_mid_dma.c b/drivers/dma/intel_mid_dma.c
index 19a0c64d45d3..01929ed6659d 100644
--- a/drivers/dma/intel_mid_dma.c
+++ b/drivers/dma/intel_mid_dma.c
@@ -395,10 +395,10 @@ static int midc_lli_fill_sg(struct intel_mid_dma_chan *midc,
395 midc->dma->block_size); 395 midc->dma->block_size);
396 /*Populate SAR and DAR values*/ 396 /*Populate SAR and DAR values*/
397 sg_phy_addr = sg_phys(sg); 397 sg_phy_addr = sg_phys(sg);
398 if (desc->dirn == DMA_TO_DEVICE) { 398 if (desc->dirn == DMA_MEM_TO_DEV) {
399 lli_bloc_desc->sar = sg_phy_addr; 399 lli_bloc_desc->sar = sg_phy_addr;
400 lli_bloc_desc->dar = mids->dma_slave.dst_addr; 400 lli_bloc_desc->dar = mids->dma_slave.dst_addr;
401 } else if (desc->dirn == DMA_FROM_DEVICE) { 401 } else if (desc->dirn == DMA_DEV_TO_MEM) {
402 lli_bloc_desc->sar = mids->dma_slave.src_addr; 402 lli_bloc_desc->sar = mids->dma_slave.src_addr;
403 lli_bloc_desc->dar = sg_phy_addr; 403 lli_bloc_desc->dar = sg_phy_addr;
404 } 404 }
@@ -632,13 +632,13 @@ static struct dma_async_tx_descriptor *intel_mid_dma_prep_memcpy(
632 if (midc->dma->pimr_mask) { 632 if (midc->dma->pimr_mask) {
633 cfg_hi.cfgx.protctl = 0x0; /*default value*/ 633 cfg_hi.cfgx.protctl = 0x0; /*default value*/
634 cfg_hi.cfgx.fifo_mode = 1; 634 cfg_hi.cfgx.fifo_mode = 1;
635 if (mids->dma_slave.direction == DMA_TO_DEVICE) { 635 if (mids->dma_slave.direction == DMA_MEM_TO_DEV) {
636 cfg_hi.cfgx.src_per = 0; 636 cfg_hi.cfgx.src_per = 0;
637 if (mids->device_instance == 0) 637 if (mids->device_instance == 0)
638 cfg_hi.cfgx.dst_per = 3; 638 cfg_hi.cfgx.dst_per = 3;
639 if (mids->device_instance == 1) 639 if (mids->device_instance == 1)
640 cfg_hi.cfgx.dst_per = 1; 640 cfg_hi.cfgx.dst_per = 1;
641 } else if (mids->dma_slave.direction == DMA_FROM_DEVICE) { 641 } else if (mids->dma_slave.direction == DMA_DEV_TO_MEM) {
642 if (mids->device_instance == 0) 642 if (mids->device_instance == 0)
643 cfg_hi.cfgx.src_per = 2; 643 cfg_hi.cfgx.src_per = 2;
644 if (mids->device_instance == 1) 644 if (mids->device_instance == 1)
@@ -682,11 +682,11 @@ static struct dma_async_tx_descriptor *intel_mid_dma_prep_memcpy(
682 ctl_lo.ctlx.sinc = 0; 682 ctl_lo.ctlx.sinc = 0;
683 ctl_lo.ctlx.dinc = 0; 683 ctl_lo.ctlx.dinc = 0;
684 } else { 684 } else {
685 if (mids->dma_slave.direction == DMA_TO_DEVICE) { 685 if (mids->dma_slave.direction == DMA_MEM_TO_DEV) {
686 ctl_lo.ctlx.sinc = 0; 686 ctl_lo.ctlx.sinc = 0;
687 ctl_lo.ctlx.dinc = 2; 687 ctl_lo.ctlx.dinc = 2;
688 ctl_lo.ctlx.tt_fc = 1; 688 ctl_lo.ctlx.tt_fc = 1;
689 } else if (mids->dma_slave.direction == DMA_FROM_DEVICE) { 689 } else if (mids->dma_slave.direction == DMA_DEV_TO_MEM) {
690 ctl_lo.ctlx.sinc = 2; 690 ctl_lo.ctlx.sinc = 2;
691 ctl_lo.ctlx.dinc = 0; 691 ctl_lo.ctlx.dinc = 0;
692 ctl_lo.ctlx.tt_fc = 2; 692 ctl_lo.ctlx.tt_fc = 2;
@@ -732,7 +732,7 @@ err_desc_get:
732 */ 732 */
733static struct dma_async_tx_descriptor *intel_mid_dma_prep_slave_sg( 733static struct dma_async_tx_descriptor *intel_mid_dma_prep_slave_sg(
734 struct dma_chan *chan, struct scatterlist *sgl, 734 struct dma_chan *chan, struct scatterlist *sgl,
735 unsigned int sg_len, enum dma_data_direction direction, 735 unsigned int sg_len, enum dma_transfer_direction direction,
736 unsigned long flags) 736 unsigned long flags)
737{ 737{
738 struct intel_mid_dma_chan *midc = NULL; 738 struct intel_mid_dma_chan *midc = NULL;
diff --git a/drivers/dma/intel_mid_dma_regs.h b/drivers/dma/intel_mid_dma_regs.h
index aea5ee88ce03..c6de919a6401 100644
--- a/drivers/dma/intel_mid_dma_regs.h
+++ b/drivers/dma/intel_mid_dma_regs.h
@@ -262,7 +262,7 @@ struct intel_mid_dma_desc {
262 unsigned int lli_length; 262 unsigned int lli_length;
263 unsigned int current_lli; 263 unsigned int current_lli;
264 dma_addr_t next; 264 dma_addr_t next;
265 enum dma_data_direction dirn; 265 enum dma_transfer_direction dirn;
266 enum dma_status status; 266 enum dma_status status;
267 enum dma_slave_buswidth width; /*width of DMA txn*/ 267 enum dma_slave_buswidth width; /*width of DMA txn*/
268 enum intel_mid_dma_mode cfg_mode; /*mode configuration*/ 268 enum intel_mid_dma_mode cfg_mode; /*mode configuration*/
diff --git a/drivers/dma/ipu/ipu_idmac.c b/drivers/dma/ipu/ipu_idmac.c
index 0e5ef33f90a1..e16e280b26eb 100644
--- a/drivers/dma/ipu/ipu_idmac.c
+++ b/drivers/dma/ipu/ipu_idmac.c
@@ -1364,7 +1364,7 @@ static void ipu_gc_tasklet(unsigned long arg)
1364/* Allocate and initialise a transfer descriptor. */ 1364/* Allocate and initialise a transfer descriptor. */
1365static struct dma_async_tx_descriptor *idmac_prep_slave_sg(struct dma_chan *chan, 1365static struct dma_async_tx_descriptor *idmac_prep_slave_sg(struct dma_chan *chan,
1366 struct scatterlist *sgl, unsigned int sg_len, 1366 struct scatterlist *sgl, unsigned int sg_len,
1367 enum dma_data_direction direction, unsigned long tx_flags) 1367 enum dma_transfer_direction direction, unsigned long tx_flags)
1368{ 1368{
1369 struct idmac_channel *ichan = to_idmac_chan(chan); 1369 struct idmac_channel *ichan = to_idmac_chan(chan);
1370 struct idmac_tx_desc *desc = NULL; 1370 struct idmac_tx_desc *desc = NULL;
@@ -1376,7 +1376,7 @@ static struct dma_async_tx_descriptor *idmac_prep_slave_sg(struct dma_chan *chan
1376 chan->chan_id != IDMAC_IC_7) 1376 chan->chan_id != IDMAC_IC_7)
1377 return NULL; 1377 return NULL;
1378 1378
1379 if (direction != DMA_FROM_DEVICE && direction != DMA_TO_DEVICE) { 1379 if (direction != DMA_DEV_TO_MEM && direction != DMA_MEM_TO_DEV) {
1380 dev_err(chan->device->dev, "Invalid DMA direction %d!\n", direction); 1380 dev_err(chan->device->dev, "Invalid DMA direction %d!\n", direction);
1381 return NULL; 1381 return NULL;
1382 } 1382 }
diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c
index b4588bdd98bb..bdf4672b2553 100644
--- a/drivers/dma/mxs-dma.c
+++ b/drivers/dma/mxs-dma.c
@@ -377,7 +377,7 @@ static void mxs_dma_free_chan_resources(struct dma_chan *chan)
377 377
378static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg( 378static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg(
379 struct dma_chan *chan, struct scatterlist *sgl, 379 struct dma_chan *chan, struct scatterlist *sgl,
380 unsigned int sg_len, enum dma_data_direction direction, 380 unsigned int sg_len, enum dma_transfer_direction direction,
381 unsigned long append) 381 unsigned long append)
382{ 382{
383 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 383 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
@@ -450,7 +450,7 @@ static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg(
450 ccw->bits |= CCW_CHAIN; 450 ccw->bits |= CCW_CHAIN;
451 ccw->bits |= CCW_HALT_ON_TERM; 451 ccw->bits |= CCW_HALT_ON_TERM;
452 ccw->bits |= CCW_TERM_FLUSH; 452 ccw->bits |= CCW_TERM_FLUSH;
453 ccw->bits |= BF_CCW(direction == DMA_FROM_DEVICE ? 453 ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ?
454 MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, 454 MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ,
455 COMMAND); 455 COMMAND);
456 456
@@ -472,7 +472,7 @@ err_out:
472 472
473static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic( 473static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic(
474 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 474 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
475 size_t period_len, enum dma_data_direction direction) 475 size_t period_len, enum dma_transfer_direction direction)
476{ 476{
477 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 477 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
478 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 478 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
@@ -515,7 +515,7 @@ static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic(
515 ccw->bits |= CCW_IRQ; 515 ccw->bits |= CCW_IRQ;
516 ccw->bits |= CCW_HALT_ON_TERM; 516 ccw->bits |= CCW_HALT_ON_TERM;
517 ccw->bits |= CCW_TERM_FLUSH; 517 ccw->bits |= CCW_TERM_FLUSH;
518 ccw->bits |= BF_CCW(direction == DMA_FROM_DEVICE ? 518 ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ?
519 MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, COMMAND); 519 MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, COMMAND);
520 520
521 dma_addr += period_len; 521 dma_addr += period_len;
diff --git a/drivers/dma/pch_dma.c b/drivers/dma/pch_dma.c
index 60aca37e22ea..823f58179f9d 100644
--- a/drivers/dma/pch_dma.c
+++ b/drivers/dma/pch_dma.c
@@ -99,7 +99,7 @@ struct pch_dma_desc {
99struct pch_dma_chan { 99struct pch_dma_chan {
100 struct dma_chan chan; 100 struct dma_chan chan;
101 void __iomem *membase; 101 void __iomem *membase;
102 enum dma_data_direction dir; 102 enum dma_transfer_direction dir;
103 struct tasklet_struct tasklet; 103 struct tasklet_struct tasklet;
104 unsigned long err_status; 104 unsigned long err_status;
105 105
@@ -224,7 +224,7 @@ static void pdc_set_dir(struct dma_chan *chan)
224 mask_ctl = DMA_MASK_CTL0_MODE & ~(DMA_CTL0_MODE_MASK_BITS << 224 mask_ctl = DMA_MASK_CTL0_MODE & ~(DMA_CTL0_MODE_MASK_BITS <<
225 (DMA_CTL0_BITS_PER_CH * chan->chan_id)); 225 (DMA_CTL0_BITS_PER_CH * chan->chan_id));
226 val &= mask_mode; 226 val &= mask_mode;
227 if (pd_chan->dir == DMA_TO_DEVICE) 227 if (pd_chan->dir == DMA_MEM_TO_DEV)
228 val |= 0x1 << (DMA_CTL0_BITS_PER_CH * chan->chan_id + 228 val |= 0x1 << (DMA_CTL0_BITS_PER_CH * chan->chan_id +
229 DMA_CTL0_DIR_SHIFT_BITS); 229 DMA_CTL0_DIR_SHIFT_BITS);
230 else 230 else
@@ -242,7 +242,7 @@ static void pdc_set_dir(struct dma_chan *chan)
242 mask_ctl = DMA_MASK_CTL2_MODE & ~(DMA_CTL0_MODE_MASK_BITS << 242 mask_ctl = DMA_MASK_CTL2_MODE & ~(DMA_CTL0_MODE_MASK_BITS <<
243 (DMA_CTL0_BITS_PER_CH * ch)); 243 (DMA_CTL0_BITS_PER_CH * ch));
244 val &= mask_mode; 244 val &= mask_mode;
245 if (pd_chan->dir == DMA_TO_DEVICE) 245 if (pd_chan->dir == DMA_MEM_TO_DEV)
246 val |= 0x1 << (DMA_CTL0_BITS_PER_CH * ch + 246 val |= 0x1 << (DMA_CTL0_BITS_PER_CH * ch +
247 DMA_CTL0_DIR_SHIFT_BITS); 247 DMA_CTL0_DIR_SHIFT_BITS);
248 else 248 else
@@ -607,7 +607,7 @@ static void pd_issue_pending(struct dma_chan *chan)
607 607
608static struct dma_async_tx_descriptor *pd_prep_slave_sg(struct dma_chan *chan, 608static struct dma_async_tx_descriptor *pd_prep_slave_sg(struct dma_chan *chan,
609 struct scatterlist *sgl, unsigned int sg_len, 609 struct scatterlist *sgl, unsigned int sg_len,
610 enum dma_data_direction direction, unsigned long flags) 610 enum dma_transfer_direction direction, unsigned long flags)
611{ 611{
612 struct pch_dma_chan *pd_chan = to_pd_chan(chan); 612 struct pch_dma_chan *pd_chan = to_pd_chan(chan);
613 struct pch_dma_slave *pd_slave = chan->private; 613 struct pch_dma_slave *pd_slave = chan->private;
@@ -623,9 +623,9 @@ static struct dma_async_tx_descriptor *pd_prep_slave_sg(struct dma_chan *chan,
623 return NULL; 623 return NULL;
624 } 624 }
625 625
626 if (direction == DMA_FROM_DEVICE) 626 if (direction == DMA_DEV_TO_MEM)
627 reg = pd_slave->rx_reg; 627 reg = pd_slave->rx_reg;
628 else if (direction == DMA_TO_DEVICE) 628 else if (direction == DMA_MEM_TO_DEV)
629 reg = pd_slave->tx_reg; 629 reg = pd_slave->tx_reg;
630 else 630 else
631 return NULL; 631 return NULL;
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index 186b8221803e..e0da795bdcb3 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -320,14 +320,14 @@ static int pl330_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, unsigned
320 case DMA_SLAVE_CONFIG: 320 case DMA_SLAVE_CONFIG:
321 slave_config = (struct dma_slave_config *)arg; 321 slave_config = (struct dma_slave_config *)arg;
322 322
323 if (slave_config->direction == DMA_TO_DEVICE) { 323 if (slave_config->direction == DMA_MEM_TO_DEV) {
324 if (slave_config->dst_addr) 324 if (slave_config->dst_addr)
325 pch->fifo_addr = slave_config->dst_addr; 325 pch->fifo_addr = slave_config->dst_addr;
326 if (slave_config->dst_addr_width) 326 if (slave_config->dst_addr_width)
327 pch->burst_sz = __ffs(slave_config->dst_addr_width); 327 pch->burst_sz = __ffs(slave_config->dst_addr_width);
328 if (slave_config->dst_maxburst) 328 if (slave_config->dst_maxburst)
329 pch->burst_len = slave_config->dst_maxburst; 329 pch->burst_len = slave_config->dst_maxburst;
330 } else if (slave_config->direction == DMA_FROM_DEVICE) { 330 } else if (slave_config->direction == DMA_DEV_TO_MEM) {
331 if (slave_config->src_addr) 331 if (slave_config->src_addr)
332 pch->fifo_addr = slave_config->src_addr; 332 pch->fifo_addr = slave_config->src_addr;
333 if (slave_config->src_addr_width) 333 if (slave_config->src_addr_width)
@@ -597,7 +597,7 @@ static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
597 597
598static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic( 598static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
599 struct dma_chan *chan, dma_addr_t dma_addr, size_t len, 599 struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
600 size_t period_len, enum dma_data_direction direction) 600 size_t period_len, enum dma_transfer_direction direction)
601{ 601{
602 struct dma_pl330_desc *desc; 602 struct dma_pl330_desc *desc;
603 struct dma_pl330_chan *pch = to_pchan(chan); 603 struct dma_pl330_chan *pch = to_pchan(chan);
@@ -612,13 +612,13 @@ static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
612 } 612 }
613 613
614 switch (direction) { 614 switch (direction) {
615 case DMA_TO_DEVICE: 615 case DMA_MEM_TO_DEV:
616 desc->rqcfg.src_inc = 1; 616 desc->rqcfg.src_inc = 1;
617 desc->rqcfg.dst_inc = 0; 617 desc->rqcfg.dst_inc = 0;
618 src = dma_addr; 618 src = dma_addr;
619 dst = pch->fifo_addr; 619 dst = pch->fifo_addr;
620 break; 620 break;
621 case DMA_FROM_DEVICE: 621 case DMA_DEV_TO_MEM:
622 desc->rqcfg.src_inc = 0; 622 desc->rqcfg.src_inc = 0;
623 desc->rqcfg.dst_inc = 1; 623 desc->rqcfg.dst_inc = 1;
624 src = pch->fifo_addr; 624 src = pch->fifo_addr;
@@ -687,7 +687,7 @@ pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
687 687
688static struct dma_async_tx_descriptor * 688static struct dma_async_tx_descriptor *
689pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 689pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
690 unsigned int sg_len, enum dma_data_direction direction, 690 unsigned int sg_len, enum dma_transfer_direction direction,
691 unsigned long flg) 691 unsigned long flg)
692{ 692{
693 struct dma_pl330_desc *first, *desc = NULL; 693 struct dma_pl330_desc *first, *desc = NULL;
@@ -702,9 +702,9 @@ pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
702 return NULL; 702 return NULL;
703 703
704 /* Make sure the direction is consistent */ 704 /* Make sure the direction is consistent */
705 if ((direction == DMA_TO_DEVICE && 705 if ((direction == DMA_MEM_TO_DEV &&
706 peri->rqtype != MEMTODEV) || 706 peri->rqtype != MEMTODEV) ||
707 (direction == DMA_FROM_DEVICE && 707 (direction == DMA_DEV_TO_MEM &&
708 peri->rqtype != DEVTOMEM)) { 708 peri->rqtype != DEVTOMEM)) {
709 dev_err(pch->dmac->pif.dev, "%s:%d Invalid Direction\n", 709 dev_err(pch->dmac->pif.dev, "%s:%d Invalid Direction\n",
710 __func__, __LINE__); 710 __func__, __LINE__);
@@ -747,7 +747,7 @@ pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
747 else 747 else
748 list_add_tail(&desc->node, &first->node); 748 list_add_tail(&desc->node, &first->node);
749 749
750 if (direction == DMA_TO_DEVICE) { 750 if (direction == DMA_MEM_TO_DEV) {
751 desc->rqcfg.src_inc = 1; 751 desc->rqcfg.src_inc = 1;
752 desc->rqcfg.dst_inc = 0; 752 desc->rqcfg.dst_inc = 0;
753 fill_px(&desc->px, 753 fill_px(&desc->px,
diff --git a/drivers/dma/shdma.c b/drivers/dma/shdma.c
index 81809c2b46ab..592304fb41a6 100644
--- a/drivers/dma/shdma.c
+++ b/drivers/dma/shdma.c
@@ -23,7 +23,6 @@
23#include <linux/interrupt.h> 23#include <linux/interrupt.h>
24#include <linux/dmaengine.h> 24#include <linux/dmaengine.h>
25#include <linux/delay.h> 25#include <linux/delay.h>
26#include <linux/dma-mapping.h>
27#include <linux/platform_device.h> 26#include <linux/platform_device.h>
28#include <linux/pm_runtime.h> 27#include <linux/pm_runtime.h>
29#include <linux/sh_dma.h> 28#include <linux/sh_dma.h>
@@ -479,19 +478,19 @@ static void sh_dmae_free_chan_resources(struct dma_chan *chan)
479 * @sh_chan: DMA channel 478 * @sh_chan: DMA channel
480 * @flags: DMA transfer flags 479 * @flags: DMA transfer flags
481 * @dest: destination DMA address, incremented when direction equals 480 * @dest: destination DMA address, incremented when direction equals
482 * DMA_FROM_DEVICE or DMA_BIDIRECTIONAL 481 * DMA_DEV_TO_MEM
483 * @src: source DMA address, incremented when direction equals 482 * @src: source DMA address, incremented when direction equals
484 * DMA_TO_DEVICE or DMA_BIDIRECTIONAL 483 * DMA_MEM_TO_DEV
485 * @len: DMA transfer length 484 * @len: DMA transfer length
486 * @first: if NULL, set to the current descriptor and cookie set to -EBUSY 485 * @first: if NULL, set to the current descriptor and cookie set to -EBUSY
487 * @direction: needed for slave DMA to decide which address to keep constant, 486 * @direction: needed for slave DMA to decide which address to keep constant,
488 * equals DMA_BIDIRECTIONAL for MEMCPY 487 * equals DMA_MEM_TO_MEM for MEMCPY
489 * Returns 0 or an error 488 * Returns 0 or an error
490 * Locks: called with desc_lock held 489 * Locks: called with desc_lock held
491 */ 490 */
492static struct sh_desc *sh_dmae_add_desc(struct sh_dmae_chan *sh_chan, 491static struct sh_desc *sh_dmae_add_desc(struct sh_dmae_chan *sh_chan,
493 unsigned long flags, dma_addr_t *dest, dma_addr_t *src, size_t *len, 492 unsigned long flags, dma_addr_t *dest, dma_addr_t *src, size_t *len,
494 struct sh_desc **first, enum dma_data_direction direction) 493 struct sh_desc **first, enum dma_transfer_direction direction)
495{ 494{
496 struct sh_desc *new; 495 struct sh_desc *new;
497 size_t copy_size; 496 size_t copy_size;
@@ -531,9 +530,9 @@ static struct sh_desc *sh_dmae_add_desc(struct sh_dmae_chan *sh_chan,
531 new->direction = direction; 530 new->direction = direction;
532 531
533 *len -= copy_size; 532 *len -= copy_size;
534 if (direction == DMA_BIDIRECTIONAL || direction == DMA_TO_DEVICE) 533 if (direction == DMA_MEM_TO_MEM || direction == DMA_MEM_TO_DEV)
535 *src += copy_size; 534 *src += copy_size;
536 if (direction == DMA_BIDIRECTIONAL || direction == DMA_FROM_DEVICE) 535 if (direction == DMA_MEM_TO_MEM || direction == DMA_DEV_TO_MEM)
537 *dest += copy_size; 536 *dest += copy_size;
538 537
539 return new; 538 return new;
@@ -546,12 +545,12 @@ static struct sh_desc *sh_dmae_add_desc(struct sh_dmae_chan *sh_chan,
546 * converted to scatter-gather to guarantee consistent locking and a correct 545 * converted to scatter-gather to guarantee consistent locking and a correct
547 * list manipulation. For slave DMA direction carries the usual meaning, and, 546 * list manipulation. For slave DMA direction carries the usual meaning, and,
548 * logically, the SG list is RAM and the addr variable contains slave address, 547 * logically, the SG list is RAM and the addr variable contains slave address,
549 * e.g., the FIFO I/O register. For MEMCPY direction equals DMA_BIDIRECTIONAL 548 * e.g., the FIFO I/O register. For MEMCPY direction equals DMA_MEM_TO_MEM
550 * and the SG list contains only one element and points at the source buffer. 549 * and the SG list contains only one element and points at the source buffer.
551 */ 550 */
552static struct dma_async_tx_descriptor *sh_dmae_prep_sg(struct sh_dmae_chan *sh_chan, 551static struct dma_async_tx_descriptor *sh_dmae_prep_sg(struct sh_dmae_chan *sh_chan,
553 struct scatterlist *sgl, unsigned int sg_len, dma_addr_t *addr, 552 struct scatterlist *sgl, unsigned int sg_len, dma_addr_t *addr,
554 enum dma_data_direction direction, unsigned long flags) 553 enum dma_transfer_direction direction, unsigned long flags)
555{ 554{
556 struct scatterlist *sg; 555 struct scatterlist *sg;
557 struct sh_desc *first = NULL, *new = NULL /* compiler... */; 556 struct sh_desc *first = NULL, *new = NULL /* compiler... */;
@@ -592,7 +591,7 @@ static struct dma_async_tx_descriptor *sh_dmae_prep_sg(struct sh_dmae_chan *sh_c
592 dev_dbg(sh_chan->dev, "Add SG #%d@%p[%d], dma %llx\n", 591 dev_dbg(sh_chan->dev, "Add SG #%d@%p[%d], dma %llx\n",
593 i, sg, len, (unsigned long long)sg_addr); 592 i, sg, len, (unsigned long long)sg_addr);
594 593
595 if (direction == DMA_FROM_DEVICE) 594 if (direction == DMA_DEV_TO_MEM)
596 new = sh_dmae_add_desc(sh_chan, flags, 595 new = sh_dmae_add_desc(sh_chan, flags,
597 &sg_addr, addr, &len, &first, 596 &sg_addr, addr, &len, &first,
598 direction); 597 direction);
@@ -646,13 +645,13 @@ static struct dma_async_tx_descriptor *sh_dmae_prep_memcpy(
646 sg_dma_address(&sg) = dma_src; 645 sg_dma_address(&sg) = dma_src;
647 sg_dma_len(&sg) = len; 646 sg_dma_len(&sg) = len;
648 647
649 return sh_dmae_prep_sg(sh_chan, &sg, 1, &dma_dest, DMA_BIDIRECTIONAL, 648 return sh_dmae_prep_sg(sh_chan, &sg, 1, &dma_dest, DMA_MEM_TO_MEM,
650 flags); 649 flags);
651} 650}
652 651
653static struct dma_async_tx_descriptor *sh_dmae_prep_slave_sg( 652static struct dma_async_tx_descriptor *sh_dmae_prep_slave_sg(
654 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, 653 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
655 enum dma_data_direction direction, unsigned long flags) 654 enum dma_transfer_direction direction, unsigned long flags)
656{ 655{
657 struct sh_dmae_slave *param; 656 struct sh_dmae_slave *param;
658 struct sh_dmae_chan *sh_chan; 657 struct sh_dmae_chan *sh_chan;
@@ -996,7 +995,7 @@ static void dmae_do_tasklet(unsigned long data)
996 spin_lock_irq(&sh_chan->desc_lock); 995 spin_lock_irq(&sh_chan->desc_lock);
997 list_for_each_entry(desc, &sh_chan->ld_queue, node) { 996 list_for_each_entry(desc, &sh_chan->ld_queue, node) {
998 if (desc->mark == DESC_SUBMITTED && 997 if (desc->mark == DESC_SUBMITTED &&
999 ((desc->direction == DMA_FROM_DEVICE && 998 ((desc->direction == DMA_DEV_TO_MEM &&
1000 (desc->hw.dar + desc->hw.tcr) == dar_buf) || 999 (desc->hw.dar + desc->hw.tcr) == dar_buf) ||
1001 (desc->hw.sar + desc->hw.tcr) == sar_buf)) { 1000 (desc->hw.sar + desc->hw.tcr) == sar_buf)) {
1002 dev_dbg(sh_chan->dev, "done #%d@%p dst %u\n", 1001 dev_dbg(sh_chan->dev, "done #%d@%p dst %u\n",
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 13259cad0ceb..15b311d54b74 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -217,7 +217,7 @@ struct d40_chan {
217 struct d40_log_lli_full *lcpa; 217 struct d40_log_lli_full *lcpa;
218 /* Runtime reconfiguration */ 218 /* Runtime reconfiguration */
219 dma_addr_t runtime_addr; 219 dma_addr_t runtime_addr;
220 enum dma_data_direction runtime_direction; 220 enum dma_transfer_direction runtime_direction;
221}; 221};
222 222
223/** 223/**
@@ -1855,7 +1855,7 @@ err:
1855} 1855}
1856 1856
1857static dma_addr_t 1857static dma_addr_t
1858d40_get_dev_addr(struct d40_chan *chan, enum dma_data_direction direction) 1858d40_get_dev_addr(struct d40_chan *chan, enum dma_transfer_direction direction)
1859{ 1859{
1860 struct stedma40_platform_data *plat = chan->base->plat_data; 1860 struct stedma40_platform_data *plat = chan->base->plat_data;
1861 struct stedma40_chan_cfg *cfg = &chan->dma_cfg; 1861 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
@@ -1864,9 +1864,9 @@ d40_get_dev_addr(struct d40_chan *chan, enum dma_data_direction direction)
1864 if (chan->runtime_addr) 1864 if (chan->runtime_addr)
1865 return chan->runtime_addr; 1865 return chan->runtime_addr;
1866 1866
1867 if (direction == DMA_FROM_DEVICE) 1867 if (direction == DMA_DEV_TO_MEM)
1868 addr = plat->dev_rx[cfg->src_dev_type]; 1868 addr = plat->dev_rx[cfg->src_dev_type];
1869 else if (direction == DMA_TO_DEVICE) 1869 else if (direction == DMA_MEM_TO_DEV)
1870 addr = plat->dev_tx[cfg->dst_dev_type]; 1870 addr = plat->dev_tx[cfg->dst_dev_type];
1871 1871
1872 return addr; 1872 return addr;
@@ -1875,7 +1875,7 @@ d40_get_dev_addr(struct d40_chan *chan, enum dma_data_direction direction)
1875static struct dma_async_tx_descriptor * 1875static struct dma_async_tx_descriptor *
1876d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src, 1876d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
1877 struct scatterlist *sg_dst, unsigned int sg_len, 1877 struct scatterlist *sg_dst, unsigned int sg_len,
1878 enum dma_data_direction direction, unsigned long dma_flags) 1878 enum dma_transfer_direction direction, unsigned long dma_flags)
1879{ 1879{
1880 struct d40_chan *chan = container_of(dchan, struct d40_chan, chan); 1880 struct d40_chan *chan = container_of(dchan, struct d40_chan, chan);
1881 dma_addr_t src_dev_addr = 0; 1881 dma_addr_t src_dev_addr = 0;
@@ -1902,9 +1902,9 @@ d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
1902 if (direction != DMA_NONE) { 1902 if (direction != DMA_NONE) {
1903 dma_addr_t dev_addr = d40_get_dev_addr(chan, direction); 1903 dma_addr_t dev_addr = d40_get_dev_addr(chan, direction);
1904 1904
1905 if (direction == DMA_FROM_DEVICE) 1905 if (direction == DMA_DEV_TO_MEM)
1906 src_dev_addr = dev_addr; 1906 src_dev_addr = dev_addr;
1907 else if (direction == DMA_TO_DEVICE) 1907 else if (direction == DMA_MEM_TO_DEV)
1908 dst_dev_addr = dev_addr; 1908 dst_dev_addr = dev_addr;
1909 } 1909 }
1910 1910
@@ -2108,10 +2108,10 @@ d40_prep_memcpy_sg(struct dma_chan *chan,
2108static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan, 2108static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan,
2109 struct scatterlist *sgl, 2109 struct scatterlist *sgl,
2110 unsigned int sg_len, 2110 unsigned int sg_len,
2111 enum dma_data_direction direction, 2111 enum dma_transfer_direction direction,
2112 unsigned long dma_flags) 2112 unsigned long dma_flags)
2113{ 2113{
2114 if (direction != DMA_FROM_DEVICE && direction != DMA_TO_DEVICE) 2114 if (direction != DMA_DEV_TO_MEM && direction != DMA_MEM_TO_DEV)
2115 return NULL; 2115 return NULL;
2116 2116
2117 return d40_prep_sg(chan, sgl, sgl, sg_len, direction, dma_flags); 2117 return d40_prep_sg(chan, sgl, sgl, sg_len, direction, dma_flags);
@@ -2120,7 +2120,7 @@ static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan,
2120static struct dma_async_tx_descriptor * 2120static struct dma_async_tx_descriptor *
2121dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr, 2121dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,
2122 size_t buf_len, size_t period_len, 2122 size_t buf_len, size_t period_len,
2123 enum dma_data_direction direction) 2123 enum dma_transfer_direction direction)
2124{ 2124{
2125 unsigned int periods = buf_len / period_len; 2125 unsigned int periods = buf_len / period_len;
2126 struct dma_async_tx_descriptor *txd; 2126 struct dma_async_tx_descriptor *txd;
@@ -2269,7 +2269,7 @@ static int d40_set_runtime_config(struct dma_chan *chan,
2269 dst_addr_width = config->dst_addr_width; 2269 dst_addr_width = config->dst_addr_width;
2270 dst_maxburst = config->dst_maxburst; 2270 dst_maxburst = config->dst_maxburst;
2271 2271
2272 if (config->direction == DMA_FROM_DEVICE) { 2272 if (config->direction == DMA_DEV_TO_MEM) {
2273 dma_addr_t dev_addr_rx = 2273 dma_addr_t dev_addr_rx =
2274 d40c->base->plat_data->dev_rx[cfg->src_dev_type]; 2274 d40c->base->plat_data->dev_rx[cfg->src_dev_type];
2275 2275
@@ -2292,7 +2292,7 @@ static int d40_set_runtime_config(struct dma_chan *chan,
2292 if (dst_maxburst == 0) 2292 if (dst_maxburst == 0)
2293 dst_maxburst = src_maxburst; 2293 dst_maxburst = src_maxburst;
2294 2294
2295 } else if (config->direction == DMA_TO_DEVICE) { 2295 } else if (config->direction == DMA_MEM_TO_DEV) {
2296 dma_addr_t dev_addr_tx = 2296 dma_addr_t dev_addr_tx =
2297 d40c->base->plat_data->dev_tx[cfg->dst_dev_type]; 2297 d40c->base->plat_data->dev_tx[cfg->dst_dev_type];
2298 2298
@@ -2357,7 +2357,7 @@ static int d40_set_runtime_config(struct dma_chan *chan,
2357 "configured channel %s for %s, data width %d/%d, " 2357 "configured channel %s for %s, data width %d/%d, "
2358 "maxburst %d/%d elements, LE, no flow control\n", 2358 "maxburst %d/%d elements, LE, no flow control\n",
2359 dma_chan_name(chan), 2359 dma_chan_name(chan),
2360 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX", 2360 (config->direction == DMA_DEV_TO_MEM) ? "RX" : "TX",
2361 src_addr_width, dst_addr_width, 2361 src_addr_width, dst_addr_width,
2362 src_maxburst, dst_maxburst); 2362 src_maxburst, dst_maxburst);
2363 2363
diff --git a/drivers/dma/timb_dma.c b/drivers/dma/timb_dma.c
index a4a398f2ef61..8c880729b094 100644
--- a/drivers/dma/timb_dma.c
+++ b/drivers/dma/timb_dma.c
@@ -90,7 +90,7 @@ struct timb_dma_chan {
90 struct list_head queue; 90 struct list_head queue;
91 struct list_head free_list; 91 struct list_head free_list;
92 unsigned int bytes_per_line; 92 unsigned int bytes_per_line;
93 enum dma_data_direction direction; 93 enum dma_transfer_direction direction;
94 unsigned int descs; /* Descriptors to allocate */ 94 unsigned int descs; /* Descriptors to allocate */
95 unsigned int desc_elems; /* number of elems per descriptor */ 95 unsigned int desc_elems; /* number of elems per descriptor */
96}; 96};
@@ -235,7 +235,7 @@ static void __td_start_dma(struct timb_dma_chan *td_chan)
235 "td_chan: %p, chan: %d, membase: %p\n", 235 "td_chan: %p, chan: %d, membase: %p\n",
236 td_chan, td_chan->chan.chan_id, td_chan->membase); 236 td_chan, td_chan->chan.chan_id, td_chan->membase);
237 237
238 if (td_chan->direction == DMA_FROM_DEVICE) { 238 if (td_chan->direction == DMA_DEV_TO_MEM) {
239 239
240 /* descriptor address */ 240 /* descriptor address */
241 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_RX_DHAR); 241 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_RX_DHAR);
@@ -278,7 +278,7 @@ static void __td_finish(struct timb_dma_chan *td_chan)
278 txd->cookie); 278 txd->cookie);
279 279
280 /* make sure to stop the transfer */ 280 /* make sure to stop the transfer */
281 if (td_chan->direction == DMA_FROM_DEVICE) 281 if (td_chan->direction == DMA_DEV_TO_MEM)
282 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_RX_ER); 282 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_RX_ER);
283/* Currently no support for stopping DMA transfers 283/* Currently no support for stopping DMA transfers
284 else 284 else
@@ -398,7 +398,7 @@ static struct timb_dma_desc *td_alloc_init_desc(struct timb_dma_chan *td_chan)
398 td_desc->txd.flags = DMA_CTRL_ACK; 398 td_desc->txd.flags = DMA_CTRL_ACK;
399 399
400 td_desc->txd.phys = dma_map_single(chan2dmadev(chan), 400 td_desc->txd.phys = dma_map_single(chan2dmadev(chan),
401 td_desc->desc_list, td_desc->desc_list_len, DMA_TO_DEVICE); 401 td_desc->desc_list, td_desc->desc_list_len, DMA_MEM_TO_DEV);
402 402
403 err = dma_mapping_error(chan2dmadev(chan), td_desc->txd.phys); 403 err = dma_mapping_error(chan2dmadev(chan), td_desc->txd.phys);
404 if (err) { 404 if (err) {
@@ -419,7 +419,7 @@ static void td_free_desc(struct timb_dma_desc *td_desc)
419{ 419{
420 dev_dbg(chan2dev(td_desc->txd.chan), "Freeing desc: %p\n", td_desc); 420 dev_dbg(chan2dev(td_desc->txd.chan), "Freeing desc: %p\n", td_desc);
421 dma_unmap_single(chan2dmadev(td_desc->txd.chan), td_desc->txd.phys, 421 dma_unmap_single(chan2dmadev(td_desc->txd.chan), td_desc->txd.phys,
422 td_desc->desc_list_len, DMA_TO_DEVICE); 422 td_desc->desc_list_len, DMA_MEM_TO_DEV);
423 423
424 kfree(td_desc->desc_list); 424 kfree(td_desc->desc_list);
425 kfree(td_desc); 425 kfree(td_desc);
@@ -558,7 +558,7 @@ static void td_issue_pending(struct dma_chan *chan)
558 558
559static struct dma_async_tx_descriptor *td_prep_slave_sg(struct dma_chan *chan, 559static struct dma_async_tx_descriptor *td_prep_slave_sg(struct dma_chan *chan,
560 struct scatterlist *sgl, unsigned int sg_len, 560 struct scatterlist *sgl, unsigned int sg_len,
561 enum dma_data_direction direction, unsigned long flags) 561 enum dma_transfer_direction direction, unsigned long flags)
562{ 562{
563 struct timb_dma_chan *td_chan = 563 struct timb_dma_chan *td_chan =
564 container_of(chan, struct timb_dma_chan, chan); 564 container_of(chan, struct timb_dma_chan, chan);
@@ -606,7 +606,7 @@ static struct dma_async_tx_descriptor *td_prep_slave_sg(struct dma_chan *chan,
606 } 606 }
607 607
608 dma_sync_single_for_device(chan2dmadev(chan), td_desc->txd.phys, 608 dma_sync_single_for_device(chan2dmadev(chan), td_desc->txd.phys,
609 td_desc->desc_list_len, DMA_TO_DEVICE); 609 td_desc->desc_list_len, DMA_MEM_TO_DEV);
610 610
611 return &td_desc->txd; 611 return &td_desc->txd;
612} 612}
@@ -775,8 +775,8 @@ static int __devinit td_probe(struct platform_device *pdev)
775 td_chan->descs = pchan->descriptors; 775 td_chan->descs = pchan->descriptors;
776 td_chan->desc_elems = pchan->descriptor_elements; 776 td_chan->desc_elems = pchan->descriptor_elements;
777 td_chan->bytes_per_line = pchan->bytes_per_line; 777 td_chan->bytes_per_line = pchan->bytes_per_line;
778 td_chan->direction = pchan->rx ? DMA_FROM_DEVICE : 778 td_chan->direction = pchan->rx ? DMA_DEV_TO_MEM :
779 DMA_TO_DEVICE; 779 DMA_MEM_TO_DEV;
780 780
781 td_chan->membase = td->membase + 781 td_chan->membase = td->membase +
782 (i / 2) * TIMBDMA_INSTANCE_OFFSET + 782 (i / 2) * TIMBDMA_INSTANCE_OFFSET +
diff --git a/drivers/dma/txx9dmac.c b/drivers/dma/txx9dmac.c
index cbd83e362b5e..6122c364cf11 100644
--- a/drivers/dma/txx9dmac.c
+++ b/drivers/dma/txx9dmac.c
@@ -845,7 +845,7 @@ txx9dmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
845 845
846static struct dma_async_tx_descriptor * 846static struct dma_async_tx_descriptor *
847txx9dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 847txx9dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
848 unsigned int sg_len, enum dma_data_direction direction, 848 unsigned int sg_len, enum dma_transfer_direction direction,
849 unsigned long flags) 849 unsigned long flags)
850{ 850{
851 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan); 851 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
@@ -860,9 +860,9 @@ txx9dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
860 860
861 BUG_ON(!ds || !ds->reg_width); 861 BUG_ON(!ds || !ds->reg_width);
862 if (ds->tx_reg) 862 if (ds->tx_reg)
863 BUG_ON(direction != DMA_TO_DEVICE); 863 BUG_ON(direction != DMA_MEM_TO_DEV);
864 else 864 else
865 BUG_ON(direction != DMA_FROM_DEVICE); 865 BUG_ON(direction != DMA_DEV_TO_MEM);
866 if (unlikely(!sg_len)) 866 if (unlikely(!sg_len))
867 return NULL; 867 return NULL;
868 868
@@ -882,7 +882,7 @@ txx9dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
882 mem = sg_dma_address(sg); 882 mem = sg_dma_address(sg);
883 883
884 if (__is_dmac64(ddev)) { 884 if (__is_dmac64(ddev)) {
885 if (direction == DMA_TO_DEVICE) { 885 if (direction == DMA_MEM_TO_DEV) {
886 desc->hwdesc.SAR = mem; 886 desc->hwdesc.SAR = mem;
887 desc->hwdesc.DAR = ds->tx_reg; 887 desc->hwdesc.DAR = ds->tx_reg;
888 } else { 888 } else {
@@ -891,7 +891,7 @@ txx9dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
891 } 891 }
892 desc->hwdesc.CNTR = sg_dma_len(sg); 892 desc->hwdesc.CNTR = sg_dma_len(sg);
893 } else { 893 } else {
894 if (direction == DMA_TO_DEVICE) { 894 if (direction == DMA_MEM_TO_DEV) {
895 desc->hwdesc32.SAR = mem; 895 desc->hwdesc32.SAR = mem;
896 desc->hwdesc32.DAR = ds->tx_reg; 896 desc->hwdesc32.DAR = ds->tx_reg;
897 } else { 897 } else {
@@ -900,7 +900,7 @@ txx9dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
900 } 900 }
901 desc->hwdesc32.CNTR = sg_dma_len(sg); 901 desc->hwdesc32.CNTR = sg_dma_len(sg);
902 } 902 }
903 if (direction == DMA_TO_DEVICE) { 903 if (direction == DMA_MEM_TO_DEV) {
904 sai = ds->reg_width; 904 sai = ds->reg_width;
905 dai = 0; 905 dai = 0;
906 } else { 906 } else {