diff options
author | Dong Aisheng <dong.aisheng@linaro.org> | 2012-05-04 08:12:15 -0400 |
---|---|---|
committer | Shawn Guo <shawn.guo@linaro.org> | 2012-05-12 01:32:17 -0400 |
commit | f5b7efccdb057a2cc8ee32c83d2f034e494a1f4a (patch) | |
tree | 72674434b2219f27dbf8101dce7b8adadc3339f9 /drivers/dma | |
parent | 6c4d4efb9d19017f0eef3893912f3dec513ef8e9 (diff) |
dma: mxs-dma: use global stmp_device functionality
This can get rid of the mach-dependency.
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Huang Shijie <b32955@freescale.com>
Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Wolfram Sang <w.sang@pengutronix.de>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'drivers/dma')
-rw-r--r-- | drivers/dma/Kconfig | 1 | ||||
-rw-r--r-- | drivers/dma/mxs-dma.c | 26 |
2 files changed, 14 insertions, 13 deletions
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index ef378b5b17e4..aadeb5be9dba 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig | |||
@@ -238,6 +238,7 @@ config IMX_DMA | |||
238 | config MXS_DMA | 238 | config MXS_DMA |
239 | bool "MXS DMA support" | 239 | bool "MXS DMA support" |
240 | depends on SOC_IMX23 || SOC_IMX28 | 240 | depends on SOC_IMX23 || SOC_IMX28 |
241 | select STMP_DEVICE | ||
241 | select DMA_ENGINE | 242 | select DMA_ENGINE |
242 | help | 243 | help |
243 | Support the MXS DMA engine. This engine including APBH-DMA | 244 | Support the MXS DMA engine. This engine including APBH-DMA |
diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c index 655d4ce6ed0d..bd278187fd81 100644 --- a/drivers/dma/mxs-dma.c +++ b/drivers/dma/mxs-dma.c | |||
@@ -23,10 +23,10 @@ | |||
23 | #include <linux/dmaengine.h> | 23 | #include <linux/dmaengine.h> |
24 | #include <linux/delay.h> | 24 | #include <linux/delay.h> |
25 | #include <linux/fsl/mxs-dma.h> | 25 | #include <linux/fsl/mxs-dma.h> |
26 | #include <linux/stmp_device.h> | ||
26 | 27 | ||
27 | #include <asm/irq.h> | 28 | #include <asm/irq.h> |
28 | #include <mach/mxs.h> | 29 | #include <mach/mxs.h> |
29 | #include <mach/common.h> | ||
30 | 30 | ||
31 | #include "dmaengine.h" | 31 | #include "dmaengine.h" |
32 | 32 | ||
@@ -138,10 +138,10 @@ static void mxs_dma_reset_chan(struct mxs_dma_chan *mxs_chan) | |||
138 | 138 | ||
139 | if (dma_is_apbh() && apbh_is_old()) | 139 | if (dma_is_apbh() && apbh_is_old()) |
140 | writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL), | 140 | writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL), |
141 | mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR); | 141 | mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); |
142 | else | 142 | else |
143 | writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL), | 143 | writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL), |
144 | mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR); | 144 | mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET); |
145 | } | 145 | } |
146 | 146 | ||
147 | static void mxs_dma_enable_chan(struct mxs_dma_chan *mxs_chan) | 147 | static void mxs_dma_enable_chan(struct mxs_dma_chan *mxs_chan) |
@@ -170,10 +170,10 @@ static void mxs_dma_pause_chan(struct mxs_dma_chan *mxs_chan) | |||
170 | /* freeze the channel */ | 170 | /* freeze the channel */ |
171 | if (dma_is_apbh() && apbh_is_old()) | 171 | if (dma_is_apbh() && apbh_is_old()) |
172 | writel(1 << chan_id, | 172 | writel(1 << chan_id, |
173 | mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR); | 173 | mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); |
174 | else | 174 | else |
175 | writel(1 << chan_id, | 175 | writel(1 << chan_id, |
176 | mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR); | 176 | mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET); |
177 | 177 | ||
178 | mxs_chan->status = DMA_PAUSED; | 178 | mxs_chan->status = DMA_PAUSED; |
179 | } | 179 | } |
@@ -186,10 +186,10 @@ static void mxs_dma_resume_chan(struct mxs_dma_chan *mxs_chan) | |||
186 | /* unfreeze the channel */ | 186 | /* unfreeze the channel */ |
187 | if (dma_is_apbh() && apbh_is_old()) | 187 | if (dma_is_apbh() && apbh_is_old()) |
188 | writel(1 << chan_id, | 188 | writel(1 << chan_id, |
189 | mxs_dma->base + HW_APBHX_CTRL0 + MXS_CLR_ADDR); | 189 | mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_CLR); |
190 | else | 190 | else |
191 | writel(1 << chan_id, | 191 | writel(1 << chan_id, |
192 | mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_CLR_ADDR); | 192 | mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_CLR); |
193 | 193 | ||
194 | mxs_chan->status = DMA_IN_PROGRESS; | 194 | mxs_chan->status = DMA_IN_PROGRESS; |
195 | } | 195 | } |
@@ -220,11 +220,11 @@ static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id) | |||
220 | /* completion status */ | 220 | /* completion status */ |
221 | stat1 = readl(mxs_dma->base + HW_APBHX_CTRL1); | 221 | stat1 = readl(mxs_dma->base + HW_APBHX_CTRL1); |
222 | stat1 &= MXS_DMA_CHANNELS_MASK; | 222 | stat1 &= MXS_DMA_CHANNELS_MASK; |
223 | writel(stat1, mxs_dma->base + HW_APBHX_CTRL1 + MXS_CLR_ADDR); | 223 | writel(stat1, mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_CLR); |
224 | 224 | ||
225 | /* error status */ | 225 | /* error status */ |
226 | stat2 = readl(mxs_dma->base + HW_APBHX_CTRL2); | 226 | stat2 = readl(mxs_dma->base + HW_APBHX_CTRL2); |
227 | writel(stat2, mxs_dma->base + HW_APBHX_CTRL2 + MXS_CLR_ADDR); | 227 | writel(stat2, mxs_dma->base + HW_APBHX_CTRL2 + STMP_OFFSET_REG_CLR); |
228 | 228 | ||
229 | /* | 229 | /* |
230 | * When both completion and error of termination bits set at the | 230 | * When both completion and error of termination bits set at the |
@@ -567,7 +567,7 @@ static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma) | |||
567 | if (ret) | 567 | if (ret) |
568 | return ret; | 568 | return ret; |
569 | 569 | ||
570 | ret = mxs_reset_block(mxs_dma->base); | 570 | ret = stmp_reset_block(mxs_dma->base); |
571 | if (ret) | 571 | if (ret) |
572 | goto err_out; | 572 | goto err_out; |
573 | 573 | ||
@@ -580,14 +580,14 @@ static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma) | |||
580 | /* enable apbh burst */ | 580 | /* enable apbh burst */ |
581 | if (dma_is_apbh()) { | 581 | if (dma_is_apbh()) { |
582 | writel(BM_APBH_CTRL0_APB_BURST_EN, | 582 | writel(BM_APBH_CTRL0_APB_BURST_EN, |
583 | mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR); | 583 | mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); |
584 | writel(BM_APBH_CTRL0_APB_BURST8_EN, | 584 | writel(BM_APBH_CTRL0_APB_BURST8_EN, |
585 | mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR); | 585 | mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); |
586 | } | 586 | } |
587 | 587 | ||
588 | /* enable irq for all the channels */ | 588 | /* enable irq for all the channels */ |
589 | writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS, | 589 | writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS, |
590 | mxs_dma->base + HW_APBHX_CTRL1 + MXS_SET_ADDR); | 590 | mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_SET); |
591 | 591 | ||
592 | err_out: | 592 | err_out: |
593 | clk_disable_unprepare(mxs_dma->clk); | 593 | clk_disable_unprepare(mxs_dma->clk); |