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authorTony Lindgren <tony@atomide.com>2012-11-09 17:58:01 -0500
committerTony Lindgren <tony@atomide.com>2012-11-09 17:58:01 -0500
commitedf8dde393f879fc2d8c22d4bc01ff8d37b80e1a (patch)
tree61425adc8b2059a9c12a3ce66ba7361fea1b0bb3 /drivers/dma
parent6ba54ab4a49bbad736b0254aa6bdf0cb83013815 (diff)
parent3d70f8c617a436c7146ecb81df2265b4626dfe89 (diff)
Merge branch 'linus' into omap-for-v3.8/cleanup-headers-prepare-multiplatform-v3
Diffstat (limited to 'drivers/dma')
-rw-r--r--drivers/dma/Kconfig11
-rw-r--r--drivers/dma/dw_dmac_regs.h18
-rw-r--r--drivers/dma/imx-dma.c4
-rw-r--r--drivers/dma/sirf-dma.c4
4 files changed, 29 insertions, 8 deletions
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 677cd6e4e1a1..d4c12180c654 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -90,6 +90,17 @@ config DW_DMAC
90 Support the Synopsys DesignWare AHB DMA controller. This 90 Support the Synopsys DesignWare AHB DMA controller. This
91 can be integrated in chips such as the Atmel AT32ap7000. 91 can be integrated in chips such as the Atmel AT32ap7000.
92 92
93config DW_DMAC_BIG_ENDIAN_IO
94 bool "Use big endian I/O register access"
95 default y if AVR32
96 depends on DW_DMAC
97 help
98 Say yes here to use big endian I/O access when reading and writing
99 to the DMA controller registers. This is needed on some platforms,
100 like the Atmel AVR32 architecture.
101
102 If unsure, use the default setting.
103
93config AT_HDMAC 104config AT_HDMAC
94 tristate "Atmel AHB DMA support" 105 tristate "Atmel AHB DMA support"
95 depends on ARCH_AT91 106 depends on ARCH_AT91
diff --git a/drivers/dma/dw_dmac_regs.h b/drivers/dma/dw_dmac_regs.h
index ff39fa6cd2bc..88965597b7d0 100644
--- a/drivers/dma/dw_dmac_regs.h
+++ b/drivers/dma/dw_dmac_regs.h
@@ -98,9 +98,17 @@ struct dw_dma_regs {
98 u32 DW_PARAMS; 98 u32 DW_PARAMS;
99}; 99};
100 100
101#ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO
102#define dma_readl_native ioread32be
103#define dma_writel_native iowrite32be
104#else
105#define dma_readl_native readl
106#define dma_writel_native writel
107#endif
108
101/* To access the registers in early stage of probe */ 109/* To access the registers in early stage of probe */
102#define dma_read_byaddr(addr, name) \ 110#define dma_read_byaddr(addr, name) \
103 readl((addr) + offsetof(struct dw_dma_regs, name)) 111 dma_readl_native((addr) + offsetof(struct dw_dma_regs, name))
104 112
105/* Bitfields in DW_PARAMS */ 113/* Bitfields in DW_PARAMS */
106#define DW_PARAMS_NR_CHAN 8 /* number of channels */ 114#define DW_PARAMS_NR_CHAN 8 /* number of channels */
@@ -216,9 +224,9 @@ __dwc_regs(struct dw_dma_chan *dwc)
216} 224}
217 225
218#define channel_readl(dwc, name) \ 226#define channel_readl(dwc, name) \
219 readl(&(__dwc_regs(dwc)->name)) 227 dma_readl_native(&(__dwc_regs(dwc)->name))
220#define channel_writel(dwc, name, val) \ 228#define channel_writel(dwc, name, val) \
221 writel((val), &(__dwc_regs(dwc)->name)) 229 dma_writel_native((val), &(__dwc_regs(dwc)->name))
222 230
223static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan) 231static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan)
224{ 232{
@@ -246,9 +254,9 @@ static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw)
246} 254}
247 255
248#define dma_readl(dw, name) \ 256#define dma_readl(dw, name) \
249 readl(&(__dw_regs(dw)->name)) 257 dma_readl_native(&(__dw_regs(dw)->name))
250#define dma_writel(dw, name, val) \ 258#define dma_writel(dw, name, val) \
251 writel((val), &(__dw_regs(dw)->name)) 259 dma_writel_native((val), &(__dw_regs(dw)->name))
252 260
253#define channel_set_bit(dw, reg, mask) \ 261#define channel_set_bit(dw, reg, mask) \
254 dma_writel(dw, reg, ((mask) << 8) | (mask)) 262 dma_writel(dw, reg, ((mask) << 8) | (mask))
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index f11b5b2b1a1c..7d9554cc4976 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -474,8 +474,10 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
474 slot = i; 474 slot = i;
475 break; 475 break;
476 } 476 }
477 if (slot < 0) 477 if (slot < 0) {
478 spin_unlock_irqrestore(&imxdma->lock, flags);
478 return -EBUSY; 479 return -EBUSY;
480 }
479 481
480 imxdma->slots_2d[slot].xsr = d->x; 482 imxdma->slots_2d[slot].xsr = d->x;
481 imxdma->slots_2d[slot].ysr = d->y; 483 imxdma->slots_2d[slot].ysr = d->y;
diff --git a/drivers/dma/sirf-dma.c b/drivers/dma/sirf-dma.c
index 64385cde044b..d451caace806 100644
--- a/drivers/dma/sirf-dma.c
+++ b/drivers/dma/sirf-dma.c
@@ -109,7 +109,7 @@ static void sirfsoc_dma_execute(struct sirfsoc_dma_chan *schan)
109 sdesc = list_first_entry(&schan->queued, struct sirfsoc_dma_desc, 109 sdesc = list_first_entry(&schan->queued, struct sirfsoc_dma_desc,
110 node); 110 node);
111 /* Move the first queued descriptor to active list */ 111 /* Move the first queued descriptor to active list */
112 list_move_tail(&schan->queued, &schan->active); 112 list_move_tail(&sdesc->node, &schan->active);
113 113
114 /* Start the DMA transfer */ 114 /* Start the DMA transfer */
115 writel_relaxed(sdesc->width, sdma->base + SIRFSOC_DMA_WIDTH_0 + 115 writel_relaxed(sdesc->width, sdma->base + SIRFSOC_DMA_WIDTH_0 +
@@ -428,7 +428,7 @@ static struct dma_async_tx_descriptor *sirfsoc_dma_prep_interleaved(
428 unsigned long iflags; 428 unsigned long iflags;
429 int ret; 429 int ret;
430 430
431 if ((xt->dir != DMA_MEM_TO_DEV) || (xt->dir != DMA_DEV_TO_MEM)) { 431 if ((xt->dir != DMA_MEM_TO_DEV) && (xt->dir != DMA_DEV_TO_MEM)) {
432 ret = -EINVAL; 432 ret = -EINVAL;
433 goto err_dir; 433 goto err_dir;
434 } 434 }