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authorAl Viro <viro@ftp.linux.org.uk>2008-03-28 23:10:18 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2008-03-30 17:20:24 -0400
commita4e6d5d3817ebae167e78e5957cd9e624be200c7 (patch)
tree5d69f988bc7bdb5d4c5f9c31210fc1d98848c76a /drivers/dma
parentf0bb3cfde03ae6d492447883f786c6ee9a4db2ca (diff)
fix the broken annotations in fsldma
a) every bitwise declaration will give a unique type; use typedefs. b) no need to bother with the stuff pointed to by iomem pointers, unless it's accessed directly. noderef will force us to use helpers anyway. Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/dma')
-rw-r--r--drivers/dma/fsldma.h47
1 files changed, 27 insertions, 20 deletions
diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h
index fddd6aee2a63..6faf07ba0d0e 100644
--- a/drivers/dma/fsldma.h
+++ b/drivers/dma/fsldma.h
@@ -75,12 +75,15 @@
75#define FSL_DMA_DGSR_EOSI 0x02 75#define FSL_DMA_DGSR_EOSI 0x02
76#define FSL_DMA_DGSR_EOLSI 0x01 76#define FSL_DMA_DGSR_EOLSI 0x01
77 77
78typedef u64 __bitwise v64;
79typedef u32 __bitwise v32;
80
78struct fsl_dma_ld_hw { 81struct fsl_dma_ld_hw {
79 u64 __bitwise src_addr; 82 v64 src_addr;
80 u64 __bitwise dst_addr; 83 v64 dst_addr;
81 u64 __bitwise next_ln_addr; 84 v64 next_ln_addr;
82 u32 __bitwise count; 85 v32 count;
83 u32 __bitwise reserve; 86 v32 reserve;
84} __attribute__((aligned(32))); 87} __attribute__((aligned(32)));
85 88
86struct fsl_desc_sw { 89struct fsl_desc_sw {
@@ -92,13 +95,13 @@ struct fsl_desc_sw {
92} __attribute__((aligned(32))); 95} __attribute__((aligned(32)));
93 96
94struct fsl_dma_chan_regs { 97struct fsl_dma_chan_regs {
95 u32 __bitwise mr; /* 0x00 - Mode Register */ 98 u32 mr; /* 0x00 - Mode Register */
96 u32 __bitwise sr; /* 0x04 - Status Register */ 99 u32 sr; /* 0x04 - Status Register */
97 u64 __bitwise cdar; /* 0x08 - Current descriptor address register */ 100 u64 cdar; /* 0x08 - Current descriptor address register */
98 u64 __bitwise sar; /* 0x10 - Source Address Register */ 101 u64 sar; /* 0x10 - Source Address Register */
99 u64 __bitwise dar; /* 0x18 - Destination Address Register */ 102 u64 dar; /* 0x18 - Destination Address Register */
100 u32 __bitwise bcr; /* 0x20 - Byte Count Register */ 103 u32 bcr; /* 0x20 - Byte Count Register */
101 u64 __bitwise ndar; /* 0x24 - Next Descriptor Address Register */ 104 u64 ndar; /* 0x24 - Next Descriptor Address Register */
102}; 105};
103 106
104struct fsl_dma_chan; 107struct fsl_dma_chan;
@@ -151,25 +154,27 @@ struct fsl_dma_chan {
151#ifndef __powerpc64__ 154#ifndef __powerpc64__
152static u64 in_be64(const u64 __iomem *addr) 155static u64 in_be64(const u64 __iomem *addr)
153{ 156{
154 return ((u64)in_be32((u32 *)addr) << 32) | (in_be32((u32 *)addr + 1)); 157 return ((u64)in_be32((u32 __iomem *)addr) << 32) |
158 (in_be32((u32 __iomem *)addr + 1));
155} 159}
156 160
157static void out_be64(u64 __iomem *addr, u64 val) 161static void out_be64(u64 __iomem *addr, u64 val)
158{ 162{
159 out_be32((u32 *)addr, val >> 32); 163 out_be32((u32 __iomem *)addr, val >> 32);
160 out_be32((u32 *)addr + 1, (u32)val); 164 out_be32((u32 __iomem *)addr + 1, (u32)val);
161} 165}
162 166
163/* There is no asm instructions for 64 bits reverse loads and stores */ 167/* There is no asm instructions for 64 bits reverse loads and stores */
164static u64 in_le64(const u64 __iomem *addr) 168static u64 in_le64(const u64 __iomem *addr)
165{ 169{
166 return ((u64)in_le32((u32 *)addr + 1) << 32) | (in_le32((u32 *)addr)); 170 return ((u64)in_le32((u32 __iomem *)addr + 1) << 32) |
171 (in_le32((u32 __iomem *)addr));
167} 172}
168 173
169static void out_le64(u64 __iomem *addr, u64 val) 174static void out_le64(u64 __iomem *addr, u64 val)
170{ 175{
171 out_le32((u32 *)addr + 1, val >> 32); 176 out_le32((u32 __iomem *)addr + 1, val >> 32);
172 out_le32((u32 *)addr, (u32)val); 177 out_le32((u32 __iomem *)addr, (u32)val);
173} 178}
174#endif 179#endif
175 180
@@ -182,9 +187,11 @@ static void out_le64(u64 __iomem *addr, u64 val)
182 187
183#define DMA_TO_CPU(fsl_chan, d, width) \ 188#define DMA_TO_CPU(fsl_chan, d, width) \
184 (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \ 189 (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
185 be##width##_to_cpu(d) : le##width##_to_cpu(d)) 190 be##width##_to_cpu((__force __be##width)(v##width)d) : \
191 le##width##_to_cpu((__force __le##width)(v##width)d))
186#define CPU_TO_DMA(fsl_chan, c, width) \ 192#define CPU_TO_DMA(fsl_chan, c, width) \
187 (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \ 193 (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
188 cpu_to_be##width(c) : cpu_to_le##width(c)) 194 (__force v##width)cpu_to_be##width(c) : \
195 (__force v##width)cpu_to_le##width(c))
189 196
190#endif /* __DMA_FSLDMA_H */ 197#endif /* __DMA_FSLDMA_H */