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authorLinus Walleij <linus.walleij@linaro.org>2013-01-04 07:42:35 -0500
committerLinus Walleij <linus.walleij@linaro.org>2013-01-07 11:36:20 -0500
commit250eac8027c90b881408c40eeeb7b9cb8249304e (patch)
tree851878e390137222681564554282bb3cf3baa605 /drivers/dma
parent24dbcd8a0376856c31f03501e9eada577d5ad648 (diff)
dma: coh901318: remove hardcoded target addresses
Nowadays the clients should use the dmaengine framework to tell the DMA driver what target address to use, so delete these addresses, they are for an out-of-tree driver anyway. Acked-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/dma')
-rw-r--r--drivers/dma/coh901318.c19
1 files changed, 0 insertions, 19 deletions
diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c
index 06d97955c544..15e314af22f7 100644
--- a/drivers/dma/coh901318.c
+++ b/drivers/dma/coh901318.c
@@ -23,7 +23,6 @@
23#include <linux/debugfs.h> 23#include <linux/debugfs.h>
24#include <linux/platform_data/dma-coh901318.h> 24#include <linux/platform_data/dma-coh901318.h>
25#include <mach/coh901318.h> 25#include <mach/coh901318.h>
26#include <mach/u300-regs.h>
27 26
28#include "coh901318_lli.h" 27#include "coh901318_lli.h"
29#include "dmaengine.h" 28#include "dmaengine.h"
@@ -99,13 +98,11 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
99 .number = U300_DMA_MSL_TX_0, 98 .number = U300_DMA_MSL_TX_0,
100 .name = "MSL TX 0", 99 .name = "MSL TX 0",
101 .priority_high = 0, 100 .priority_high = 0,
102 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20,
103 }, 101 },
104 { 102 {
105 .number = U300_DMA_MSL_TX_1, 103 .number = U300_DMA_MSL_TX_1,
106 .name = "MSL TX 1", 104 .name = "MSL TX 1",
107 .priority_high = 0, 105 .priority_high = 0,
108 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20,
109 .param.config = COH901318_CX_CFG_CH_DISABLE | 106 .param.config = COH901318_CX_CFG_CH_DISABLE |
110 COH901318_CX_CFG_LCR_DISABLE | 107 COH901318_CX_CFG_LCR_DISABLE |
111 COH901318_CX_CFG_TC_IRQ_ENABLE | 108 COH901318_CX_CFG_TC_IRQ_ENABLE |
@@ -157,7 +154,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
157 .number = U300_DMA_MSL_TX_2, 154 .number = U300_DMA_MSL_TX_2,
158 .name = "MSL TX 2", 155 .name = "MSL TX 2",
159 .priority_high = 0, 156 .priority_high = 0,
160 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20,
161 .param.config = COH901318_CX_CFG_CH_DISABLE | 157 .param.config = COH901318_CX_CFG_CH_DISABLE |
162 COH901318_CX_CFG_LCR_DISABLE | 158 COH901318_CX_CFG_LCR_DISABLE |
163 COH901318_CX_CFG_TC_IRQ_ENABLE | 159 COH901318_CX_CFG_TC_IRQ_ENABLE |
@@ -210,7 +206,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
210 .number = U300_DMA_MSL_TX_3, 206 .number = U300_DMA_MSL_TX_3,
211 .name = "MSL TX 3", 207 .name = "MSL TX 3",
212 .priority_high = 0, 208 .priority_high = 0,
213 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20,
214 .param.config = COH901318_CX_CFG_CH_DISABLE | 209 .param.config = COH901318_CX_CFG_CH_DISABLE |
215 COH901318_CX_CFG_LCR_DISABLE | 210 COH901318_CX_CFG_LCR_DISABLE |
216 COH901318_CX_CFG_TC_IRQ_ENABLE | 211 COH901318_CX_CFG_TC_IRQ_ENABLE |
@@ -262,7 +257,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
262 .number = U300_DMA_MSL_TX_4, 257 .number = U300_DMA_MSL_TX_4,
263 .name = "MSL TX 4", 258 .name = "MSL TX 4",
264 .priority_high = 0, 259 .priority_high = 0,
265 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20,
266 .param.config = COH901318_CX_CFG_CH_DISABLE | 260 .param.config = COH901318_CX_CFG_CH_DISABLE |
267 COH901318_CX_CFG_LCR_DISABLE | 261 COH901318_CX_CFG_LCR_DISABLE |
268 COH901318_CX_CFG_TC_IRQ_ENABLE | 262 COH901318_CX_CFG_TC_IRQ_ENABLE |
@@ -314,25 +308,21 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
314 .number = U300_DMA_MSL_TX_5, 308 .number = U300_DMA_MSL_TX_5,
315 .name = "MSL TX 5", 309 .name = "MSL TX 5",
316 .priority_high = 0, 310 .priority_high = 0,
317 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20,
318 }, 311 },
319 { 312 {
320 .number = U300_DMA_MSL_TX_6, 313 .number = U300_DMA_MSL_TX_6,
321 .name = "MSL TX 6", 314 .name = "MSL TX 6",
322 .priority_high = 0, 315 .priority_high = 0,
323 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20,
324 }, 316 },
325 { 317 {
326 .number = U300_DMA_MSL_RX_0, 318 .number = U300_DMA_MSL_RX_0,
327 .name = "MSL RX 0", 319 .name = "MSL RX 0",
328 .priority_high = 0, 320 .priority_high = 0,
329 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220,
330 }, 321 },
331 { 322 {
332 .number = U300_DMA_MSL_RX_1, 323 .number = U300_DMA_MSL_RX_1,
333 .name = "MSL RX 1", 324 .name = "MSL RX 1",
334 .priority_high = 0, 325 .priority_high = 0,
335 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220,
336 .param.config = COH901318_CX_CFG_CH_DISABLE | 326 .param.config = COH901318_CX_CFG_CH_DISABLE |
337 COH901318_CX_CFG_LCR_DISABLE | 327 COH901318_CX_CFG_LCR_DISABLE |
338 COH901318_CX_CFG_TC_IRQ_ENABLE | 328 COH901318_CX_CFG_TC_IRQ_ENABLE |
@@ -371,7 +361,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
371 .number = U300_DMA_MSL_RX_2, 361 .number = U300_DMA_MSL_RX_2,
372 .name = "MSL RX 2", 362 .name = "MSL RX 2",
373 .priority_high = 0, 363 .priority_high = 0,
374 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220,
375 .param.config = COH901318_CX_CFG_CH_DISABLE | 364 .param.config = COH901318_CX_CFG_CH_DISABLE |
376 COH901318_CX_CFG_LCR_DISABLE | 365 COH901318_CX_CFG_LCR_DISABLE |
377 COH901318_CX_CFG_TC_IRQ_ENABLE | 366 COH901318_CX_CFG_TC_IRQ_ENABLE |
@@ -423,7 +412,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
423 .number = U300_DMA_MSL_RX_3, 412 .number = U300_DMA_MSL_RX_3,
424 .name = "MSL RX 3", 413 .name = "MSL RX 3",
425 .priority_high = 0, 414 .priority_high = 0,
426 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220,
427 .param.config = COH901318_CX_CFG_CH_DISABLE | 415 .param.config = COH901318_CX_CFG_CH_DISABLE |
428 COH901318_CX_CFG_LCR_DISABLE | 416 COH901318_CX_CFG_LCR_DISABLE |
429 COH901318_CX_CFG_TC_IRQ_ENABLE | 417 COH901318_CX_CFG_TC_IRQ_ENABLE |
@@ -475,7 +463,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
475 .number = U300_DMA_MSL_RX_4, 463 .number = U300_DMA_MSL_RX_4,
476 .name = "MSL RX 4", 464 .name = "MSL RX 4",
477 .priority_high = 0, 465 .priority_high = 0,
478 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220,
479 .param.config = COH901318_CX_CFG_CH_DISABLE | 466 .param.config = COH901318_CX_CFG_CH_DISABLE |
480 COH901318_CX_CFG_LCR_DISABLE | 467 COH901318_CX_CFG_LCR_DISABLE |
481 COH901318_CX_CFG_TC_IRQ_ENABLE | 468 COH901318_CX_CFG_TC_IRQ_ENABLE |
@@ -527,7 +514,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
527 .number = U300_DMA_MSL_RX_5, 514 .number = U300_DMA_MSL_RX_5,
528 .name = "MSL RX 5", 515 .name = "MSL RX 5",
529 .priority_high = 0, 516 .priority_high = 0,
530 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220,
531 .param.config = COH901318_CX_CFG_CH_DISABLE | 517 .param.config = COH901318_CX_CFG_CH_DISABLE |
532 COH901318_CX_CFG_LCR_DISABLE | 518 COH901318_CX_CFG_LCR_DISABLE |
533 COH901318_CX_CFG_TC_IRQ_ENABLE | 519 COH901318_CX_CFG_TC_IRQ_ENABLE |
@@ -579,7 +565,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
579 .number = U300_DMA_MSL_RX_6, 565 .number = U300_DMA_MSL_RX_6,
580 .name = "MSL RX 6", 566 .name = "MSL RX 6",
581 .priority_high = 0, 567 .priority_high = 0,
582 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
583 }, 568 },
584 /* 569 /*
585 * Don't set up device address, burst count or size of src 570 * Don't set up device address, burst count or size of src
@@ -715,7 +700,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
715 .number = U300_DMA_PCM_I2S0_TX, 700 .number = U300_DMA_PCM_I2S0_TX,
716 .name = "PCM I2S0 TX", 701 .name = "PCM I2S0 TX",
717 .priority_high = 1, 702 .priority_high = 1,
718 .dev_addr = U300_PCM_I2S0_BASE + 0x14,
719 .param.config = COH901318_CX_CFG_CH_DISABLE | 703 .param.config = COH901318_CX_CFG_CH_DISABLE |
720 COH901318_CX_CFG_LCR_DISABLE | 704 COH901318_CX_CFG_LCR_DISABLE |
721 COH901318_CX_CFG_TC_IRQ_ENABLE | 705 COH901318_CX_CFG_TC_IRQ_ENABLE |
@@ -767,7 +751,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
767 .number = U300_DMA_PCM_I2S0_RX, 751 .number = U300_DMA_PCM_I2S0_RX,
768 .name = "PCM I2S0 RX", 752 .name = "PCM I2S0 RX",
769 .priority_high = 1, 753 .priority_high = 1,
770 .dev_addr = U300_PCM_I2S0_BASE + 0x10,
771 .param.config = COH901318_CX_CFG_CH_DISABLE | 754 .param.config = COH901318_CX_CFG_CH_DISABLE |
772 COH901318_CX_CFG_LCR_DISABLE | 755 COH901318_CX_CFG_LCR_DISABLE |
773 COH901318_CX_CFG_TC_IRQ_ENABLE | 756 COH901318_CX_CFG_TC_IRQ_ENABLE |
@@ -819,7 +802,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
819 .number = U300_DMA_PCM_I2S1_TX, 802 .number = U300_DMA_PCM_I2S1_TX,
820 .name = "PCM I2S1 TX", 803 .name = "PCM I2S1 TX",
821 .priority_high = 1, 804 .priority_high = 1,
822 .dev_addr = U300_PCM_I2S1_BASE + 0x14,
823 .param.config = COH901318_CX_CFG_CH_DISABLE | 805 .param.config = COH901318_CX_CFG_CH_DISABLE |
824 COH901318_CX_CFG_LCR_DISABLE | 806 COH901318_CX_CFG_LCR_DISABLE |
825 COH901318_CX_CFG_TC_IRQ_ENABLE | 807 COH901318_CX_CFG_TC_IRQ_ENABLE |
@@ -871,7 +853,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
871 .number = U300_DMA_PCM_I2S1_RX, 853 .number = U300_DMA_PCM_I2S1_RX,
872 .name = "PCM I2S1 RX", 854 .name = "PCM I2S1 RX",
873 .priority_high = 1, 855 .priority_high = 1,
874 .dev_addr = U300_PCM_I2S1_BASE + 0x10,
875 .param.config = COH901318_CX_CFG_CH_DISABLE | 856 .param.config = COH901318_CX_CFG_CH_DISABLE |
876 COH901318_CX_CFG_LCR_DISABLE | 857 COH901318_CX_CFG_LCR_DISABLE |
877 COH901318_CX_CFG_TC_IRQ_ENABLE | 858 COH901318_CX_CFG_TC_IRQ_ENABLE |