diff options
author | Dan Williams <dan.j.williams@intel.com> | 2011-02-14 06:36:51 -0500 |
---|---|---|
committer | Dan Williams <dan.j.williams@intel.com> | 2011-02-14 06:36:51 -0500 |
commit | 0670e7157f75ec6d2231fbc6f67b075d6b6d486f (patch) | |
tree | 64591858de42da54afc979338ee083d1e6d672a0 /drivers/dma | |
parent | 80cc07af0f6692a7d8fdc5087594d1988a701266 (diff) | |
parent | 4aa5f366431fef0afca0df348ca9782c63ac9911 (diff) |
Merge branch 'dw_dmac' into dmaengine
Diffstat (limited to 'drivers/dma')
-rw-r--r-- | drivers/dma/dw_dmac.c | 36 |
1 files changed, 22 insertions, 14 deletions
diff --git a/drivers/dma/dw_dmac.c b/drivers/dma/dw_dmac.c index a3991ab0d67e..08dab3badad2 100644 --- a/drivers/dma/dw_dmac.c +++ b/drivers/dma/dw_dmac.c | |||
@@ -32,15 +32,18 @@ | |||
32 | * which does not support descriptor writeback. | 32 | * which does not support descriptor writeback. |
33 | */ | 33 | */ |
34 | 34 | ||
35 | /* NOTE: DMS+SMS is system-specific. We should get this information | 35 | #define DWC_DEFAULT_CTLLO(private) ({ \ |
36 | * from the platform code somehow. | 36 | struct dw_dma_slave *__slave = (private); \ |
37 | */ | 37 | int dms = __slave ? __slave->dst_master : 0; \ |
38 | #define DWC_DEFAULT_CTLLO (DWC_CTLL_DST_MSIZE(0) \ | 38 | int sms = __slave ? __slave->src_master : 1; \ |
39 | | DWC_CTLL_SRC_MSIZE(0) \ | 39 | \ |
40 | | DWC_CTLL_DMS(0) \ | 40 | (DWC_CTLL_DST_MSIZE(0) \ |
41 | | DWC_CTLL_SMS(1) \ | 41 | | DWC_CTLL_SRC_MSIZE(0) \ |
42 | | DWC_CTLL_LLP_D_EN \ | 42 | | DWC_CTLL_LLP_D_EN \ |
43 | | DWC_CTLL_LLP_S_EN) | 43 | | DWC_CTLL_LLP_S_EN \ |
44 | | DWC_CTLL_DMS(dms) \ | ||
45 | | DWC_CTLL_SMS(sms)); \ | ||
46 | }) | ||
44 | 47 | ||
45 | /* | 48 | /* |
46 | * This is configuration-dependent and usually a funny size like 4095. | 49 | * This is configuration-dependent and usually a funny size like 4095. |
@@ -291,6 +294,9 @@ static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) | |||
291 | return; | 294 | return; |
292 | } | 295 | } |
293 | 296 | ||
297 | if (list_empty(&dwc->active_list)) | ||
298 | return; | ||
299 | |||
294 | dev_vdbg(chan2dev(&dwc->chan), "scan_descriptors: llp=0x%x\n", llp); | 300 | dev_vdbg(chan2dev(&dwc->chan), "scan_descriptors: llp=0x%x\n", llp); |
295 | 301 | ||
296 | list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { | 302 | list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { |
@@ -588,7 +594,7 @@ dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |||
588 | else | 594 | else |
589 | src_width = dst_width = 0; | 595 | src_width = dst_width = 0; |
590 | 596 | ||
591 | ctllo = DWC_DEFAULT_CTLLO | 597 | ctllo = DWC_DEFAULT_CTLLO(chan->private) |
592 | | DWC_CTLL_DST_WIDTH(dst_width) | 598 | | DWC_CTLL_DST_WIDTH(dst_width) |
593 | | DWC_CTLL_SRC_WIDTH(src_width) | 599 | | DWC_CTLL_SRC_WIDTH(src_width) |
594 | | DWC_CTLL_DST_INC | 600 | | DWC_CTLL_DST_INC |
@@ -669,7 +675,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |||
669 | 675 | ||
670 | switch (direction) { | 676 | switch (direction) { |
671 | case DMA_TO_DEVICE: | 677 | case DMA_TO_DEVICE: |
672 | ctllo = (DWC_DEFAULT_CTLLO | 678 | ctllo = (DWC_DEFAULT_CTLLO(chan->private) |
673 | | DWC_CTLL_DST_WIDTH(reg_width) | 679 | | DWC_CTLL_DST_WIDTH(reg_width) |
674 | | DWC_CTLL_DST_FIX | 680 | | DWC_CTLL_DST_FIX |
675 | | DWC_CTLL_SRC_INC | 681 | | DWC_CTLL_SRC_INC |
@@ -714,7 +720,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |||
714 | } | 720 | } |
715 | break; | 721 | break; |
716 | case DMA_FROM_DEVICE: | 722 | case DMA_FROM_DEVICE: |
717 | ctllo = (DWC_DEFAULT_CTLLO | 723 | ctllo = (DWC_DEFAULT_CTLLO(chan->private) |
718 | | DWC_CTLL_SRC_WIDTH(reg_width) | 724 | | DWC_CTLL_SRC_WIDTH(reg_width) |
719 | | DWC_CTLL_DST_INC | 725 | | DWC_CTLL_DST_INC |
720 | | DWC_CTLL_SRC_FIX | 726 | | DWC_CTLL_SRC_FIX |
@@ -1126,7 +1132,7 @@ struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, | |||
1126 | case DMA_TO_DEVICE: | 1132 | case DMA_TO_DEVICE: |
1127 | desc->lli.dar = dws->tx_reg; | 1133 | desc->lli.dar = dws->tx_reg; |
1128 | desc->lli.sar = buf_addr + (period_len * i); | 1134 | desc->lli.sar = buf_addr + (period_len * i); |
1129 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO | 1135 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan->private) |
1130 | | DWC_CTLL_DST_WIDTH(reg_width) | 1136 | | DWC_CTLL_DST_WIDTH(reg_width) |
1131 | | DWC_CTLL_SRC_WIDTH(reg_width) | 1137 | | DWC_CTLL_SRC_WIDTH(reg_width) |
1132 | | DWC_CTLL_DST_FIX | 1138 | | DWC_CTLL_DST_FIX |
@@ -1137,7 +1143,7 @@ struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, | |||
1137 | case DMA_FROM_DEVICE: | 1143 | case DMA_FROM_DEVICE: |
1138 | desc->lli.dar = buf_addr + (period_len * i); | 1144 | desc->lli.dar = buf_addr + (period_len * i); |
1139 | desc->lli.sar = dws->rx_reg; | 1145 | desc->lli.sar = dws->rx_reg; |
1140 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO | 1146 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan->private) |
1141 | | DWC_CTLL_SRC_WIDTH(reg_width) | 1147 | | DWC_CTLL_SRC_WIDTH(reg_width) |
1142 | | DWC_CTLL_DST_WIDTH(reg_width) | 1148 | | DWC_CTLL_DST_WIDTH(reg_width) |
1143 | | DWC_CTLL_DST_INC | 1149 | | DWC_CTLL_DST_INC |
@@ -1335,6 +1341,8 @@ static int __init dw_probe(struct platform_device *pdev) | |||
1335 | 1341 | ||
1336 | dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); | 1342 | dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); |
1337 | dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); | 1343 | dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); |
1344 | if (pdata->is_private) | ||
1345 | dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask); | ||
1338 | dw->dma.dev = &pdev->dev; | 1346 | dw->dma.dev = &pdev->dev; |
1339 | dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; | 1347 | dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; |
1340 | dw->dma.device_free_chan_resources = dwc_free_chan_resources; | 1348 | dw->dma.device_free_chan_resources = dwc_free_chan_resources; |