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authorDan Williams <dan.j.williams@intel.com>2009-09-08 20:42:54 -0400
committerDan Williams <dan.j.williams@intel.com>2009-09-08 20:42:54 -0400
commit2aec048cdc4a5a81163a42a61df903f76a27e737 (patch)
tree00347decc9b145f4c805c8475b980d2641b8ec11 /drivers/dma
parent128f2d567f906d38b11d993d8d97b9b988848e26 (diff)
ioat3: hardware version 3.2 register / descriptor definitions
ioat3.2 adds raid5 and raid6 offload capabilities. Signed-off-by: Tom Picard <tom.s.picard@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/dma')
-rw-r--r--drivers/dma/ioat/dma.h2
-rw-r--r--drivers/dma/ioat/dma_v2.h26
-rw-r--r--drivers/dma/ioat/hw.h142
-rw-r--r--drivers/dma/ioat/registers.h17
4 files changed, 185 insertions, 2 deletions
diff --git a/drivers/dma/ioat/dma.h b/drivers/dma/ioat/dma.h
index d9d6a7e3cd76..0d94e7804c13 100644
--- a/drivers/dma/ioat/dma.h
+++ b/drivers/dma/ioat/dma.h
@@ -155,7 +155,7 @@ ioat_is_complete(struct dma_chan *c, dma_cookie_t cookie,
155 155
156/** 156/**
157 * struct ioat_desc_sw - wrapper around hardware descriptor 157 * struct ioat_desc_sw - wrapper around hardware descriptor
158 * @hw: hardware DMA descriptor 158 * @hw: hardware DMA descriptor (for memcpy)
159 * @node: this descriptor will either be on the free list, 159 * @node: this descriptor will either be on the free list,
160 * or attached to a transaction list (async_tx.tx_list) 160 * or attached to a transaction list (async_tx.tx_list)
161 * @txd: the generic software descriptor for all engines 161 * @txd: the generic software descriptor for all engines
diff --git a/drivers/dma/ioat/dma_v2.h b/drivers/dma/ioat/dma_v2.h
index 9baa3d6065ff..ed4bb82a283d 100644
--- a/drivers/dma/ioat/dma_v2.h
+++ b/drivers/dma/ioat/dma_v2.h
@@ -114,8 +114,32 @@ static inline u16 ioat2_xferlen_to_descs(struct ioat2_dma_chan *ioat, size_t len
114 return num_descs; 114 return num_descs;
115} 115}
116 116
117/**
118 * struct ioat_ring_ent - wrapper around hardware descriptor
119 * @hw: hardware DMA descriptor (for memcpy)
120 * @fill: hardware fill descriptor
121 * @xor: hardware xor descriptor
122 * @xor_ex: hardware xor extension descriptor
123 * @pq: hardware pq descriptor
124 * @pq_ex: hardware pq extension descriptor
125 * @pqu: hardware pq update descriptor
126 * @raw: hardware raw (un-typed) descriptor
127 * @txd: the generic software descriptor for all engines
128 * @len: total transaction length for unmap
129 * @id: identifier for debug
130 */
131
117struct ioat_ring_ent { 132struct ioat_ring_ent {
118 struct ioat_dma_descriptor *hw; 133 union {
134 struct ioat_dma_descriptor *hw;
135 struct ioat_fill_descriptor *fill;
136 struct ioat_xor_descriptor *xor;
137 struct ioat_xor_ext_descriptor *xor_ex;
138 struct ioat_pq_descriptor *pq;
139 struct ioat_pq_ext_descriptor *pq_ex;
140 struct ioat_pq_update_descriptor *pqu;
141 struct ioat_raw_descriptor *raw;
142 };
119 struct dma_async_tx_descriptor txd; 143 struct dma_async_tx_descriptor txd;
120 size_t len; 144 size_t len;
121 #ifdef DEBUG 145 #ifdef DEBUG
diff --git a/drivers/dma/ioat/hw.h b/drivers/dma/ioat/hw.h
index 7481fb13ce00..99afb12bd409 100644
--- a/drivers/dma/ioat/hw.h
+++ b/drivers/dma/ioat/hw.h
@@ -37,6 +37,7 @@
37#define IOAT_VER_1_2 0x12 /* Version 1.2 */ 37#define IOAT_VER_1_2 0x12 /* Version 1.2 */
38#define IOAT_VER_2_0 0x20 /* Version 2.0 */ 38#define IOAT_VER_2_0 0x20 /* Version 2.0 */
39#define IOAT_VER_3_0 0x30 /* Version 3.0 */ 39#define IOAT_VER_3_0 0x30 /* Version 3.0 */
40#define IOAT_VER_3_2 0x32 /* Version 3.2 */
40 41
41struct ioat_dma_descriptor { 42struct ioat_dma_descriptor {
42 uint32_t size; 43 uint32_t size;
@@ -55,6 +56,7 @@ struct ioat_dma_descriptor {
55 unsigned int dest_dca:1; 56 unsigned int dest_dca:1;
56 unsigned int hint:1; 57 unsigned int hint:1;
57 unsigned int rsvd2:13; 58 unsigned int rsvd2:13;
59 #define IOAT_OP_COPY 0x00
58 unsigned int op:8; 60 unsigned int op:8;
59 } ctl_f; 61 } ctl_f;
60 }; 62 };
@@ -70,4 +72,144 @@ struct ioat_dma_descriptor {
70 }; 72 };
71 uint64_t user2; 73 uint64_t user2;
72}; 74};
75
76struct ioat_fill_descriptor {
77 uint32_t size;
78 union {
79 uint32_t ctl;
80 struct {
81 unsigned int int_en:1;
82 unsigned int rsvd:1;
83 unsigned int dest_snoop_dis:1;
84 unsigned int compl_write:1;
85 unsigned int fence:1;
86 unsigned int rsvd2:2;
87 unsigned int dest_brk:1;
88 unsigned int bundle:1;
89 unsigned int rsvd4:15;
90 #define IOAT_OP_FILL 0x01
91 unsigned int op:8;
92 } ctl_f;
93 };
94 uint64_t src_data;
95 uint64_t dst_addr;
96 uint64_t next;
97 uint64_t rsv1;
98 uint64_t next_dst_addr;
99 uint64_t user1;
100 uint64_t user2;
101};
102
103struct ioat_xor_descriptor {
104 uint32_t size;
105 union {
106 uint32_t ctl;
107 struct {
108 unsigned int int_en:1;
109 unsigned int src_snoop_dis:1;
110 unsigned int dest_snoop_dis:1;
111 unsigned int compl_write:1;
112 unsigned int fence:1;
113 unsigned int src_cnt:3;
114 unsigned int bundle:1;
115 unsigned int dest_dca:1;
116 unsigned int hint:1;
117 unsigned int rsvd:13;
118 #define IOAT_OP_XOR 0x87
119 #define IOAT_OP_XOR_VAL 0x88
120 unsigned int op:8;
121 } ctl_f;
122 };
123 uint64_t src_addr;
124 uint64_t dst_addr;
125 uint64_t next;
126 uint64_t src_addr2;
127 uint64_t src_addr3;
128 uint64_t src_addr4;
129 uint64_t src_addr5;
130};
131
132struct ioat_xor_ext_descriptor {
133 uint64_t src_addr6;
134 uint64_t src_addr7;
135 uint64_t src_addr8;
136 uint64_t next;
137 uint64_t rsvd[4];
138};
139
140struct ioat_pq_descriptor {
141 uint32_t size;
142 union {
143 uint32_t ctl;
144 struct {
145 unsigned int int_en:1;
146 unsigned int src_snoop_dis:1;
147 unsigned int dest_snoop_dis:1;
148 unsigned int compl_write:1;
149 unsigned int fence:1;
150 unsigned int src_cnt:3;
151 unsigned int bundle:1;
152 unsigned int dest_dca:1;
153 unsigned int hint:1;
154 unsigned int p_disable:1;
155 unsigned int q_disable:1;
156 unsigned int rsvd:11;
157 #define IOAT_OP_PQ 0x89
158 #define IOAT_OP_PQ_VAL 0x8a
159 unsigned int op:8;
160 } ctl_f;
161 };
162 uint64_t src_addr;
163 uint64_t p_addr;
164 uint64_t next;
165 uint64_t src_addr2;
166 uint64_t src_addr3;
167 uint8_t coef[8];
168 uint64_t q_addr;
169};
170
171struct ioat_pq_ext_descriptor {
172 uint64_t src_addr4;
173 uint64_t src_addr5;
174 uint64_t src_addr6;
175 uint64_t next;
176 uint64_t src_addr7;
177 uint64_t src_addr8;
178 uint64_t rsvd[2];
179};
180
181struct ioat_pq_update_descriptor {
182 uint32_t size;
183 union {
184 uint32_t ctl;
185 struct {
186 unsigned int int_en:1;
187 unsigned int src_snoop_dis:1;
188 unsigned int dest_snoop_dis:1;
189 unsigned int compl_write:1;
190 unsigned int fence:1;
191 unsigned int src_cnt:3;
192 unsigned int bundle:1;
193 unsigned int dest_dca:1;
194 unsigned int hint:1;
195 unsigned int p_disable:1;
196 unsigned int q_disable:1;
197 unsigned int rsvd:3;
198 unsigned int coef:8;
199 #define IOAT_OP_PQ_UP 0x8b
200 unsigned int op:8;
201 } ctl_f;
202 };
203 uint64_t src_addr;
204 uint64_t p_addr;
205 uint64_t next;
206 uint64_t src_addr2;
207 uint64_t p_src;
208 uint64_t q_src;
209 uint64_t q_addr;
210};
211
212struct ioat_raw_descriptor {
213 uint64_t field[8];
214};
73#endif 215#endif
diff --git a/drivers/dma/ioat/registers.h b/drivers/dma/ioat/registers.h
index e4334a195380..85d04b8c563c 100644
--- a/drivers/dma/ioat/registers.h
+++ b/drivers/dma/ioat/registers.h
@@ -64,6 +64,20 @@
64 64
65#define IOAT_DEVICE_STATUS_OFFSET 0x0E /* 16-bit */ 65#define IOAT_DEVICE_STATUS_OFFSET 0x0E /* 16-bit */
66#define IOAT_DEVICE_STATUS_DEGRADED_MODE 0x0001 66#define IOAT_DEVICE_STATUS_DEGRADED_MODE 0x0001
67#define IOAT_DEVICE_MMIO_RESTRICTED 0x0002
68#define IOAT_DEVICE_MEMORY_BYPASS 0x0004
69#define IOAT_DEVICE_ADDRESS_REMAPPING 0x0008
70
71#define IOAT_DMA_CAP_OFFSET 0x10 /* 32-bit */
72#define IOAT_CAP_PAGE_BREAK 0x00000001
73#define IOAT_CAP_CRC 0x00000002
74#define IOAT_CAP_SKIP_MARKER 0x00000004
75#define IOAT_CAP_DCA 0x00000010
76#define IOAT_CAP_CRC_MOVE 0x00000020
77#define IOAT_CAP_FILL_BLOCK 0x00000040
78#define IOAT_CAP_APIC 0x00000080
79#define IOAT_CAP_XOR 0x00000100
80#define IOAT_CAP_PQ 0x00000200
67 81
68#define IOAT_CHANNEL_MMIO_SIZE 0x80 /* Each Channel MMIO space is this size */ 82#define IOAT_CHANNEL_MMIO_SIZE 0x80 /* Each Channel MMIO space is this size */
69 83
@@ -224,6 +238,9 @@
224#define IOAT_CHANERR_INT_CONFIGURATION_ERR 0x2000 238#define IOAT_CHANERR_INT_CONFIGURATION_ERR 0x2000
225#define IOAT_CHANERR_SOFT_ERR 0x4000 239#define IOAT_CHANERR_SOFT_ERR 0x4000
226#define IOAT_CHANERR_UNAFFILIATED_ERR 0x8000 240#define IOAT_CHANERR_UNAFFILIATED_ERR 0x8000
241#define IOAT_CHANERR_XOR_P_OR_CRC_ERR 0x10000
242#define IOAT_CHANERR_XOR_Q_ERR 0x20000
243#define IOAT_CHANERR_DESCRIPTOR_COUNT_ERR 0x40000
227 244
228#define IOAT_CHANERR_MASK_OFFSET 0x2C /* 32-bit Channel Error Register */ 245#define IOAT_CHANERR_MASK_OFFSET 0x2C /* 32-bit Channel Error Register */
229 246
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 17:32:12 -0500