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authorVinod Koul <vinod.koul@linux.intel.com>2011-10-13 13:04:23 -0400
committerVinod Koul <vinod.koul@linux.intel.com>2011-10-27 11:23:43 -0400
commitdb8196df4bb6f117caa163aa73b0f16fd62290bd (patch)
treeb86531031482037d9b31ad57479f2f7091020957 /drivers/dma/timb_dma.c
parent49920bc66984a512f4bcc7735a61642cd0e4d6f2 (diff)
dmaengine: move drivers to dma_transfer_direction
fixup usage of dma direction by introducing dma_transfer_direction, this patch moves dma/drivers/* to use new enum Cc: Jassi Brar <jaswinder.singh@linaro.org> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Viresh Kumar <viresh.kumar@st.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Mika Westerberg <mika.westerberg@iki.fi> Cc: H Hartley Sweeten <hartleys@visionengravers.com> Cc: Li Yang <leoli@freescale.com> Cc: Zhang Wei <zw@zh-kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Cc: Shawn Guo <shawn.guo@freescale.com> Cc: Yong Wang <yong.y.wang@intel.com> Cc: Tomoya MORINAGA <tomoya-linux@dsn.lapis-semi.com> Cc: Boojin Kim <boojin.kim@samsung.com> Cc: Barry Song <Baohua.Song@csr.com> Acked-by: Mika Westerberg <mika.westerberg@iki.fi> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Viresh Kumar <viresh.kumar@st.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
Diffstat (limited to 'drivers/dma/timb_dma.c')
-rw-r--r--drivers/dma/timb_dma.c18
1 files changed, 9 insertions, 9 deletions
diff --git a/drivers/dma/timb_dma.c b/drivers/dma/timb_dma.c
index a4a398f2ef61..8c880729b094 100644
--- a/drivers/dma/timb_dma.c
+++ b/drivers/dma/timb_dma.c
@@ -90,7 +90,7 @@ struct timb_dma_chan {
90 struct list_head queue; 90 struct list_head queue;
91 struct list_head free_list; 91 struct list_head free_list;
92 unsigned int bytes_per_line; 92 unsigned int bytes_per_line;
93 enum dma_data_direction direction; 93 enum dma_transfer_direction direction;
94 unsigned int descs; /* Descriptors to allocate */ 94 unsigned int descs; /* Descriptors to allocate */
95 unsigned int desc_elems; /* number of elems per descriptor */ 95 unsigned int desc_elems; /* number of elems per descriptor */
96}; 96};
@@ -235,7 +235,7 @@ static void __td_start_dma(struct timb_dma_chan *td_chan)
235 "td_chan: %p, chan: %d, membase: %p\n", 235 "td_chan: %p, chan: %d, membase: %p\n",
236 td_chan, td_chan->chan.chan_id, td_chan->membase); 236 td_chan, td_chan->chan.chan_id, td_chan->membase);
237 237
238 if (td_chan->direction == DMA_FROM_DEVICE) { 238 if (td_chan->direction == DMA_DEV_TO_MEM) {
239 239
240 /* descriptor address */ 240 /* descriptor address */
241 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_RX_DHAR); 241 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_RX_DHAR);
@@ -278,7 +278,7 @@ static void __td_finish(struct timb_dma_chan *td_chan)
278 txd->cookie); 278 txd->cookie);
279 279
280 /* make sure to stop the transfer */ 280 /* make sure to stop the transfer */
281 if (td_chan->direction == DMA_FROM_DEVICE) 281 if (td_chan->direction == DMA_DEV_TO_MEM)
282 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_RX_ER); 282 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_RX_ER);
283/* Currently no support for stopping DMA transfers 283/* Currently no support for stopping DMA transfers
284 else 284 else
@@ -398,7 +398,7 @@ static struct timb_dma_desc *td_alloc_init_desc(struct timb_dma_chan *td_chan)
398 td_desc->txd.flags = DMA_CTRL_ACK; 398 td_desc->txd.flags = DMA_CTRL_ACK;
399 399
400 td_desc->txd.phys = dma_map_single(chan2dmadev(chan), 400 td_desc->txd.phys = dma_map_single(chan2dmadev(chan),
401 td_desc->desc_list, td_desc->desc_list_len, DMA_TO_DEVICE); 401 td_desc->desc_list, td_desc->desc_list_len, DMA_MEM_TO_DEV);
402 402
403 err = dma_mapping_error(chan2dmadev(chan), td_desc->txd.phys); 403 err = dma_mapping_error(chan2dmadev(chan), td_desc->txd.phys);
404 if (err) { 404 if (err) {
@@ -419,7 +419,7 @@ static void td_free_desc(struct timb_dma_desc *td_desc)
419{ 419{
420 dev_dbg(chan2dev(td_desc->txd.chan), "Freeing desc: %p\n", td_desc); 420 dev_dbg(chan2dev(td_desc->txd.chan), "Freeing desc: %p\n", td_desc);
421 dma_unmap_single(chan2dmadev(td_desc->txd.chan), td_desc->txd.phys, 421 dma_unmap_single(chan2dmadev(td_desc->txd.chan), td_desc->txd.phys,
422 td_desc->desc_list_len, DMA_TO_DEVICE); 422 td_desc->desc_list_len, DMA_MEM_TO_DEV);
423 423
424 kfree(td_desc->desc_list); 424 kfree(td_desc->desc_list);
425 kfree(td_desc); 425 kfree(td_desc);
@@ -558,7 +558,7 @@ static void td_issue_pending(struct dma_chan *chan)
558 558
559static struct dma_async_tx_descriptor *td_prep_slave_sg(struct dma_chan *chan, 559static struct dma_async_tx_descriptor *td_prep_slave_sg(struct dma_chan *chan,
560 struct scatterlist *sgl, unsigned int sg_len, 560 struct scatterlist *sgl, unsigned int sg_len,
561 enum dma_data_direction direction, unsigned long flags) 561 enum dma_transfer_direction direction, unsigned long flags)
562{ 562{
563 struct timb_dma_chan *td_chan = 563 struct timb_dma_chan *td_chan =
564 container_of(chan, struct timb_dma_chan, chan); 564 container_of(chan, struct timb_dma_chan, chan);
@@ -606,7 +606,7 @@ static struct dma_async_tx_descriptor *td_prep_slave_sg(struct dma_chan *chan,
606 } 606 }
607 607
608 dma_sync_single_for_device(chan2dmadev(chan), td_desc->txd.phys, 608 dma_sync_single_for_device(chan2dmadev(chan), td_desc->txd.phys,
609 td_desc->desc_list_len, DMA_TO_DEVICE); 609 td_desc->desc_list_len, DMA_MEM_TO_DEV);
610 610
611 return &td_desc->txd; 611 return &td_desc->txd;
612} 612}
@@ -775,8 +775,8 @@ static int __devinit td_probe(struct platform_device *pdev)
775 td_chan->descs = pchan->descriptors; 775 td_chan->descs = pchan->descriptors;
776 td_chan->desc_elems = pchan->descriptor_elements; 776 td_chan->desc_elems = pchan->descriptor_elements;
777 td_chan->bytes_per_line = pchan->bytes_per_line; 777 td_chan->bytes_per_line = pchan->bytes_per_line;
778 td_chan->direction = pchan->rx ? DMA_FROM_DEVICE : 778 td_chan->direction = pchan->rx ? DMA_DEV_TO_MEM :
779 DMA_TO_DEVICE; 779 DMA_MEM_TO_DEV;
780 780
781 td_chan->membase = td->membase + 781 td_chan->membase = td->membase +
782 (i / 2) * TIMBDMA_INSTANCE_OFFSET + 782 (i / 2) * TIMBDMA_INSTANCE_OFFSET +