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authorJonas Aaberg <jonas.aberg@stericsson.com>2010-08-09 08:08:34 -0400
committerDan Williams <dan.j.williams@intel.com>2010-09-22 17:53:46 -0400
commit767a9675c4a68ada55f0f30d629db627bd47f012 (patch)
tree00cdf68f481bc818962367b6fa3255bd8040843e /drivers/dma/ste_dma40_ll.h
parentaa182ae2621877e0c111922696c84c538b82ad14 (diff)
DMAENGINE: ste_dma40: code clean-up
This patch includes non functional code clean up changes, file header updates and a few magic numbers got defined. Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/dma/ste_dma40_ll.h')
-rw-r--r--drivers/dma/ste_dma40_ll.h30
1 files changed, 18 insertions, 12 deletions
diff --git a/drivers/dma/ste_dma40_ll.h b/drivers/dma/ste_dma40_ll.h
index be35fadddf75..a51ec187b5cf 100644
--- a/drivers/dma/ste_dma40_ll.h
+++ b/drivers/dma/ste_dma40_ll.h
@@ -1,10 +1,8 @@
1/* 1/*
2 * driver/dma/ste_dma40_ll.h 2 * Copyright (C) ST-Ericsson SA 2007-2010
3 * 3 * Author: Per Friden <per.friden@stericsson.com> for ST-Ericsson SA
4 * Copyright (C) ST-Ericsson 2007-2010 4 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson SA
5 * License terms: GNU General Public License (GPL) version 2 5 * License terms: GNU General Public License (GPL) version 2
6 * Author: Per Friden <per.friden@stericsson.com>
7 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
8 */ 6 */
9#ifndef STE_DMA40_LL_H 7#ifndef STE_DMA40_LL_H
10#define STE_DMA40_LL_H 8#define STE_DMA40_LL_H
@@ -289,10 +287,13 @@ struct d40_lcla_elem {
289/* Physical channels */ 287/* Physical channels */
290 288
291void d40_phy_cfg(struct stedma40_chan_cfg *cfg, 289void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
292 u32 *src_cfg, u32 *dst_cfg, bool is_log); 290 u32 *src_cfg,
291 u32 *dst_cfg,
292 bool is_log);
293 293
294void d40_log_cfg(struct stedma40_chan_cfg *cfg, 294void d40_log_cfg(struct stedma40_chan_cfg *cfg,
295 u32 *lcsp1, u32 *lcsp2); 295 u32 *lcsp1,
296 u32 *lcsp2);
296 297
297int d40_phy_sg_to_lli(struct scatterlist *sg, 298int d40_phy_sg_to_lli(struct scatterlist *sg,
298 int sg_len, 299 int sg_len,
@@ -321,10 +322,13 @@ void d40_phy_lli_write(void __iomem *virtbase,
321/* Logical channels */ 322/* Logical channels */
322 323
323void d40_log_fill_lli(struct d40_log_lli *lli, 324void d40_log_fill_lli(struct d40_log_lli *lli,
324 dma_addr_t data, u32 data_size, 325 dma_addr_t data,
325 u32 lli_next_off, u32 reg_cfg, 326 u32 data_size,
327 u32 lli_next_off,
328 u32 reg_cfg,
326 u32 data_width, 329 u32 data_width,
327 bool term_int, bool addr_inc); 330 bool term_int,
331 bool addr_inc);
328 332
329int d40_log_sg_to_dev(struct d40_lcla_elem *lcla, 333int d40_log_sg_to_dev(struct d40_lcla_elem *lcla,
330 struct scatterlist *sg, 334 struct scatterlist *sg,
@@ -334,7 +338,8 @@ int d40_log_sg_to_dev(struct d40_lcla_elem *lcla,
334 u32 src_data_width, 338 u32 src_data_width,
335 u32 dst_data_width, 339 u32 dst_data_width,
336 enum dma_data_direction direction, 340 enum dma_data_direction direction,
337 dma_addr_t dev_addr, int max_len, 341 dma_addr_t dev_addr,
342 int max_len,
338 int llis_per_log); 343 int llis_per_log);
339 344
340int d40_log_lli_write(struct d40_log_lli_full *lcpa, 345int d40_log_lli_write(struct d40_log_lli_full *lcpa,
@@ -350,6 +355,7 @@ int d40_log_sg_to_lli(int lcla_id,
350 struct d40_log_lli *lli_sg, 355 struct d40_log_lli *lli_sg,
351 u32 lcsp13, /* src or dst*/ 356 u32 lcsp13, /* src or dst*/
352 u32 data_width, 357 u32 data_width,
353 int max_len, int llis_per_log); 358 int max_len,
359 int llis_per_log);
354 360
355#endif /* STE_DMA40_LLI_H */ 361#endif /* STE_DMA40_LLI_H */