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authorRabin Vincent <rabin.vincent@stericsson.com>2011-01-25 05:18:11 -0500
committerDan Williams <dan.j.williams@intel.com>2011-01-31 01:27:16 -0500
commitac2c0a387194f45c759572b3462d1bf92ec92f00 (patch)
tree81f5e1e9132d56a2e4ba5063c0ecaf722e04b970 /drivers/dma/ste_dma40.c
parent4d5949009e585b2bcf09dc4de625351f987a1e6d (diff)
dma40: allow realtime and priority for event lines
DB8500v2's DMA40 (revision 3) allows setting event lines as high priority and real time. Acked-by: Per Forlin <per.forlin@stericsson.com> Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/dma/ste_dma40.c')
-rw-r--r--drivers/dma/ste_dma40.c34
1 files changed, 34 insertions, 0 deletions
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 0faae662ad15..ce5516221581 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -1724,6 +1724,38 @@ bool stedma40_filter(struct dma_chan *chan, void *data)
1724} 1724}
1725EXPORT_SYMBOL(stedma40_filter); 1725EXPORT_SYMBOL(stedma40_filter);
1726 1726
1727static void __d40_set_prio_rt(struct d40_chan *d40c, int dev_type, bool src)
1728{
1729 bool realtime = d40c->dma_cfg.realtime;
1730 bool highprio = d40c->dma_cfg.high_priority;
1731 u32 prioreg = highprio ? D40_DREG_PSEG1 : D40_DREG_PCEG1;
1732 u32 rtreg = realtime ? D40_DREG_RSEG1 : D40_DREG_RCEG1;
1733 u32 event = D40_TYPE_TO_EVENT(dev_type);
1734 u32 group = D40_TYPE_TO_GROUP(dev_type);
1735 u32 bit = 1 << event;
1736
1737 /* Destination event lines are stored in the upper halfword */
1738 if (!src)
1739 bit <<= 16;
1740
1741 writel(bit, d40c->base->virtbase + prioreg + group * 4);
1742 writel(bit, d40c->base->virtbase + rtreg + group * 4);
1743}
1744
1745static void d40_set_prio_realtime(struct d40_chan *d40c)
1746{
1747 if (d40c->base->rev < 3)
1748 return;
1749
1750 if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
1751 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
1752 __d40_set_prio_rt(d40c, d40c->dma_cfg.src_dev_type, true);
1753
1754 if ((d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH) ||
1755 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
1756 __d40_set_prio_rt(d40c, d40c->dma_cfg.dst_dev_type, false);
1757}
1758
1727/* DMA ENGINE functions */ 1759/* DMA ENGINE functions */
1728static int d40_alloc_chan_resources(struct dma_chan *chan) 1760static int d40_alloc_chan_resources(struct dma_chan *chan)
1729{ 1761{
@@ -1756,6 +1788,8 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
1756 d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg, 1788 d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg,
1757 &d40c->dst_def_cfg, chan_is_logical(d40c)); 1789 &d40c->dst_def_cfg, chan_is_logical(d40c));
1758 1790
1791 d40_set_prio_realtime(d40c);
1792
1759 if (chan_is_logical(d40c)) { 1793 if (chan_is_logical(d40c)) {
1760 d40_log_cfg(&d40c->dma_cfg, 1794 d40_log_cfg(&d40c->dma_cfg,
1761 &d40c->log_def.lcsp1, &d40c->log_def.lcsp3); 1795 &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);