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authorRabin Vincent <rabin.vincent@stericsson.com>2011-01-25 05:18:08 -0500
committerDan Williams <dan.j.williams@intel.com>2011-01-31 01:27:16 -0500
commit724a8577d80c6f8e9ac680be1cf419eddbd6f2a1 (patch)
tree9e6dd06f0ef4e5775d3f1000c0d8c943facfb519 /drivers/dma/ste_dma40.c
parent8ca84687b91322b9eafeaf4da43a21684cd0316e (diff)
dma40: use helpers for channel type check
The somewhat confusing check d40c->log_num == D40_PHY_CHAN and its variants are used in several places to check if a channel is logical or physical. Use appropriately named helpers to do this to make the code more readable. Acked-by: Per Forlin <per.forlin@stericsson.com> Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/dma/ste_dma40.c')
-rw-r--r--drivers/dma/ste_dma40.c54
1 files changed, 32 insertions, 22 deletions
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 3d4cea3cff35..0073988cdaf6 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -306,6 +306,16 @@ static struct device *chan2dev(struct d40_chan *d40c)
306 return &d40c->chan.dev->device; 306 return &d40c->chan.dev->device;
307} 307}
308 308
309static bool chan_is_physical(struct d40_chan *chan)
310{
311 return chan->log_num == D40_PHY_CHAN;
312}
313
314static bool chan_is_logical(struct d40_chan *chan)
315{
316 return !chan_is_physical(chan);
317}
318
309static void __iomem *chan_base(struct d40_chan *chan) 319static void __iomem *chan_base(struct d40_chan *chan)
310{ 320{
311 return chan->base->virtbase + D40_DREG_PCBASE + 321 return chan->base->virtbase + D40_DREG_PCBASE +
@@ -400,7 +410,7 @@ static int d40_lcla_free_all(struct d40_chan *d40c,
400 int i; 410 int i;
401 int ret = -EINVAL; 411 int ret = -EINVAL;
402 412
403 if (d40c->log_num == D40_PHY_CHAN) 413 if (chan_is_physical(d40c))
404 return 0; 414 return 0;
405 415
406 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags); 416 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
@@ -472,7 +482,7 @@ static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
472{ 482{
473 int curr_lcla = -EINVAL, next_lcla; 483 int curr_lcla = -EINVAL, next_lcla;
474 484
475 if (d40c->log_num == D40_PHY_CHAN) { 485 if (chan_is_physical(d40c)) {
476 d40_phy_lli_write(d40c->base->virtbase, 486 d40_phy_lli_write(d40c->base->virtbase,
477 d40c->phy_chan->num, 487 d40c->phy_chan->num,
478 d40d->lli_phy.dst, 488 d40d->lli_phy.dst,
@@ -788,7 +798,7 @@ static u32 d40_get_prmo(struct d40_chan *d40c)
788 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG, 798 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG,
789 }; 799 };
790 800
791 if (d40c->log_num == D40_PHY_CHAN) 801 if (chan_is_physical(d40c))
792 return phy_map[d40c->dma_cfg.mode_opt]; 802 return phy_map[d40c->dma_cfg.mode_opt];
793 else 803 else
794 return log_map[d40c->dma_cfg.mode_opt]; 804 return log_map[d40c->dma_cfg.mode_opt];
@@ -802,7 +812,7 @@ static void d40_config_write(struct d40_chan *d40c)
802 /* Odd addresses are even addresses + 4 */ 812 /* Odd addresses are even addresses + 4 */
803 addr_base = (d40c->phy_chan->num % 2) * 4; 813 addr_base = (d40c->phy_chan->num % 2) * 4;
804 /* Setup channel mode to logical or physical */ 814 /* Setup channel mode to logical or physical */
805 var = ((u32)(d40c->log_num != D40_PHY_CHAN) + 1) << 815 var = ((u32)(chan_is_logical(d40c)) + 1) <<
806 D40_CHAN_POS(d40c->phy_chan->num); 816 D40_CHAN_POS(d40c->phy_chan->num);
807 writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base); 817 writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);
808 818
@@ -811,7 +821,7 @@ static void d40_config_write(struct d40_chan *d40c)
811 821
812 writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base); 822 writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
813 823
814 if (d40c->log_num != D40_PHY_CHAN) { 824 if (chan_is_logical(d40c)) {
815 int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS) 825 int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS)
816 & D40_SREG_ELEM_LOG_LIDX_MASK; 826 & D40_SREG_ELEM_LOG_LIDX_MASK;
817 void __iomem *chanbase = chan_base(d40c); 827 void __iomem *chanbase = chan_base(d40c);
@@ -830,7 +840,7 @@ static u32 d40_residue(struct d40_chan *d40c)
830{ 840{
831 u32 num_elt; 841 u32 num_elt;
832 842
833 if (d40c->log_num != D40_PHY_CHAN) 843 if (chan_is_logical(d40c))
834 num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK) 844 num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
835 >> D40_MEM_LCSP2_ECNT_POS; 845 >> D40_MEM_LCSP2_ECNT_POS;
836 else { 846 else {
@@ -846,7 +856,7 @@ static bool d40_tx_is_linked(struct d40_chan *d40c)
846{ 856{
847 bool is_link; 857 bool is_link;
848 858
849 if (d40c->log_num != D40_PHY_CHAN) 859 if (chan_is_logical(d40c))
850 is_link = readl(&d40c->lcpa->lcsp3) & D40_MEM_LCSP3_DLOS_MASK; 860 is_link = readl(&d40c->lcpa->lcsp3) & D40_MEM_LCSP3_DLOS_MASK;
851 else 861 else
852 is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK) 862 is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK)
@@ -869,7 +879,7 @@ static int d40_pause(struct dma_chan *chan)
869 879
870 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ); 880 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
871 if (res == 0) { 881 if (res == 0) {
872 if (d40c->log_num != D40_PHY_CHAN) { 882 if (chan_is_logical(d40c)) {
873 d40_config_set_event(d40c, false); 883 d40_config_set_event(d40c, false);
874 /* Resume the other logical channels if any */ 884 /* Resume the other logical channels if any */
875 if (d40_chan_has_events(d40c)) 885 if (d40_chan_has_events(d40c))
@@ -895,7 +905,7 @@ static int d40_resume(struct dma_chan *chan)
895 spin_lock_irqsave(&d40c->lock, flags); 905 spin_lock_irqsave(&d40c->lock, flags);
896 906
897 if (d40c->base->rev == 0) 907 if (d40c->base->rev == 0)
898 if (d40c->log_num != D40_PHY_CHAN) { 908 if (chan_is_logical(d40c)) {
899 res = d40_channel_execute_command(d40c, 909 res = d40_channel_execute_command(d40c,
900 D40_DMA_SUSPEND_REQ); 910 D40_DMA_SUSPEND_REQ);
901 goto no_suspend; 911 goto no_suspend;
@@ -904,7 +914,7 @@ static int d40_resume(struct dma_chan *chan)
904 /* If bytes left to transfer or linked tx resume job */ 914 /* If bytes left to transfer or linked tx resume job */
905 if (d40_residue(d40c) || d40_tx_is_linked(d40c)) { 915 if (d40_residue(d40c) || d40_tx_is_linked(d40c)) {
906 916
907 if (d40c->log_num != D40_PHY_CHAN) 917 if (chan_is_logical(d40c))
908 d40_config_set_event(d40c, true); 918 d40_config_set_event(d40c, true);
909 919
910 res = d40_channel_execute_command(d40c, D40_DMA_RUN); 920 res = d40_channel_execute_command(d40c, D40_DMA_RUN);
@@ -944,7 +954,7 @@ static int d40_start(struct d40_chan *d40c)
944 if (d40c->base->rev == 0) { 954 if (d40c->base->rev == 0) {
945 int err; 955 int err;
946 956
947 if (d40c->log_num != D40_PHY_CHAN) { 957 if (chan_is_logical(d40c)) {
948 err = d40_channel_execute_command(d40c, 958 err = d40_channel_execute_command(d40c,
949 D40_DMA_SUSPEND_REQ); 959 D40_DMA_SUSPEND_REQ);
950 if (err) 960 if (err)
@@ -952,7 +962,7 @@ static int d40_start(struct d40_chan *d40c)
952 } 962 }
953 } 963 }
954 964
955 if (d40c->log_num != D40_PHY_CHAN) 965 if (chan_is_logical(d40c))
956 d40_config_set_event(d40c, true); 966 d40_config_set_event(d40c, true);
957 967
958 return d40_channel_execute_command(d40c, D40_DMA_RUN); 968 return d40_channel_execute_command(d40c, D40_DMA_RUN);
@@ -1495,7 +1505,7 @@ static int d40_free_dma(struct d40_chan *d40c)
1495 return res; 1505 return res;
1496 } 1506 }
1497 1507
1498 if (d40c->log_num != D40_PHY_CHAN) { 1508 if (chan_is_logical(d40c)) {
1499 /* Release logical channel, deactivate the event line */ 1509 /* Release logical channel, deactivate the event line */
1500 1510
1501 d40_config_set_event(d40c, false); 1511 d40_config_set_event(d40c, false);
@@ -1548,7 +1558,7 @@ static bool d40_is_paused(struct d40_chan *d40c)
1548 1558
1549 spin_lock_irqsave(&d40c->lock, flags); 1559 spin_lock_irqsave(&d40c->lock, flags);
1550 1560
1551 if (d40c->log_num == D40_PHY_CHAN) { 1561 if (chan_is_physical(d40c)) {
1552 if (d40c->phy_chan->num % 2 == 0) 1562 if (d40c->phy_chan->num % 2 == 0)
1553 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE; 1563 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1554 else 1564 else
@@ -1638,7 +1648,7 @@ struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan,
1638 d40d->lli_current = 0; 1648 d40d->lli_current = 0;
1639 d40d->txd.flags = dma_flags; 1649 d40d->txd.flags = dma_flags;
1640 1650
1641 if (d40c->log_num != D40_PHY_CHAN) { 1651 if (chan_is_logical(d40c)) {
1642 1652
1643 if (d40_pool_lli_alloc(d40d, d40d->lli_len, true) < 0) { 1653 if (d40_pool_lli_alloc(d40d, d40d->lli_len, true) < 0) {
1644 dev_err(&d40c->chan.dev->device, 1654 dev_err(&d40c->chan.dev->device,
@@ -1765,9 +1775,9 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
1765 1775
1766 /* Fill in basic CFG register values */ 1776 /* Fill in basic CFG register values */
1767 d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg, 1777 d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg,
1768 &d40c->dst_def_cfg, d40c->log_num != D40_PHY_CHAN); 1778 &d40c->dst_def_cfg, chan_is_logical(d40c));
1769 1779
1770 if (d40c->log_num != D40_PHY_CHAN) { 1780 if (chan_is_logical(d40c)) {
1771 d40_log_cfg(&d40c->dma_cfg, 1781 d40_log_cfg(&d40c->dma_cfg,
1772 &d40c->log_def.lcsp1, &d40c->log_def.lcsp3); 1782 &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
1773 1783
@@ -1857,7 +1867,7 @@ static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
1857 1867
1858 d40d->txd.tx_submit = d40_tx_submit; 1868 d40d->txd.tx_submit = d40_tx_submit;
1859 1869
1860 if (d40c->log_num != D40_PHY_CHAN) { 1870 if (chan_is_logical(d40c)) {
1861 1871
1862 if (d40_pool_lli_alloc(d40d, d40d->lli_len, true) < 0) { 1872 if (d40_pool_lli_alloc(d40d, d40d->lli_len, true) < 0) {
1863 dev_err(&d40c->chan.dev->device, 1873 dev_err(&d40c->chan.dev->device,
@@ -2093,7 +2103,7 @@ static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan,
2093 if (d40d == NULL) 2103 if (d40d == NULL)
2094 goto err; 2104 goto err;
2095 2105
2096 if (d40c->log_num != D40_PHY_CHAN) 2106 if (chan_is_logical(d40c))
2097 err = d40_prep_slave_sg_log(d40d, d40c, sgl, sg_len, 2107 err = d40_prep_slave_sg_log(d40d, d40c, sgl, sg_len,
2098 direction, dma_flags); 2108 direction, dma_flags);
2099 else 2109 else
@@ -2103,7 +2113,7 @@ static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan,
2103 dev_err(&d40c->chan.dev->device, 2113 dev_err(&d40c->chan.dev->device,
2104 "[%s] Failed to prepare %s slave sg job: %d\n", 2114 "[%s] Failed to prepare %s slave sg job: %d\n",
2105 __func__, 2115 __func__,
2106 d40c->log_num != D40_PHY_CHAN ? "log" : "phy", err); 2116 chan_is_logical(d40c) ? "log" : "phy", err);
2107 goto err; 2117 goto err;
2108 } 2118 }
2109 2119
@@ -2253,7 +2263,7 @@ static void d40_set_runtime_config(struct dma_chan *chan,
2253 return; 2263 return;
2254 } 2264 }
2255 2265
2256 if (d40c->log_num != D40_PHY_CHAN) { 2266 if (chan_is_logical(d40c)) {
2257 if (config_maxburst >= 16) 2267 if (config_maxburst >= 16)
2258 psize = STEDMA40_PSIZE_LOG_16; 2268 psize = STEDMA40_PSIZE_LOG_16;
2259 else if (config_maxburst >= 8) 2269 else if (config_maxburst >= 8)
@@ -2286,7 +2296,7 @@ static void d40_set_runtime_config(struct dma_chan *chan,
2286 cfg->dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL; 2296 cfg->dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2287 2297
2288 /* Fill in register values */ 2298 /* Fill in register values */
2289 if (d40c->log_num != D40_PHY_CHAN) 2299 if (chan_is_logical(d40c))
2290 d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3); 2300 d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2291 else 2301 else
2292 d40_phy_cfg(cfg, &d40c->src_def_cfg, 2302 d40_phy_cfg(cfg, &d40c->src_def_cfg,