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authorRussell King <rmk+kernel@arm.linux.org.uk>2013-11-06 12:15:16 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2014-04-03 19:30:18 -0400
commit59871902703c47acc730555be41bd9cb36d3700c (patch)
treedffebe3d0fdb69b7031be8eb8514a38954b297de /drivers/dma/omap-dma.c
parent965aeb4df1f2142f5a6407c6d40b7196be719582 (diff)
dmaengine: omap-dma: move barrier to omap_dma_start_desc()
We don't need to issue a barrier for every segment of a DMA transfer; doing this just once per descriptor will do. Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'drivers/dma/omap-dma.c')
-rw-r--r--drivers/dma/omap-dma.c8
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index 49609275b2e7..49b303296d75 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -195,7 +195,6 @@ static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
195 195
196 val = c->plat->dma_read(CCR, c->dma_ch); 196 val = c->plat->dma_read(CCR, c->dma_ch);
197 val |= CCR_ENABLE; 197 val |= CCR_ENABLE;
198 mb();
199 c->plat->dma_write(val, CCR, c->dma_ch); 198 c->plat->dma_write(val, CCR, c->dma_ch);
200} 199}
201 200
@@ -301,6 +300,13 @@ static void omap_dma_start_desc(struct omap_chan *c)
301 c->desc = d = to_omap_dma_desc(&vd->tx); 300 c->desc = d = to_omap_dma_desc(&vd->tx);
302 c->sgidx = 0; 301 c->sgidx = 0;
303 302
303 /*
304 * This provides the necessary barrier to ensure data held in
305 * DMA coherent memory is visible to the DMA engine prior to
306 * the transfer starting.
307 */
308 mb();
309
304 c->plat->dma_write(d->ccr, CCR, c->dma_ch); 310 c->plat->dma_write(d->ccr, CCR, c->dma_ch);
305 if (dma_omap1()) 311 if (dma_omap1())
306 c->plat->dma_write(d->ccr >> 16, CCR2, c->dma_ch); 312 c->plat->dma_write(d->ccr >> 16, CCR2, c->dma_ch);