diff options
author | Ezequiel Garcia <ezequiel.garcia@free-electrons.com> | 2014-08-27 09:52:52 -0400 |
---|---|---|
committer | Vinod Koul <vinod.koul@intel.com> | 2014-09-23 10:47:00 -0400 |
commit | 0e7488ed01235fdd24ce7f0295dbbea0d45311bb (patch) | |
tree | a1ff4f76484f071eefbfcc9df1f7f795da95bebb /drivers/dma/mv_xor.h | |
parent | dfc97661bdeadb57d35458430612072119b1c72f (diff) |
dma: mv_xor: Remove all interrupt magic numbers
This commit replaces the current magic numbers in the interrupt handling
with proper macros, which makes more readable and self-documenting.
While here replace the BUG() with a noisy WARN_ON(). There's no reason
to tear down the entire system for an DMA IRQ error.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'drivers/dma/mv_xor.h')
-rw-r--r-- | drivers/dma/mv_xor.h | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/drivers/dma/mv_xor.h b/drivers/dma/mv_xor.h index e03021ebed9a..ae41c31c6ea5 100644 --- a/drivers/dma/mv_xor.h +++ b/drivers/dma/mv_xor.h | |||
@@ -34,6 +34,9 @@ | |||
34 | #define XOR_OPERATION_MODE_MEMCPY 2 | 34 | #define XOR_OPERATION_MODE_MEMCPY 2 |
35 | #define XOR_DESCRIPTOR_SWAP BIT(14) | 35 | #define XOR_DESCRIPTOR_SWAP BIT(14) |
36 | 36 | ||
37 | #define XOR_DESC_DMA_OWNED BIT(31) | ||
38 | #define XOR_DESC_EOD_INT_EN BIT(31) | ||
39 | |||
37 | #define XOR_CURR_DESC(chan) (chan->mmr_high_base + 0x10 + (chan->idx * 4)) | 40 | #define XOR_CURR_DESC(chan) (chan->mmr_high_base + 0x10 + (chan->idx * 4)) |
38 | #define XOR_NEXT_DESC(chan) (chan->mmr_high_base + 0x00 + (chan->idx * 4)) | 41 | #define XOR_NEXT_DESC(chan) (chan->mmr_high_base + 0x00 + (chan->idx * 4)) |
39 | #define XOR_BYTE_COUNT(chan) (chan->mmr_high_base + 0x20 + (chan->idx * 4)) | 42 | #define XOR_BYTE_COUNT(chan) (chan->mmr_high_base + 0x20 + (chan->idx * 4)) |
@@ -48,7 +51,24 @@ | |||
48 | #define XOR_INTR_MASK(chan) (chan->mmr_base + 0x40) | 51 | #define XOR_INTR_MASK(chan) (chan->mmr_base + 0x40) |
49 | #define XOR_ERROR_CAUSE(chan) (chan->mmr_base + 0x50) | 52 | #define XOR_ERROR_CAUSE(chan) (chan->mmr_base + 0x50) |
50 | #define XOR_ERROR_ADDR(chan) (chan->mmr_base + 0x60) | 53 | #define XOR_ERROR_ADDR(chan) (chan->mmr_base + 0x60) |
51 | #define XOR_INTR_MASK_VALUE 0x3F5 | 54 | |
55 | #define XOR_INT_END_OF_DESC BIT(0) | ||
56 | #define XOR_INT_END_OF_CHAIN BIT(1) | ||
57 | #define XOR_INT_STOPPED BIT(2) | ||
58 | #define XOR_INT_PAUSED BIT(3) | ||
59 | #define XOR_INT_ERR_DECODE BIT(4) | ||
60 | #define XOR_INT_ERR_RDPROT BIT(5) | ||
61 | #define XOR_INT_ERR_WRPROT BIT(6) | ||
62 | #define XOR_INT_ERR_OWN BIT(7) | ||
63 | #define XOR_INT_ERR_PAR BIT(8) | ||
64 | #define XOR_INT_ERR_MBUS BIT(9) | ||
65 | |||
66 | #define XOR_INTR_ERRORS (XOR_INT_ERR_DECODE | XOR_INT_ERR_RDPROT | \ | ||
67 | XOR_INT_ERR_WRPROT | XOR_INT_ERR_OWN | \ | ||
68 | XOR_INT_ERR_PAR | XOR_INT_ERR_MBUS) | ||
69 | |||
70 | #define XOR_INTR_MASK_VALUE (XOR_INT_END_OF_DESC | \ | ||
71 | XOR_INT_STOPPED | XOR_INTR_ERRORS) | ||
52 | 72 | ||
53 | #define WINDOW_BASE(w) (0x50 + ((w) << 2)) | 73 | #define WINDOW_BASE(w) (0x50 + ((w) << 2)) |
54 | #define WINDOW_SIZE(w) (0x70 + ((w) << 2)) | 74 | #define WINDOW_SIZE(w) (0x70 + ((w) << 2)) |