diff options
author | Dan Williams <dan.j.williams@intel.com> | 2008-04-17 23:17:26 -0400 |
---|---|---|
committer | Dan Williams <dan.j.williams@intel.com> | 2008-04-17 16:25:54 -0400 |
commit | 636bdeaa1243327501edfd2a597ed7443eb4239a (patch) | |
tree | 59b894f124e3664ea4a537d7c07c527abdb9c8da /drivers/dma/iop-adma.c | |
parent | c4fe15541d0ef5cc8cc1ce43057663851f8fc387 (diff) |
dmaengine: ack to flags: make use of the unused bits in the 'ack' field
'ack' is currently a simple integer that flags whether or not a client is done
touching fields in the given descriptor. It is effectively just a single bit
of information. Converting this to a flags parameter allows the other bits to
be put to use to control completion actions, like dma-unmap, and capture
results, like xor-zero-sum == 0.
Changes are one of:
1/ convert all open-coded ->ack manipulations to use async_tx_ack
and async_tx_test_ack.
2/ set the ack bit at prep time where possible
3/ make drivers store the flags at prep time
4/ add flags to the device_prep_dma_interrupt prototype
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/dma/iop-adma.c')
-rw-r--r-- | drivers/dma/iop-adma.c | 39 |
1 files changed, 21 insertions, 18 deletions
diff --git a/drivers/dma/iop-adma.c b/drivers/dma/iop-adma.c index 93252294f32b..762b729672e0 100644 --- a/drivers/dma/iop-adma.c +++ b/drivers/dma/iop-adma.c | |||
@@ -111,7 +111,7 @@ iop_adma_clean_slot(struct iop_adma_desc_slot *desc, | |||
111 | /* the client is allowed to attach dependent operations | 111 | /* the client is allowed to attach dependent operations |
112 | * until 'ack' is set | 112 | * until 'ack' is set |
113 | */ | 113 | */ |
114 | if (!desc->async_tx.ack) | 114 | if (!async_tx_test_ack(&desc->async_tx)) |
115 | return 0; | 115 | return 0; |
116 | 116 | ||
117 | /* leave the last descriptor in the chain | 117 | /* leave the last descriptor in the chain |
@@ -148,7 +148,7 @@ static void __iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan) | |||
148 | "this_desc: %#x next_desc: %#x ack: %d\n", | 148 | "this_desc: %#x next_desc: %#x ack: %d\n", |
149 | iter->async_tx.cookie, iter->idx, busy, | 149 | iter->async_tx.cookie, iter->idx, busy, |
150 | iter->async_tx.phys, iop_desc_get_next_desc(iter), | 150 | iter->async_tx.phys, iop_desc_get_next_desc(iter), |
151 | iter->async_tx.ack); | 151 | async_tx_test_ack(&iter->async_tx)); |
152 | prefetch(_iter); | 152 | prefetch(_iter); |
153 | prefetch(&_iter->async_tx); | 153 | prefetch(&_iter->async_tx); |
154 | 154 | ||
@@ -338,9 +338,7 @@ retry: | |||
338 | 338 | ||
339 | /* pre-ack all but the last descriptor */ | 339 | /* pre-ack all but the last descriptor */ |
340 | if (num_slots != slots_per_op) | 340 | if (num_slots != slots_per_op) |
341 | iter->async_tx.ack = 1; | 341 | async_tx_ack(&iter->async_tx); |
342 | else | ||
343 | iter->async_tx.ack = 0; | ||
344 | 342 | ||
345 | list_add_tail(&iter->chain_node, &chain); | 343 | list_add_tail(&iter->chain_node, &chain); |
346 | alloc_tail = iter; | 344 | alloc_tail = iter; |
@@ -513,7 +511,7 @@ static int iop_adma_alloc_chan_resources(struct dma_chan *chan) | |||
513 | } | 511 | } |
514 | 512 | ||
515 | static struct dma_async_tx_descriptor * | 513 | static struct dma_async_tx_descriptor * |
516 | iop_adma_prep_dma_interrupt(struct dma_chan *chan) | 514 | iop_adma_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags) |
517 | { | 515 | { |
518 | struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); | 516 | struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); |
519 | struct iop_adma_desc_slot *sw_desc, *grp_start; | 517 | struct iop_adma_desc_slot *sw_desc, *grp_start; |
@@ -528,6 +526,7 @@ iop_adma_prep_dma_interrupt(struct dma_chan *chan) | |||
528 | grp_start = sw_desc->group_head; | 526 | grp_start = sw_desc->group_head; |
529 | iop_desc_init_interrupt(grp_start, iop_chan); | 527 | iop_desc_init_interrupt(grp_start, iop_chan); |
530 | grp_start->unmap_len = 0; | 528 | grp_start->unmap_len = 0; |
529 | sw_desc->async_tx.flags = flags; | ||
531 | } | 530 | } |
532 | spin_unlock_bh(&iop_chan->lock); | 531 | spin_unlock_bh(&iop_chan->lock); |
533 | 532 | ||
@@ -560,6 +559,7 @@ iop_adma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dma_dest, | |||
560 | iop_desc_set_memcpy_src_addr(grp_start, dma_src); | 559 | iop_desc_set_memcpy_src_addr(grp_start, dma_src); |
561 | sw_desc->unmap_src_cnt = 1; | 560 | sw_desc->unmap_src_cnt = 1; |
562 | sw_desc->unmap_len = len; | 561 | sw_desc->unmap_len = len; |
562 | sw_desc->async_tx.flags = flags; | ||
563 | } | 563 | } |
564 | spin_unlock_bh(&iop_chan->lock); | 564 | spin_unlock_bh(&iop_chan->lock); |
565 | 565 | ||
@@ -592,6 +592,7 @@ iop_adma_prep_dma_memset(struct dma_chan *chan, dma_addr_t dma_dest, | |||
592 | iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest); | 592 | iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest); |
593 | sw_desc->unmap_src_cnt = 1; | 593 | sw_desc->unmap_src_cnt = 1; |
594 | sw_desc->unmap_len = len; | 594 | sw_desc->unmap_len = len; |
595 | sw_desc->async_tx.flags = flags; | ||
595 | } | 596 | } |
596 | spin_unlock_bh(&iop_chan->lock); | 597 | spin_unlock_bh(&iop_chan->lock); |
597 | 598 | ||
@@ -625,6 +626,7 @@ iop_adma_prep_dma_xor(struct dma_chan *chan, dma_addr_t dma_dest, | |||
625 | iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest); | 626 | iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest); |
626 | sw_desc->unmap_src_cnt = src_cnt; | 627 | sw_desc->unmap_src_cnt = src_cnt; |
627 | sw_desc->unmap_len = len; | 628 | sw_desc->unmap_len = len; |
629 | sw_desc->async_tx.flags = flags; | ||
628 | while (src_cnt--) | 630 | while (src_cnt--) |
629 | iop_desc_set_xor_src_addr(grp_start, src_cnt, | 631 | iop_desc_set_xor_src_addr(grp_start, src_cnt, |
630 | dma_src[src_cnt]); | 632 | dma_src[src_cnt]); |
@@ -661,6 +663,7 @@ iop_adma_prep_dma_zero_sum(struct dma_chan *chan, dma_addr_t *dma_src, | |||
661 | __func__, grp_start->xor_check_result); | 663 | __func__, grp_start->xor_check_result); |
662 | sw_desc->unmap_src_cnt = src_cnt; | 664 | sw_desc->unmap_src_cnt = src_cnt; |
663 | sw_desc->unmap_len = len; | 665 | sw_desc->unmap_len = len; |
666 | sw_desc->async_tx.flags = flags; | ||
664 | while (src_cnt--) | 667 | while (src_cnt--) |
665 | iop_desc_set_zero_sum_src_addr(grp_start, src_cnt, | 668 | iop_desc_set_zero_sum_src_addr(grp_start, src_cnt, |
666 | dma_src[src_cnt]); | 669 | dma_src[src_cnt]); |
@@ -847,11 +850,11 @@ static int __devinit iop_adma_memcpy_self_test(struct iop_adma_device *device) | |||
847 | src_dma = dma_map_single(dma_chan->device->dev, src, | 850 | src_dma = dma_map_single(dma_chan->device->dev, src, |
848 | IOP_ADMA_TEST_SIZE, DMA_TO_DEVICE); | 851 | IOP_ADMA_TEST_SIZE, DMA_TO_DEVICE); |
849 | tx = iop_adma_prep_dma_memcpy(dma_chan, dest_dma, src_dma, | 852 | tx = iop_adma_prep_dma_memcpy(dma_chan, dest_dma, src_dma, |
850 | IOP_ADMA_TEST_SIZE, 1); | 853 | IOP_ADMA_TEST_SIZE, |
854 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | ||
851 | 855 | ||
852 | cookie = iop_adma_tx_submit(tx); | 856 | cookie = iop_adma_tx_submit(tx); |
853 | iop_adma_issue_pending(dma_chan); | 857 | iop_adma_issue_pending(dma_chan); |
854 | async_tx_ack(tx); | ||
855 | msleep(1); | 858 | msleep(1); |
856 | 859 | ||
857 | if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != | 860 | if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != |
@@ -947,11 +950,11 @@ iop_adma_xor_zero_sum_self_test(struct iop_adma_device *device) | |||
947 | dma_srcs[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i], | 950 | dma_srcs[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i], |
948 | 0, PAGE_SIZE, DMA_TO_DEVICE); | 951 | 0, PAGE_SIZE, DMA_TO_DEVICE); |
949 | tx = iop_adma_prep_dma_xor(dma_chan, dest_dma, dma_srcs, | 952 | tx = iop_adma_prep_dma_xor(dma_chan, dest_dma, dma_srcs, |
950 | IOP_ADMA_NUM_SRC_TEST, PAGE_SIZE, 1); | 953 | IOP_ADMA_NUM_SRC_TEST, PAGE_SIZE, |
954 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | ||
951 | 955 | ||
952 | cookie = iop_adma_tx_submit(tx); | 956 | cookie = iop_adma_tx_submit(tx); |
953 | iop_adma_issue_pending(dma_chan); | 957 | iop_adma_issue_pending(dma_chan); |
954 | async_tx_ack(tx); | ||
955 | msleep(8); | 958 | msleep(8); |
956 | 959 | ||
957 | if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != | 960 | if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != |
@@ -994,11 +997,11 @@ iop_adma_xor_zero_sum_self_test(struct iop_adma_device *device) | |||
994 | DMA_TO_DEVICE); | 997 | DMA_TO_DEVICE); |
995 | tx = iop_adma_prep_dma_zero_sum(dma_chan, dma_srcs, | 998 | tx = iop_adma_prep_dma_zero_sum(dma_chan, dma_srcs, |
996 | IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE, | 999 | IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE, |
997 | &zero_sum_result, 1); | 1000 | &zero_sum_result, |
1001 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | ||
998 | 1002 | ||
999 | cookie = iop_adma_tx_submit(tx); | 1003 | cookie = iop_adma_tx_submit(tx); |
1000 | iop_adma_issue_pending(dma_chan); | 1004 | iop_adma_issue_pending(dma_chan); |
1001 | async_tx_ack(tx); | ||
1002 | msleep(8); | 1005 | msleep(8); |
1003 | 1006 | ||
1004 | if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) { | 1007 | if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) { |
@@ -1018,11 +1021,11 @@ iop_adma_xor_zero_sum_self_test(struct iop_adma_device *device) | |||
1018 | /* test memset */ | 1021 | /* test memset */ |
1019 | dma_addr = dma_map_page(dma_chan->device->dev, dest, 0, | 1022 | dma_addr = dma_map_page(dma_chan->device->dev, dest, 0, |
1020 | PAGE_SIZE, DMA_FROM_DEVICE); | 1023 | PAGE_SIZE, DMA_FROM_DEVICE); |
1021 | tx = iop_adma_prep_dma_memset(dma_chan, dma_addr, 0, PAGE_SIZE, 1); | 1024 | tx = iop_adma_prep_dma_memset(dma_chan, dma_addr, 0, PAGE_SIZE, |
1025 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | ||
1022 | 1026 | ||
1023 | cookie = iop_adma_tx_submit(tx); | 1027 | cookie = iop_adma_tx_submit(tx); |
1024 | iop_adma_issue_pending(dma_chan); | 1028 | iop_adma_issue_pending(dma_chan); |
1025 | async_tx_ack(tx); | ||
1026 | msleep(8); | 1029 | msleep(8); |
1027 | 1030 | ||
1028 | if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) { | 1031 | if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) { |
@@ -1050,11 +1053,11 @@ iop_adma_xor_zero_sum_self_test(struct iop_adma_device *device) | |||
1050 | DMA_TO_DEVICE); | 1053 | DMA_TO_DEVICE); |
1051 | tx = iop_adma_prep_dma_zero_sum(dma_chan, dma_srcs, | 1054 | tx = iop_adma_prep_dma_zero_sum(dma_chan, dma_srcs, |
1052 | IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE, | 1055 | IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE, |
1053 | &zero_sum_result, 1); | 1056 | &zero_sum_result, |
1057 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | ||
1054 | 1058 | ||
1055 | cookie = iop_adma_tx_submit(tx); | 1059 | cookie = iop_adma_tx_submit(tx); |
1056 | iop_adma_issue_pending(dma_chan); | 1060 | iop_adma_issue_pending(dma_chan); |
1057 | async_tx_ack(tx); | ||
1058 | msleep(8); | 1061 | msleep(8); |
1059 | 1062 | ||
1060 | if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) { | 1063 | if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) { |
@@ -1287,7 +1290,7 @@ static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan) | |||
1287 | grp_start = sw_desc->group_head; | 1290 | grp_start = sw_desc->group_head; |
1288 | 1291 | ||
1289 | list_splice_init(&sw_desc->async_tx.tx_list, &iop_chan->chain); | 1292 | list_splice_init(&sw_desc->async_tx.tx_list, &iop_chan->chain); |
1290 | sw_desc->async_tx.ack = 1; | 1293 | async_tx_ack(&sw_desc->async_tx); |
1291 | iop_desc_init_memcpy(grp_start, 0); | 1294 | iop_desc_init_memcpy(grp_start, 0); |
1292 | iop_desc_set_byte_count(grp_start, iop_chan, 0); | 1295 | iop_desc_set_byte_count(grp_start, iop_chan, 0); |
1293 | iop_desc_set_dest_addr(grp_start, iop_chan, 0); | 1296 | iop_desc_set_dest_addr(grp_start, iop_chan, 0); |
@@ -1343,7 +1346,7 @@ static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan) | |||
1343 | if (sw_desc) { | 1346 | if (sw_desc) { |
1344 | grp_start = sw_desc->group_head; | 1347 | grp_start = sw_desc->group_head; |
1345 | list_splice_init(&sw_desc->async_tx.tx_list, &iop_chan->chain); | 1348 | list_splice_init(&sw_desc->async_tx.tx_list, &iop_chan->chain); |
1346 | sw_desc->async_tx.ack = 1; | 1349 | async_tx_ack(&sw_desc->async_tx); |
1347 | iop_desc_init_null_xor(grp_start, 2, 0); | 1350 | iop_desc_init_null_xor(grp_start, 2, 0); |
1348 | iop_desc_set_byte_count(grp_start, iop_chan, 0); | 1351 | iop_desc_set_byte_count(grp_start, iop_chan, 0); |
1349 | iop_desc_set_dest_addr(grp_start, iop_chan, 0); | 1352 | iop_desc_set_dest_addr(grp_start, iop_chan, 0); |