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authorChris Leech <christopher.leech@intel.com>2006-05-23 20:35:34 -0400
committerDavid S. Miller <davem@sunset.davemloft.net>2006-06-18 00:18:46 -0400
commit0bbd5f4e97ff9c057b385a1886b4aed1fb0300f1 (patch)
tree0c3d8528c31e8291fb78c2e7a287910987ed2888 /drivers/dma/ioatdma_hw.h
parentc13c8260da3155f2cefb63b0d1b7dcdcb405c644 (diff)
[I/OAT]: Driver for the Intel(R) I/OAT DMA engine
Adds a new ioatdma driver Signed-off-by: Chris Leech <christopher.leech@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/dma/ioatdma_hw.h')
-rw-r--r--drivers/dma/ioatdma_hw.h52
1 files changed, 52 insertions, 0 deletions
diff --git a/drivers/dma/ioatdma_hw.h b/drivers/dma/ioatdma_hw.h
new file mode 100644
index 000000000000..4d7a12880be3
--- /dev/null
+++ b/drivers/dma/ioatdma_hw.h
@@ -0,0 +1,52 @@
1/*
2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
20 */
21#ifndef _IOAT_HW_H_
22#define _IOAT_HW_H_
23
24/* PCI Configuration Space Values */
25#define IOAT_PCI_VID 0x8086
26#define IOAT_PCI_DID 0x1A38
27#define IOAT_PCI_RID 0x00
28#define IOAT_PCI_SVID 0x8086
29#define IOAT_PCI_SID 0x8086
30#define IOAT_VER 0x12 /* Version 1.2 */
31
32struct ioat_dma_descriptor {
33 uint32_t size;
34 uint32_t ctl;
35 uint64_t src_addr;
36 uint64_t dst_addr;
37 uint64_t next;
38 uint64_t rsv1;
39 uint64_t rsv2;
40 uint64_t user1;
41 uint64_t user2;
42};
43
44#define IOAT_DMA_DESCRIPTOR_CTL_INT_GN 0x00000001
45#define IOAT_DMA_DESCRIPTOR_CTL_SRC_SN 0x00000002
46#define IOAT_DMA_DESCRIPTOR_CTL_DST_SN 0x00000004
47#define IOAT_DMA_DESCRIPTOR_CTL_CP_STS 0x00000008
48#define IOAT_DMA_DESCRIPTOR_CTL_FRAME 0x00000010
49#define IOAT_DMA_DESCRIPTOR_NUL 0x00000020
50#define IOAT_DMA_DESCRIPTOR_OPCODE 0xFF000000
51
52#endif