aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/dma/ioat_dma.c
diff options
context:
space:
mode:
authorDan Williams <dan.j.williams@intel.com>2008-04-17 23:17:26 -0400
committerDan Williams <dan.j.williams@intel.com>2008-04-17 16:25:54 -0400
commit636bdeaa1243327501edfd2a597ed7443eb4239a (patch)
tree59b894f124e3664ea4a537d7c07c527abdb9c8da /drivers/dma/ioat_dma.c
parentc4fe15541d0ef5cc8cc1ce43057663851f8fc387 (diff)
dmaengine: ack to flags: make use of the unused bits in the 'ack' field
'ack' is currently a simple integer that flags whether or not a client is done touching fields in the given descriptor. It is effectively just a single bit of information. Converting this to a flags parameter allows the other bits to be put to use to control completion actions, like dma-unmap, and capture results, like xor-zero-sum == 0. Changes are one of: 1/ convert all open-coded ->ack manipulations to use async_tx_ack and async_tx_test_ack. 2/ set the ack bit at prep time where possible 3/ make drivers store the flags at prep time 4/ add flags to the device_prep_dma_interrupt prototype Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/dma/ioat_dma.c')
-rw-r--r--drivers/dma/ioat_dma.c24
1 files changed, 12 insertions, 12 deletions
diff --git a/drivers/dma/ioat_dma.c b/drivers/dma/ioat_dma.c
index 1517fe4e2d14..318e8a22d814 100644
--- a/drivers/dma/ioat_dma.c
+++ b/drivers/dma/ioat_dma.c
@@ -212,14 +212,14 @@ static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx)
212 u32 copy; 212 u32 copy;
213 size_t len; 213 size_t len;
214 dma_addr_t src, dst; 214 dma_addr_t src, dst;
215 int orig_ack; 215 unsigned long orig_flags;
216 unsigned int desc_count = 0; 216 unsigned int desc_count = 0;
217 217
218 /* src and dest and len are stored in the initial descriptor */ 218 /* src and dest and len are stored in the initial descriptor */
219 len = first->len; 219 len = first->len;
220 src = first->src; 220 src = first->src;
221 dst = first->dst; 221 dst = first->dst;
222 orig_ack = first->async_tx.ack; 222 orig_flags = first->async_tx.flags;
223 new = first; 223 new = first;
224 224
225 spin_lock_bh(&ioat_chan->desc_lock); 225 spin_lock_bh(&ioat_chan->desc_lock);
@@ -228,7 +228,7 @@ static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx)
228 do { 228 do {
229 copy = min_t(size_t, len, ioat_chan->xfercap); 229 copy = min_t(size_t, len, ioat_chan->xfercap);
230 230
231 new->async_tx.ack = 1; 231 async_tx_ack(&new->async_tx);
232 232
233 hw = new->hw; 233 hw = new->hw;
234 hw->size = copy; 234 hw->size = copy;
@@ -264,7 +264,7 @@ static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx)
264 } 264 }
265 265
266 new->tx_cnt = desc_count; 266 new->tx_cnt = desc_count;
267 new->async_tx.ack = orig_ack; /* client is in control of this ack */ 267 new->async_tx.flags = orig_flags; /* client is in control of this ack */
268 268
269 /* store the original values for use in later cleanup */ 269 /* store the original values for use in later cleanup */
270 if (new != first) { 270 if (new != first) {
@@ -304,14 +304,14 @@ static dma_cookie_t ioat2_tx_submit(struct dma_async_tx_descriptor *tx)
304 u32 copy; 304 u32 copy;
305 size_t len; 305 size_t len;
306 dma_addr_t src, dst; 306 dma_addr_t src, dst;
307 int orig_ack; 307 unsigned long orig_flags;
308 unsigned int desc_count = 0; 308 unsigned int desc_count = 0;
309 309
310 /* src and dest and len are stored in the initial descriptor */ 310 /* src and dest and len are stored in the initial descriptor */
311 len = first->len; 311 len = first->len;
312 src = first->src; 312 src = first->src;
313 dst = first->dst; 313 dst = first->dst;
314 orig_ack = first->async_tx.ack; 314 orig_flags = first->async_tx.flags;
315 new = first; 315 new = first;
316 316
317 /* 317 /*
@@ -321,7 +321,7 @@ static dma_cookie_t ioat2_tx_submit(struct dma_async_tx_descriptor *tx)
321 do { 321 do {
322 copy = min_t(size_t, len, ioat_chan->xfercap); 322 copy = min_t(size_t, len, ioat_chan->xfercap);
323 323
324 new->async_tx.ack = 1; 324 async_tx_ack(&new->async_tx);
325 325
326 hw = new->hw; 326 hw = new->hw;
327 hw->size = copy; 327 hw->size = copy;
@@ -349,7 +349,7 @@ static dma_cookie_t ioat2_tx_submit(struct dma_async_tx_descriptor *tx)
349 } 349 }
350 350
351 new->tx_cnt = desc_count; 351 new->tx_cnt = desc_count;
352 new->async_tx.ack = orig_ack; /* client is in control of this ack */ 352 new->async_tx.flags = orig_flags; /* client is in control of this ack */
353 353
354 /* store the original values for use in later cleanup */ 354 /* store the original values for use in later cleanup */
355 if (new != first) { 355 if (new != first) {
@@ -714,7 +714,7 @@ static struct dma_async_tx_descriptor *ioat1_dma_prep_memcpy(
714 new->len = len; 714 new->len = len;
715 new->dst = dma_dest; 715 new->dst = dma_dest;
716 new->src = dma_src; 716 new->src = dma_src;
717 new->async_tx.ack = 0; 717 new->async_tx.flags = flags;
718 return &new->async_tx; 718 return &new->async_tx;
719 } else 719 } else
720 return NULL; 720 return NULL;
@@ -742,7 +742,7 @@ static struct dma_async_tx_descriptor *ioat2_dma_prep_memcpy(
742 new->len = len; 742 new->len = len;
743 new->dst = dma_dest; 743 new->dst = dma_dest;
744 new->src = dma_src; 744 new->src = dma_src;
745 new->async_tx.ack = 0; 745 new->async_tx.flags = flags;
746 return &new->async_tx; 746 return &new->async_tx;
747 } else 747 } else
748 return NULL; 748 return NULL;
@@ -842,7 +842,7 @@ static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan)
842 * a completed entry, but not the last, so clean 842 * a completed entry, but not the last, so clean
843 * up if the client is done with the descriptor 843 * up if the client is done with the descriptor
844 */ 844 */
845 if (desc->async_tx.ack) { 845 if (async_tx_test_ack(&desc->async_tx)) {
846 list_del(&desc->node); 846 list_del(&desc->node);
847 list_add_tail(&desc->node, 847 list_add_tail(&desc->node,
848 &ioat_chan->free_desc); 848 &ioat_chan->free_desc);
@@ -979,7 +979,7 @@ static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat_chan)
979 desc->hw->size = 0; 979 desc->hw->size = 0;
980 desc->hw->src_addr = 0; 980 desc->hw->src_addr = 0;
981 desc->hw->dst_addr = 0; 981 desc->hw->dst_addr = 0;
982 desc->async_tx.ack = 1; 982 async_tx_ack(&desc->async_tx);
983 switch (ioat_chan->device->version) { 983 switch (ioat_chan->device->version) {
984 case IOAT_VER_1_2: 984 case IOAT_VER_1_2:
985 desc->hw->next = 0; 985 desc->hw->next = 0;