diff options
author | Maciej Sosnowski <maciej.sosnowski@intel.com> | 2008-07-22 20:30:57 -0400 |
---|---|---|
committer | Dan Williams <dan.j.williams@intel.com> | 2008-07-22 20:30:57 -0400 |
commit | 7f1b358a236ee9c19657a619ac6f2dcabcaa0924 (patch) | |
tree | 04eade38d4f8da94d7051f51875ed500b49b4756 /drivers/dma/ioat_dca.c | |
parent | 16a37acaaf4aaa631ba3f83710ed6cdb1a597520 (diff) |
I/OAT: I/OAT version 3.0 support
This patch adds to ioatdma and dca modules
support for Intel I/OAT DMA engine ver.3 (aka CB3 device).
The main features of I/OAT ver.3 are:
* 8 single channel DMA devices (8 channels total)
* 8 DCA providers, each can accept 2 requesters
* 8-bit TAG values and 32-bit extended APIC IDs
Signed-off-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/dma/ioat_dca.c')
-rw-r--r-- | drivers/dma/ioat_dca.c | 244 |
1 files changed, 237 insertions, 7 deletions
diff --git a/drivers/dma/ioat_dca.c b/drivers/dma/ioat_dca.c index 9e922760b7ff..6cf622da0286 100644 --- a/drivers/dma/ioat_dca.c +++ b/drivers/dma/ioat_dca.c | |||
@@ -37,12 +37,18 @@ | |||
37 | #include "ioatdma_registers.h" | 37 | #include "ioatdma_registers.h" |
38 | 38 | ||
39 | /* | 39 | /* |
40 | * Bit 16 of a tag map entry is the "valid" bit, if it is set then bits 0:15 | 40 | * Bit 7 of a tag map entry is the "valid" bit, if it is set then bits 0:6 |
41 | * contain the bit number of the APIC ID to map into the DCA tag. If the valid | 41 | * contain the bit number of the APIC ID to map into the DCA tag. If the valid |
42 | * bit is not set, then the value must be 0 or 1 and defines the bit in the tag. | 42 | * bit is not set, then the value must be 0 or 1 and defines the bit in the tag. |
43 | */ | 43 | */ |
44 | #define DCA_TAG_MAP_VALID 0x80 | 44 | #define DCA_TAG_MAP_VALID 0x80 |
45 | 45 | ||
46 | #define DCA3_TAG_MAP_BIT_TO_INV 0x80 | ||
47 | #define DCA3_TAG_MAP_BIT_TO_SEL 0x40 | ||
48 | #define DCA3_TAG_MAP_LITERAL_VAL 0x1 | ||
49 | |||
50 | #define DCA_TAG_MAP_MASK 0xDF | ||
51 | |||
46 | /* | 52 | /* |
47 | * "Legacy" DCA systems do not implement the DCA register set in the | 53 | * "Legacy" DCA systems do not implement the DCA register set in the |
48 | * I/OAT device. Software needs direct support for their tag mappings. | 54 | * I/OAT device. Software needs direct support for their tag mappings. |
@@ -95,6 +101,7 @@ struct ioat_dca_slot { | |||
95 | }; | 101 | }; |
96 | 102 | ||
97 | #define IOAT_DCA_MAX_REQ 6 | 103 | #define IOAT_DCA_MAX_REQ 6 |
104 | #define IOAT3_DCA_MAX_REQ 2 | ||
98 | 105 | ||
99 | struct ioat_dca_priv { | 106 | struct ioat_dca_priv { |
100 | void __iomem *iobase; | 107 | void __iomem *iobase; |
@@ -171,7 +178,9 @@ static int ioat_dca_remove_requester(struct dca_provider *dca, | |||
171 | return -ENODEV; | 178 | return -ENODEV; |
172 | } | 179 | } |
173 | 180 | ||
174 | static u8 ioat_dca_get_tag(struct dca_provider *dca, int cpu) | 181 | static u8 ioat_dca_get_tag(struct dca_provider *dca, |
182 | struct device *dev, | ||
183 | int cpu) | ||
175 | { | 184 | { |
176 | struct ioat_dca_priv *ioatdca = dca_priv(dca); | 185 | struct ioat_dca_priv *ioatdca = dca_priv(dca); |
177 | int i, apic_id, bit, value; | 186 | int i, apic_id, bit, value; |
@@ -193,10 +202,26 @@ static u8 ioat_dca_get_tag(struct dca_provider *dca, int cpu) | |||
193 | return tag; | 202 | return tag; |
194 | } | 203 | } |
195 | 204 | ||
205 | static int ioat_dca_dev_managed(struct dca_provider *dca, | ||
206 | struct device *dev) | ||
207 | { | ||
208 | struct ioat_dca_priv *ioatdca = dca_priv(dca); | ||
209 | struct pci_dev *pdev; | ||
210 | int i; | ||
211 | |||
212 | pdev = to_pci_dev(dev); | ||
213 | for (i = 0; i < ioatdca->max_requesters; i++) { | ||
214 | if (ioatdca->req_slots[i].pdev == pdev) | ||
215 | return 1; | ||
216 | } | ||
217 | return 0; | ||
218 | } | ||
219 | |||
196 | static struct dca_ops ioat_dca_ops = { | 220 | static struct dca_ops ioat_dca_ops = { |
197 | .add_requester = ioat_dca_add_requester, | 221 | .add_requester = ioat_dca_add_requester, |
198 | .remove_requester = ioat_dca_remove_requester, | 222 | .remove_requester = ioat_dca_remove_requester, |
199 | .get_tag = ioat_dca_get_tag, | 223 | .get_tag = ioat_dca_get_tag, |
224 | .dev_managed = ioat_dca_dev_managed, | ||
200 | }; | 225 | }; |
201 | 226 | ||
202 | 227 | ||
@@ -207,6 +232,8 @@ struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase) | |||
207 | u8 *tag_map = NULL; | 232 | u8 *tag_map = NULL; |
208 | int i; | 233 | int i; |
209 | int err; | 234 | int err; |
235 | u8 version; | ||
236 | u8 max_requesters; | ||
210 | 237 | ||
211 | if (!system_has_dca_enabled(pdev)) | 238 | if (!system_has_dca_enabled(pdev)) |
212 | return NULL; | 239 | return NULL; |
@@ -237,15 +264,20 @@ struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase) | |||
237 | if (tag_map == NULL) | 264 | if (tag_map == NULL) |
238 | return NULL; | 265 | return NULL; |
239 | 266 | ||
267 | version = readb(iobase + IOAT_VER_OFFSET); | ||
268 | if (version == IOAT_VER_3_0) | ||
269 | max_requesters = IOAT3_DCA_MAX_REQ; | ||
270 | else | ||
271 | max_requesters = IOAT_DCA_MAX_REQ; | ||
272 | |||
240 | dca = alloc_dca_provider(&ioat_dca_ops, | 273 | dca = alloc_dca_provider(&ioat_dca_ops, |
241 | sizeof(*ioatdca) + | 274 | sizeof(*ioatdca) + |
242 | (sizeof(struct ioat_dca_slot) * IOAT_DCA_MAX_REQ)); | 275 | (sizeof(struct ioat_dca_slot) * max_requesters)); |
243 | if (!dca) | 276 | if (!dca) |
244 | return NULL; | 277 | return NULL; |
245 | 278 | ||
246 | ioatdca = dca_priv(dca); | 279 | ioatdca = dca_priv(dca); |
247 | ioatdca->max_requesters = IOAT_DCA_MAX_REQ; | 280 | ioatdca->max_requesters = max_requesters; |
248 | |||
249 | ioatdca->dca_base = iobase + 0x54; | 281 | ioatdca->dca_base = iobase + 0x54; |
250 | 282 | ||
251 | /* copy over the APIC ID to DCA tag mapping */ | 283 | /* copy over the APIC ID to DCA tag mapping */ |
@@ -323,11 +355,13 @@ static int ioat2_dca_remove_requester(struct dca_provider *dca, | |||
323 | return -ENODEV; | 355 | return -ENODEV; |
324 | } | 356 | } |
325 | 357 | ||
326 | static u8 ioat2_dca_get_tag(struct dca_provider *dca, int cpu) | 358 | static u8 ioat2_dca_get_tag(struct dca_provider *dca, |
359 | struct device *dev, | ||
360 | int cpu) | ||
327 | { | 361 | { |
328 | u8 tag; | 362 | u8 tag; |
329 | 363 | ||
330 | tag = ioat_dca_get_tag(dca, cpu); | 364 | tag = ioat_dca_get_tag(dca, dev, cpu); |
331 | tag = (~tag) & 0x1F; | 365 | tag = (~tag) & 0x1F; |
332 | return tag; | 366 | return tag; |
333 | } | 367 | } |
@@ -336,6 +370,7 @@ static struct dca_ops ioat2_dca_ops = { | |||
336 | .add_requester = ioat2_dca_add_requester, | 370 | .add_requester = ioat2_dca_add_requester, |
337 | .remove_requester = ioat2_dca_remove_requester, | 371 | .remove_requester = ioat2_dca_remove_requester, |
338 | .get_tag = ioat2_dca_get_tag, | 372 | .get_tag = ioat2_dca_get_tag, |
373 | .dev_managed = ioat_dca_dev_managed, | ||
339 | }; | 374 | }; |
340 | 375 | ||
341 | static int ioat2_dca_count_dca_slots(void __iomem *iobase, u16 dca_offset) | 376 | static int ioat2_dca_count_dca_slots(void __iomem *iobase, u16 dca_offset) |
@@ -425,3 +460,198 @@ struct dca_provider *ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase) | |||
425 | 460 | ||
426 | return dca; | 461 | return dca; |
427 | } | 462 | } |
463 | |||
464 | static int ioat3_dca_add_requester(struct dca_provider *dca, struct device *dev) | ||
465 | { | ||
466 | struct ioat_dca_priv *ioatdca = dca_priv(dca); | ||
467 | struct pci_dev *pdev; | ||
468 | int i; | ||
469 | u16 id; | ||
470 | u16 global_req_table; | ||
471 | |||
472 | /* This implementation only supports PCI-Express */ | ||
473 | if (dev->bus != &pci_bus_type) | ||
474 | return -ENODEV; | ||
475 | pdev = to_pci_dev(dev); | ||
476 | id = dcaid_from_pcidev(pdev); | ||
477 | |||
478 | if (ioatdca->requester_count == ioatdca->max_requesters) | ||
479 | return -ENODEV; | ||
480 | |||
481 | for (i = 0; i < ioatdca->max_requesters; i++) { | ||
482 | if (ioatdca->req_slots[i].pdev == NULL) { | ||
483 | /* found an empty slot */ | ||
484 | ioatdca->requester_count++; | ||
485 | ioatdca->req_slots[i].pdev = pdev; | ||
486 | ioatdca->req_slots[i].rid = id; | ||
487 | global_req_table = | ||
488 | readw(ioatdca->dca_base + IOAT3_DCA_GREQID_OFFSET); | ||
489 | writel(id | IOAT_DCA_GREQID_VALID, | ||
490 | ioatdca->iobase + global_req_table + (i * 4)); | ||
491 | return i; | ||
492 | } | ||
493 | } | ||
494 | /* Error, ioatdma->requester_count is out of whack */ | ||
495 | return -EFAULT; | ||
496 | } | ||
497 | |||
498 | static int ioat3_dca_remove_requester(struct dca_provider *dca, | ||
499 | struct device *dev) | ||
500 | { | ||
501 | struct ioat_dca_priv *ioatdca = dca_priv(dca); | ||
502 | struct pci_dev *pdev; | ||
503 | int i; | ||
504 | u16 global_req_table; | ||
505 | |||
506 | /* This implementation only supports PCI-Express */ | ||
507 | if (dev->bus != &pci_bus_type) | ||
508 | return -ENODEV; | ||
509 | pdev = to_pci_dev(dev); | ||
510 | |||
511 | for (i = 0; i < ioatdca->max_requesters; i++) { | ||
512 | if (ioatdca->req_slots[i].pdev == pdev) { | ||
513 | global_req_table = | ||
514 | readw(ioatdca->dca_base + IOAT3_DCA_GREQID_OFFSET); | ||
515 | writel(0, ioatdca->iobase + global_req_table + (i * 4)); | ||
516 | ioatdca->req_slots[i].pdev = NULL; | ||
517 | ioatdca->req_slots[i].rid = 0; | ||
518 | ioatdca->requester_count--; | ||
519 | return i; | ||
520 | } | ||
521 | } | ||
522 | return -ENODEV; | ||
523 | } | ||
524 | |||
525 | static u8 ioat3_dca_get_tag(struct dca_provider *dca, | ||
526 | struct device *dev, | ||
527 | int cpu) | ||
528 | { | ||
529 | u8 tag; | ||
530 | |||
531 | struct ioat_dca_priv *ioatdca = dca_priv(dca); | ||
532 | int i, apic_id, bit, value; | ||
533 | u8 entry; | ||
534 | |||
535 | tag = 0; | ||
536 | apic_id = cpu_physical_id(cpu); | ||
537 | |||
538 | for (i = 0; i < IOAT_TAG_MAP_LEN; i++) { | ||
539 | entry = ioatdca->tag_map[i]; | ||
540 | if (entry & DCA3_TAG_MAP_BIT_TO_SEL) { | ||
541 | bit = entry & | ||
542 | ~(DCA3_TAG_MAP_BIT_TO_SEL | DCA3_TAG_MAP_BIT_TO_INV); | ||
543 | value = (apic_id & (1 << bit)) ? 1 : 0; | ||
544 | } else if (entry & DCA3_TAG_MAP_BIT_TO_INV) { | ||
545 | bit = entry & ~DCA3_TAG_MAP_BIT_TO_INV; | ||
546 | value = (apic_id & (1 << bit)) ? 0 : 1; | ||
547 | } else { | ||
548 | value = (entry & DCA3_TAG_MAP_LITERAL_VAL) ? 1 : 0; | ||
549 | } | ||
550 | tag |= (value << i); | ||
551 | } | ||
552 | |||
553 | return tag; | ||
554 | } | ||
555 | |||
556 | static struct dca_ops ioat3_dca_ops = { | ||
557 | .add_requester = ioat3_dca_add_requester, | ||
558 | .remove_requester = ioat3_dca_remove_requester, | ||
559 | .get_tag = ioat3_dca_get_tag, | ||
560 | .dev_managed = ioat_dca_dev_managed, | ||
561 | }; | ||
562 | |||
563 | static int ioat3_dca_count_dca_slots(void *iobase, u16 dca_offset) | ||
564 | { | ||
565 | int slots = 0; | ||
566 | u32 req; | ||
567 | u16 global_req_table; | ||
568 | |||
569 | global_req_table = readw(iobase + dca_offset + IOAT3_DCA_GREQID_OFFSET); | ||
570 | if (global_req_table == 0) | ||
571 | return 0; | ||
572 | |||
573 | do { | ||
574 | req = readl(iobase + global_req_table + (slots * sizeof(u32))); | ||
575 | slots++; | ||
576 | } while ((req & IOAT_DCA_GREQID_LASTID) == 0); | ||
577 | |||
578 | return slots; | ||
579 | } | ||
580 | |||
581 | struct dca_provider *ioat3_dca_init(struct pci_dev *pdev, void __iomem *iobase) | ||
582 | { | ||
583 | struct dca_provider *dca; | ||
584 | struct ioat_dca_priv *ioatdca; | ||
585 | int slots; | ||
586 | int i; | ||
587 | int err; | ||
588 | u16 dca_offset; | ||
589 | u16 csi_fsb_control; | ||
590 | u16 pcie_control; | ||
591 | u8 bit; | ||
592 | |||
593 | union { | ||
594 | u64 full; | ||
595 | struct { | ||
596 | u32 low; | ||
597 | u32 high; | ||
598 | }; | ||
599 | } tag_map; | ||
600 | |||
601 | if (!system_has_dca_enabled(pdev)) | ||
602 | return NULL; | ||
603 | |||
604 | dca_offset = readw(iobase + IOAT_DCAOFFSET_OFFSET); | ||
605 | if (dca_offset == 0) | ||
606 | return NULL; | ||
607 | |||
608 | slots = ioat3_dca_count_dca_slots(iobase, dca_offset); | ||
609 | if (slots == 0) | ||
610 | return NULL; | ||
611 | |||
612 | dca = alloc_dca_provider(&ioat3_dca_ops, | ||
613 | sizeof(*ioatdca) | ||
614 | + (sizeof(struct ioat_dca_slot) * slots)); | ||
615 | if (!dca) | ||
616 | return NULL; | ||
617 | |||
618 | ioatdca = dca_priv(dca); | ||
619 | ioatdca->iobase = iobase; | ||
620 | ioatdca->dca_base = iobase + dca_offset; | ||
621 | ioatdca->max_requesters = slots; | ||
622 | |||
623 | /* some bios might not know to turn these on */ | ||
624 | csi_fsb_control = readw(ioatdca->dca_base + IOAT3_CSI_CONTROL_OFFSET); | ||
625 | if ((csi_fsb_control & IOAT3_CSI_CONTROL_PREFETCH) == 0) { | ||
626 | csi_fsb_control |= IOAT3_CSI_CONTROL_PREFETCH; | ||
627 | writew(csi_fsb_control, | ||
628 | ioatdca->dca_base + IOAT3_CSI_CONTROL_OFFSET); | ||
629 | } | ||
630 | pcie_control = readw(ioatdca->dca_base + IOAT3_PCI_CONTROL_OFFSET); | ||
631 | if ((pcie_control & IOAT3_PCI_CONTROL_MEMWR) == 0) { | ||
632 | pcie_control |= IOAT3_PCI_CONTROL_MEMWR; | ||
633 | writew(pcie_control, | ||
634 | ioatdca->dca_base + IOAT3_PCI_CONTROL_OFFSET); | ||
635 | } | ||
636 | |||
637 | |||
638 | /* TODO version, compatibility and configuration checks */ | ||
639 | |||
640 | /* copy out the APIC to DCA tag map */ | ||
641 | tag_map.low = | ||
642 | readl(ioatdca->dca_base + IOAT3_APICID_TAG_MAP_OFFSET_LOW); | ||
643 | tag_map.high = | ||
644 | readl(ioatdca->dca_base + IOAT3_APICID_TAG_MAP_OFFSET_HIGH); | ||
645 | for (i = 0; i < 8; i++) { | ||
646 | bit = tag_map.full >> (8 * i); | ||
647 | ioatdca->tag_map[i] = bit & DCA_TAG_MAP_MASK; | ||
648 | } | ||
649 | |||
650 | err = register_dca_provider(dca, &pdev->dev); | ||
651 | if (err) { | ||
652 | free_dca_provider(dca); | ||
653 | return NULL; | ||
654 | } | ||
655 | |||
656 | return dca; | ||
657 | } | ||