ioat: switch watchdog and reset handler from workqueue to timer

In order to support dynamic resizing of the descriptor ring or polling
for a descriptor in the presence of a hung channel the reset handler
needs to make progress while in a non-preemptible context.  The current
workqueue implementation precludes polling channel reset completion
under spin_lock().

This conversion also allows us to return to opportunistic cleanup in the
ioat2 case as the timer implementation guarantees at least one cleanup
after every descriptor is submitted.  This means the worst case
completion latency becomes the timer frequency (for exceptional
circumstances), but with the benefit of avoiding busy waiting when the
lock is contended.

Signed-off-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>

1 files changed, 11 insertions, 11 deletions

diff --git a/drivers/dma/ioat/registers.h b/drivers/dma/ioat/registers.h
index 4380f6fbf056..e4334a195380 100644
--- a/drivers/dma/ioat/registers.h
+++ b/drivers/dma/ioat/registers.h
@@ -101,11 +101,11 @@
 #define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR  (~0x3fULL)
 #define IOAT_CHANSTS_SOFT_ERR                   0x10ULL
 #define IOAT_CHANSTS_UNAFFILIATED_ERR           0x8ULL
-#define IOAT_CHANSTS_DMA_TRANSFER_STATUS        0x7ULL
-#define IOAT_CHANSTS_DMA_TRANSFER_STATUS_ACTIVE 0x0
-#define IOAT_CHANSTS_DMA_TRANSFER_STATUS_DONE   0x1
-#define IOAT_CHANSTS_DMA_TRANSFER_STATUS_SUSPENDED      0x2
-#define IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED 0x3
+#define IOAT_CHANSTS_STATUS     0x7ULL
+#define IOAT_CHANSTS_ACTIVE     0x0
+#define IOAT_CHANSTS_DONE       0x1
+#define IOAT_CHANSTS_SUSPENDED  0x2
+#define IOAT_CHANSTS_HALTED     0x3
 
 
 
@@ -208,18 +208,18 @@
 #define IOAT_CDAR_OFFSET_HIGH                   0x24
 
 #define IOAT_CHANERR_OFFSET                     0x28    /* 32-bit Channel Error Register */
-#define IOAT_CHANERR_DMA_TRANSFER_SRC_ADDR_ERR  0x0001
-#define IOAT_CHANERR_DMA_TRANSFER_DEST_ADDR_ERR 0x0002
-#define IOAT_CHANERR_NEXT_DESCRIPTOR_ADDR_ERR   0x0004
-#define IOAT_CHANERR_NEXT_DESCRIPTOR_ALIGNMENT_ERR      0x0008
+#define IOAT_CHANERR_SRC_ADDR_ERR       0x0001
+#define IOAT_CHANERR_DEST_ADDR_ERR      0x0002
+#define IOAT_CHANERR_NEXT_ADDR_ERR      0x0004
+#define IOAT_CHANERR_NEXT_DESC_ALIGN_ERR        0x0008
 #define IOAT_CHANERR_CHAIN_ADDR_VALUE_ERR       0x0010
 #define IOAT_CHANERR_CHANCMD_ERR                0x0020
 #define IOAT_CHANERR_CHIPSET_UNCORRECTABLE_DATA_INTEGRITY_ERR   0x0040
 #define IOAT_CHANERR_DMA_UNCORRECTABLE_DATA_INTEGRITY_ERR       0x0080
 #define IOAT_CHANERR_READ_DATA_ERR              0x0100
 #define IOAT_CHANERR_WRITE_DATA_ERR             0x0200
-#define IOAT_CHANERR_DESCRIPTOR_CONTROL_ERR     0x0400
-#define IOAT_CHANERR_DESCRIPTOR_LENGTH_ERR      0x0800
+#define IOAT_CHANERR_CONTROL_ERR        0x0400
+#define IOAT_CHANERR_LENGTH_ERR 0x0800
 #define IOAT_CHANERR_COMPLETION_ADDR_ERR        0x1000
 #define IOAT_CHANERR_INT_CONFIGURATION_ERR      0x2000
 #define IOAT_CHANERR_SOFT_ERR                   0x4000