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authorDan Williams <dan.j.williams@intel.com>2009-09-08 15:01:21 -0400
committerDan Williams <dan.j.williams@intel.com>2009-09-08 20:30:24 -0400
commitf6ab95b55735fa03cad8d0f966647e5df206e207 (patch)
tree958127a8b5e171d53d26cd1a40d128e34bf8c7b1 /drivers/dma/ioat/dma.c
parentbb3207863014c7310593146f11fbc6573eab43c8 (diff)
ioat: preserve chanctrl bits when re-arming interrupts
The register write in ioat_dma_cleanup_tasklet is unfortunate in two ways: 1/ It clears the extra 'enable' bits that we set at alloc_chan_resources time 2/ It gives the impression that it disables interrupts when it is in fact re-arming interrupts [ Impact: fix, persist the value of the chanctrl register when re-arming ] Signed-off-by: Maciej Sosnowski <maciej.sosnowski@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/dma/ioat/dma.c')
-rw-r--r--drivers/dma/ioat/dma.c10
1 files changed, 3 insertions, 7 deletions
diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c
index 5173ba97ba31..6dd0af194b8a 100644
--- a/drivers/dma/ioat/dma.c
+++ b/drivers/dma/ioat/dma.c
@@ -452,7 +452,6 @@ static int ioat1_dma_alloc_chan_resources(struct dma_chan *c)
452 struct ioat_dma_chan *ioat = to_ioat_chan(c); 452 struct ioat_dma_chan *ioat = to_ioat_chan(c);
453 struct ioat_chan_common *chan = &ioat->base; 453 struct ioat_chan_common *chan = &ioat->base;
454 struct ioat_desc_sw *desc; 454 struct ioat_desc_sw *desc;
455 u16 chanctrl;
456 u32 chanerr; 455 u32 chanerr;
457 int i; 456 int i;
458 LIST_HEAD(tmp_list); 457 LIST_HEAD(tmp_list);
@@ -462,10 +461,7 @@ static int ioat1_dma_alloc_chan_resources(struct dma_chan *c)
462 return ioat->desccount; 461 return ioat->desccount;
463 462
464 /* Setup register to interrupt and write completion status on error */ 463 /* Setup register to interrupt and write completion status on error */
465 chanctrl = IOAT_CHANCTRL_ERR_INT_EN | 464 writew(IOAT_CHANCTRL_RUN, chan->reg_base + IOAT_CHANCTRL_OFFSET);
466 IOAT_CHANCTRL_ANY_ERR_ABORT_EN |
467 IOAT_CHANCTRL_ERR_COMPLETION_EN;
468 writew(chanctrl, chan->reg_base + IOAT_CHANCTRL_OFFSET);
469 465
470 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); 466 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
471 if (chanerr) { 467 if (chanerr) {
@@ -672,9 +668,9 @@ ioat1_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest,
672static void ioat1_cleanup_tasklet(unsigned long data) 668static void ioat1_cleanup_tasklet(unsigned long data)
673{ 669{
674 struct ioat_dma_chan *chan = (void *)data; 670 struct ioat_dma_chan *chan = (void *)data;
671
675 ioat1_cleanup(chan); 672 ioat1_cleanup(chan);
676 writew(IOAT_CHANCTRL_INT_DISABLE, 673 writew(IOAT_CHANCTRL_RUN, chan->base.reg_base + IOAT_CHANCTRL_OFFSET);
677 chan->base.reg_base + IOAT_CHANCTRL_OFFSET);
678} 674}
679 675
680static void ioat_unmap(struct pci_dev *pdev, dma_addr_t addr, size_t len, 676static void ioat_unmap(struct pci_dev *pdev, dma_addr_t addr, size_t len,