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authorDan Williams <dan.j.williams@intel.com>2009-09-08 20:42:56 -0400
committerDan Williams <dan.j.williams@intel.com>2009-09-08 20:42:56 -0400
commit5669e31c5a4874f1634bc0ffba268a6e2fa0cdd2 (patch)
tree3ef3f6724e7a812ba83b420c3915c4a46762aeb7 /drivers/dma/ioat/dma.c
parentbf40a6869c9198bdf56fe173961feb89e9f0d961 (diff)
ioat: add 'ioat' sysfs attributes
Export driver attributes for diagnostic purposes: 'ring_size': total number of descriptors available to the engine 'ring_active': number of descriptors in-flight 'capabilities': supported operation types for this channel 'version': Intel(R) QuickData specfication revision This also allows some chattiness to be removed from the driver startup as this information is now available via sysfs. Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/dma/ioat/dma.c')
-rw-r--r--drivers/dma/ioat/dma.c120
1 files changed, 114 insertions, 6 deletions
diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c
index 70262c0131d9..cb08f8108496 100644
--- a/drivers/dma/ioat/dma.c
+++ b/drivers/dma/ioat/dma.c
@@ -263,6 +263,7 @@ static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx)
263 if (!test_and_set_bit(IOAT_COMPLETION_PENDING, &chan->state)) 263 if (!test_and_set_bit(IOAT_COMPLETION_PENDING, &chan->state))
264 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); 264 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
265 265
266 ioat->active += desc->hw->tx_cnt;
266 ioat->pending += desc->hw->tx_cnt; 267 ioat->pending += desc->hw->tx_cnt;
267 if (ioat->pending >= ioat_pending_level) 268 if (ioat->pending >= ioat_pending_level)
268 __ioat1_dma_memcpy_issue_pending(ioat); 269 __ioat1_dma_memcpy_issue_pending(ioat);
@@ -611,6 +612,7 @@ static void __cleanup(struct ioat_dma_chan *ioat, unsigned long phys_complete)
611 chan->completed_cookie = tx->cookie; 612 chan->completed_cookie = tx->cookie;
612 tx->cookie = 0; 613 tx->cookie = 0;
613 ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw); 614 ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw);
615 ioat->active -= desc->hw->tx_cnt;
614 if (tx->callback) { 616 if (tx->callback) {
615 tx->callback(tx->callback_param); 617 tx->callback(tx->callback_param);
616 tx->callback = NULL; 618 tx->callback = NULL;
@@ -1028,13 +1030,8 @@ int __devinit ioat_probe(struct ioatdma_device *device)
1028 dma_cap_set(DMA_MEMCPY, dma->cap_mask); 1030 dma_cap_set(DMA_MEMCPY, dma->cap_mask);
1029 dma->dev = &pdev->dev; 1031 dma->dev = &pdev->dev;
1030 1032
1031 dev_err(dev, "Intel(R) I/OAT DMA Engine found,"
1032 " %d channels, device version 0x%02x, driver version %s\n",
1033 dma->chancnt, device->version, IOAT_DMA_VERSION);
1034
1035 if (!dma->chancnt) { 1033 if (!dma->chancnt) {
1036 dev_err(dev, "Intel(R) I/OAT DMA Engine problem found: " 1034 dev_err(dev, "zero channels detected\n");
1037 "zero channels detected\n");
1038 goto err_setup_interrupts; 1035 goto err_setup_interrupts;
1039 } 1036 }
1040 1037
@@ -1085,6 +1082,113 @@ static void ioat1_intr_quirk(struct ioatdma_device *device)
1085 pci_write_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, dmactrl); 1082 pci_write_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, dmactrl);
1086} 1083}
1087 1084
1085static ssize_t ring_size_show(struct dma_chan *c, char *page)
1086{
1087 struct ioat_dma_chan *ioat = to_ioat_chan(c);
1088
1089 return sprintf(page, "%d\n", ioat->desccount);
1090}
1091static struct ioat_sysfs_entry ring_size_attr = __ATTR_RO(ring_size);
1092
1093static ssize_t ring_active_show(struct dma_chan *c, char *page)
1094{
1095 struct ioat_dma_chan *ioat = to_ioat_chan(c);
1096
1097 return sprintf(page, "%d\n", ioat->active);
1098}
1099static struct ioat_sysfs_entry ring_active_attr = __ATTR_RO(ring_active);
1100
1101static ssize_t cap_show(struct dma_chan *c, char *page)
1102{
1103 struct dma_device *dma = c->device;
1104
1105 return sprintf(page, "copy%s%s%s%s%s%s\n",
1106 dma_has_cap(DMA_PQ, dma->cap_mask) ? " pq" : "",
1107 dma_has_cap(DMA_PQ_VAL, dma->cap_mask) ? " pq_val" : "",
1108 dma_has_cap(DMA_XOR, dma->cap_mask) ? " xor" : "",
1109 dma_has_cap(DMA_XOR_VAL, dma->cap_mask) ? " xor_val" : "",
1110 dma_has_cap(DMA_MEMSET, dma->cap_mask) ? " fill" : "",
1111 dma_has_cap(DMA_INTERRUPT, dma->cap_mask) ? " intr" : "");
1112
1113}
1114struct ioat_sysfs_entry ioat_cap_attr = __ATTR_RO(cap);
1115
1116static ssize_t version_show(struct dma_chan *c, char *page)
1117{
1118 struct dma_device *dma = c->device;
1119 struct ioatdma_device *device = to_ioatdma_device(dma);
1120
1121 return sprintf(page, "%d.%d\n",
1122 device->version >> 4, device->version & 0xf);
1123}
1124struct ioat_sysfs_entry ioat_version_attr = __ATTR_RO(version);
1125
1126static struct attribute *ioat1_attrs[] = {
1127 &ring_size_attr.attr,
1128 &ring_active_attr.attr,
1129 &ioat_cap_attr.attr,
1130 &ioat_version_attr.attr,
1131 NULL,
1132};
1133
1134static ssize_t
1135ioat_attr_show(struct kobject *kobj, struct attribute *attr, char *page)
1136{
1137 struct ioat_sysfs_entry *entry;
1138 struct ioat_chan_common *chan;
1139
1140 entry = container_of(attr, struct ioat_sysfs_entry, attr);
1141 chan = container_of(kobj, struct ioat_chan_common, kobj);
1142
1143 if (!entry->show)
1144 return -EIO;
1145 return entry->show(&chan->common, page);
1146}
1147
1148struct sysfs_ops ioat_sysfs_ops = {
1149 .show = ioat_attr_show,
1150};
1151
1152static struct kobj_type ioat1_ktype = {
1153 .sysfs_ops = &ioat_sysfs_ops,
1154 .default_attrs = ioat1_attrs,
1155};
1156
1157void ioat_kobject_add(struct ioatdma_device *device, struct kobj_type *type)
1158{
1159 struct dma_device *dma = &device->common;
1160 struct dma_chan *c;
1161
1162 list_for_each_entry(c, &dma->channels, device_node) {
1163 struct ioat_chan_common *chan = to_chan_common(c);
1164 struct kobject *parent = &c->dev->device.kobj;
1165 int err;
1166
1167 err = kobject_init_and_add(&chan->kobj, type, parent, "quickdata");
1168 if (err) {
1169 dev_warn(to_dev(chan),
1170 "sysfs init error (%d), continuing...\n", err);
1171 kobject_put(&chan->kobj);
1172 set_bit(IOAT_KOBJ_INIT_FAIL, &chan->state);
1173 }
1174 }
1175}
1176
1177void ioat_kobject_del(struct ioatdma_device *device)
1178{
1179 struct dma_device *dma = &device->common;
1180 struct dma_chan *c;
1181
1182 list_for_each_entry(c, &dma->channels, device_node) {
1183 struct ioat_chan_common *chan = to_chan_common(c);
1184
1185 if (!test_bit(IOAT_KOBJ_INIT_FAIL, &chan->state)) {
1186 kobject_del(&chan->kobj);
1187 kobject_put(&chan->kobj);
1188 }
1189 }
1190}
1191
1088int __devinit ioat1_dma_probe(struct ioatdma_device *device, int dca) 1192int __devinit ioat1_dma_probe(struct ioatdma_device *device, int dca)
1089{ 1193{
1090 struct pci_dev *pdev = device->pdev; 1194 struct pci_dev *pdev = device->pdev;
@@ -1107,6 +1211,8 @@ int __devinit ioat1_dma_probe(struct ioatdma_device *device, int dca)
1107 err = ioat_register(device); 1211 err = ioat_register(device);
1108 if (err) 1212 if (err)
1109 return err; 1213 return err;
1214 ioat_kobject_add(device, &ioat1_ktype);
1215
1110 if (dca) 1216 if (dca)
1111 device->dca = ioat_dca_init(pdev, device->reg_base); 1217 device->dca = ioat_dca_init(pdev, device->reg_base);
1112 1218
@@ -1119,6 +1225,8 @@ void __devexit ioat_dma_remove(struct ioatdma_device *device)
1119 1225
1120 ioat_disable_interrupts(device); 1226 ioat_disable_interrupts(device);
1121 1227
1228 ioat_kobject_del(device);
1229
1122 dma_async_device_unregister(dma); 1230 dma_async_device_unregister(dma);
1123 1231
1124 pci_pool_destroy(device->dma_pool); 1232 pci_pool_destroy(device->dma_pool);