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authorZhang Wei <wei.zhang@freescale.com>2008-03-18 21:45:00 -0400
committerDan Williams <dan.j.williams@intel.com>2008-03-18 20:00:59 -0400
commitf79abb627f033c85a6088231f20c85bc4a9bd757 (patch)
tree151538a3a33026ae516606240a13404d1f1e7037 /drivers/dma/fsldma.h
parentf920bb6f5fe21047e669381fe4dd346f6a9d3562 (diff)
fsldma: Fix the DMA halt when using DMA_INTERRUPT async_tx transfer.
The DMA_INTERRUPT async_tx is a NULL transfer, thus the BCR(count register) is 0. When the transfer started with a byte count of zero, the DMA controller will triger a PE(programming error) event and halt, not a normal interrupt. I add special codes for PE event and DMA_INTERRUPT async_tx testing. Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/dma/fsldma.h')
-rw-r--r--drivers/dma/fsldma.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h
index ba78c42121ba..fddd6aee2a63 100644
--- a/drivers/dma/fsldma.h
+++ b/drivers/dma/fsldma.h
@@ -40,6 +40,7 @@
40#define FSL_DMA_MR_EOTIE 0x00000080 40#define FSL_DMA_MR_EOTIE 0x00000080
41 41
42#define FSL_DMA_SR_CH 0x00000020 42#define FSL_DMA_SR_CH 0x00000020
43#define FSL_DMA_SR_PE 0x00000010
43#define FSL_DMA_SR_CB 0x00000004 44#define FSL_DMA_SR_CB 0x00000004
44#define FSL_DMA_SR_TE 0x00000080 45#define FSL_DMA_SR_TE 0x00000080
45#define FSL_DMA_SR_EOSI 0x00000002 46#define FSL_DMA_SR_EOSI 0x00000002