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authorIra Snyder <iws@ovro.caltech.edu>2009-05-15 14:33:20 -0400
committerLi Yang <leoli@freescale.com>2009-05-22 04:53:56 -0400
commit776c8943f2766f2819fafd88fdfbaf418ecd6e41 (patch)
tree6309f7faa86f2c0f7b843b9263ccc13bf379ec64 /drivers/dma/fsldma.c
parentbcfb7465c03a8c62c89da374677df56f6b894d44 (diff)
fsldma: snooping is not enabled for last entry in descriptor chain
On the 83xx controller, snooping is necessary for the DMA controller to ensure cache coherence with the CPU when transferring to/from RAM. The last descriptor in a chain will always have the End-of-Chain interrupt bit set, so we can set the snoop bit while adding the End-of-Chain interrupt bit. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Li Yang <leoli@freescale.com>
Diffstat (limited to 'drivers/dma/fsldma.c')
-rw-r--r--drivers/dma/fsldma.c9
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 7313a1ae5f83..ff9194d7ebb7 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -179,9 +179,14 @@ static void dma_halt(struct fsl_dma_chan *fsl_chan)
179static void set_ld_eol(struct fsl_dma_chan *fsl_chan, 179static void set_ld_eol(struct fsl_dma_chan *fsl_chan,
180 struct fsl_desc_sw *desc) 180 struct fsl_desc_sw *desc)
181{ 181{
182 u64 snoop_bits;
183
184 snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
185 ? FSL_DMA_SNEN : 0;
186
182 desc->hw.next_ln_addr = CPU_TO_DMA(fsl_chan, 187 desc->hw.next_ln_addr = CPU_TO_DMA(fsl_chan,
183 DMA_TO_CPU(fsl_chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL, 188 DMA_TO_CPU(fsl_chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
184 64); 189 | snoop_bits, 64);
185} 190}
186 191
187static void append_ld_queue(struct fsl_dma_chan *fsl_chan, 192static void append_ld_queue(struct fsl_dma_chan *fsl_chan,