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authorIra Snyder <iws@ovro.caltech.edu>2011-03-03 02:54:54 -0500
committerDan Williams <dan.j.williams@intel.com>2011-03-11 20:52:36 -0500
commite8bd84df27c5921a9ac866aef06e044590ac118f (patch)
tree2445eb4275f72c55873a6433caacc59d5088e63a /drivers/dma/fsldma.c
parentb203bd3f6b9c3db3b1979c2ff79bb2b9be8f03a3 (diff)
fsldma: move related helper functions near each other
This is a purely cosmetic cleanup. It is nice to have related functions right next to each other in the code. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/dma/fsldma.c')
-rw-r--r--drivers/dma/fsldma.c116
1 files changed, 64 insertions, 52 deletions
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 4de947a450fc..2e1af4555b0f 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -39,33 +39,9 @@
39 39
40static const char msg_ld_oom[] = "No free memory for link descriptor\n"; 40static const char msg_ld_oom[] = "No free memory for link descriptor\n";
41 41
42static void dma_init(struct fsldma_chan *chan) 42/*
43{ 43 * Register Helpers
44 /* Reset the channel */ 44 */
45 DMA_OUT(chan, &chan->regs->mr, 0, 32);
46
47 switch (chan->feature & FSL_DMA_IP_MASK) {
48 case FSL_DMA_IP_85XX:
49 /* Set the channel to below modes:
50 * EIE - Error interrupt enable
51 * EOSIE - End of segments interrupt enable (basic mode)
52 * EOLNIE - End of links interrupt enable
53 * BWC - Bandwidth sharing among channels
54 */
55 DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_BWC
56 | FSL_DMA_MR_EIE | FSL_DMA_MR_EOLNIE
57 | FSL_DMA_MR_EOSIE, 32);
58 break;
59 case FSL_DMA_IP_83XX:
60 /* Set the channel to below modes:
61 * EOTIE - End-of-transfer interrupt enable
62 * PRC_RM - PCI read multiple
63 */
64 DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EOTIE
65 | FSL_DMA_MR_PRC_RM, 32);
66 break;
67 }
68}
69 45
70static void set_sr(struct fsldma_chan *chan, u32 val) 46static void set_sr(struct fsldma_chan *chan, u32 val)
71{ 47{
@@ -77,6 +53,30 @@ static u32 get_sr(struct fsldma_chan *chan)
77 return DMA_IN(chan, &chan->regs->sr, 32); 53 return DMA_IN(chan, &chan->regs->sr, 32);
78} 54}
79 55
56static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr)
57{
58 DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64);
59}
60
61static dma_addr_t get_cdar(struct fsldma_chan *chan)
62{
63 return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN;
64}
65
66static dma_addr_t get_ndar(struct fsldma_chan *chan)
67{
68 return DMA_IN(chan, &chan->regs->ndar, 64);
69}
70
71static u32 get_bcr(struct fsldma_chan *chan)
72{
73 return DMA_IN(chan, &chan->regs->bcr, 32);
74}
75
76/*
77 * Descriptor Helpers
78 */
79
80static void set_desc_cnt(struct fsldma_chan *chan, 80static void set_desc_cnt(struct fsldma_chan *chan,
81 struct fsl_dma_ld_hw *hw, u32 count) 81 struct fsl_dma_ld_hw *hw, u32 count)
82{ 82{
@@ -113,24 +113,49 @@ static void set_desc_next(struct fsldma_chan *chan,
113 hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64); 113 hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64);
114} 114}
115 115
116static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr) 116static void set_ld_eol(struct fsldma_chan *chan,
117 struct fsl_desc_sw *desc)
117{ 118{
118 DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64); 119 u64 snoop_bits;
119}
120 120
121static dma_addr_t get_cdar(struct fsldma_chan *chan) 121 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
122{ 122 ? FSL_DMA_SNEN : 0;
123 return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN;
124}
125 123
126static dma_addr_t get_ndar(struct fsldma_chan *chan) 124 desc->hw.next_ln_addr = CPU_TO_DMA(chan,
127{ 125 DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
128 return DMA_IN(chan, &chan->regs->ndar, 64); 126 | snoop_bits, 64);
129} 127}
130 128
131static u32 get_bcr(struct fsldma_chan *chan) 129/*
130 * DMA Engine Hardware Control Helpers
131 */
132
133static void dma_init(struct fsldma_chan *chan)
132{ 134{
133 return DMA_IN(chan, &chan->regs->bcr, 32); 135 /* Reset the channel */
136 DMA_OUT(chan, &chan->regs->mr, 0, 32);
137
138 switch (chan->feature & FSL_DMA_IP_MASK) {
139 case FSL_DMA_IP_85XX:
140 /* Set the channel to below modes:
141 * EIE - Error interrupt enable
142 * EOSIE - End of segments interrupt enable (basic mode)
143 * EOLNIE - End of links interrupt enable
144 * BWC - Bandwidth sharing among channels
145 */
146 DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_BWC
147 | FSL_DMA_MR_EIE | FSL_DMA_MR_EOLNIE
148 | FSL_DMA_MR_EOSIE, 32);
149 break;
150 case FSL_DMA_IP_83XX:
151 /* Set the channel to below modes:
152 * EOTIE - End-of-transfer interrupt enable
153 * PRC_RM - PCI read multiple
154 */
155 DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EOTIE
156 | FSL_DMA_MR_PRC_RM, 32);
157 break;
158 }
134} 159}
135 160
136static int dma_is_idle(struct fsldma_chan *chan) 161static int dma_is_idle(struct fsldma_chan *chan)
@@ -185,19 +210,6 @@ static void dma_halt(struct fsldma_chan *chan)
185 dev_err(chan->dev, "DMA halt timeout!\n"); 210 dev_err(chan->dev, "DMA halt timeout!\n");
186} 211}
187 212
188static void set_ld_eol(struct fsldma_chan *chan,
189 struct fsl_desc_sw *desc)
190{
191 u64 snoop_bits;
192
193 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
194 ? FSL_DMA_SNEN : 0;
195
196 desc->hw.next_ln_addr = CPU_TO_DMA(chan,
197 DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
198 | snoop_bits, 64);
199}
200
201/** 213/**
202 * fsl_chan_set_src_loop_size - Set source address hold transfer size 214 * fsl_chan_set_src_loop_size - Set source address hold transfer size
203 * @chan : Freescale DMA channel 215 * @chan : Freescale DMA channel