diff options
author | Linus Walleij <linus.walleij@stericsson.com> | 2010-03-02 16:17:44 -0500 |
---|---|---|
committer | Dan Williams <dan.j.williams@intel.com> | 2010-03-02 16:17:44 -0500 |
commit | 0b58828c923e57f1bfbbd2c4277ceb60666314fa (patch) | |
tree | 399402924ea132fdea66a0fce141c9cae6020b8e /drivers/dma/coh901318_lli.c | |
parent | b87108a772e001af3fa79f9cfd87b190375f47a2 (diff) |
DMAENGINE: COH 901 318 remove irq counting
This removes the pointless irq counting for the COH 901 318, as
it turns out the hardware will only ever fire one IRQ for a linked
list anyway. In the process also a missing spinlock was introduced.
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/dma/coh901318_lli.c')
-rw-r--r-- | drivers/dma/coh901318_lli.c | 13 |
1 files changed, 3 insertions, 10 deletions
diff --git a/drivers/dma/coh901318_lli.c b/drivers/dma/coh901318_lli.c index f5120f238a4d..5f9af1956eab 100644 --- a/drivers/dma/coh901318_lli.c +++ b/drivers/dma/coh901318_lli.c | |||
@@ -166,8 +166,7 @@ coh901318_lli_fill_memcpy(struct coh901318_pool *pool, | |||
166 | lli->src_addr = src; | 166 | lli->src_addr = src; |
167 | lli->dst_addr = dst; | 167 | lli->dst_addr = dst; |
168 | 168 | ||
169 | /* One irq per single transfer */ | 169 | return 0; |
170 | return 1; | ||
171 | } | 170 | } |
172 | 171 | ||
173 | int | 172 | int |
@@ -223,8 +222,7 @@ coh901318_lli_fill_single(struct coh901318_pool *pool, | |||
223 | lli->src_addr = src; | 222 | lli->src_addr = src; |
224 | lli->dst_addr = dst; | 223 | lli->dst_addr = dst; |
225 | 224 | ||
226 | /* One irq per single transfer */ | 225 | return 0; |
227 | return 1; | ||
228 | } | 226 | } |
229 | 227 | ||
230 | int | 228 | int |
@@ -240,7 +238,6 @@ coh901318_lli_fill_sg(struct coh901318_pool *pool, | |||
240 | u32 ctrl_sg; | 238 | u32 ctrl_sg; |
241 | dma_addr_t src = 0; | 239 | dma_addr_t src = 0; |
242 | dma_addr_t dst = 0; | 240 | dma_addr_t dst = 0; |
243 | int nbr_of_irq = 0; | ||
244 | u32 bytes_to_transfer; | 241 | u32 bytes_to_transfer; |
245 | u32 elem_size; | 242 | u32 elem_size; |
246 | 243 | ||
@@ -269,9 +266,6 @@ coh901318_lli_fill_sg(struct coh901318_pool *pool, | |||
269 | ctrl_sg = ctrl ? ctrl : ctrl_last; | 266 | ctrl_sg = ctrl ? ctrl : ctrl_last; |
270 | 267 | ||
271 | 268 | ||
272 | if ((ctrl_sg & ctrl_irq_mask)) | ||
273 | nbr_of_irq++; | ||
274 | |||
275 | if (dir == DMA_TO_DEVICE) | 269 | if (dir == DMA_TO_DEVICE) |
276 | /* increment source address */ | 270 | /* increment source address */ |
277 | src = sg_dma_address(sg); | 271 | src = sg_dma_address(sg); |
@@ -310,8 +304,7 @@ coh901318_lli_fill_sg(struct coh901318_pool *pool, | |||
310 | } | 304 | } |
311 | spin_unlock(&pool->lock); | 305 | spin_unlock(&pool->lock); |
312 | 306 | ||
313 | /* There can be many IRQs per sg transfer */ | 307 | return 0; |
314 | return nbr_of_irq; | ||
315 | err: | 308 | err: |
316 | spin_unlock(&pool->lock); | 309 | spin_unlock(&pool->lock); |
317 | return -EINVAL; | 310 | return -EINVAL; |