aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/dma/coh901318.c
diff options
context:
space:
mode:
authorLinus Walleij <linus.walleij@linaro.org>2013-01-04 07:50:49 -0500
committerLinus Walleij <linus.walleij@linaro.org>2013-01-07 11:36:24 -0500
commit9aab4d6f087a042d702b6e16346378731eeaf48e (patch)
tree27784ff762822fd09ffb4813e98e4ef3ae98f8b9 /drivers/dma/coh901318.c
parent250eac8027c90b881408c40eeeb7b9cb8249304e (diff)
dma: coh901318: skip hard-coded addresses
Remove hard-coded target addresses altogether. Skip the prefix "runtime_*" from the variables, since all of these are now runtime and their names are unique enough already. Acked-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/dma/coh901318.c')
-rw-r--r--drivers/dma/coh901318.c35
1 files changed, 13 insertions, 22 deletions
diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c
index 15e314af22f7..7fa54fb7ab68 100644
--- a/drivers/dma/coh901318.c
+++ b/drivers/dma/coh901318.c
@@ -1141,8 +1141,8 @@ struct coh901318_chan {
1141 unsigned long nbr_active_done; 1141 unsigned long nbr_active_done;
1142 unsigned long busy; 1142 unsigned long busy;
1143 1143
1144 u32 runtime_addr; 1144 u32 addr;
1145 u32 runtime_ctrl; 1145 u32 ctrl;
1146 1146
1147 struct coh901318_base *base; 1147 struct coh901318_base *base;
1148}; 1148};
@@ -1253,15 +1253,6 @@ static inline struct coh901318_chan *to_coh901318_chan(struct dma_chan *chan)
1253 return container_of(chan, struct coh901318_chan, chan); 1253 return container_of(chan, struct coh901318_chan, chan);
1254} 1254}
1255 1255
1256static inline dma_addr_t
1257cohc_dev_addr(struct coh901318_chan *cohc)
1258{
1259 /* Runtime supplied address will take precedence */
1260 if (cohc->runtime_addr)
1261 return cohc->runtime_addr;
1262 return cohc->base->platform->chan_conf[cohc->id].dev_addr;
1263}
1264
1265static inline const struct coh901318_params * 1256static inline const struct coh901318_params *
1266cohc_chan_param(struct coh901318_chan *cohc) 1257cohc_chan_param(struct coh901318_chan *cohc)
1267{ 1258{
@@ -2118,9 +2109,9 @@ coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2118 * sure the bits you set per peripheral channel are 2109 * sure the bits you set per peripheral channel are
2119 * cleared in the default config from the platform. 2110 * cleared in the default config from the platform.
2120 */ 2111 */
2121 ctrl_chained |= cohc->runtime_ctrl; 2112 ctrl_chained |= cohc->ctrl;
2122 ctrl_last |= cohc->runtime_ctrl; 2113 ctrl_last |= cohc->ctrl;
2123 ctrl |= cohc->runtime_ctrl; 2114 ctrl |= cohc->ctrl;
2124 2115
2125 if (direction == DMA_MEM_TO_DEV) { 2116 if (direction == DMA_MEM_TO_DEV) {
2126 u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE | 2117 u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE |
@@ -2169,7 +2160,7 @@ coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2169 2160
2170 /* initiate allocated lli list */ 2161 /* initiate allocated lli list */
2171 ret = coh901318_lli_fill_sg(&cohc->base->pool, lli, sgl, sg_len, 2162 ret = coh901318_lli_fill_sg(&cohc->base->pool, lli, sgl, sg_len,
2172 cohc_dev_addr(cohc), 2163 cohc->addr,
2173 ctrl_chained, 2164 ctrl_chained,
2174 ctrl, 2165 ctrl,
2175 ctrl_last, 2166 ctrl_last,
@@ -2310,7 +2301,7 @@ static void coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
2310 dma_addr_t addr; 2301 dma_addr_t addr;
2311 enum dma_slave_buswidth addr_width; 2302 enum dma_slave_buswidth addr_width;
2312 u32 maxburst; 2303 u32 maxburst;
2313 u32 runtime_ctrl = 0; 2304 u32 ctrl = 0;
2314 int i = 0; 2305 int i = 0;
2315 2306
2316 /* We only support mem to per or per to mem transfers */ 2307 /* We only support mem to per or per to mem transfers */
@@ -2331,7 +2322,7 @@ static void coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
2331 addr_width); 2322 addr_width);
2332 switch (addr_width) { 2323 switch (addr_width) {
2333 case DMA_SLAVE_BUSWIDTH_1_BYTE: 2324 case DMA_SLAVE_BUSWIDTH_1_BYTE:
2334 runtime_ctrl |= 2325 ctrl |=
2335 COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS | 2326 COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS |
2336 COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS; 2327 COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS;
2337 2328
@@ -2343,7 +2334,7 @@ static void coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
2343 2334
2344 break; 2335 break;
2345 case DMA_SLAVE_BUSWIDTH_2_BYTES: 2336 case DMA_SLAVE_BUSWIDTH_2_BYTES:
2346 runtime_ctrl |= 2337 ctrl |=
2347 COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS | 2338 COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS |
2348 COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS; 2339 COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS;
2349 2340
@@ -2356,7 +2347,7 @@ static void coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
2356 break; 2347 break;
2357 case DMA_SLAVE_BUSWIDTH_4_BYTES: 2348 case DMA_SLAVE_BUSWIDTH_4_BYTES:
2358 /* Direction doesn't matter here, it's 32/32 bits */ 2349 /* Direction doesn't matter here, it's 32/32 bits */
2359 runtime_ctrl |= 2350 ctrl |=
2360 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 2351 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
2361 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS; 2352 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS;
2362 2353
@@ -2373,13 +2364,13 @@ static void coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
2373 return; 2364 return;
2374 } 2365 }
2375 2366
2376 runtime_ctrl |= burst_sizes[i].reg; 2367 ctrl |= burst_sizes[i].reg;
2377 dev_dbg(COHC_2_DEV(cohc), 2368 dev_dbg(COHC_2_DEV(cohc),
2378 "selected burst size %d bytes for address width %d bytes, maxburst %d\n", 2369 "selected burst size %d bytes for address width %d bytes, maxburst %d\n",
2379 burst_sizes[i].burst_8bit, addr_width, maxburst); 2370 burst_sizes[i].burst_8bit, addr_width, maxburst);
2380 2371
2381 cohc->runtime_addr = addr; 2372 cohc->addr = addr;
2382 cohc->runtime_ctrl = runtime_ctrl; 2373 cohc->ctrl = ctrl;
2383} 2374}
2384 2375
2385static int 2376static int