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authorLinus Walleij <linus.walleij@linaro.org>2011-07-01 10:47:28 -0400
committerVinod Koul <vinod.koul@intel.com>2011-07-13 19:26:59 -0400
commitb89243dd0e6a1c96a4a346cb3e1ba2c637cdfe98 (patch)
tree44cf691c79d5ce229ec0afe76d04ebd438c1576e /drivers/dma/coh901318.c
parent98ca528916c47ad17f78a07b45e49de3940fba77 (diff)
dmaengine/coh901318: fix slave submission semantics
While testing Per Forlins MMC speed improvements I noticed a semantic bug in the COH901318 driver: it will write to channel registers in the prep_slave_sg() function, instead of deferring it to later, breaking the assumption from the drivers to be able to queue up new jobs while another job is running. Fix this by storing up the initial register writes in the job descriptors and write them to hardware when we process the descriptor instead. Now the stress tests work. Acked-by: Per Forlin <per.forlin@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'drivers/dma/coh901318.c')
-rw-r--r--drivers/dma/coh901318.c19
1 files changed, 12 insertions, 7 deletions
diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c
index af8c0b5ed70f..a7fca1653933 100644
--- a/drivers/dma/coh901318.c
+++ b/drivers/dma/coh901318.c
@@ -40,6 +40,8 @@ struct coh901318_desc {
40 struct coh901318_lli *lli; 40 struct coh901318_lli *lli;
41 enum dma_data_direction dir; 41 enum dma_data_direction dir;
42 unsigned long flags; 42 unsigned long flags;
43 u32 head_config;
44 u32 head_ctrl;
43}; 45};
44 46
45struct coh901318_base { 47struct coh901318_base {
@@ -660,6 +662,9 @@ static struct coh901318_desc *coh901318_queue_start(struct coh901318_chan *cohc)
660 662
661 coh901318_desc_submit(cohc, cohd); 663 coh901318_desc_submit(cohc, cohd);
662 664
665 /* Program the transaction head */
666 coh901318_set_conf(cohc, cohd->head_config);
667 coh901318_set_ctrl(cohc, cohd->head_ctrl);
663 coh901318_prep_linked_list(cohc, cohd->lli); 668 coh901318_prep_linked_list(cohc, cohd->lli);
664 669
665 /* start dma job on this channel */ 670 /* start dma job on this channel */
@@ -1090,8 +1095,6 @@ coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
1090 } else 1095 } else
1091 goto err_direction; 1096 goto err_direction;
1092 1097
1093 coh901318_set_conf(cohc, config);
1094
1095 /* The dma only supports transmitting packages up to 1098 /* The dma only supports transmitting packages up to
1096 * MAX_DMA_PACKET_SIZE. Calculate to total number of 1099 * MAX_DMA_PACKET_SIZE. Calculate to total number of
1097 * dma elemts required to send the entire sg list 1100 * dma elemts required to send the entire sg list
@@ -1128,16 +1131,18 @@ coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
1128 if (ret) 1131 if (ret)
1129 goto err_lli_fill; 1132 goto err_lli_fill;
1130 1133
1131 /*
1132 * Set the default ctrl for the channel to the one from the lli,
1133 * things may have changed due to odd buffer alignment etc.
1134 */
1135 coh901318_set_ctrl(cohc, lli->control);
1136 1134
1137 COH_DBG(coh901318_list_print(cohc, lli)); 1135 COH_DBG(coh901318_list_print(cohc, lli));
1138 1136
1139 /* Pick a descriptor to handle this transfer */ 1137 /* Pick a descriptor to handle this transfer */
1140 cohd = coh901318_desc_get(cohc); 1138 cohd = coh901318_desc_get(cohc);
1139 cohd->head_config = config;
1140 /*
1141 * Set the default head ctrl for the channel to the one from the
1142 * lli, things may have changed due to odd buffer alignment
1143 * etc.
1144 */
1145 cohd->head_ctrl = lli->control;
1141 cohd->dir = direction; 1146 cohd->dir = direction;
1142 cohd->flags = flags; 1147 cohd->flags = flags;
1143 cohd->desc.tx_submit = coh901318_tx_submit; 1148 cohd->desc.tx_submit = coh901318_tx_submit;