Merge branch 'devfreq-for-next' of git://git.infradead.org/users/kmpark/linux-samsung into pm-devfreq

* 'devfreq-for-next' of git://git.infradead.org/users/kmpark/linux-samsung: (765 commits)
  PM/Devfreq: Add Exynos4-bus device DVFS driver for Exynos4210/4212/4412.
  pci: Fix hotplug of Express Module with pci bridges
  i2c-eg20t: correct the driver init order of pch_i2c_probe()
  I2C: OMAP: fix FIFO usage for OMAP4
  i2c-s3c2410: Fix return code of s3c24xx_i2c_parse_dt_gpio
  i2c: i2c-s3c2410: Add a cpu_relax() to busy wait for bus idle
  Linux 3.2-rc6
  Revert "drm/i915: fix infinite recursion on unbind due to ilk vt-d w/a"
  btrfs: lower the dirty balance poll interval
  drm/i915/dp: Dither down to 6bpc if it makes the mode fit
  drm/i915: enable semaphores on per-device defaults
  drm/i915: don't set unpin_work if vblank_get fails
  drm/i915: By default, enable RC6 on IVB and SNB when reasonable
  iommu: Export intel_iommu_enabled to signal when iommu is in use
  drm/i915/sdvo: Include LVDS panels for the IS_DIGITAL check
  drm/i915: prevent division by zero when asking for chipset power
  drm/i915: add PCH info to i915_capabilities
  drm/i915: set the right SDVO transcoder for CPT
  drm/i915: no-lvds quirk for ASUS AT5NM10T-I
  sched: Fix select_idle_sibling() regression in selecting an idle SMT sibling
  ...

3 files changed, 1151 insertions, 0 deletions

diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index 8f0491037080..464fa2147dfb 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -65,4 +65,17 @@ config DEVFREQ_GOV_USERSPACE
 
 comment "DEVFREQ Drivers"
 
+config ARM_EXYNOS4_BUS_DEVFREQ
+        bool "ARM Exynos4210/4212/4412 Memory Bus DEVFREQ Driver"
+        depends on CPU_EXYNOS4210 || CPU_EXYNOS4212 || CPU_EXYNOS4412
+        select ARCH_HAS_OPP
+        select DEVFREQ_GOV_SIMPLE_ONDEMAND
+        help
+          This adds the DEVFREQ driver for Exynos4210 memory bus (vdd_int)
+          and Exynos4212/4412 memory interface and bus (vdd_mif + vdd_int).
+          It reads PPMU counters of memory controllers and adjusts
+          the operating frequencies and voltages with OPP support.
+          To operate with optimal voltages, ASV support is required
+          (CONFIG_EXYNOS_ASV).
+
 endif # PM_DEVFREQ
diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
index 4564a89e970a..8c464234f7e7 100644
--- a/drivers/devfreq/Makefile
+++ b/drivers/devfreq/Makefile
@@ -3,3 +3,6 @@ obj-$(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND)	+= governor_simpleondemand.o
 obj-$(CONFIG_DEVFREQ_GOV_PERFORMANCE)   += governor_performance.o
 obj-$(CONFIG_DEVFREQ_GOV_POWERSAVE)     += governor_powersave.o
 obj-$(CONFIG_DEVFREQ_GOV_USERSPACE)     += governor_userspace.o
+
+# DEVFREQ Drivers
+obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ)   += exynos4_bus.o
diff --git a/drivers/devfreq/exynos4_bus.c b/drivers/devfreq/exynos4_bus.c
new file mode 100644
index 000000000000..6460577d6701
--- /dev/null
+++ b/drivers/devfreq/exynos4_bus.c
@@ -0,0 +1,1135 @@
+/* drivers/devfreq/exynos4210_memorybus.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *      MyungJoo Ham <myungjoo.ham@samsung.com>
+ *
+ * EXYNOS4 - Memory/Bus clock frequency scaling support in DEVFREQ framework
+ *      This version supports EXYNOS4210 only. This changes bus frequencies
+ *      and vddint voltages. Exynos4412/4212 should be able to be supported
+ *      with minor modifications.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/mutex.h>
+#include <linux/suspend.h>
+#include <linux/opp.h>
+#include <linux/devfreq.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/module.h>
+
+/* Exynos4 ASV has been in the mailing list, but not upstreamed, yet. */
+#ifdef CONFIG_EXYNOS_ASV
+extern unsigned int exynos_result_of_asv;
+#endif
+
+#include <mach/regs-clock.h>
+
+#include <plat/map-s5p.h>
+
+#define MAX_SAFEVOLT    1200000 /* 1.2V */
+
+enum exynos4_busf_type {
+        TYPE_BUSF_EXYNOS4210,
+        TYPE_BUSF_EXYNOS4x12,
+};
+
+/* Assume that the bus is saturated if the utilization is 40% */
+#define BUS_SATURATION_RATIO    40
+
+enum ppmu_counter {
+        PPMU_PMNCNT0 = 0,
+        PPMU_PMCCNT1,
+        PPMU_PMNCNT2,
+        PPMU_PMNCNT3,
+        PPMU_PMNCNT_MAX,
+};
+struct exynos4_ppmu {
+        void __iomem *hw_base;
+        unsigned int ccnt;
+        unsigned int event;
+        unsigned int count[PPMU_PMNCNT_MAX];
+        bool ccnt_overflow;
+        bool count_overflow[PPMU_PMNCNT_MAX];
+};
+
+enum busclk_level_idx {
+        LV_0 = 0,
+        LV_1,
+        LV_2,
+        LV_3,
+        LV_4,
+        _LV_END
+};
+#define EX4210_LV_MAX   LV_2
+#define EX4x12_LV_MAX   LV_4
+#define EX4210_LV_NUM   (LV_2 + 1)
+#define EX4x12_LV_NUM   (LV_4 + 1)
+
+struct busfreq_data {
+        enum exynos4_busf_type type;
+        struct device *dev;
+        struct devfreq *devfreq;
+        bool disabled;
+        struct regulator *vdd_int;
+        struct regulator *vdd_mif; /* Exynos4412/4212 only */
+        struct opp *curr_opp;
+        struct exynos4_ppmu dmc[2];
+
+        struct notifier_block pm_notifier;
+        struct mutex lock;
+
+        /* Dividers calculated at boot/probe-time */
+        unsigned int dmc_divtable[_LV_END]; /* DMC0 */
+        unsigned int top_divtable[_LV_END];
+};
+
+struct bus_opp_table {
+        unsigned int idx;
+        unsigned long clk;
+        unsigned long volt;
+};
+
+/* 4210 controls clock of mif and voltage of int */
+static struct bus_opp_table exynos4210_busclk_table[] = {
+        {LV_0, 400000, 1150000},
+        {LV_1, 267000, 1050000},
+        {LV_2, 133000, 1025000},
+        {0, 0, 0},
+};
+
+/*
+ * MIF is the main control knob clock for exynox4x12 MIF/INT
+ * clock and voltage of both mif/int are controlled.
+ */
+static struct bus_opp_table exynos4x12_mifclk_table[] = {
+        {LV_0, 400000, 1100000},
+        {LV_1, 267000, 1000000},
+        {LV_2, 160000, 950000},
+        {LV_3, 133000, 950000},
+        {LV_4, 100000, 950000},
+        {0, 0, 0},
+};
+
+/*
+ * INT is not the control knob of 4x12. LV_x is not meant to represent
+ * the current performance. (MIF does)
+ */
+static struct bus_opp_table exynos4x12_intclk_table[] = {
+        {LV_0, 200000, 1000000},
+        {LV_1, 160000, 950000},
+        {LV_2, 133000, 925000},
+        {LV_3, 100000, 900000},
+        {0, 0, 0},
+};
+
+/* TODO: asv volt definitions are "__initdata"? */
+/* Some chips have different operating voltages */
+static unsigned int exynos4210_asv_volt[][EX4210_LV_NUM] = {
+        {1150000, 1050000, 1050000},
+        {1125000, 1025000, 1025000},
+        {1100000, 1000000, 1000000},
+        {1075000, 975000, 975000},
+        {1050000, 950000, 950000},
+};
+
+static unsigned int exynos4x12_mif_step_50[][EX4x12_LV_NUM] = {
+        /* 400      267     160     133     100 */
+        {1050000, 950000, 900000, 900000, 900000}, /* ASV0 */
+        {1050000, 950000, 900000, 900000, 900000}, /* ASV1 */
+        {1050000, 950000, 900000, 900000, 900000}, /* ASV2 */
+        {1050000, 900000, 900000, 900000, 900000}, /* ASV3 */
+        {1050000, 900000, 900000, 900000, 850000}, /* ASV4 */
+        {1050000, 900000, 900000, 850000, 850000}, /* ASV5 */
+        {1050000, 900000, 850000, 850000, 850000}, /* ASV6 */
+        {1050000, 900000, 850000, 850000, 850000}, /* ASV7 */
+        {1050000, 900000, 850000, 850000, 850000}, /* ASV8 */
+};