aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/devfreq
diff options
context:
space:
mode:
authorKukjin Kim <kgene.kim@samsung.com>2013-12-18 14:17:06 -0500
committerKukjin Kim <kgene.kim@samsung.com>2013-12-18 15:21:16 -0500
commit7d8f159188410557630a7270efe3e14a1a305c2e (patch)
tree85da5cca3bd055d5864ce35ce76be7666e7e7de1 /drivers/devfreq
parent728599439fd01a6302270171f5c4e42b14fac6d0 (diff)
PM / devfreq: move definitions for exynos4_bus into drivers/devfreq
We don't need to keep the definitions for exynos4_bus into mach-exynos/ so this moves them into drviers/devfreq with adding header file. Acked-by: MyungJoo Ham <myungjoo.ham@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'drivers/devfreq')
-rw-r--r--drivers/devfreq/exynos/exynos4_bus.c4
-rw-r--r--drivers/devfreq/exynos/exynos4_bus.h110
2 files changed, 112 insertions, 2 deletions
diff --git a/drivers/devfreq/exynos/exynos4_bus.c b/drivers/devfreq/exynos/exynos4_bus.c
index cede6f71cd63..16eb406cadb6 100644
--- a/drivers/devfreq/exynos/exynos4_bus.c
+++ b/drivers/devfreq/exynos/exynos4_bus.c
@@ -30,10 +30,10 @@
30extern unsigned int exynos_result_of_asv; 30extern unsigned int exynos_result_of_asv;
31#endif 31#endif
32 32
33#include <mach/regs-clock.h>
34
35#include <plat/map-s5p.h> 33#include <plat/map-s5p.h>
36 34
35#include "exynos4_bus.h"
36
37#define MAX_SAFEVOLT 1200000 /* 1.2V */ 37#define MAX_SAFEVOLT 1200000 /* 1.2V */
38 38
39enum exynos4_busf_type { 39enum exynos4_busf_type {
diff --git a/drivers/devfreq/exynos/exynos4_bus.h b/drivers/devfreq/exynos/exynos4_bus.h
new file mode 100644
index 000000000000..94c73c18d28c
--- /dev/null
+++ b/drivers/devfreq/exynos/exynos4_bus.h
@@ -0,0 +1,110 @@
1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
4 *
5 * EXYNOS4 BUS header
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#ifndef __DEVFREQ_EXYNOS4_BUS_H
13#define __DEVFREQ_EXYNOS4_BUS_H __FILE__
14
15#include <mach/map.h>
16
17#define EXYNOS4_CLKDIV_LEFTBUS (S5P_VA_CMU + 0x04500)
18#define EXYNOS4_CLKDIV_STAT_LEFTBUS (S5P_VA_CMU + 0x04600)
19
20#define EXYNOS4_CLKDIV_RIGHTBUS (S5P_VA_CMU + 0x08500)
21#define EXYNOS4_CLKDIV_STAT_RIGHTBUS (S5P_VA_CMU + 0x08600)
22
23#define EXYNOS4_CLKDIV_TOP (S5P_VA_CMU + 0x0C510)
24#define EXYNOS4_CLKDIV_CAM (S5P_VA_CMU + 0x0C520)
25#define EXYNOS4_CLKDIV_MFC (S5P_VA_CMU + 0x0C528)
26
27#define EXYNOS4_CLKDIV_STAT_TOP (S5P_VA_CMU + 0x0C610)
28#define EXYNOS4_CLKDIV_STAT_MFC (S5P_VA_CMU + 0x0C628)
29
30#define EXYNOS4210_CLKGATE_IP_IMAGE (S5P_VA_CMU + 0x0C930)
31#define EXYNOS4212_CLKGATE_IP_IMAGE (S5P_VA_CMU + 0x04930)
32
33#define EXYNOS4_CLKDIV_DMC0 (S5P_VA_CMU + 0x10500)
34#define EXYNOS4_CLKDIV_DMC1 (S5P_VA_CMU + 0x10504)
35#define EXYNOS4_CLKDIV_STAT_DMC0 (S5P_VA_CMU + 0x10600)
36#define EXYNOS4_CLKDIV_STAT_DMC1 (S5P_VA_CMU + 0x10604)
37
38#define EXYNOS4_DMC_PAUSE_CTRL (S5P_VA_CMU + 0x11094)
39#define EXYNOS4_DMC_PAUSE_ENABLE (1 << 0)
40
41#define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT (0)
42#define EXYNOS4_CLKDIV_DMC0_ACP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT)
43#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT (4)
44#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT)
45#define EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT (8)
46#define EXYNOS4_CLKDIV_DMC0_DPHY_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT)
47#define EXYNOS4_CLKDIV_DMC0_DMC_SHIFT (12)
48#define EXYNOS4_CLKDIV_DMC0_DMC_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT)
49#define EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT (16)
50#define EXYNOS4_CLKDIV_DMC0_DMCD_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT)
51#define EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT (20)
52#define EXYNOS4_CLKDIV_DMC0_DMCP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT)
53#define EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT (24)
54#define EXYNOS4_CLKDIV_DMC0_COPY2_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT)
55#define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT (28)
56#define EXYNOS4_CLKDIV_DMC0_CORETI_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT)
57
58#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT (0)
59#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK (0xf << EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT)
60#define EXYNOS4_CLKDIV_DMC1_C2C_SHIFT (4)
61#define EXYNOS4_CLKDIV_DMC1_C2C_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2C_SHIFT)
62#define EXYNOS4_CLKDIV_DMC1_PWI_SHIFT (8)
63#define EXYNOS4_CLKDIV_DMC1_PWI_MASK (0xf << EXYNOS4_CLKDIV_DMC1_PWI_SHIFT)
64#define EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT (12)
65#define EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT)
66#define EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT (16)
67#define EXYNOS4_CLKDIV_DMC1_DVSEM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT)
68#define EXYNOS4_CLKDIV_DMC1_DPM_SHIFT (24)
69#define EXYNOS4_CLKDIV_DMC1_DPM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DPM_SHIFT)
70
71#define EXYNOS4_CLKDIV_MFC_SHIFT (0)
72#define EXYNOS4_CLKDIV_MFC_MASK (0x7 << EXYNOS4_CLKDIV_MFC_SHIFT)
73
74#define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT (0)
75#define EXYNOS4_CLKDIV_TOP_ACLK200_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT)
76#define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT (4)
77#define EXYNOS4_CLKDIV_TOP_ACLK100_MASK (0xF << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT)
78#define EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT (8)
79#define EXYNOS4_CLKDIV_TOP_ACLK160_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT)
80#define EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT (12)
81#define EXYNOS4_CLKDIV_TOP_ACLK133_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT)
82#define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT (16)
83#define EXYNOS4_CLKDIV_TOP_ONENAND_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)
84#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT (20)
85#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT)
86#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT (24)
87#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT)
88
89#define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT (0)
90#define EXYNOS4_CLKDIV_BUS_GDLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT)
91#define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT (4)
92#define EXYNOS4_CLKDIV_BUS_GPLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)
93
94#define EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT (0)
95#define EXYNOS4_CLKDIV_CAM_FIMC0_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT)
96#define EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT (4)
97#define EXYNOS4_CLKDIV_CAM_FIMC1_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT)
98#define EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT (8)
99#define EXYNOS4_CLKDIV_CAM_FIMC2_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT)
100#define EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT (12)
101#define EXYNOS4_CLKDIV_CAM_FIMC3_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT)
102
103#define EXYNOS4_CLKDIV_CAM1 (S5P_VA_CMU + 0x0C568)
104
105#define EXYNOS4_CLKDIV_STAT_CAM1 (S5P_VA_CMU + 0x0C668)
106
107#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0)
108#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
109
110#endif /* __DEVFREQ_EXYNOS4_BUS_H */