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authorKukjin Kim <kgene.kim@samsung.com>2012-01-22 06:46:49 -0500
committerKukjin Kim <kgene.kim@samsung.com>2012-03-11 01:30:16 -0500
commit5fcc9297b8ca5bb65409f9963bd45dd9cfee8364 (patch)
tree3bea953ec869724737006d155d88db78078bb6ca /drivers/devfreq/exynos4_bus.c
parenta855039ee4b814782aebe2448d838944d2d29fcb (diff)
PM / devfreq: update the name of EXYNOS clock register
According to replacing the name of EXYNOS clock registers, this patch updates exynos4_bus.c file where it is used. Acked-by: MyungJoo Ham <myungjoo.ham@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'drivers/devfreq/exynos4_bus.c')
-rw-r--r--drivers/devfreq/exynos4_bus.c224
1 files changed, 112 insertions, 112 deletions
diff --git a/drivers/devfreq/exynos4_bus.c b/drivers/devfreq/exynos4_bus.c
index 6460577d6701..565aa98a4219 100644
--- a/drivers/devfreq/exynos4_bus.c
+++ b/drivers/devfreq/exynos4_bus.c
@@ -311,51 +311,51 @@ static int exynos4210_set_busclk(struct busfreq_data *data, struct opp *opp)
311 /* Change Divider - DMC0 */ 311 /* Change Divider - DMC0 */
312 tmp = data->dmc_divtable[index]; 312 tmp = data->dmc_divtable[index];
313 313
314 __raw_writel(tmp, S5P_CLKDIV_DMC0); 314 __raw_writel(tmp, EXYNOS4_CLKDIV_DMC0);
315 315
316 do { 316 do {
317 tmp = __raw_readl(S5P_CLKDIV_STAT_DMC0); 317 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC0);
318 } while (tmp & 0x11111111); 318 } while (tmp & 0x11111111);
319 319
320 /* Change Divider - TOP */ 320 /* Change Divider - TOP */
321 tmp = data->top_divtable[index]; 321 tmp = data->top_divtable[index];
322 322
323 __raw_writel(tmp, S5P_CLKDIV_TOP); 323 __raw_writel(tmp, EXYNOS4_CLKDIV_TOP);
324 324
325 do { 325 do {
326 tmp = __raw_readl(S5P_CLKDIV_STAT_TOP); 326 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_TOP);
327 } while (tmp & 0x11111); 327 } while (tmp & 0x11111);
328 328
329 /* Change Divider - LEFTBUS */ 329 /* Change Divider - LEFTBUS */
330 tmp = __raw_readl(S5P_CLKDIV_LEFTBUS); 330 tmp = __raw_readl(EXYNOS4_CLKDIV_LEFTBUS);
331 331
332 tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK); 332 tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
333 333
334 tmp |= ((exynos4210_clkdiv_lr_bus[index][0] << 334 tmp |= ((exynos4210_clkdiv_lr_bus[index][0] <<
335 S5P_CLKDIV_BUS_GDLR_SHIFT) | 335 EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
336 (exynos4210_clkdiv_lr_bus[index][1] << 336 (exynos4210_clkdiv_lr_bus[index][1] <<
337 S5P_CLKDIV_BUS_GPLR_SHIFT)); 337 EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
338 338
339 __raw_writel(tmp, S5P_CLKDIV_LEFTBUS); 339 __raw_writel(tmp, EXYNOS4_CLKDIV_LEFTBUS);
340 340
341 do { 341 do {
342 tmp = __raw_readl(S5P_CLKDIV_STAT_LEFTBUS); 342 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_LEFTBUS);
343 } while (tmp & 0x11); 343 } while (tmp & 0x11);
344 344
345 /* Change Divider - RIGHTBUS */ 345 /* Change Divider - RIGHTBUS */
346 tmp = __raw_readl(S5P_CLKDIV_RIGHTBUS); 346 tmp = __raw_readl(EXYNOS4_CLKDIV_RIGHTBUS);
347 347
348 tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK); 348 tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
349 349
350 tmp |= ((exynos4210_clkdiv_lr_bus[index][0] << 350 tmp |= ((exynos4210_clkdiv_lr_bus[index][0] <<
351 S5P_CLKDIV_BUS_GDLR_SHIFT) | 351 EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
352 (exynos4210_clkdiv_lr_bus[index][1] << 352 (exynos4210_clkdiv_lr_bus[index][1] <<
353 S5P_CLKDIV_BUS_GPLR_SHIFT)); 353 EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
354 354
355 __raw_writel(tmp, S5P_CLKDIV_RIGHTBUS); 355 __raw_writel(tmp, EXYNOS4_CLKDIV_RIGHTBUS);
356 356
357 do { 357 do {
358 tmp = __raw_readl(S5P_CLKDIV_STAT_RIGHTBUS); 358 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_RIGHTBUS);
359 } while (tmp & 0x11); 359 } while (tmp & 0x11);
360 360
361 return 0; 361 return 0;
@@ -376,137 +376,137 @@ static int exynos4x12_set_busclk(struct busfreq_data *data, struct opp *opp)
376 /* Change Divider - DMC0 */ 376 /* Change Divider - DMC0 */
377 tmp = data->dmc_divtable[index]; 377 tmp = data->dmc_divtable[index];
378 378
379 __raw_writel(tmp, S5P_CLKDIV_DMC0); 379 __raw_writel(tmp, EXYNOS4_CLKDIV_DMC0);
380 380
381 do { 381 do {
382 tmp = __raw_readl(S5P_CLKDIV_STAT_DMC0); 382 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC0);
383 } while (tmp & 0x11111111); 383 } while (tmp & 0x11111111);
384 384
385 /* Change Divider - DMC1 */ 385 /* Change Divider - DMC1 */
386 tmp = __raw_readl(S5P_CLKDIV_DMC1); 386 tmp = __raw_readl(EXYNOS4_CLKDIV_DMC1);
387 387
388 tmp &= ~(S5P_CLKDIV_DMC1_G2D_ACP_MASK | 388 tmp &= ~(EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK |
389 S5P_CLKDIV_DMC1_C2C_MASK | 389 EXYNOS4_CLKDIV_DMC1_C2C_MASK |
390 S5P_CLKDIV_DMC1_C2CACLK_MASK); 390 EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK);
391 391
392 tmp |= ((exynos4x12_clkdiv_dmc1[index][0] << 392 tmp |= ((exynos4x12_clkdiv_dmc1[index][0] <<
393 S5P_CLKDIV_DMC1_G2D_ACP_SHIFT) | 393 EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT) |
394 (exynos4x12_clkdiv_dmc1[index][1] << 394 (exynos4x12_clkdiv_dmc1[index][1] <<
395 S5P_CLKDIV_DMC1_C2C_SHIFT) | 395 EXYNOS4_CLKDIV_DMC1_C2C_SHIFT) |
396 (exynos4x12_clkdiv_dmc1[index][2] << 396 (exynos4x12_clkdiv_dmc1[index][2] <<
397 S5P_CLKDIV_DMC1_C2CACLK_SHIFT)); 397 EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT));
398 398
399 __raw_writel(tmp, S5P_CLKDIV_DMC1); 399 __raw_writel(tmp, EXYNOS4_CLKDIV_DMC1);
400 400
401 do { 401 do {
402 tmp = __raw_readl(S5P_CLKDIV_STAT_DMC1); 402 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC1);
403 } while (tmp & 0x111111); 403 } while (tmp & 0x111111);
404 404
405 /* Change Divider - TOP */ 405 /* Change Divider - TOP */
406 tmp = __raw_readl(S5P_CLKDIV_TOP); 406 tmp = __raw_readl(EXYNOS4_CLKDIV_TOP);
407 407
408 tmp &= ~(S5P_CLKDIV_TOP_ACLK266_GPS_MASK | 408 tmp &= ~(EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK |
409 S5P_CLKDIV_TOP_ACLK100_MASK | 409 EXYNOS4_CLKDIV_TOP_ACLK100_MASK |
410 S5P_CLKDIV_TOP_ACLK160_MASK | 410 EXYNOS4_CLKDIV_TOP_ACLK160_MASK |
411 S5P_CLKDIV_TOP_ACLK133_MASK | 411 EXYNOS4_CLKDIV_TOP_ACLK133_MASK |
412 S5P_CLKDIV_TOP_ONENAND_MASK); 412 EXYNOS4_CLKDIV_TOP_ONENAND_MASK);
413 413
414 tmp |= ((exynos4x12_clkdiv_top[index][0] << 414 tmp |= ((exynos4x12_clkdiv_top[index][0] <<
415 S5P_CLKDIV_TOP_ACLK266_GPS_SHIFT) | 415 EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT) |
416 (exynos4x12_clkdiv_top[index][1] << 416 (exynos4x12_clkdiv_top[index][1] <<
417 S5P_CLKDIV_TOP_ACLK100_SHIFT) | 417 EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) |
418 (exynos4x12_clkdiv_top[index][2] << 418 (exynos4x12_clkdiv_top[index][2] <<
419 S5P_CLKDIV_TOP_ACLK160_SHIFT) | 419 EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) |
420 (exynos4x12_clkdiv_top[index][3] << 420 (exynos4x12_clkdiv_top[index][3] <<
421 S5P_CLKDIV_TOP_ACLK133_SHIFT) | 421 EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) |
422 (exynos4x12_clkdiv_top[index][4] << 422 (exynos4x12_clkdiv_top[index][4] <<
423 S5P_CLKDIV_TOP_ONENAND_SHIFT)); 423 EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT));
424 424
425 __raw_writel(tmp, S5P_CLKDIV_TOP); 425 __raw_writel(tmp, EXYNOS4_CLKDIV_TOP);
426 426
427 do { 427 do {
428 tmp = __raw_readl(S5P_CLKDIV_STAT_TOP); 428 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_TOP);
429 } while (tmp & 0x11111); 429 } while (tmp & 0x11111);
430 430
431 /* Change Divider - LEFTBUS */ 431 /* Change Divider - LEFTBUS */
432 tmp = __raw_readl(S5P_CLKDIV_LEFTBUS); 432 tmp = __raw_readl(EXYNOS4_CLKDIV_LEFTBUS);
433 433
434 tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK); 434 tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
435 435
436 tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] << 436 tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] <<
437 S5P_CLKDIV_BUS_GDLR_SHIFT) | 437 EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
438 (exynos4x12_clkdiv_lr_bus[index][1] << 438 (exynos4x12_clkdiv_lr_bus[index][1] <<
439 S5P_CLKDIV_BUS_GPLR_SHIFT)); 439 EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
440 440
441 __raw_writel(tmp, S5P_CLKDIV_LEFTBUS); 441 __raw_writel(tmp, EXYNOS4_CLKDIV_LEFTBUS);
442 442
443 do { 443 do {
444 tmp = __raw_readl(S5P_CLKDIV_STAT_LEFTBUS); 444 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_LEFTBUS);
445 } while (tmp & 0x11); 445 } while (tmp & 0x11);
446 446
447 /* Change Divider - RIGHTBUS */ 447 /* Change Divider - RIGHTBUS */
448 tmp = __raw_readl(S5P_CLKDIV_RIGHTBUS); 448 tmp = __raw_readl(EXYNOS4_CLKDIV_RIGHTBUS);
449 449
450 tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK); 450 tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
451 451
452 tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] << 452 tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] <<
453 S5P_CLKDIV_BUS_GDLR_SHIFT) | 453 EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
454 (exynos4x12_clkdiv_lr_bus[index][1] << 454 (exynos4x12_clkdiv_lr_bus[index][1] <<
455 S5P_CLKDIV_BUS_GPLR_SHIFT)); 455 EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
456 456
457 __raw_writel(tmp, S5P_CLKDIV_RIGHTBUS); 457 __raw_writel(tmp, EXYNOS4_CLKDIV_RIGHTBUS);
458 458
459 do { 459 do {
460 tmp = __raw_readl(S5P_CLKDIV_STAT_RIGHTBUS); 460 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_RIGHTBUS);
461 } while (tmp & 0x11); 461 } while (tmp & 0x11);
462 462
463 /* Change Divider - MFC */ 463 /* Change Divider - MFC */
464 tmp = __raw_readl(S5P_CLKDIV_MFC); 464 tmp = __raw_readl(EXYNOS4_CLKDIV_MFC);
465 465
466 tmp &= ~(S5P_CLKDIV_MFC_MASK); 466 tmp &= ~(EXYNOS4_CLKDIV_MFC_MASK);
467 467
468 tmp |= ((exynos4x12_clkdiv_sclkip[index][0] << 468 tmp |= ((exynos4x12_clkdiv_sclkip[index][0] <<
469 S5P_CLKDIV_MFC_SHIFT)); 469 EXYNOS4_CLKDIV_MFC_SHIFT));
470 470
471 __raw_writel(tmp, S5P_CLKDIV_MFC); 471 __raw_writel(tmp, EXYNOS4_CLKDIV_MFC);
472 472
473 do { 473 do {
474 tmp = __raw_readl(S5P_CLKDIV_STAT_MFC); 474 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_MFC);
475 } while (tmp & 0x1); 475 } while (tmp & 0x1);
476 476
477 /* Change Divider - JPEG */ 477 /* Change Divider - JPEG */
478 tmp = __raw_readl(S5P_CLKDIV_CAM1); 478 tmp = __raw_readl(EXYNOS4_CLKDIV_CAM1);
479 479
480 tmp &= ~(S5P_CLKDIV_CAM1_JPEG_MASK); 480 tmp &= ~(EXYNOS4_CLKDIV_CAM1_JPEG_MASK);
481 481
482 tmp |= ((exynos4x12_clkdiv_sclkip[index][1] << 482 tmp |= ((exynos4x12_clkdiv_sclkip[index][1] <<
483 S5P_CLKDIV_CAM1_JPEG_SHIFT)); 483 EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT));
484 484
485 __raw_writel(tmp, S5P_CLKDIV_CAM1); 485 __raw_writel(tmp, EXYNOS4_CLKDIV_CAM1);
486 486
487 do { 487 do {
488 tmp = __raw_readl(S5P_CLKDIV_STAT_CAM1); 488 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_CAM1);
489 } while (tmp & 0x1); 489 } while (tmp & 0x1);
490 490
491 /* Change Divider - FIMC0~3 */ 491 /* Change Divider - FIMC0~3 */
492 tmp = __raw_readl(S5P_CLKDIV_CAM); 492 tmp = __raw_readl(EXYNOS4_CLKDIV_CAM);
493 493
494 tmp &= ~(S5P_CLKDIV_CAM_FIMC0_MASK | S5P_CLKDIV_CAM_FIMC1_MASK | 494 tmp &= ~(EXYNOS4_CLKDIV_CAM_FIMC0_MASK | EXYNOS4_CLKDIV_CAM_FIMC1_MASK |
495 S5P_CLKDIV_CAM_FIMC2_MASK | S5P_CLKDIV_CAM_FIMC3_MASK); 495 EXYNOS4_CLKDIV_CAM_FIMC2_MASK | EXYNOS4_CLKDIV_CAM_FIMC3_MASK);
496 496
497 tmp |= ((exynos4x12_clkdiv_sclkip[index][2] << 497 tmp |= ((exynos4x12_clkdiv_sclkip[index][2] <<
498 S5P_CLKDIV_CAM_FIMC0_SHIFT) | 498 EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT) |
499 (exynos4x12_clkdiv_sclkip[index][2] << 499 (exynos4x12_clkdiv_sclkip[index][2] <<
500 S5P_CLKDIV_CAM_FIMC1_SHIFT) | 500 EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT) |
501 (exynos4x12_clkdiv_sclkip[index][2] << 501 (exynos4x12_clkdiv_sclkip[index][2] <<
502 S5P_CLKDIV_CAM_FIMC2_SHIFT) | 502 EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT) |
503 (exynos4x12_clkdiv_sclkip[index][2] << 503 (exynos4x12_clkdiv_sclkip[index][2] <<
504 S5P_CLKDIV_CAM_FIMC3_SHIFT)); 504 EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT));
505 505
506 __raw_writel(tmp, S5P_CLKDIV_CAM); 506 __raw_writel(tmp, EXYNOS4_CLKDIV_CAM);
507 507
508 do { 508 do {
509 tmp = __raw_readl(S5P_CLKDIV_STAT_CAM1); 509 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_CAM1);
510 } while (tmp & 0x1111); 510 } while (tmp & 0x1111);
511 511
512 return 0; 512 return 0;
@@ -760,55 +760,55 @@ static int exynos4210_init_tables(struct busfreq_data *data)
760 int mgrp; 760 int mgrp;
761 int i, err = 0; 761 int i, err = 0;
762 762
763 tmp = __raw_readl(S5P_CLKDIV_DMC0); 763 tmp = __raw_readl(EXYNOS4_CLKDIV_DMC0);
764 for (i = LV_0; i < EX4210_LV_NUM; i++) { 764 for (i = LV_0; i < EX4210_LV_NUM; i++) {
765 tmp &= ~(S5P_CLKDIV_DMC0_ACP_MASK | 765 tmp &= ~(EXYNOS4_CLKDIV_DMC0_ACP_MASK |
766 S5P_CLKDIV_DMC0_ACPPCLK_MASK | 766 EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK |
767 S5P_CLKDIV_DMC0_DPHY_MASK | 767 EXYNOS4_CLKDIV_DMC0_DPHY_MASK |
768 S5P_CLKDIV_DMC0_DMC_MASK | 768 EXYNOS4_CLKDIV_DMC0_DMC_MASK |
769 S5P_CLKDIV_DMC0_DMCD_MASK | 769 EXYNOS4_CLKDIV_DMC0_DMCD_MASK |
770 S5P_CLKDIV_DMC0_DMCP_MASK | 770 EXYNOS4_CLKDIV_DMC0_DMCP_MASK |
771 S5P_CLKDIV_DMC0_COPY2_MASK | 771 EXYNOS4_CLKDIV_DMC0_COPY2_MASK |
772 S5P_CLKDIV_DMC0_CORETI_MASK); 772 EXYNOS4_CLKDIV_DMC0_CORETI_MASK);
773 773
774 tmp |= ((exynos4210_clkdiv_dmc0[i][0] << 774 tmp |= ((exynos4210_clkdiv_dmc0[i][0] <<
775 S5P_CLKDIV_DMC0_ACP_SHIFT) | 775 EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) |
776 (exynos4210_clkdiv_dmc0[i][1] << 776 (exynos4210_clkdiv_dmc0[i][1] <<
777 S5P_CLKDIV_DMC0_ACPPCLK_SHIFT) | 777 EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) |
778 (exynos4210_clkdiv_dmc0[i][2] << 778 (exynos4210_clkdiv_dmc0[i][2] <<
779 S5P_CLKDIV_DMC0_DPHY_SHIFT) | 779 EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) |
780 (exynos4210_clkdiv_dmc0[i][3] << 780 (exynos4210_clkdiv_dmc0[i][3] <<
781 S5P_CLKDIV_DMC0_DMC_SHIFT) | 781 EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) |
782 (exynos4210_clkdiv_dmc0[i][4] << 782 (exynos4210_clkdiv_dmc0[i][4] <<
783 S5P_CLKDIV_DMC0_DMCD_SHIFT) | 783 EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) |
784 (exynos4210_clkdiv_dmc0[i][5] << 784 (exynos4210_clkdiv_dmc0[i][5] <<
785 S5P_CLKDIV_DMC0_DMCP_SHIFT) | 785 EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT) |
786 (exynos4210_clkdiv_dmc0[i][6] << 786 (exynos4210_clkdiv_dmc0[i][6] <<
787 S5P_CLKDIV_DMC0_COPY2_SHIFT) | 787 EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT) |
788 (exynos4210_clkdiv_dmc0[i][7] << 788 (exynos4210_clkdiv_dmc0[i][7] <<
789 S5P_CLKDIV_DMC0_CORETI_SHIFT)); 789 EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT));
790 790
791 data->dmc_divtable[i] = tmp; 791 data->dmc_divtable[i] = tmp;
792 } 792 }
793 793
794 tmp = __raw_readl(S5P_CLKDIV_TOP); 794 tmp = __raw_readl(EXYNOS4_CLKDIV_TOP);
795 for (i = LV_0; i < EX4210_LV_NUM; i++) { 795 for (i = LV_0; i < EX4210_LV_NUM; i++) {
796 tmp &= ~(S5P_CLKDIV_TOP_ACLK200_MASK | 796 tmp &= ~(EXYNOS4_CLKDIV_TOP_ACLK200_MASK |
797 S5P_CLKDIV_TOP_ACLK100_MASK | 797 EXYNOS4_CLKDIV_TOP_ACLK100_MASK |
798 S5P_CLKDIV_TOP_ACLK160_MASK | 798 EXYNOS4_CLKDIV_TOP_ACLK160_MASK |
799 S5P_CLKDIV_TOP_ACLK133_MASK | 799 EXYNOS4_CLKDIV_TOP_ACLK133_MASK |
800 S5P_CLKDIV_TOP_ONENAND_MASK); 800 EXYNOS4_CLKDIV_TOP_ONENAND_MASK);
801 801
802 tmp |= ((exynos4210_clkdiv_top[i][0] << 802 tmp |= ((exynos4210_clkdiv_top[i][0] <<
803 S5P_CLKDIV_TOP_ACLK200_SHIFT) | 803 EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT) |
804 (exynos4210_clkdiv_top[i][1] << 804 (exynos4210_clkdiv_top[i][1] <<
805 S5P_CLKDIV_TOP_ACLK100_SHIFT) | 805 EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) |
806 (exynos4210_clkdiv_top[i][2] << 806 (exynos4210_clkdiv_top[i][2] <<
807 S5P_CLKDIV_TOP_ACLK160_SHIFT) | 807 EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) |
808 (exynos4210_clkdiv_top[i][3] << 808 (exynos4210_clkdiv_top[i][3] <<
809 S5P_CLKDIV_TOP_ACLK133_SHIFT) | 809 EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) |
810 (exynos4210_clkdiv_top[i][4] << 810 (exynos4210_clkdiv_top[i][4] <<
811 S5P_CLKDIV_TOP_ONENAND_SHIFT)); 811 EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT));
812 812
813 data->top_divtable[i] = tmp; 813 data->top_divtable[i] = tmp;
814 } 814 }
@@ -872,28 +872,28 @@ static int exynos4x12_init_tables(struct busfreq_data *data)
872 tmp |= DMC_PAUSE_ENABLE; 872 tmp |= DMC_PAUSE_ENABLE;
873 __raw_writel(tmp, S5P_DMC_PAUSE_CTRL); 873 __raw_writel(tmp, S5P_DMC_PAUSE_CTRL);
874 874
875 tmp = __raw_readl(S5P_CLKDIV_DMC0); 875 tmp = __raw_readl(EXYNOS4_CLKDIV_DMC0);
876 876
877 for (i = 0; i < EX4x12_LV_NUM; i++) { 877 for (i = 0; i < EX4x12_LV_NUM; i++) {
878 tmp &= ~(S5P_CLKDIV_DMC0_ACP_MASK | 878 tmp &= ~(EXYNOS4_CLKDIV_DMC0_ACP_MASK |
879 S5P_CLKDIV_DMC0_ACPPCLK_MASK | 879 EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK |
880 S5P_CLKDIV_DMC0_DPHY_MASK | 880 EXYNOS4_CLKDIV_DMC0_DPHY_MASK |
881 S5P_CLKDIV_DMC0_DMC_MASK | 881 EXYNOS4_CLKDIV_DMC0_DMC_MASK |
882 S5P_CLKDIV_DMC0_DMCD_MASK | 882 EXYNOS4_CLKDIV_DMC0_DMCD_MASK |
883 S5P_CLKDIV_DMC0_DMCP_MASK); 883 EXYNOS4_CLKDIV_DMC0_DMCP_MASK);
884 884
885 tmp |= ((exynos4x12_clkdiv_dmc0[i][0] << 885 tmp |= ((exynos4x12_clkdiv_dmc0[i][0] <<
886 S5P_CLKDIV_DMC0_ACP_SHIFT) | 886 EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) |
887 (exynos4x12_clkdiv_dmc0[i][1] << 887 (exynos4x12_clkdiv_dmc0[i][1] <<
888 S5P_CLKDIV_DMC0_ACPPCLK_SHIFT) | 888 EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) |
889 (exynos4x12_clkdiv_dmc0[i][2] << 889 (exynos4x12_clkdiv_dmc0[i][2] <<
890 S5P_CLKDIV_DMC0_DPHY_SHIFT) | 890 EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) |
891 (exynos4x12_clkdiv_dmc0[i][3] << 891 (exynos4x12_clkdiv_dmc0[i][3] <<
892 S5P_CLKDIV_DMC0_DMC_SHIFT) | 892 EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) |
893 (exynos4x12_clkdiv_dmc0[i][4] << 893 (exynos4x12_clkdiv_dmc0[i][4] <<
894 S5P_CLKDIV_DMC0_DMCD_SHIFT) | 894 EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) |
895 (exynos4x12_clkdiv_dmc0[i][5] << 895 (exynos4x12_clkdiv_dmc0[i][5] <<
896 S5P_CLKDIV_DMC0_DMCP_SHIFT)); 896 EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT));
897 897
898 data->dmc_divtable[i] = tmp; 898 data->dmc_divtable[i] = tmp;
899 } 899 }
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-03 02:22:52 -0500