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authorHoria Geanta <horia.geanta@freescale.com>2012-07-03 12:16:53 -0400
committerHerbert Xu <herbert@gondor.apana.org.au>2012-07-10 23:08:29 -0400
commit357fb60502ede168fa1b76b996298e0045e24b59 (patch)
tree36e350d71e7675589f95e9921beac1e1d30770d4 /drivers/crypto
parent865d506155b117edc7e668ced373030ce7108ce9 (diff)
crypto: talitos - add sha224, sha384 and sha512 to existing AEAD algorithms
With this, now all combinations of CBC: AES, 3DES-EDE with HMAC: SHA-1, SHA-224, SHA-256, SHA-384, SHA-512 are supported. Signed-off-by: Horia Geanta <horia.geanta@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto')
-rw-r--r--drivers/crypto/talitos.c161
-rw-r--r--drivers/crypto/talitos.h6
2 files changed, 166 insertions, 1 deletions
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index 2561aea52b62..efff788d2f1d 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -623,7 +623,7 @@ static void talitos_unregister_rng(struct device *dev)
623 * crypto alg 623 * crypto alg
624 */ 624 */
625#define TALITOS_CRA_PRIORITY 3000 625#define TALITOS_CRA_PRIORITY 3000
626#define TALITOS_MAX_KEY_SIZE 64 626#define TALITOS_MAX_KEY_SIZE 96
627#define TALITOS_MAX_IV_LENGTH 16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */ 627#define TALITOS_MAX_IV_LENGTH 16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
628 628
629#define MD5_BLOCK_SIZE 64 629#define MD5_BLOCK_SIZE 64
@@ -1956,6 +1956,59 @@ static struct talitos_alg_template driver_algs[] = {
1956 DESC_HDR_MODE1_MDEU_PAD | 1956 DESC_HDR_MODE1_MDEU_PAD |
1957 DESC_HDR_MODE1_MDEU_SHA1_HMAC, 1957 DESC_HDR_MODE1_MDEU_SHA1_HMAC,
1958 }, 1958 },
1959 { .type = CRYPTO_ALG_TYPE_AEAD,
1960 .alg.crypto = {
1961 .cra_name = "authenc(hmac(sha224),cbc(aes))",
1962 .cra_driver_name = "authenc-hmac-sha224-cbc-aes-talitos",
1963 .cra_blocksize = AES_BLOCK_SIZE,
1964 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1965 .cra_type = &crypto_aead_type,
1966 .cra_aead = {
1967 .setkey = aead_setkey,
1968 .setauthsize = aead_setauthsize,
1969 .encrypt = aead_encrypt,
1970 .decrypt = aead_decrypt,
1971 .givencrypt = aead_givencrypt,
1972 .geniv = "<built-in>",
1973 .ivsize = AES_BLOCK_SIZE,
1974 .maxauthsize = SHA224_DIGEST_SIZE,
1975 }
1976 },
1977 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1978 DESC_HDR_SEL0_AESU |
1979 DESC_HDR_MODE0_AESU_CBC |
1980 DESC_HDR_SEL1_MDEUA |
1981 DESC_HDR_MODE1_MDEU_INIT |
1982 DESC_HDR_MODE1_MDEU_PAD |
1983 DESC_HDR_MODE1_MDEU_SHA224_HMAC,
1984 },
1985 { .type = CRYPTO_ALG_TYPE_AEAD,
1986 .alg.crypto = {
1987 .cra_name = "authenc(hmac(sha224),cbc(des3_ede))",
1988 .cra_driver_name = "authenc-hmac-sha224-cbc-3des-talitos",
1989 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1990 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1991 .cra_type = &crypto_aead_type,
1992 .cra_aead = {
1993 .setkey = aead_setkey,
1994 .setauthsize = aead_setauthsize,
1995 .encrypt = aead_encrypt,
1996 .decrypt = aead_decrypt,
1997 .givencrypt = aead_givencrypt,
1998 .geniv = "<built-in>",
1999 .ivsize = DES3_EDE_BLOCK_SIZE,
2000 .maxauthsize = SHA224_DIGEST_SIZE,
2001 }
2002 },
2003 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2004 DESC_HDR_SEL0_DEU |
2005 DESC_HDR_MODE0_DEU_CBC |
2006 DESC_HDR_MODE0_DEU_3DES |
2007 DESC_HDR_SEL1_MDEUA |
2008 DESC_HDR_MODE1_MDEU_INIT |
2009 DESC_HDR_MODE1_MDEU_PAD |
2010 DESC_HDR_MODE1_MDEU_SHA224_HMAC,
2011 },
1959 { .type = CRYPTO_ALG_TYPE_AEAD, 2012 { .type = CRYPTO_ALG_TYPE_AEAD,
1960 .alg.crypto = { 2013 .alg.crypto = {
1961 .cra_name = "authenc(hmac(sha256),cbc(aes))", 2014 .cra_name = "authenc(hmac(sha256),cbc(aes))",
@@ -2011,6 +2064,112 @@ static struct talitos_alg_template driver_algs[] = {
2011 }, 2064 },
2012 { .type = CRYPTO_ALG_TYPE_AEAD, 2065 { .type = CRYPTO_ALG_TYPE_AEAD,
2013 .alg.crypto = { 2066 .alg.crypto = {
2067 .cra_name = "authenc(hmac(sha384),cbc(aes))",
2068 .cra_driver_name = "authenc-hmac-sha384-cbc-aes-talitos",
2069 .cra_blocksize = AES_BLOCK_SIZE,
2070 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2071 .cra_type = &crypto_aead_type,
2072 .cra_aead = {
2073 .setkey = aead_setkey,
2074 .setauthsize = aead_setauthsize,
2075 .encrypt = aead_encrypt,
2076 .decrypt = aead_decrypt,
2077 .givencrypt = aead_givencrypt,
2078 .geniv = "<built-in>",
2079 .ivsize = AES_BLOCK_SIZE,
2080 .maxauthsize = SHA384_DIGEST_SIZE,
2081 }
2082 },
2083 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2084 DESC_HDR_SEL0_AESU |
2085 DESC_HDR_MODE0_AESU_CBC |
2086 DESC_HDR_SEL1_MDEUB |
2087 DESC_HDR_MODE1_MDEU_INIT |
2088 DESC_HDR_MODE1_MDEU_PAD |
2089 DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
2090 },
2091 { .type = CRYPTO_ALG_TYPE_AEAD,
2092 .alg.crypto = {
2093 .cra_name = "authenc(hmac(sha384),cbc(des3_ede))",
2094 .cra_driver_name = "authenc-hmac-sha384-cbc-3des-talitos",
2095 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2096 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2097 .cra_type = &crypto_aead_type,
2098 .cra_aead = {
2099 .setkey = aead_setkey,
2100 .setauthsize = aead_setauthsize,
2101 .encrypt = aead_encrypt,
2102 .decrypt = aead_decrypt,
2103 .givencrypt = aead_givencrypt,
2104 .geniv = "<built-in>",
2105 .ivsize = DES3_EDE_BLOCK_SIZE,
2106 .maxauthsize = SHA384_DIGEST_SIZE,
2107 }
2108 },
2109 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2110 DESC_HDR_SEL0_DEU |
2111 DESC_HDR_MODE0_DEU_CBC |
2112 DESC_HDR_MODE0_DEU_3DES |
2113 DESC_HDR_SEL1_MDEUB |
2114 DESC_HDR_MODE1_MDEU_INIT |
2115 DESC_HDR_MODE1_MDEU_PAD |
2116 DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
2117 },
2118 { .type = CRYPTO_ALG_TYPE_AEAD,
2119 .alg.crypto = {
2120 .cra_name = "authenc(hmac(sha512),cbc(aes))",
2121 .cra_driver_name = "authenc-hmac-sha512-cbc-aes-talitos",
2122 .cra_blocksize = AES_BLOCK_SIZE,
2123 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2124 .cra_type = &crypto_aead_type,
2125 .cra_aead = {
2126 .setkey = aead_setkey,
2127 .setauthsize = aead_setauthsize,
2128 .encrypt = aead_encrypt,
2129 .decrypt = aead_decrypt,
2130 .givencrypt = aead_givencrypt,
2131 .geniv = "<built-in>",
2132 .ivsize = AES_BLOCK_SIZE,
2133 .maxauthsize = SHA512_DIGEST_SIZE,
2134 }
2135 },
2136 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2137 DESC_HDR_SEL0_AESU |
2138 DESC_HDR_MODE0_AESU_CBC |
2139 DESC_HDR_SEL1_MDEUB |
2140 DESC_HDR_MODE1_MDEU_INIT |
2141 DESC_HDR_MODE1_MDEU_PAD |
2142 DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
2143 },
2144 { .type = CRYPTO_ALG_TYPE_AEAD,
2145 .alg.crypto = {
2146 .cra_name = "authenc(hmac(sha512),cbc(des3_ede))",
2147 .cra_driver_name = "authenc-hmac-sha512-cbc-3des-talitos",
2148 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2149 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2150 .cra_type = &crypto_aead_type,
2151 .cra_aead = {
2152 .setkey = aead_setkey,
2153 .setauthsize = aead_setauthsize,
2154 .encrypt = aead_encrypt,
2155 .decrypt = aead_decrypt,
2156 .givencrypt = aead_givencrypt,
2157 .geniv = "<built-in>",
2158 .ivsize = DES3_EDE_BLOCK_SIZE,
2159 .maxauthsize = SHA512_DIGEST_SIZE,
2160 }
2161 },
2162 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2163 DESC_HDR_SEL0_DEU |
2164 DESC_HDR_MODE0_DEU_CBC |
2165 DESC_HDR_MODE0_DEU_3DES |
2166 DESC_HDR_SEL1_MDEUB |
2167 DESC_HDR_MODE1_MDEU_INIT |
2168 DESC_HDR_MODE1_MDEU_PAD |
2169 DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
2170 },
2171 { .type = CRYPTO_ALG_TYPE_AEAD,
2172 .alg.crypto = {
2014 .cra_name = "authenc(hmac(md5),cbc(aes))", 2173 .cra_name = "authenc(hmac(md5),cbc(aes))",
2015 .cra_driver_name = "authenc-hmac-md5-cbc-aes-talitos", 2174 .cra_driver_name = "authenc-hmac-md5-cbc-aes-talitos",
2016 .cra_blocksize = AES_BLOCK_SIZE, 2175 .cra_blocksize = AES_BLOCK_SIZE,
diff --git a/drivers/crypto/talitos.h b/drivers/crypto/talitos.h
index 41b80f6295ce..61a14054aa39 100644
--- a/drivers/crypto/talitos.h
+++ b/drivers/crypto/talitos.h
@@ -326,6 +326,12 @@ extern int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
326 DESC_HDR_MODE1_MDEU_HMAC) 326 DESC_HDR_MODE1_MDEU_HMAC)
327#define DESC_HDR_MODE1_MDEU_SHA1_HMAC (DESC_HDR_MODE1_MDEU_SHA1 | \ 327#define DESC_HDR_MODE1_MDEU_SHA1_HMAC (DESC_HDR_MODE1_MDEU_SHA1 | \
328 DESC_HDR_MODE1_MDEU_HMAC) 328 DESC_HDR_MODE1_MDEU_HMAC)
329#define DESC_HDR_MODE1_MDEU_SHA224_HMAC (DESC_HDR_MODE1_MDEU_SHA224 | \
330 DESC_HDR_MODE1_MDEU_HMAC)
331#define DESC_HDR_MODE1_MDEUB_SHA384_HMAC (DESC_HDR_MODE1_MDEUB_SHA384 | \
332 DESC_HDR_MODE1_MDEU_HMAC)
333#define DESC_HDR_MODE1_MDEUB_SHA512_HMAC (DESC_HDR_MODE1_MDEUB_SHA512 | \
334 DESC_HDR_MODE1_MDEU_HMAC)
329 335
330/* direction of overall data flow (DIR) */ 336/* direction of overall data flow (DIR) */
331#define DESC_HDR_DIR_INBOUND cpu_to_be32(0x00000002) 337#define DESC_HDR_DIR_INBOUND cpu_to_be32(0x00000002)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-30 18:33:48 -0500