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authorDmitry Kasatkin <dmitry.kasatkin@nokia.com>2010-11-19 09:04:23 -0500
committerHerbert Xu <herbert@gondor.apana.org.au>2010-11-27 03:37:17 -0500
commitc8eb54041acc4dedeaf0d9da34b91b8658386751 (patch)
tree1f1986d9d779aad728d048b9c1a1ff4823668055 /drivers/crypto
parent0c3cf4cc9abd854dcc6488719348a75b8f328c54 (diff)
crypto: omap-sham - DMA initialization fixes for off mode
DMA parameters for constant data were initialized during driver probe(). It seems that those settings sometimes are lost when devices goes to off mode. This patch makes DMA initialization just before use. It solves off mode problems. Fixes: NB#202786 - Aegis & SHA1 block off mode changes Signed-off-by: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto')
-rw-r--r--drivers/crypto/omap-sham.c19
1 files changed, 10 insertions, 9 deletions
diff --git a/drivers/crypto/omap-sham.c b/drivers/crypto/omap-sham.c
index 222237014007..9dfbc4ab7711 100644
--- a/drivers/crypto/omap-sham.c
+++ b/drivers/crypto/omap-sham.c
@@ -318,6 +318,16 @@ static int omap_sham_xmit_dma(struct omap_sham_dev *dd, dma_addr_t dma_addr,
318 omap_set_dma_src_params(dd->dma_lch, 0, OMAP_DMA_AMODE_POST_INC, 318 omap_set_dma_src_params(dd->dma_lch, 0, OMAP_DMA_AMODE_POST_INC,
319 dma_addr, 0, 0); 319 dma_addr, 0, 0);
320 320
321 omap_set_dma_dest_params(dd->dma_lch, 0,
322 OMAP_DMA_AMODE_CONSTANT,
323 dd->phys_base + SHA_REG_DIN(0), 0, 16);
324
325 omap_set_dma_dest_burst_mode(dd->dma_lch,
326 OMAP_DMA_DATA_BURST_16);
327
328 omap_set_dma_src_burst_mode(dd->dma_lch,
329 OMAP_DMA_DATA_BURST_4);
330
321 err = omap_sham_write_ctrl(dd, length, final, 1); 331 err = omap_sham_write_ctrl(dd, length, final, 1);
322 if (err) 332 if (err)
323 return err; 333 return err;
@@ -1071,15 +1081,6 @@ static int omap_sham_dma_init(struct omap_sham_dev *dd)
1071 dev_err(dd->dev, "Unable to request DMA channel\n"); 1081 dev_err(dd->dev, "Unable to request DMA channel\n");
1072 return err; 1082 return err;
1073 } 1083 }
1074 omap_set_dma_dest_params(dd->dma_lch, 0,
1075 OMAP_DMA_AMODE_CONSTANT,
1076 dd->phys_base + SHA_REG_DIN(0), 0, 16);
1077
1078 omap_set_dma_dest_burst_mode(dd->dma_lch,
1079 OMAP_DMA_DATA_BURST_16);
1080
1081 omap_set_dma_src_burst_mode(dd->dma_lch,
1082 OMAP_DMA_DATA_BURST_4);
1083 1084
1084 return 0; 1085 return 0;
1085} 1086}