diff options
author | Fabio Baltieri <fabio.baltieri@linaro.org> | 2013-06-25 04:54:44 -0400 |
---|---|---|
committer | Linus Walleij <linus.walleij@linaro.org> | 2013-06-25 08:50:54 -0400 |
commit | e3f511479376f073085b3a974343290cec350279 (patch) | |
tree | 5a891ac06dd71bb3f03f5ca2c8f2e0234b303e10 /drivers/crypto/ux500 | |
parent | b4a1ccdf27d140394250ddeeb274deeddc9a9b2e (diff) |
crypto: ux500/hash: use readl on iomem addresses
Always use readl when reading memory mapped registers.
Signed-off-by: Fabio Baltieri <fabio.baltieri@linaro.org>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/crypto/ux500')
-rw-r--r-- | drivers/crypto/ux500/hash/hash_core.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c index 9ca6fbb5e30d..23bda940abd7 100644 --- a/drivers/crypto/ux500/hash/hash_core.c +++ b/drivers/crypto/ux500/hash/hash_core.c | |||
@@ -473,12 +473,12 @@ static void hash_hw_write_key(struct hash_device_data *device_data, | |||
473 | HASH_SET_DIN(&word, nwords); | 473 | HASH_SET_DIN(&word, nwords); |
474 | } | 474 | } |
475 | 475 | ||
476 | while (device_data->base->str & HASH_STR_DCAL_MASK) | 476 | while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK) |
477 | cpu_relax(); | 477 | cpu_relax(); |
478 | 478 | ||
479 | HASH_SET_DCAL; | 479 | HASH_SET_DCAL; |
480 | 480 | ||
481 | while (device_data->base->str & HASH_STR_DCAL_MASK) | 481 | while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK) |
482 | cpu_relax(); | 482 | cpu_relax(); |
483 | } | 483 | } |
484 | 484 | ||
@@ -661,7 +661,7 @@ static void hash_messagepad(struct hash_device_data *device_data, | |||
661 | if (index_bytes) | 661 | if (index_bytes) |
662 | HASH_SET_DIN(message, nwords); | 662 | HASH_SET_DIN(message, nwords); |
663 | 663 | ||
664 | while (device_data->base->str & HASH_STR_DCAL_MASK) | 664 | while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK) |
665 | cpu_relax(); | 665 | cpu_relax(); |
666 | 666 | ||
667 | /* num_of_bytes == 0 => NBLW <- 0 (32 bits valid in DATAIN) */ | 667 | /* num_of_bytes == 0 => NBLW <- 0 (32 bits valid in DATAIN) */ |
@@ -676,7 +676,7 @@ static void hash_messagepad(struct hash_device_data *device_data, | |||
676 | (int)(readl_relaxed(&device_data->base->str) & | 676 | (int)(readl_relaxed(&device_data->base->str) & |
677 | HASH_STR_NBLW_MASK)); | 677 | HASH_STR_NBLW_MASK)); |
678 | 678 | ||
679 | while (device_data->base->str & HASH_STR_DCAL_MASK) | 679 | while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK) |
680 | cpu_relax(); | 680 | cpu_relax(); |
681 | } | 681 | } |
682 | 682 | ||
@@ -776,7 +776,7 @@ void hash_begin(struct hash_device_data *device_data, struct hash_ctx *ctx) | |||
776 | /* HW and SW initializations */ | 776 | /* HW and SW initializations */ |
777 | /* Note: there is no need to initialize buffer and digest members */ | 777 | /* Note: there is no need to initialize buffer and digest members */ |
778 | 778 | ||
779 | while (device_data->base->str & HASH_STR_DCAL_MASK) | 779 | while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK) |
780 | cpu_relax(); | 780 | cpu_relax(); |
781 | 781 | ||
782 | /* | 782 | /* |
@@ -962,7 +962,7 @@ static int hash_dma_final(struct ahash_request *req) | |||
962 | wait_for_completion(&ctx->device->dma.complete); | 962 | wait_for_completion(&ctx->device->dma.complete); |
963 | hash_dma_done(ctx); | 963 | hash_dma_done(ctx); |
964 | 964 | ||
965 | while (device_data->base->str & HASH_STR_DCAL_MASK) | 965 | while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK) |
966 | cpu_relax(); | 966 | cpu_relax(); |
967 | 967 | ||
968 | if (ctx->config.oper_mode == HASH_OPER_MODE_HMAC && ctx->key) { | 968 | if (ctx->config.oper_mode == HASH_OPER_MODE_HMAC && ctx->key) { |
@@ -1060,7 +1060,7 @@ int hash_hw_final(struct ahash_request *req) | |||
1060 | req_ctx->state.index); | 1060 | req_ctx->state.index); |
1061 | } else { | 1061 | } else { |
1062 | HASH_SET_DCAL; | 1062 | HASH_SET_DCAL; |
1063 | while (device_data->base->str & HASH_STR_DCAL_MASK) | 1063 | while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK) |
1064 | cpu_relax(); | 1064 | cpu_relax(); |
1065 | } | 1065 | } |
1066 | 1066 | ||
@@ -1189,7 +1189,7 @@ int hash_resume_state(struct hash_device_data *device_data, | |||
1189 | temp_cr = device_state->temp_cr; | 1189 | temp_cr = device_state->temp_cr; |
1190 | writel_relaxed(temp_cr & HASH_CR_RESUME_MASK, &device_data->base->cr); | 1190 | writel_relaxed(temp_cr & HASH_CR_RESUME_MASK, &device_data->base->cr); |
1191 | 1191 | ||
1192 | if (device_data->base->cr & HASH_CR_MODE_MASK) | 1192 | if (readl(&device_data->base->cr) & HASH_CR_MODE_MASK) |
1193 | hash_mode = HASH_OPER_MODE_HMAC; | 1193 | hash_mode = HASH_OPER_MODE_HMAC; |
1194 | else | 1194 | else |
1195 | hash_mode = HASH_OPER_MODE_HASH; | 1195 | hash_mode = HASH_OPER_MODE_HASH; |
@@ -1233,7 +1233,7 @@ int hash_save_state(struct hash_device_data *device_data, | |||
1233 | * actually makes sure that there isn't any ongoing calculation in the | 1233 | * actually makes sure that there isn't any ongoing calculation in the |
1234 | * hardware. | 1234 | * hardware. |
1235 | */ | 1235 | */ |
1236 | while (device_data->base->str & HASH_STR_DCAL_MASK) | 1236 | while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK) |
1237 | cpu_relax(); | 1237 | cpu_relax(); |
1238 | 1238 | ||
1239 | temp_cr = readl_relaxed(&device_data->base->cr); | 1239 | temp_cr = readl_relaxed(&device_data->base->cr); |
@@ -1242,7 +1242,7 @@ int hash_save_state(struct hash_device_data *device_data, | |||
1242 | 1242 | ||
1243 | device_state->din_reg = readl_relaxed(&device_data->base->din); | 1243 | device_state->din_reg = readl_relaxed(&device_data->base->din); |
1244 | 1244 | ||
1245 | if (device_data->base->cr & HASH_CR_MODE_MASK) | 1245 | if (readl(&device_data->base->cr) & HASH_CR_MODE_MASK) |
1246 | hash_mode = HASH_OPER_MODE_HMAC; | 1246 | hash_mode = HASH_OPER_MODE_HMAC; |
1247 | else | 1247 | else |
1248 | hash_mode = HASH_OPER_MODE_HASH; | 1248 | hash_mode = HASH_OPER_MODE_HASH; |