diff options
author | Prashant Gaikwad <pgaikwad@nvidia.com> | 2012-06-05 00:29:43 -0400 |
---|---|---|
committer | Stephen Warren <swarren@nvidia.com> | 2012-06-12 12:32:57 -0400 |
commit | 0df1ed4b12840f1d17b373ee5c05877c375ddc3e (patch) | |
tree | 350df38d78c31662a30a2c43c80d54de8f4f64b5 /drivers/crypto/tegra-aes.c | |
parent | 65d2bdd343bd07c8de7df7352186bfe57994b5e7 (diff) |
crypto: add clk_prepare/clk_unprepare
Use clk_prepare/clk_unprepare as required by the generic clk framework.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto/tegra-aes.c')
-rw-r--r-- | drivers/crypto/tegra-aes.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/crypto/tegra-aes.c b/drivers/crypto/tegra-aes.c index 422a9766c7c9..ac236f6724f4 100644 --- a/drivers/crypto/tegra-aes.c +++ b/drivers/crypto/tegra-aes.c | |||
@@ -572,7 +572,7 @@ static void aes_workqueue_handler(struct work_struct *work) | |||
572 | struct tegra_aes_dev *dd = aes_dev; | 572 | struct tegra_aes_dev *dd = aes_dev; |
573 | int ret; | 573 | int ret; |
574 | 574 | ||
575 | ret = clk_enable(dd->aes_clk); | 575 | ret = clk_prepare_enable(dd->aes_clk); |
576 | if (ret) | 576 | if (ret) |
577 | BUG_ON("clock enable failed"); | 577 | BUG_ON("clock enable failed"); |
578 | 578 | ||
@@ -581,7 +581,7 @@ static void aes_workqueue_handler(struct work_struct *work) | |||
581 | ret = tegra_aes_handle_req(dd); | 581 | ret = tegra_aes_handle_req(dd); |
582 | } while (!ret); | 582 | } while (!ret); |
583 | 583 | ||
584 | clk_disable(dd->aes_clk); | 584 | clk_disable_unprepare(dd->aes_clk); |
585 | } | 585 | } |
586 | 586 | ||
587 | static irqreturn_t aes_irq(int irq, void *dev_id) | 587 | static irqreturn_t aes_irq(int irq, void *dev_id) |
@@ -673,7 +673,7 @@ static int tegra_aes_get_random(struct crypto_rng *tfm, u8 *rdata, | |||
673 | /* take mutex to access the aes hw */ | 673 | /* take mutex to access the aes hw */ |
674 | mutex_lock(&aes_lock); | 674 | mutex_lock(&aes_lock); |
675 | 675 | ||
676 | ret = clk_enable(dd->aes_clk); | 676 | ret = clk_prepare_enable(dd->aes_clk); |
677 | if (ret) | 677 | if (ret) |
678 | return ret; | 678 | return ret; |
679 | 679 | ||
@@ -700,7 +700,7 @@ static int tegra_aes_get_random(struct crypto_rng *tfm, u8 *rdata, | |||
700 | } | 700 | } |
701 | 701 | ||
702 | out: | 702 | out: |
703 | clk_disable(dd->aes_clk); | 703 | clk_disable_unprepare(dd->aes_clk); |
704 | mutex_unlock(&aes_lock); | 704 | mutex_unlock(&aes_lock); |
705 | 705 | ||
706 | dev_dbg(dd->dev, "%s: done\n", __func__); | 706 | dev_dbg(dd->dev, "%s: done\n", __func__); |
@@ -758,7 +758,7 @@ static int tegra_aes_rng_reset(struct crypto_rng *tfm, u8 *seed, | |||
758 | 758 | ||
759 | dd->flags = FLAGS_ENCRYPT | FLAGS_RNG; | 759 | dd->flags = FLAGS_ENCRYPT | FLAGS_RNG; |
760 | 760 | ||
761 | ret = clk_enable(dd->aes_clk); | 761 | ret = clk_prepare_enable(dd->aes_clk); |
762 | if (ret) | 762 | if (ret) |
763 | return ret; | 763 | return ret; |
764 | 764 | ||
@@ -788,7 +788,7 @@ static int tegra_aes_rng_reset(struct crypto_rng *tfm, u8 *seed, | |||
788 | memcpy(dd->dt, dt, DEFAULT_RNG_BLK_SZ); | 788 | memcpy(dd->dt, dt, DEFAULT_RNG_BLK_SZ); |
789 | 789 | ||
790 | out: | 790 | out: |
791 | clk_disable(dd->aes_clk); | 791 | clk_disable_unprepare(dd->aes_clk); |
792 | mutex_unlock(&aes_lock); | 792 | mutex_unlock(&aes_lock); |
793 | 793 | ||
794 | dev_dbg(dd->dev, "%s: done\n", __func__); | 794 | dev_dbg(dd->dev, "%s: done\n", __func__); |