crypto: talitos - Perform auth check in h/w if on sec 2.1 and above

SEC version 2.1 and above adds the capability to do the IPSec ICV
memcmp in h/w. Results of the cmp are written back in the descriptor
header, along with the done status.  A new callback is added that
checks these ICCR bits instead of performing the memcmp on the core,
and is enabled by h/w capability.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

After testing on different parts, another condition was added
before using h/w auth check because different
SEC revisions require different handling.

The SEC 3.0 allows a more flexible link table where
the auth data can span separate link table entries.
The SEC 2.4/2.1 does not support this case.
So a test was added in the decrypt routine
for a fragmented case; the h/w auth check is disallowed for
revisions not having the extent in the link table;
in this case the hw auth check is done by software.

A portion of a previous change for SEC 3.0 link table handling
was removed since it became dead code with the hw auth check supported.

This seems to be the best compromise for using hw auth check
on supporting SEC revisions; it keeps the link table logic
simpler for the fragmented cases.

Signed-off-by: Lee Nipper <lee.nipper@freescale.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

1 files changed, 8 insertions, 0 deletions

diff --git a/drivers/crypto/talitos.h b/drivers/crypto/talitos.h
index e6b87770df03..125560a1d5f7 100644
--- a/drivers/crypto/talitos.h
+++ b/drivers/crypto/talitos.h
@@ -56,6 +56,7 @@
 #define   TALITOS_CCCR_CONT             0x2    /* channel continue */
 #define   TALITOS_CCCR_RESET            0x1    /* channel reset */
 #define TALITOS_CCCR_LO(ch)             (ch * TALITOS_CH_STRIDE + 0x110c)
+#define   TALITOS_CCCR_LO_IWSE          0x80   /* chan. ICCR writeback enab. */
 #define   TALITOS_CCCR_LO_CDWE          0x10   /* chan. done writeback enab. */
 #define   TALITOS_CCCR_LO_NT            0x4    /* notification type */
 #define   TALITOS_CCCR_LO_CDIE          0x2    /* channel done IRQ enable */
@@ -103,6 +104,9 @@
 #define TALITOS_AESUISR_LO              0x4034
 #define TALITOS_MDEUISR                 0x6030 /* message digest unit */
 #define TALITOS_MDEUISR_LO              0x6034
+#define TALITOS_MDEUICR                 0x6038 /* interrupt control */
+#define TALITOS_MDEUICR_LO              0x603c
+#define   TALITOS_MDEUICR_LO_ICE        0x4000 /* integrity check IRQ enable */
 #define TALITOS_AFEUISR                 0x8030 /* arc4 unit */
 #define TALITOS_AFEUISR_LO              0x8034
 #define TALITOS_RNGUISR                 0xa030 /* random number unit */
@@ -131,6 +135,9 @@
 
 /* written back when done */
 #define DESC_HDR_DONE                   __constant_cpu_to_be32(0xff000000)
+#define DESC_HDR_LO_ICCR1_MASK          __constant_cpu_to_be32(0x00180000)
+#define DESC_HDR_LO_ICCR1_PASS          __constant_cpu_to_be32(0x00080000)
+#define DESC_HDR_LO_ICCR1_FAIL          __constant_cpu_to_be32(0x00100000)
 
 /* primary execution unit select */
 #define DESC_HDR_SEL0_MASK              __constant_cpu_to_be32(0xf0000000)
@@ -169,6 +176,7 @@
 #define DESC_HDR_SEL1_CRCU              __constant_cpu_to_be32(0x00080000)
 
 /* secondary execution unit mode (MODE1) and derivatives */
+#define DESC_HDR_MODE1_MDEU_CICV        __constant_cpu_to_be32(0x00004000)
 #define DESC_HDR_MODE1_MDEU_INIT        __constant_cpu_to_be32(0x00001000)
 #define DESC_HDR_MODE1_MDEU_HMAC        __constant_cpu_to_be32(0x00000800)
 #define DESC_HDR_MODE1_MDEU_PAD         __constant_cpu_to_be32(0x00000400)