crypto: talitos - add support for sha224

SEC h/w versions 2.1 and above support sha224 via explicit instruction.

Performing sha224 ahashes on earlier versions is still possible because
they support sha256 (sha224 is sha256 with different initial constants
and a different truncation length).  We do this by overriding hardware
context self-initialization, and perform it manually in s/w instead.

Thanks to Lee for his fixes for correct execution on actual sec2.0 h/w.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off by: Lee Nipper <lee.nipper@gmail.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

1 files changed, 3 insertions, 1 deletions

diff --git a/drivers/crypto/talitos.h b/drivers/crypto/talitos.h
index 05c57b730e99..0b746aca4587 100644
--- a/drivers/crypto/talitos.h
+++ b/drivers/crypto/talitos.h
@@ -1,7 +1,7 @@
 /*
  * Freescale SEC (talitos) device register and descriptor header defines
  *
- * Copyright (c) 2006-2008 Freescale Semiconductor, Inc.
+ * Copyright (c) 2006-2010 Freescale Semiconductor, Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -164,6 +164,7 @@
 #define DESC_HDR_MODE0_MDEU_INIT        cpu_to_be32(0x01000000)
 #define DESC_HDR_MODE0_MDEU_HMAC        cpu_to_be32(0x00800000)
 #define DESC_HDR_MODE0_MDEU_PAD         cpu_to_be32(0x00400000)
+#define DESC_HDR_MODE0_MDEU_SHA224      cpu_to_be32(0x00300000)
 #define DESC_HDR_MODE0_MDEU_MD5         cpu_to_be32(0x00200000)
 #define DESC_HDR_MODE0_MDEU_SHA256      cpu_to_be32(0x00100000)
 #define DESC_HDR_MODE0_MDEU_SHA1        cpu_to_be32(0x00000000)
@@ -187,6 +188,7 @@
 #define DESC_HDR_MODE1_MDEU_INIT        cpu_to_be32(0x00001000)
 #define DESC_HDR_MODE1_MDEU_HMAC        cpu_to_be32(0x00000800)
 #define DESC_HDR_MODE1_MDEU_PAD         cpu_to_be32(0x00000400)
+#define DESC_HDR_MODE1_MDEU_SHA224      cpu_to_be32(0x00000300)
 #define DESC_HDR_MODE1_MDEU_MD5         cpu_to_be32(0x00000200)
 #define DESC_HDR_MODE1_MDEU_SHA256      cpu_to_be32(0x00000100)
 #define DESC_HDR_MODE1_MDEU_SHA1        cpu_to_be32(0x00000000)