ARM: Orion: CESA: Add support for clk

Some orion platforms support gating of the clock. If the clock exists
enable/disbale it as appropriate.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Jamie Lentin <jm@lentin.co.uk>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

1 files changed, 14 insertions, 0 deletions

diff --git a/drivers/crypto/mv_cesa.c b/drivers/crypto/mv_cesa.c
index e6ecc5f23943..1cc6b3f3e262 100644
--- a/drivers/crypto/mv_cesa.c
+++ b/drivers/crypto/mv_cesa.c
@@ -16,6 +16,7 @@
 #include <linux/scatterlist.h>
 #include <linux/slab.h>
 #include <linux/module.h>
+#include <linux/clk.h>
 #include <crypto/internal/hash.h>
 #include <crypto/sha.h>
 
@@ -79,6 +80,7 @@ struct crypto_priv {
         void __iomem *reg;
         void __iomem *sram;
         int irq;
+        struct clk *clk;
         struct task_struct *queue_th;
 
         /* the lock protects queue and eng_st */
@@ -1053,6 +1055,12 @@ static int mv_probe(struct platform_device *pdev)
         if (ret)
                 goto err_thread;
 
+        /* Not all platforms can gate the clock, so it is not
+           an error if the clock does not exists. */
+        cp->clk = clk_get(&pdev->dev, NULL);
+        if (!IS_ERR(cp->clk))
+                clk_prepare_enable(cp->clk);
+
         writel(SEC_INT_ACCEL0_DONE, cpg->reg + SEC_ACCEL_INT_MASK);
         writel(SEC_CFG_STOP_DIG_ERR, cpg->reg + SEC_ACCEL_CFG);
         writel(SRAM_CONFIG, cpg->reg + SEC_ACCEL_DESC_P0);
@@ -1118,6 +1126,12 @@ static int mv_remove(struct platform_device *pdev)
         memset(cp->sram, 0, cp->sram_size);
         iounmap(cp->sram);
         iounmap(cp->reg);
+
+        if (!IS_ERR(cp->clk)) {
+                clk_disable_unprepare(cp->clk);
+                clk_put(cp->clk);
+        }
+
         kfree(cp);
         cpg = NULL;
         return 0;