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authorRafael J. Wysocki <rafael.j.wysocki@intel.com>2013-08-26 20:37:54 -0400
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2013-08-26 20:37:54 -0400
commitf7b2ed43b59b432c9266b1da8613f18dc04440b5 (patch)
treea50b2151fe0762a0b27709305777a9545bdc87b4 /drivers/cpufreq
parent09198f8feff1fcdf03994f35955292f85b299bd6 (diff)
parentfae19b84724ff93c1ac59ce1eecc1411f8269d9e (diff)
Merge branch 'cpufreq-fixes' of git://git.linaro.org/people/vireshk/linux into pm-cpufreq
Pull cpufreq fixes for v3.12 from Viresh Kumar. * 'cpufreq-fixes' of git://git.linaro.org/people/vireshk/linux: cpufreq: imx6q: Fix clock enable balance cpufreq: tegra: fix the wrong clock name
Diffstat (limited to 'drivers/cpufreq')
-rw-r--r--drivers/cpufreq/imx6q-cpufreq.c17
-rw-r--r--drivers/cpufreq/tegra-cpufreq.c4
2 files changed, 2 insertions, 19 deletions
diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
index b16632bb5a56..3e396543aea4 100644
--- a/drivers/cpufreq/imx6q-cpufreq.c
+++ b/drivers/cpufreq/imx6q-cpufreq.c
@@ -117,28 +117,11 @@ static int imx6q_set_target(struct cpufreq_policy *policy,
117 * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it 117 * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
118 * - Disable pll2_pfd2_396m_clk 118 * - Disable pll2_pfd2_396m_clk
119 */ 119 */
120 clk_prepare_enable(pll2_pfd2_396m_clk);
121 clk_set_parent(step_clk, pll2_pfd2_396m_clk); 120 clk_set_parent(step_clk, pll2_pfd2_396m_clk);
122 clk_set_parent(pll1_sw_clk, step_clk); 121 clk_set_parent(pll1_sw_clk, step_clk);
123 if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) { 122 if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
124 clk_set_rate(pll1_sys_clk, freqs.new * 1000); 123 clk_set_rate(pll1_sys_clk, freqs.new * 1000);
125 /*
126 * If we are leaving 396 MHz set-point, we need to enable
127 * pll1_sys_clk and disable pll2_pfd2_396m_clk to keep
128 * their use count correct.
129 */
130 if (freqs.old * 1000 <= clk_get_rate(pll2_pfd2_396m_clk)) {
131 clk_prepare_enable(pll1_sys_clk);
132 clk_disable_unprepare(pll2_pfd2_396m_clk);
133 }
134 clk_set_parent(pll1_sw_clk, pll1_sys_clk); 124 clk_set_parent(pll1_sw_clk, pll1_sys_clk);
135 clk_disable_unprepare(pll2_pfd2_396m_clk);
136 } else {
137 /*
138 * Disable pll1_sys_clk if pll2_pfd2_396m_clk is sufficient
139 * to provide the frequency.
140 */
141 clk_disable_unprepare(pll1_sys_clk);
142 } 125 }
143 126
144 /* Ensure the arm clock divider is what we expect */ 127 /* Ensure the arm clock divider is what we expect */
diff --git a/drivers/cpufreq/tegra-cpufreq.c b/drivers/cpufreq/tegra-cpufreq.c
index cd66b85d927c..a7b876fdc1d8 100644
--- a/drivers/cpufreq/tegra-cpufreq.c
+++ b/drivers/cpufreq/tegra-cpufreq.c
@@ -255,7 +255,7 @@ static struct cpufreq_driver tegra_cpufreq_driver = {
255 255
256static int __init tegra_cpufreq_init(void) 256static int __init tegra_cpufreq_init(void)
257{ 257{
258 cpu_clk = clk_get_sys(NULL, "cpu"); 258 cpu_clk = clk_get_sys(NULL, "cclk");
259 if (IS_ERR(cpu_clk)) 259 if (IS_ERR(cpu_clk))
260 return PTR_ERR(cpu_clk); 260 return PTR_ERR(cpu_clk);
261 261
@@ -263,7 +263,7 @@ static int __init tegra_cpufreq_init(void)
263 if (IS_ERR(pll_x_clk)) 263 if (IS_ERR(pll_x_clk))
264 return PTR_ERR(pll_x_clk); 264 return PTR_ERR(pll_x_clk);
265 265
266 pll_p_clk = clk_get_sys(NULL, "pll_p_cclk"); 266 pll_p_clk = clk_get_sys(NULL, "pll_p");
267 if (IS_ERR(pll_p_clk)) 267 if (IS_ERR(pll_p_clk))
268 return PTR_ERR(pll_p_clk); 268 return PTR_ERR(pll_p_clk);
269 269