Merge branch 'timers/clockevents' of git://git.linaro.org/people/dlezcano/clockevents into timers/core

5 files changed, 417 insertions, 1 deletions

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index f151c6cf27c3..0a04257edf65 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -85,3 +85,8 @@ config CLKSRC_SAMSUNG_PWM
           Samsung S3C, S5P and Exynos SoCs, replacing an earlier driver
           for all devicetree enabled platforms. This driver will be
           needed only on systems that do not have the Exynos MCT available.
+
+config VF_PIT_TIMER
+        bool
+        help
+          Support for Period Interrupt Timer on Freescale Vybrid Family SoCs.
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 8d979c72aa94..4853ea0f8fd5 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -22,10 +22,12 @@ obj-$(CONFIG_ARCH_PRIMA2)	+= timer-prima2.o
 obj-$(CONFIG_SUN4I_TIMER)       += sun4i_timer.o
 obj-$(CONFIG_ARCH_TEGRA)        += tegra20_timer.o
 obj-$(CONFIG_VT8500_TIMER)      += vt8500_timer.o
+obj-$(CONFIG_ARCH_NSPIRE)       += zevio-timer.o
 obj-$(CONFIG_ARCH_BCM)          += bcm_kona_timer.o
 obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence_ttc_timer.o
 obj-$(CONFIG_CLKSRC_EXYNOS_MCT) += exynos_mct.o
 obj-$(CONFIG_CLKSRC_SAMSUNG_PWM)        += samsung_pwm_timer.o
+obj-$(CONFIG_VF_PIT_TIMER)      += vf_pit_timer.o
 
 obj-$(CONFIG_ARM_ARCH_TIMER)            += arm_arch_timer.o
 obj-$(CONFIG_CLKSRC_METAG_GENERIC)      += metag_generic.o
diff --git a/drivers/clocksource/dw_apb_timer_of.c b/drivers/clocksource/dw_apb_timer_of.c
index 8d2f809a0967..af13b8559b61 100644
--- a/drivers/clocksource/dw_apb_timer_of.c
+++ b/drivers/clocksource/dw_apb_timer_of.c
@@ -43,7 +43,7 @@ static void add_clockevent(struct device_node *event_timer)
         u32 irq, rate;
 
         irq = irq_of_parse_and_map(event_timer, 0);
-        if (irq == NO_IRQ)
+        if (irq == 0)
                 panic("No IRQ for clock event timer");
 
         timer_get_base_and_rate(event_timer, &iobase, &rate);
diff --git a/drivers/clocksource/vf_pit_timer.c b/drivers/clocksource/vf_pit_timer.c
new file mode 100644
index 000000000000..598399d57fc5
--- /dev/null
+++ b/drivers/clocksource/vf_pit_timer.c
@@ -0,0 +1,194 @@
+/*
+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/clockchips.h>
+#include <linux/clk.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <asm/sched_clock.h>
+
+/*
+ * Each pit takes 0x10 Bytes register space
+ */
+#define PITMCR          0x00
+#define PIT0_OFFSET     0x100
+#define PITn_OFFSET(n)  (PIT0_OFFSET + 0x10 * (n))
+#define PITLDVAL        0x00
+#define PITCVAL         0x04
+#define PITTCTRL        0x08
+#define PITTFLG         0x0c
+
+#define PITMCR_MDIS     (0x1 << 1)
+
+#define PITTCTRL_TEN    (0x1 << 0)
+#define PITTCTRL_TIE    (0x1 << 1)
+#define PITCTRL_CHN     (0x1 << 2)
+
+#define PITTFLG_TIF     0x1
+
+static void __iomem *clksrc_base;
+static void __iomem *clkevt_base;
+static unsigned long cycle_per_jiffy;
+
+static inline void pit_timer_enable(void)
+{
+        __raw_writel(PITTCTRL_TEN | PITTCTRL_TIE, clkevt_base + PITTCTRL);
+}
+
+static inline void pit_timer_disable(void)
+{
+        __raw_writel(0, clkevt_base + PITTCTRL);
+}
+
+static inline void pit_irq_acknowledge(void)
+{
+        __raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG);
+}
+
+static unsigned int pit_read_sched_clock(void)
+{
+        return __raw_readl(clksrc_base + PITCVAL);
+}
+
+static int __init pit_clocksource_init(unsigned long rate)
+{
+        /* set the max load value and start the clock source counter */
+        __raw_writel(0, clksrc_base + PITTCTRL);
+        __raw_writel(~0UL, clksrc_base + PITLDVAL);
+        __raw_writel(PITTCTRL_TEN, clksrc_base + PITTCTRL);
+
+        setup_sched_clock(pit_read_sched_clock, 32, rate);
+        return clocksource_mmio_init(clksrc_base + PITCVAL, "vf-pit", rate,
+                        300, 32, clocksource_mmio_readl_down);
+}
+
+static int pit_set_next_event(unsigned long delta,
+                                struct clock_event_device *unused)
+{
+        /*
+         * set a new value to PITLDVAL register will not restart the timer,
+         * to abort the current cycle and start a timer period with the new
+         * value, the timer must be disabled and enabled again.
+         * and the PITLAVAL should be set to delta minus one according to pit
+         * hardware requirement.
+         */
+        pit_timer_disable();
+        __raw_writel(delta - 1, clkevt_base + PITLDVAL);
+        pit_timer_enable();
+
+        return 0;
+}
+
+static void pit_set_mode(enum clock_event_mode mode,
+                                struct clock_event_device *evt)
+{
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                pit_set_next_event(cycle_per_jiffy, evt);
+                break;
+        default:
+                break;
+        }
+}
+
+static irqreturn_t pit_timer_interrupt(int irq, void *dev_id)
+{
+        struct clock_event_device *evt = dev_id;
+
+        pit_irq_acknowledge();
+
+        /*
+         * pit hardware doesn't support oneshot, it will generate an interrupt
+         * and reload the counter value from PITLDVAL when PITCVAL reach zero,
+         * and start the counter again. So software need to disable the timer
+         * to stop the counter loop in ONESHOT mode.
+         */
+        if (likely(evt->mode == CLOCK_EVT_MODE_ONESHOT))
+                pit_timer_disable();
+
+        evt->event_handler(evt);
+
+        return IRQ_HANDLED;
+}
+
+static struct clock_event_device clockevent_pit = {
+        .name           = "VF pit timer",
+        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+        .set_mode       = pit_set_mode,
+        .set_next_event = pit_set_next_event,
+        .rating         = 300,
+};
+
+static struct irqaction pit_timer_irq = {
+        .name           = "VF pit timer",
+        .flags          = IRQF_TIMER | IRQF_IRQPOLL,
+        .handler        = pit_timer_interrupt,
+        .dev_id         = &clockevent_pit,
+};
+
+static int __init pit_clockevent_init(unsigned long rate, int irq)
+{
+        __raw_writel(0, clkevt_base + PITTCTRL);
+        __raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG);
+
+        BUG_ON(setup_irq(irq, &pit_timer_irq));
+
+        clockevent_pit.cpumask = cpumask_of(0);
+        clockevent_pit.irq = irq;
+        /*
+         * The value for the LDVAL register trigger is calculated as:
+         * LDVAL trigger = (period / clock period) - 1
+         * The pit is a 32-bit down count timer, when the conter value
+         * reaches 0, it will generate an interrupt, thus the minimal
+         * LDVAL trigger value is 1. And then the min_delta is
+         * minimal LDVAL trigger value + 1, and the max_delta is full 32-bit.
+         */
+        clockevents_config_and_register(&clockevent_pit, rate, 2, 0xffffffff);
+
+        return 0;
+}
+
+static void __init pit_timer_init(struct device_node *np)
+{
+        struct clk *pit_clk;
+        void __iomem *timer_base;
+        unsigned long clk_rate;
+        int irq;
+
+        timer_base = of_iomap(np, 0);
+        BUG_ON(!timer_base);
+
+        /*
+         * PIT0 and PIT1 can be chained to build a 64-bit timer,
+         * so choose PIT2 as clocksource, PIT3 as clockevent device,
+         * and leave PIT0 and PIT1 unused for anyone else who needs them.
+         */
+        clksrc_base = timer_base + PITn_OFFSET(2);
+        clkevt_base = timer_base + PITn_OFFSET(3);
+
+        irq = irq_of_parse_and_map(np, 0);
+        BUG_ON(irq <= 0);
+
+        pit_clk = of_clk_get(np, 0);
+        BUG_ON(IS_ERR(pit_clk));
+
+        BUG_ON(clk_prepare_enable(pit_clk));
+
+        clk_rate = clk_get_rate(pit_clk);
+        cycle_per_jiffy = clk_rate / (HZ);
+
+        /* enable the pit module */
+        __raw_writel(~PITMCR_MDIS, timer_base + PITMCR);
+
+        BUG_ON(pit_clocksource_init(clk_rate));
+
+        pit_clockevent_init(clk_rate, irq);
+}
+CLOCKSOURCE_OF_DECLARE(vf610, "fsl,vf610-pit", pit_timer_init);
diff --git a/drivers/clocksource/zevio-timer.c b/drivers/clocksource/zevio-timer.c
new file mode 100644
index 000000000000..ca81809d159d
--- /dev/null
+++ b/drivers/clocksource/zevio-timer.c
@@ -0,0 +1,215 @@
+/*
+ *  linux/drivers/clocksource/zevio-timer.c
+ *
+ *  Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/cpumask.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+
+#define IO_CURRENT_VAL  0x00
+#define IO_DIVIDER      0x04
+#define IO_CONTROL      0x08
+
+#define IO_TIMER1       0x00
+#define IO_TIMER2       0x0C
+
+#define IO_MATCH_BEGIN  0x18
+#define IO_MATCH(x)     (IO_MATCH_BEGIN + ((x) << 2))
+
+#define IO_INTR_STS     0x00
+#define IO_INTR_ACK     0x00
+#define IO_INTR_MSK     0x04
+
+#define CNTL_STOP_TIMER (1 << 4)
+#define CNTL_RUN_TIMER  (0 << 4)
+
+#define CNTL_INC        (1 << 3)
+#define CNTL_DEC        (0 << 3)
+
+#define CNTL_TOZERO     0
+#define CNTL_MATCH(x)   ((x) + 1)
+#define CNTL_FOREVER    7
+
+/* There are 6 match registers but we only use one. */
+#define TIMER_MATCH     0
+
+#define TIMER_INTR_MSK  (1 << (TIMER_MATCH))
+#define TIMER_INTR_ALL  0x3F
+
+struct zevio_timer {
+        void __iomem *base;
+        void __iomem *timer1, *timer2;
+        void __iomem *interrupt_regs;
+
+        struct clk *clk;
+        struct clock_event_device clkevt;
+        struct irqaction clkevt_irq;
+
+        char clocksource_name[64];
+        char clockevent_name[64];
+};
+
+static int zevio_timer_set_event(unsigned long delta,
+                                 struct clock_event_device *dev)
+{
+        struct zevio_timer *timer = container_of(dev, struct zevio_timer,
+                                                 clkevt);
+
+        writel(delta, timer->timer1 + IO_CURRENT_VAL);
+        writel(CNTL_RUN_TIMER | CNTL_DEC | CNTL_MATCH(TIMER_MATCH),
+                        timer->timer1 + IO_CONTROL);
+
+        return 0;
+}
+
+static void zevio_timer_set_mode(enum clock_event_mode mode,
+                                 struct clock_event_device *dev)
+{
+        struct zevio_timer *timer = container_of(dev, struct zevio_timer,
+                                                 clkevt);
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_RESUME:
+        case CLOCK_EVT_MODE_ONESHOT:
+                /* Enable timer interrupts */
+                writel(TIMER_INTR_MSK, timer->interrupt_regs + IO_INTR_MSK);
+                writel(TIMER_INTR_ALL, timer->interrupt_regs + IO_INTR_ACK);
+                break;
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_UNUSED:
+                /* Disable timer interrupts */
+                writel(0, timer->interrupt_regs + IO_INTR_MSK);
+                writel(TIMER_INTR_ALL, timer->interrupt_regs + IO_INTR_ACK);
+                /* Stop timer */
+                writel(CNTL_STOP_TIMER, timer->timer1 + IO_CONTROL);
+                break;
+        case CLOCK_EVT_MODE_PERIODIC:
+        default:
+                /* Unsupported */
+                break;
+        }
+}
+
+static irqreturn_t zevio_timer_interrupt(int irq, void *dev_id)
+{
+        struct zevio_timer *timer = dev_id;
+        u32 intr;
+
+        intr = readl(timer->interrupt_regs + IO_INTR_ACK);
+        if (!(intr & TIMER_INTR_MSK))
+                return IRQ_NONE;
+
+        writel(TIMER_INTR_MSK, timer->interrupt_regs + IO_INTR_ACK);
+        writel(CNTL_STOP_TIMER, timer->timer1 + IO_CONTROL);
+
+        if (timer->clkevt.event_handler)
+                timer->clkevt.event_handler(&timer->clkevt);
+
+        return IRQ_HANDLED;
+}
+
+static int __init zevio_timer_add(struct device_node *node)
+{
+        struct zevio_timer *timer;
+        struct resource res;
+        int irqnr, ret;
+
+        timer = kzalloc(sizeof(*timer), GFP_KERNEL);
+        if (!timer)
+                return -ENOMEM;
+
+        timer->base = of_iomap(node, 0);
+        if (!timer->base) {
+                ret = -EINVAL;
+                goto error_free;
+        }
+        timer->timer1 = timer->base + IO_TIMER1;
+        timer->timer2 = timer->base + IO_TIMER2;
+
+        timer->clk = of_clk_get(node, 0);
+        if (IS_ERR(timer->clk)) {
+                ret = PTR_ERR(timer->clk);
+                pr_err("Timer clock not found! (error %d)\n", ret);
+                goto error_unmap;
+        }
+
+        timer->interrupt_regs = of_iomap(node, 1);
+        irqnr = irq_of_parse_and_map(node, 0);
+
+        of_address_to_resource(node, 0, &res);
+        scnprintf(timer->clocksource_name, sizeof(timer->clocksource_name),
+                        "%llx.%s_clocksource",
+                        (unsigned long long)res.start, node->name);
+
+        scnprintf(timer->clockevent_name, sizeof(timer->clockevent_name),
+                        "%llx.%s_clockevent",
+                        (unsigned long long)res.start, node->name);
+
+        if (timer->interrupt_regs && irqnr) {
+                timer->clkevt.name              = timer->clockevent_name;
+                timer->clkevt.set_next_event    = zevio_timer_set_event;
+                timer->clkevt.set_mode          = zevio_timer_set_mode;
+                timer->clkevt.rating            = 200;
+                timer->clkevt.cpumask           = cpu_all_mask;
+                timer->clkevt.features          = CLOCK_EVT_FEAT_ONESHOT;
+                timer->clkevt.irq               = irqnr;
+
+                writel(CNTL_STOP_TIMER, timer->timer1 + IO_CONTROL);
+                writel(0, timer->timer1 + IO_DIVIDER);
+
+                /* Start with timer interrupts disabled */
+                writel(0, timer->interrupt_regs + IO_INTR_MSK);
+                writel(TIMER_INTR_ALL, timer->interrupt_regs + IO_INTR_ACK);
+
+                /* Interrupt to occur when timer value matches 0 */
+                writel(0, timer->base + IO_MATCH(TIMER_MATCH));
+
+                timer->clkevt_irq.name          = timer->clockevent_name;
+                timer->clkevt_irq.handler       = zevio_timer_interrupt;
+                timer->clkevt_irq.dev_id        = timer;
+                timer->clkevt_irq.flags         = IRQF_TIMER | IRQF_IRQPOLL;
+
+                setup_irq(irqnr, &timer->clkevt_irq);
+
+                clockevents_config_and_register(&timer->clkevt,
+                                clk_get_rate(timer->clk), 0x0001, 0xffff);
+                pr_info("Added %s as clockevent\n", timer->clockevent_name);
+        }
+
+        writel(CNTL_STOP_TIMER, timer->timer2 + IO_CONTROL);
+        writel(0, timer->timer2 + IO_CURRENT_VAL);
+        writel(0, timer->timer2 + IO_DIVIDER);
+        writel(CNTL_RUN_TIMER | CNTL_FOREVER | CNTL_INC,
+                        timer->timer2 + IO_CONTROL);
+
+        clocksource_mmio_init(timer->timer2 + IO_CURRENT_VAL,
+                        timer->clocksource_name,
+                        clk_get_rate(timer->clk),
+                        200, 16,
+                        clocksource_mmio_readw_up);
+
+        pr_info("Added %s as clocksource\n", timer->clocksource_name);
+
+        return 0;
+error_unmap:
+        iounmap(timer->base);
+error_free:
+        kfree(timer);
+        return ret;
+}
+
+CLOCKSOURCE_OF_DECLARE(zevio_timer, "lsi,zevio-timer", zevio_timer_add);