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authorKumar Gala <galak@codeaurora.org>2014-01-29 18:01:37 -0500
committerKumar Gala <galak@codeaurora.org>2014-02-06 17:20:41 -0500
commit7d6d45f86969acd57850ab4d91ea002db08ff235 (patch)
tree1d639119d0312bf0a94b1805396124e8e135c70d /drivers/clocksource
parent8fc1b0f87d9fcc7f05873c70b3003328c3d7defa (diff)
clocksource: qcom: split building of legacy vs multiplatform support
The majority of the clocksource code for the Qualcomm platform is shared between newer (multiplatform) and older platforms. However there is a bit of code that isn't, so only build it for the appropriate config. Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Kumar Gala <galak@codeaurora.org>
Diffstat (limited to 'drivers/clocksource')
-rw-r--r--drivers/clocksource/qcom-timer.c23
1 files changed, 12 insertions, 11 deletions
diff --git a/drivers/clocksource/qcom-timer.c b/drivers/clocksource/qcom-timer.c
index dca829ec859b..e807acf4c665 100644
--- a/drivers/clocksource/qcom-timer.c
+++ b/drivers/clocksource/qcom-timer.c
@@ -106,15 +106,6 @@ static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
106 return readl_relaxed(source_base + TIMER_COUNT_VAL); 106 return readl_relaxed(source_base + TIMER_COUNT_VAL);
107} 107}
108 108
109static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
110{
111 /*
112 * Shift timer count down by a constant due to unreliable lower bits
113 * on some targets.
114 */
115 return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
116}
117
118static struct clocksource msm_clocksource = { 109static struct clocksource msm_clocksource = {
119 .name = "dg_timer", 110 .name = "dg_timer",
120 .rating = 300, 111 .rating = 300,
@@ -228,7 +219,7 @@ err:
228 sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz); 219 sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz);
229} 220}
230 221
231#ifdef CONFIG_OF 222#ifdef CONFIG_ARCH_QCOM
232static void __init msm_dt_timer_init(struct device_node *np) 223static void __init msm_dt_timer_init(struct device_node *np)
233{ 224{
234 u32 freq; 225 u32 freq;
@@ -281,7 +272,7 @@ static void __init msm_dt_timer_init(struct device_node *np)
281} 272}
282CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init); 273CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
283CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init); 274CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);
284#endif 275#else
285 276
286static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source, 277static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source,
287 u32 sts) 278 u32 sts)
@@ -301,6 +292,15 @@ static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source,
301 return 0; 292 return 0;
302} 293}
303 294
295static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
296{
297 /*
298 * Shift timer count down by a constant due to unreliable lower bits
299 * on some targets.
300 */
301 return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
302}
303
304void __init msm7x01_timer_init(void) 304void __init msm7x01_timer_init(void)
305{ 305{
306 struct clocksource *cs = &msm_clocksource; 306 struct clocksource *cs = &msm_clocksource;
@@ -327,3 +327,4 @@ void __init qsd8x50_timer_init(void)
327 return; 327 return;
328 msm_timer_init(19200000 / 4, 32, 7, false); 328 msm_timer_init(19200000 / 4, 32, 7, false);
329} 329}
330#endif