diff options
| author | Thomas Gleixner <tglx@linutronix.de> | 2009-03-23 09:50:03 -0400 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2009-03-23 16:20:20 -0400 |
| commit | 80c5520811d3805adcb15c570ea5e2d489fa5d0b (patch) | |
| tree | ae797a7f4af39f80e77526533d06ac23b439f0ab /drivers/clocksource | |
| parent | b3e3b302cf6dc8d60b67f0e84d1fa5648889c038 (diff) | |
| parent | 8c083f081d0014057901c68a0a3e0f8ca7ac8d23 (diff) | |
Merge branch 'cpus4096' into irq/threaded
Conflicts:
arch/parisc/kernel/irq.c
kernel/irq/handle.c
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'drivers/clocksource')
| -rw-r--r-- | drivers/clocksource/acpi_pm.c | 2 | ||||
| -rw-r--r-- | drivers/clocksource/cyclone.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clocksource/acpi_pm.c b/drivers/clocksource/acpi_pm.c index e1129fad96dd..ee19b6e8fcb4 100644 --- a/drivers/clocksource/acpi_pm.c +++ b/drivers/clocksource/acpi_pm.c | |||
| @@ -143,7 +143,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_LE, | |||
| 143 | #endif | 143 | #endif |
| 144 | 144 | ||
| 145 | #ifndef CONFIG_X86_64 | 145 | #ifndef CONFIG_X86_64 |
| 146 | #include "mach_timer.h" | 146 | #include <asm/mach_timer.h> |
| 147 | #define PMTMR_EXPECTED_RATE \ | 147 | #define PMTMR_EXPECTED_RATE \ |
| 148 | ((CALIBRATE_LATCH * (PMTMR_TICKS_PER_SEC >> 10)) / (CLOCK_TICK_RATE>>10)) | 148 | ((CALIBRATE_LATCH * (PMTMR_TICKS_PER_SEC >> 10)) / (CLOCK_TICK_RATE>>10)) |
| 149 | /* | 149 | /* |
diff --git a/drivers/clocksource/cyclone.c b/drivers/clocksource/cyclone.c index 1bde303b970b..8615059a8729 100644 --- a/drivers/clocksource/cyclone.c +++ b/drivers/clocksource/cyclone.c | |||
| @@ -7,7 +7,7 @@ | |||
| 7 | #include <asm/pgtable.h> | 7 | #include <asm/pgtable.h> |
| 8 | #include <asm/io.h> | 8 | #include <asm/io.h> |
| 9 | 9 | ||
| 10 | #include "mach_timer.h" | 10 | #include <asm/mach_timer.h> |
| 11 | 11 | ||
| 12 | #define CYCLONE_CBAR_ADDR 0xFEB00CD0 /* base address ptr */ | 12 | #define CYCLONE_CBAR_ADDR 0xFEB00CD0 /* base address ptr */ |
| 13 | #define CYCLONE_PMCC_OFFSET 0x51A0 /* offset to control register */ | 13 | #define CYCLONE_PMCC_OFFSET 0x51A0 /* offset to control register */ |