Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull timer changes from Ingo Molnar:
  - ARM clocksource/clockevent improvements and fixes
  - generic timekeeping updates: TAI fixes/improvements, cleanups
  - Posix cpu timer cleanups and improvements
  - dynticks updates: full dynticks bugfixes, optimizations and cleanups

* 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (46 commits)
  clocksource: Timer-sun5i: Switch to sched_clock_register()
  timekeeping: Remove comment that's mostly out of date
  rtc-cmos: Add an alarm disable quirk
  timekeeper: fix comment typo for tk_setup_internals()
  timekeeping: Fix missing timekeeping_update in suspend path
  timekeeping: Fix CLOCK_TAI timer/nanosleep delays
  tick/timekeeping: Call update_wall_time outside the jiffies lock
  timekeeping: Avoid possible deadlock from clock_was_set_delayed
  timekeeping: Fix potential lost pv notification of time change
  timekeeping: Fix lost updates to tai adjustment
  clocksource: sh_cmt: Add clk_prepare/unprepare support
  clocksource: bcm_kona_timer: Remove unused bcm_timer_ids
  clocksource: vt8500: Remove deprecated IRQF_DISABLED
  clocksource: tegra: Remove deprecated IRQF_DISABLED
  clocksource: misc drivers: Remove deprecated IRQF_DISABLED
  clocksource: sh_mtu2: Remove unnecessary platform_set_drvdata()
  clocksource: sh_tmu: Remove unnecessary platform_set_drvdata()
  clocksource: armada-370-xp: Enable timer divider only when needed
  clocksource: clksrc-of: Warn if no clock sources are found
  clocksource: orion: Switch to sched_clock_register()
  ...

19 files changed, 248 insertions, 47 deletions

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 634c4d6dd45a..cd6950fd8caf 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -37,6 +37,10 @@ config SUN4I_TIMER
         select CLKSRC_MMIO
         bool
 
+config SUN5I_HSTIMER
+        select CLKSRC_MMIO
+        bool
+
 config VT8500_TIMER
         bool
 
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 33621efb9148..358358d87b6d 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_ARCH_MOXART)	+= moxart_timer.o
 obj-$(CONFIG_ARCH_MXS)          += mxs_timer.o
 obj-$(CONFIG_ARCH_PRIMA2)       += timer-prima2.o
 obj-$(CONFIG_SUN4I_TIMER)       += sun4i_timer.o
+obj-$(CONFIG_SUN5I_HSTIMER)     += timer-sun5i.o
 obj-$(CONFIG_ARCH_TEGRA)        += tegra20_timer.o
 obj-$(CONFIG_VT8500_TIMER)      += vt8500_timer.o
 obj-$(CONFIG_ARCH_NSPIRE)       += zevio-timer.o
diff --git a/drivers/clocksource/arm_global_timer.c b/drivers/clocksource/arm_global_timer.c
index c639b1a9e996..0fc31d029e52 100644
--- a/drivers/clocksource/arm_global_timer.c
+++ b/drivers/clocksource/arm_global_timer.c
@@ -202,7 +202,7 @@ static struct clocksource gt_clocksource = {
 };
 
 #ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
-static u32 notrace gt_sched_clock_read(void)
+static u64 notrace gt_sched_clock_read(void)
 {
         return gt_counter_read();
 }
@@ -217,7 +217,7 @@ static void __init gt_clocksource_init(void)
         writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
 
 #ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
-        setup_sched_clock(gt_sched_clock_read, 32, gt_clk_rate);
+        sched_clock_register(gt_sched_clock_read, 64, gt_clk_rate);
 #endif
         clocksource_register_hz(&gt_clocksource, gt_clk_rate);
 }
diff --git a/drivers/clocksource/bcm_kona_timer.c b/drivers/clocksource/bcm_kona_timer.c
index 0d7d8c3ed6b2..5176e761166b 100644
--- a/drivers/clocksource/bcm_kona_timer.c
+++ b/drivers/clocksource/bcm_kona_timer.c
@@ -98,12 +98,6 @@ kona_timer_get_counter(void *timer_base, uint32_t *msw, uint32_t *lsw)
         return;
 }
 
-static const struct of_device_id bcm_timer_ids[] __initconst = {
-        {.compatible = "brcm,kona-timer"},
-        {.compatible = "bcm,kona-timer"}, /* deprecated name */
-        {},
-};
-
 static void __init kona_timers_init(struct device_node *node)
 {
         u32 freq;
diff --git a/drivers/clocksource/cadence_ttc_timer.c b/drivers/clocksource/cadence_ttc_timer.c
index a92350b55d32..63f176de0d02 100644
--- a/drivers/clocksource/cadence_ttc_timer.c
+++ b/drivers/clocksource/cadence_ttc_timer.c
@@ -160,7 +160,7 @@ static cycle_t __ttc_clocksource_read(struct clocksource *cs)
                                 TTC_COUNT_VAL_OFFSET);
 }
 
-static u32 notrace ttc_sched_clock_read(void)
+static u64 notrace ttc_sched_clock_read(void)
 {
         return __raw_readl(ttc_sched_clock_val_reg);
 }
@@ -308,7 +308,7 @@ static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base)
         }
 
         ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET;
-        setup_sched_clock(ttc_sched_clock_read, 16, ttccs->ttc.freq / PRESCALE);
+        sched_clock_register(ttc_sched_clock_read, 16, ttccs->ttc.freq / PRESCALE);
 }
 
 static int ttc_rate_change_clockevent_cb(struct notifier_block *nb,
@@ -393,8 +393,7 @@ static void __init ttc_setup_clockevent(struct clk *clk,
         __raw_writel(0x1,  ttcce->ttc.base_addr + TTC_IER_OFFSET);
 
         err = request_irq(irq, ttc_clock_event_interrupt,
-                          IRQF_DISABLED | IRQF_TIMER,
-                          ttcce->ce.name, ttcce);
+                          IRQF_TIMER, ttcce->ce.name, ttcce);
         if (WARN_ON(err)) {
                 kfree(ttcce);
                 return;
diff --git a/drivers/clocksource/clksrc-of.c b/drivers/clocksource/clksrc-of.c
index b9ddd9e3a2f5..ae2e4278c42a 100644
--- a/drivers/clocksource/clksrc-of.c
+++ b/drivers/clocksource/clksrc-of.c
@@ -28,6 +28,7 @@ void __init clocksource_of_init(void)
         struct device_node *np;
         const struct of_device_id *match;
         clocksource_of_init_fn init_func;
+        unsigned clocksources = 0;
 
         for_each_matching_node_and_match(np, __clksrc_of_table, &match) {
                 if (!of_device_is_available(np))
@@ -35,5 +36,8 @@ void __init clocksource_of_init(void)
 
                 init_func = match->data;
                 init_func(np);
+                clocksources++;
         }
+        if (!clocksources)
+                pr_crit("%s: no matching clocksources found\n", __func__);
 }
diff --git a/drivers/clocksource/cs5535-clockevt.c b/drivers/clocksource/cs5535-clockevt.c
index ea210482dd20..db2105290898 100644
--- a/drivers/clocksource/cs5535-clockevt.c
+++ b/drivers/clocksource/cs5535-clockevt.c
@@ -131,7 +131,7 @@ static irqreturn_t mfgpt_tick(int irq, void *dev_id)
 
 static struct irqaction mfgptirq  = {
         .handler = mfgpt_tick,
-        .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_TIMER | IRQF_SHARED,
+        .flags = IRQF_NOBALANCING | IRQF_TIMER | IRQF_SHARED,
         .name = DRV_NAME,
 };
 
diff --git a/drivers/clocksource/dw_apb_timer.c b/drivers/clocksource/dw_apb_timer.c
index e54ca1062d8e..f3656a6b0382 100644
--- a/drivers/clocksource/dw_apb_timer.c
+++ b/drivers/clocksource/dw_apb_timer.c
@@ -243,8 +243,7 @@ dw_apb_clockevent_init(int cpu, const char *name, unsigned rating,
         dw_ced->irqaction.dev_id        = &dw_ced->ced;
         dw_ced->irqaction.irq           = irq;
         dw_ced->irqaction.flags         = IRQF_TIMER | IRQF_IRQPOLL |
-                                          IRQF_NOBALANCING |
-                                          IRQF_DISABLED;
+                                          IRQF_NOBALANCING;
 
         dw_ced->eoi = apbt_eoi;
         err = setup_irq(irq, &dw_ced->irqaction);
diff --git a/drivers/clocksource/nomadik-mtu.c b/drivers/clocksource/nomadik-mtu.c
index ed7b73b508e0..152a3f3875ee 100644
--- a/drivers/clocksource/nomadik-mtu.c
+++ b/drivers/clocksource/nomadik-mtu.c
@@ -187,7 +187,7 @@ static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
 
 static struct irqaction nmdk_timer_irq = {
         .name           = "Nomadik Timer Tick",
-        .flags          = IRQF_DISABLED | IRQF_TIMER,
+        .flags          = IRQF_TIMER,
         .handler        = nmdk_timer_interrupt,
         .dev_id         = &nmdk_clkevt,
 };
diff --git a/drivers/clocksource/samsung_pwm_timer.c b/drivers/clocksource/samsung_pwm_timer.c
index 85082e8d3052..5645cfc90c41 100644
--- a/drivers/clocksource/samsung_pwm_timer.c
+++ b/drivers/clocksource/samsung_pwm_timer.c
@@ -264,7 +264,7 @@ static irqreturn_t samsung_clock_event_isr(int irq, void *dev_id)
 
 static struct irqaction samsung_clock_event_irq = {
         .name           = "samsung_time_irq",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .flags          = IRQF_TIMER | IRQF_IRQPOLL,
         .handler        = samsung_clock_event_isr,
         .dev_id         = &time_event_device,
 };
diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c
index 0965e9848b3d..0b1836a6c539 100644
--- a/drivers/clocksource/sh_cmt.c
+++ b/drivers/clocksource/sh_cmt.c
@@ -634,12 +634,18 @@ static int sh_cmt_clock_event_next(unsigned long delta,
 
 static void sh_cmt_clock_event_suspend(struct clock_event_device *ced)
 {
-        pm_genpd_syscore_poweroff(&ced_to_sh_cmt(ced)->pdev->dev);
+        struct sh_cmt_priv *p = ced_to_sh_cmt(ced);
+
+        pm_genpd_syscore_poweroff(&p->pdev->dev);
+        clk_unprepare(p->clk);
 }
 
 static void sh_cmt_clock_event_resume(struct clock_event_device *ced)
 {
-        pm_genpd_syscore_poweron(&ced_to_sh_cmt(ced)->pdev->dev);
+        struct sh_cmt_priv *p = ced_to_sh_cmt(ced);
+
+        clk_prepare(p->clk);
+        pm_genpd_syscore_poweron(&p->pdev->dev);
 }
 
 static void sh_cmt_register_clockevent(struct sh_cmt_priv *p,
@@ -726,8 +732,7 @@ static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
         p->irqaction.name = dev_name(&p->pdev->dev);
         p->irqaction.handler = sh_cmt_interrupt;
         p->irqaction.dev_id = p;
-        p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
-                             IRQF_IRQPOLL  | IRQF_NOBALANCING;
+        p->irqaction.flags = IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING;
 
         /* get hold of clock */
         p->clk = clk_get(&p->pdev->dev, "cmt_fck");
@@ -737,6 +742,10 @@ static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
                 goto err2;
         }
 
+        ret = clk_prepare(p->clk);
+        if (ret < 0)
+                goto err3;
+
         if (res2 && (resource_size(res2) == 4)) {
                 /* assume both CMSTR and CMCSR to be 32-bit */
                 p->read_control = sh_cmt_read32;
@@ -773,19 +782,21 @@ static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
                               cfg->clocksource_rating);
         if (ret) {
                 dev_err(&p->pdev->dev, "registration failed\n");
-                goto err3;
+                goto err4;
         }
         p->cs_enabled = false;
 
         ret = setup_irq(irq, &p->irqaction);
         if (ret) {
                 dev_err(&p->pdev->dev, "failed to request irq %d\n", irq);
-                goto err3;
+                goto err4;
         }
 
         platform_set_drvdata(pdev, p);
 
         return 0;
+err4:
+        clk_unprepare(p->clk);
 err3:
         clk_put(p->clk);
 err2:
diff --git a/drivers/clocksource/sh_mtu2.c b/drivers/clocksource/sh_mtu2.c
index 3cf12834681e..e30d76e0a6fa 100644
--- a/drivers/clocksource/sh_mtu2.c
+++ b/drivers/clocksource/sh_mtu2.c
@@ -302,8 +302,7 @@ static int sh_mtu2_setup(struct sh_mtu2_priv *p, struct platform_device *pdev)
         p->irqaction.handler = sh_mtu2_interrupt;
         p->irqaction.dev_id = p;
         p->irqaction.irq = irq;
-        p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
-                             IRQF_IRQPOLL  | IRQF_NOBALANCING;
+        p->irqaction.flags = IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING;
 
         /* get hold of clock */
         p->clk = clk_get(&p->pdev->dev, "mtu2_fck");
@@ -358,7 +357,6 @@ static int sh_mtu2_probe(struct platform_device *pdev)
         ret = sh_mtu2_setup(p, pdev);
         if (ret) {
                 kfree(p);
-                platform_set_drvdata(pdev, NULL);
                 pm_runtime_idle(&pdev->dev);
                 return ret;
         }
diff --git a/drivers/clocksource/sh_tmu.c b/drivers/clocksource/sh_tmu.c
index 63557cda0a7d..ecd7b60bfdfa 100644
--- a/drivers/clocksource/sh_tmu.c
+++ b/drivers/clocksource/sh_tmu.c
@@ -462,8 +462,7 @@ static int sh_tmu_setup(struct sh_tmu_priv *p, struct platform_device *pdev)
         p->irqaction.handler = sh_tmu_interrupt;
         p->irqaction.dev_id = p;
         p->irqaction.irq = irq;
-        p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
-                             IRQF_IRQPOLL  | IRQF_NOBALANCING;
+        p->irqaction.flags = IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING;
 
         /* get hold of clock */
         p->clk = clk_get(&p->pdev->dev, "tmu_fck");
@@ -523,7 +522,6 @@ static int sh_tmu_probe(struct platform_device *pdev)
         ret = sh_tmu_setup(p, pdev);
         if (ret) {
                 kfree(p);
-                platform_set_drvdata(pdev, NULL);
                 pm_runtime_idle(&pdev->dev);
                 return ret;
         }
diff --git a/drivers/clocksource/sun4i_timer.c b/drivers/clocksource/sun4i_timer.c
index a4f6119aafd8..bf497afba9ad 100644
--- a/drivers/clocksource/sun4i_timer.c
+++ b/drivers/clocksource/sun4i_timer.c
@@ -114,7 +114,7 @@ static int sun4i_clkevt_next_event(unsigned long evt,
 
 static struct clock_event_device sun4i_clockevent = {
         .name = "sun4i_tick",
-        .rating = 300,
+        .rating = 350,
         .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
         .set_mode = sun4i_clkevt_mode,
         .set_next_event = sun4i_clkevt_next_event,
@@ -138,7 +138,7 @@ static struct irqaction sun4i_timer_irq = {
         .dev_id = &sun4i_clockevent,
 };
 
-static u32 sun4i_timer_sched_read(void)
+static u64 notrace sun4i_timer_sched_read(void)
 {
         return ~readl(timer_base + TIMER_CNTVAL_REG(1));
 }
@@ -170,9 +170,9 @@ static void __init sun4i_timer_init(struct device_node *node)
                TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
                timer_base + TIMER_CTL_REG(1));
 
-        setup_sched_clock(sun4i_timer_sched_read, 32, rate);
+        sched_clock_register(sun4i_timer_sched_read, 32, rate);
         clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name,
-                              rate, 300, 32, clocksource_mmio_readl_down);
+                              rate, 350, 32, clocksource_mmio_readl_down);
 
         ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
 
@@ -190,7 +190,8 @@ static void __init sun4i_timer_init(struct device_node *node)
         val = readl(timer_base + TIMER_IRQ_EN_REG);
         writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
 
-        sun4i_clockevent.cpumask = cpumask_of(0);
+        sun4i_clockevent.cpumask = cpu_possible_mask;
+        sun4i_clockevent.irq = irq;
 
         clockevents_config_and_register(&sun4i_clockevent, rate,
                                         TIMER_SYNC_TICKS, 0xffffffff);
diff --git a/drivers/clocksource/tegra20_timer.c b/drivers/clocksource/tegra20_timer.c
index 642849256d82..d1869f02051c 100644
--- a/drivers/clocksource/tegra20_timer.c
+++ b/drivers/clocksource/tegra20_timer.c
@@ -149,7 +149,7 @@ static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
 
 static struct irqaction tegra_timer_irq = {
         .name           = "timer0",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_HIGH,
+        .flags          = IRQF_TIMER | IRQF_TRIGGER_HIGH,
         .handler        = tegra_timer_interrupt,
         .dev_id         = &tegra_clockevent,
 };
diff --git a/drivers/clocksource/time-armada-370-xp.c b/drivers/clocksource/time-armada-370-xp.c
index 4e7f6802e840..ee8691b89944 100644
--- a/drivers/clocksource/time-armada-370-xp.c
+++ b/drivers/clocksource/time-armada-370-xp.c
@@ -76,6 +76,7 @@
 static void __iomem *timer_base, *local_base;
 static unsigned int timer_clk;
 static bool timer25Mhz = true;
+static u32 enable_mask;
 
 /*
  * Number of timer ticks per jiffy.
@@ -121,8 +122,7 @@ armada_370_xp_clkevt_next_event(unsigned long delta,
         /*
          * Enable the timer.
          */
-        local_timer_ctrl_clrset(TIMER0_RELOAD_EN,
-                                TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT));
+        local_timer_ctrl_clrset(TIMER0_RELOAD_EN, enable_mask);
         return 0;
 }
 
@@ -141,9 +141,7 @@ armada_370_xp_clkevt_mode(enum clock_event_mode mode,
                 /*
                  * Enable timer.
                  */
-                local_timer_ctrl_clrset(0, TIMER0_RELOAD_EN |
-                                           TIMER0_EN |
-                                           TIMER0_DIV(TIMER_DIVIDER_SHIFT));
+                local_timer_ctrl_clrset(0, TIMER0_RELOAD_EN | enable_mask);
         } else {
                 /*
                  * Disable timer.
@@ -240,10 +238,13 @@ static void __init armada_370_xp_timer_common_init(struct device_node *np)
         WARN_ON(!timer_base);
         local_base = of_iomap(np, 1);
 
-        if (timer25Mhz)
+        if (timer25Mhz) {
                 set = TIMER0_25MHZ;             
-        else
+                enable_mask = TIMER0_EN;
+        } else {
                 clr = TIMER0_25MHZ;
+                enable_mask = TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT);
+        }
         timer_ctrl_clrset(clr, set);
         local_timer_ctrl_clrset(clr, set);
 
@@ -262,8 +263,7 @@ static void __init armada_370_xp_timer_common_init(struct device_node *np)
         writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
         writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
 
-        timer_ctrl_clrset(0, TIMER0_EN | TIMER0_RELOAD_EN |
-                             TIMER0_DIV(TIMER_DIVIDER_SHIFT));
+        timer_ctrl_clrset(0, TIMER0_RELOAD_EN | enable_mask);
 
         /*
          * Set scale and timer for sched_clock.
diff --git a/drivers/clocksource/time-orion.c b/drivers/clocksource/time-orion.c
index 9c7f018a67ca..20066222f3f2 100644
--- a/drivers/clocksource/time-orion.c
+++ b/drivers/clocksource/time-orion.c
@@ -53,7 +53,7 @@ EXPORT_SYMBOL(orion_timer_ctrl_clrset);
 /*
  * Free-running clocksource handling.
  */
-static u32 notrace orion_read_sched_clock(void)
+static u64 notrace orion_read_sched_clock(void)
 {
         return ~readl(timer_base + TIMER0_VAL);
 }
@@ -135,7 +135,7 @@ static void __init orion_timer_init(struct device_node *np)
         clocksource_mmio_init(timer_base + TIMER0_VAL, "orion_clocksource",
                               clk_get_rate(clk), 300, 32,
                               clocksource_mmio_readl_down);
-        setup_sched_clock(orion_read_sched_clock, 32, clk_get_rate(clk));
+        sched_clock_register(orion_read_sched_clock, 32, clk_get_rate(clk));
 
         /* setup timer1 as clockevent timer */
         if (setup_irq(irq, &orion_clkevt_irq))
diff --git a/drivers/clocksource/timer-sun5i.c b/drivers/clocksource/timer-sun5i.c
new file mode 100644
index 000000000000..deebcd6469fc
--- /dev/null
+++ b/drivers/clocksource/timer-sun5i.c
@@ -0,0 +1,192 @@
+/*
+ * Allwinner SoCs hstimer driver.
+ *
+ * Copyright (C) 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/irqreturn.h>
+#include <linux/sched_clock.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#define TIMER_IRQ_EN_REG                0x00
+#define TIMER_IRQ_EN(val)                       BIT(val)
+#define TIMER_IRQ_ST_REG                0x04
+#define TIMER_CTL_REG(val)              (0x20 * (val) + 0x10)
+#define TIMER_CTL_ENABLE                        BIT(0)
+#define TIMER_CTL_RELOAD                        BIT(1)
+#define TIMER_CTL_CLK_PRES(val)                 (((val) & 0x7) << 4)
+#define TIMER_CTL_ONESHOT                       BIT(7)
+#define TIMER_INTVAL_LO_REG(val)        (0x20 * (val) + 0x14)
+#define TIMER_INTVAL_HI_REG(val)        (0x20 * (val) + 0x18)
+#define TIMER_CNTVAL_LO_REG(val)        (0x20 * (val) + 0x1c)
+#define TIMER_CNTVAL_HI_REG(val)        (0x20 * (val) + 0x20)
+
+#define TIMER_SYNC_TICKS        3
+
+static void __iomem *timer_base;
+static u32 ticks_per_jiffy;
+
+/*
+ * When we disable a timer, we need to wait at least for 2 cycles of
+ * the timer source clock. We will use for that the clocksource timer
+ * that is already setup and runs at the same frequency than the other
+ * timers, and we never will be disabled.
+ */
+static void sun5i_clkevt_sync(void)
+{
+        u32 old = readl(timer_base + TIMER_CNTVAL_LO_REG(1));
+
+        while ((old - readl(timer_base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS)
+                cpu_relax();
+}
+
+static void sun5i_clkevt_time_stop(u8 timer)
+{
+        u32 val = readl(timer_base + TIMER_CTL_REG(timer));
+        writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer));
+
+        sun5i_clkevt_sync();
+}
+
+static void sun5i_clkevt_time_setup(u8 timer, u32 delay)
+{
+        writel(delay, timer_base + TIMER_INTVAL_LO_REG(timer));
+}
+
+static void sun5i_clkevt_time_start(u8 timer, bool periodic)
+{
+        u32 val = readl(timer_base + TIMER_CTL_REG(timer));
+
+        if (periodic)
+                val &= ~TIMER_CTL_ONESHOT;
+        else
+                val |= TIMER_CTL_ONESHOT;
+
+        writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
+               timer_base + TIMER_CTL_REG(timer));
+}
+
+static void sun5i_clkevt_mode(enum clock_event_mode mode,
+                              struct clock_event_device *clk)
+{
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                sun5i_clkevt_time_stop(0);
+                sun5i_clkevt_time_setup(0, ticks_per_jiffy);
+                sun5i_clkevt_time_start(0, true);
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+                sun5i_clkevt_time_stop(0);
+                sun5i_clkevt_time_start(0, false);
+                break;
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        default:
+                sun5i_clkevt_time_stop(0);
+                break;
+        }
+}
+
+static int sun5i_clkevt_next_event(unsigned long evt,
+                                   struct clock_event_device *unused)
+{
+        sun5i_clkevt_time_stop(0);
+        sun5i_clkevt_time_setup(0, evt - TIMER_SYNC_TICKS);
+        sun5i_clkevt_time_start(0, false);
+
+        return 0;
+}
+
+static struct clock_event_device sun5i_clockevent = {
+        .name = "sun5i_tick",
+        .rating = 340,
+        .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+        .set_mode = sun5i_clkevt_mode,
+        .set_next_event = sun5i_clkevt_next_event,
+};
+
+
+static irqreturn_t sun5i_timer_interrupt(int irq, void *dev_id)
+{
+        struct clock_event_device *evt = (struct clock_event_device *)dev_id;
+
+        writel(0x1, timer_base + TIMER_IRQ_ST_REG);
+        evt->event_handler(evt);
+
+        return IRQ_HANDLED;
+}
+
+static struct irqaction sun5i_timer_irq = {
+        .name = "sun5i_timer0",
+        .flags = IRQF_TIMER | IRQF_IRQPOLL,
+        .handler = sun5i_timer_interrupt,
+        .dev_id = &sun5i_clockevent,
+};
+
+static u64 sun5i_timer_sched_read(void)
+{
+        return ~readl(timer_base + TIMER_CNTVAL_LO_REG(1));
+}
+
+static void __init sun5i_timer_init(struct device_node *node)
+{
+        unsigned long rate;
+        struct clk *clk;
+        int ret, irq;
+        u32 val;
+
+        timer_base = of_iomap(node, 0);
+        if (!timer_base)
+                panic("Can't map registers");
+
+        irq = irq_of_parse_and_map(node, 0);
+        if (irq <= 0)
+                panic("Can't parse IRQ");
+
+        clk = of_clk_get(node, 0);
+        if (IS_ERR(clk))
+                panic("Can't get timer clock");
+        clk_prepare_enable(clk);
+        rate = clk_get_rate(clk);
+
+        writel(~0, timer_base + TIMER_INTVAL_LO_REG(1));
+        writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
+               timer_base + TIMER_CTL_REG(1));
+
+        sched_clock_register(sun5i_timer_sched_read, 32, rate);
+        clocksource_mmio_init(timer_base + TIMER_CNTVAL_LO_REG(1), node->name,
+                              rate, 340, 32, clocksource_mmio_readl_down);
+
+        ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
+
+        ret = setup_irq(irq, &sun5i_timer_irq);
+        if (ret)
+                pr_warn("failed to setup irq %d\n", irq);
+
+        /* Enable timer0 interrupt */
+        val = readl(timer_base + TIMER_IRQ_EN_REG);
+        writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
+
+        sun5i_clockevent.cpumask = cpu_possible_mask;
+        sun5i_clockevent.irq = irq;
+
+        clockevents_config_and_register(&sun5i_clockevent, rate,
+                                        TIMER_SYNC_TICKS, 0xffffffff);
+}
+CLOCKSOURCE_OF_DECLARE(sun5i_a13, "allwinner,sun5i-a13-hstimer",
+                       sun5i_timer_init);
+CLOCKSOURCE_OF_DECLARE(sun7i_a20, "allwinner,sun7i-a20-hstimer",
+                       sun5i_timer_init);
diff --git a/drivers/clocksource/vt8500_timer.c b/drivers/clocksource/vt8500_timer.c
index ad3c0e83a779..1098ed3b9b89 100644
--- a/drivers/clocksource/vt8500_timer.c
+++ b/drivers/clocksource/vt8500_timer.c
@@ -124,7 +124,7 @@ static irqreturn_t vt8500_timer_interrupt(int irq, void *dev_id)
 
 static struct irqaction irq = {
         .name    = "vt8500_timer",
-        .flags   = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .flags   = IRQF_TIMER | IRQF_IRQPOLL,
         .handler = vt8500_timer_interrupt,
         .dev_id  = &clockevent,
 };