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authorLinus Torvalds <torvalds@linux-foundation.org>2013-07-06 17:09:38 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-07-06 17:09:38 -0400
commit21884a83b2192a00885d7244a1dda32debd2fbc7 (patch)
treee00267bbcac32f0114b3d21a20c61107d2314c40 /drivers/clocksource
parent8b70a90cabafb6a6e1a0d3f838b38355fe48337e (diff)
parent73b0cd674ccc64c921e25bd7154f26d342116539 (diff)
Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull timer core updates from Thomas Gleixner: "The timer changes contain: - posix timer code consolidation and fixes for odd corner cases - sched_clock implementation moved from ARM to core code to avoid duplication by other architectures - alarm timer updates - clocksource and clockevents unregistration facilities - clocksource/events support for new hardware - precise nanoseconds RTC readout (Xen feature) - generic support for Xen suspend/resume oddities - the usual lot of fixes and cleanups all over the place The parts which touch other areas (ARM/XEN) have been coordinated with the relevant maintainers. Though this results in an handful of trivial to solve merge conflicts, which we preferred over nasty cross tree merge dependencies. The patches which have been committed in the last few days are bug fixes plus the posix timer lot. The latter was in akpms queue and next for quite some time; they just got forgotten and Frederic collected them last minute." * 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (59 commits) hrtimer: Remove unused variable hrtimers: Move SMP function call to thread context clocksource: Reselect clocksource when watchdog validated high-res capability posix-cpu-timers: don't account cpu timer after stopped thread runtime accounting posix_timers: fix racy timer delta caching on task exit posix-timers: correctly get dying task time sample in posix_cpu_timer_schedule() selftests: add basic posix timers selftests posix_cpu_timers: consolidate expired timers check posix_cpu_timers: consolidate timer list cleanups posix_cpu_timer: consolidate expiry time type tick: Sanitize broadcast control logic tick: Prevent uncontrolled switch to oneshot mode tick: Make oneshot broadcast robust vs. CPU offlining x86: xen: Sync the CMOS RTC as well as the Xen wallclock x86: xen: Sync the wallclock when the system time is set timekeeping: Indicate that clock was set in the pvclock gtod notifier timekeeping: Pass flags instead of multiple bools to timekeeping_update() xen: Remove clock_was_set() call in the resume path hrtimers: Support resuming with two or more CPUs online (but stopped) timer: Fix jiffies wrap behavior of round_jiffies_common() ...
Diffstat (limited to 'drivers/clocksource')
-rw-r--r--drivers/clocksource/Kconfig5
-rw-r--r--drivers/clocksource/Makefile3
-rw-r--r--drivers/clocksource/bcm2835_timer.c2
-rw-r--r--drivers/clocksource/clksrc-dbx500-prcmu.c3
-rw-r--r--drivers/clocksource/dummy_timer.c69
-rw-r--r--drivers/clocksource/dw_apb_timer.c12
-rw-r--r--drivers/clocksource/dw_apb_timer_of.c6
-rw-r--r--drivers/clocksource/mxs_timer.c2
-rw-r--r--drivers/clocksource/nomadik-mtu.c2
-rw-r--r--drivers/clocksource/samsung_pwm_timer.c2
-rw-r--r--drivers/clocksource/tegra20_timer.c2
-rw-r--r--drivers/clocksource/time-armada-370-xp.c2
-rw-r--r--drivers/clocksource/timer-marco.c2
-rw-r--r--drivers/clocksource/timer-prima2.c2
-rw-r--r--drivers/clocksource/vf_pit_timer.c194
-rw-r--r--drivers/clocksource/zevio-timer.c215
16 files changed, 497 insertions, 26 deletions
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 5871933c4e51..81465c21f873 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -87,3 +87,8 @@ config CLKSRC_SAMSUNG_PWM
87 Samsung S3C, S5P and Exynos SoCs, replacing an earlier driver 87 Samsung S3C, S5P and Exynos SoCs, replacing an earlier driver
88 for all devicetree enabled platforms. This driver will be 88 for all devicetree enabled platforms. This driver will be
89 needed only on systems that do not have the Exynos MCT available. 89 needed only on systems that do not have the Exynos MCT available.
90
91config VF_PIT_TIMER
92 bool
93 help
94 Support for Period Interrupt Timer on Freescale Vybrid Family SoCs.
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 8d979c72aa94..9ba8b4d867e3 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -22,10 +22,13 @@ obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o
22obj-$(CONFIG_SUN4I_TIMER) += sun4i_timer.o 22obj-$(CONFIG_SUN4I_TIMER) += sun4i_timer.o
23obj-$(CONFIG_ARCH_TEGRA) += tegra20_timer.o 23obj-$(CONFIG_ARCH_TEGRA) += tegra20_timer.o
24obj-$(CONFIG_VT8500_TIMER) += vt8500_timer.o 24obj-$(CONFIG_VT8500_TIMER) += vt8500_timer.o
25obj-$(CONFIG_ARCH_NSPIRE) += zevio-timer.o
25obj-$(CONFIG_ARCH_BCM) += bcm_kona_timer.o 26obj-$(CONFIG_ARCH_BCM) += bcm_kona_timer.o
26obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence_ttc_timer.o 27obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence_ttc_timer.o
27obj-$(CONFIG_CLKSRC_EXYNOS_MCT) += exynos_mct.o 28obj-$(CONFIG_CLKSRC_EXYNOS_MCT) += exynos_mct.o
28obj-$(CONFIG_CLKSRC_SAMSUNG_PWM) += samsung_pwm_timer.o 29obj-$(CONFIG_CLKSRC_SAMSUNG_PWM) += samsung_pwm_timer.o
30obj-$(CONFIG_VF_PIT_TIMER) += vf_pit_timer.o
29 31
30obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o 32obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
31obj-$(CONFIG_CLKSRC_METAG_GENERIC) += metag_generic.o 33obj-$(CONFIG_CLKSRC_METAG_GENERIC) += metag_generic.o
34obj-$(CONFIG_ARCH_HAS_TICK_BROADCAST) += dummy_timer.o
diff --git a/drivers/clocksource/bcm2835_timer.c b/drivers/clocksource/bcm2835_timer.c
index 766611d29945..07ea7ce900dc 100644
--- a/drivers/clocksource/bcm2835_timer.c
+++ b/drivers/clocksource/bcm2835_timer.c
@@ -28,8 +28,8 @@
28#include <linux/of_platform.h> 28#include <linux/of_platform.h>
29#include <linux/slab.h> 29#include <linux/slab.h>
30#include <linux/string.h> 30#include <linux/string.h>
31#include <linux/sched_clock.h>
31 32
32#include <asm/sched_clock.h>
33#include <asm/irq.h> 33#include <asm/irq.h>
34 34
35#define REG_CONTROL 0x00 35#define REG_CONTROL 0x00
diff --git a/drivers/clocksource/clksrc-dbx500-prcmu.c b/drivers/clocksource/clksrc-dbx500-prcmu.c
index 77398f8c19a0..a9fd4ad25674 100644
--- a/drivers/clocksource/clksrc-dbx500-prcmu.c
+++ b/drivers/clocksource/clksrc-dbx500-prcmu.c
@@ -14,8 +14,7 @@
14 */ 14 */
15#include <linux/clockchips.h> 15#include <linux/clockchips.h>
16#include <linux/clksrc-dbx500-prcmu.h> 16#include <linux/clksrc-dbx500-prcmu.h>
17 17#include <linux/sched_clock.h>
18#include <asm/sched_clock.h>
19 18
20#define RATE_32K 32768 19#define RATE_32K 32768
21 20
diff --git a/drivers/clocksource/dummy_timer.c b/drivers/clocksource/dummy_timer.c
new file mode 100644
index 000000000000..1f55f9620338
--- /dev/null
+++ b/drivers/clocksource/dummy_timer.c
@@ -0,0 +1,69 @@
1/*
2 * linux/drivers/clocksource/dummy_timer.c
3 *
4 * Copyright (C) 2013 ARM Ltd.
5 * All Rights Reserved
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/clockchips.h>
12#include <linux/cpu.h>
13#include <linux/init.h>
14#include <linux/percpu.h>
15#include <linux/cpumask.h>
16
17static DEFINE_PER_CPU(struct clock_event_device, dummy_timer_evt);
18
19static void dummy_timer_set_mode(enum clock_event_mode mode,
20 struct clock_event_device *evt)
21{
22 /*
23 * Core clockevents code will call this when exchanging timer devices.
24 * We don't need to do anything here.
25 */
26}
27
28static void __cpuinit dummy_timer_setup(void)
29{
30 int cpu = smp_processor_id();
31 struct clock_event_device *evt = __this_cpu_ptr(&dummy_timer_evt);
32
33 evt->name = "dummy_timer";
34 evt->features = CLOCK_EVT_FEAT_PERIODIC |
35 CLOCK_EVT_FEAT_ONESHOT |
36 CLOCK_EVT_FEAT_DUMMY;
37 evt->rating = 100;
38 evt->set_mode = dummy_timer_set_mode;
39 evt->cpumask = cpumask_of(cpu);
40
41 clockevents_register_device(evt);
42}
43
44static int __cpuinit dummy_timer_cpu_notify(struct notifier_block *self,
45 unsigned long action, void *hcpu)
46{
47 if ((action & ~CPU_TASKS_FROZEN) == CPU_STARTING)
48 dummy_timer_setup();
49
50 return NOTIFY_OK;
51}
52
53static struct notifier_block dummy_timer_cpu_nb __cpuinitdata = {
54 .notifier_call = dummy_timer_cpu_notify,
55};
56
57static int __init dummy_timer_register(void)
58{
59 int err = register_cpu_notifier(&dummy_timer_cpu_nb);
60 if (err)
61 return err;
62
63 /* We won't get a call on the boot CPU, so register immediately */
64 if (num_possible_cpus() > 1)
65 dummy_timer_setup();
66
67 return 0;
68}
69early_initcall(dummy_timer_register);
diff --git a/drivers/clocksource/dw_apb_timer.c b/drivers/clocksource/dw_apb_timer.c
index 8c2a35f26d9b..e54ca1062d8e 100644
--- a/drivers/clocksource/dw_apb_timer.c
+++ b/drivers/clocksource/dw_apb_timer.c
@@ -387,15 +387,3 @@ cycle_t dw_apb_clocksource_read(struct dw_apb_clocksource *dw_cs)
387{ 387{
388 return (cycle_t)~apbt_readl(&dw_cs->timer, APBTMR_N_CURRENT_VALUE); 388 return (cycle_t)~apbt_readl(&dw_cs->timer, APBTMR_N_CURRENT_VALUE);
389} 389}
390
391/**
392 * dw_apb_clocksource_unregister() - unregister and free a clocksource.
393 *
394 * @dw_cs: The clocksource to unregister/free.
395 */
396void dw_apb_clocksource_unregister(struct dw_apb_clocksource *dw_cs)
397{
398 clocksource_unregister(&dw_cs->cs);
399
400 kfree(dw_cs);
401}
diff --git a/drivers/clocksource/dw_apb_timer_of.c b/drivers/clocksource/dw_apb_timer_of.c
index cef554432a33..4cbae4f762b1 100644
--- a/drivers/clocksource/dw_apb_timer_of.c
+++ b/drivers/clocksource/dw_apb_timer_of.c
@@ -21,9 +21,7 @@
21#include <linux/of_address.h> 21#include <linux/of_address.h>
22#include <linux/of_irq.h> 22#include <linux/of_irq.h>
23#include <linux/clk.h> 23#include <linux/clk.h>
24 24#include <linux/sched_clock.h>
25#include <asm/mach/time.h>
26#include <asm/sched_clock.h>
27 25
28static void timer_get_base_and_rate(struct device_node *np, 26static void timer_get_base_and_rate(struct device_node *np,
29 void __iomem **base, u32 *rate) 27 void __iomem **base, u32 *rate)
@@ -68,7 +66,7 @@ static void add_clockevent(struct device_node *event_timer)
68 u32 irq, rate; 66 u32 irq, rate;
69 67
70 irq = irq_of_parse_and_map(event_timer, 0); 68 irq = irq_of_parse_and_map(event_timer, 0);
71 if (irq == NO_IRQ) 69 if (irq == 0)
72 panic("No IRQ for clock event timer"); 70 panic("No IRQ for clock event timer");
73 71
74 timer_get_base_and_rate(event_timer, &iobase, &rate); 72 timer_get_base_and_rate(event_timer, &iobase, &rate);
diff --git a/drivers/clocksource/mxs_timer.c b/drivers/clocksource/mxs_timer.c
index 02af4204af86..0f5e65f74dc3 100644
--- a/drivers/clocksource/mxs_timer.c
+++ b/drivers/clocksource/mxs_timer.c
@@ -29,9 +29,9 @@
29#include <linux/of_address.h> 29#include <linux/of_address.h>
30#include <linux/of_irq.h> 30#include <linux/of_irq.h>
31#include <linux/stmp_device.h> 31#include <linux/stmp_device.h>
32#include <linux/sched_clock.h>
32 33
33#include <asm/mach/time.h> 34#include <asm/mach/time.h>
34#include <asm/sched_clock.h>
35 35
36/* 36/*
37 * There are 2 versions of the timrot on Freescale MXS-based SoCs. 37 * There are 2 versions of the timrot on Freescale MXS-based SoCs.
diff --git a/drivers/clocksource/nomadik-mtu.c b/drivers/clocksource/nomadik-mtu.c
index b9415b622f55..7d2c2c56f73c 100644
--- a/drivers/clocksource/nomadik-mtu.c
+++ b/drivers/clocksource/nomadik-mtu.c
@@ -21,8 +21,8 @@
21#include <linux/delay.h> 21#include <linux/delay.h>
22#include <linux/err.h> 22#include <linux/err.h>
23#include <linux/platform_data/clocksource-nomadik-mtu.h> 23#include <linux/platform_data/clocksource-nomadik-mtu.h>
24#include <linux/sched_clock.h>
24#include <asm/mach/time.h> 25#include <asm/mach/time.h>
25#include <asm/sched_clock.h>
26 26
27/* 27/*
28 * The MTU device hosts four different counters, with 4 set of 28 * The MTU device hosts four different counters, with 4 set of
diff --git a/drivers/clocksource/samsung_pwm_timer.c b/drivers/clocksource/samsung_pwm_timer.c
index 0234c8d2c8f2..584b5472eea3 100644
--- a/drivers/clocksource/samsung_pwm_timer.c
+++ b/drivers/clocksource/samsung_pwm_timer.c
@@ -21,10 +21,10 @@
21#include <linux/of_irq.h> 21#include <linux/of_irq.h>
22#include <linux/platform_device.h> 22#include <linux/platform_device.h>
23#include <linux/slab.h> 23#include <linux/slab.h>
24#include <linux/sched_clock.h>
24 25
25#include <clocksource/samsung_pwm.h> 26#include <clocksource/samsung_pwm.h>
26 27
27#include <asm/sched_clock.h>
28 28
29/* 29/*
30 * Clocksource driver 30 * Clocksource driver
diff --git a/drivers/clocksource/tegra20_timer.c b/drivers/clocksource/tegra20_timer.c
index ae877b021b54..93961703b887 100644
--- a/drivers/clocksource/tegra20_timer.c
+++ b/drivers/clocksource/tegra20_timer.c
@@ -26,10 +26,10 @@
26#include <linux/io.h> 26#include <linux/io.h>
27#include <linux/of_address.h> 27#include <linux/of_address.h>
28#include <linux/of_irq.h> 28#include <linux/of_irq.h>
29#include <linux/sched_clock.h>
29 30
30#include <asm/mach/time.h> 31#include <asm/mach/time.h>
31#include <asm/smp_twd.h> 32#include <asm/smp_twd.h>
32#include <asm/sched_clock.h>
33 33
34#define RTC_SECONDS 0x08 34#define RTC_SECONDS 0x08
35#define RTC_SHADOW_SECONDS 0x0c 35#define RTC_SHADOW_SECONDS 0x0c
diff --git a/drivers/clocksource/time-armada-370-xp.c b/drivers/clocksource/time-armada-370-xp.c
index 47a673070d70..efdca3263afe 100644
--- a/drivers/clocksource/time-armada-370-xp.c
+++ b/drivers/clocksource/time-armada-370-xp.c
@@ -27,8 +27,8 @@
27#include <linux/of_address.h> 27#include <linux/of_address.h>
28#include <linux/irq.h> 28#include <linux/irq.h>
29#include <linux/module.h> 29#include <linux/module.h>
30#include <linux/sched_clock.h>
30 31
31#include <asm/sched_clock.h>
32#include <asm/localtimer.h> 32#include <asm/localtimer.h>
33#include <linux/percpu.h> 33#include <linux/percpu.h>
34/* 34/*
diff --git a/drivers/clocksource/timer-marco.c b/drivers/clocksource/timer-marco.c
index 97738dbf3e3b..e5dc9129ca26 100644
--- a/drivers/clocksource/timer-marco.c
+++ b/drivers/clocksource/timer-marco.c
@@ -17,7 +17,7 @@
17#include <linux/of.h> 17#include <linux/of.h>
18#include <linux/of_irq.h> 18#include <linux/of_irq.h>
19#include <linux/of_address.h> 19#include <linux/of_address.h>
20#include <asm/sched_clock.h> 20#include <linux/sched_clock.h>
21#include <asm/localtimer.h> 21#include <asm/localtimer.h>
22#include <asm/mach/time.h> 22#include <asm/mach/time.h>
23 23
diff --git a/drivers/clocksource/timer-prima2.c b/drivers/clocksource/timer-prima2.c
index 760882665d7a..ef3cfb269d8b 100644
--- a/drivers/clocksource/timer-prima2.c
+++ b/drivers/clocksource/timer-prima2.c
@@ -18,7 +18,7 @@
18#include <linux/of.h> 18#include <linux/of.h>
19#include <linux/of_irq.h> 19#include <linux/of_irq.h>
20#include <linux/of_address.h> 20#include <linux/of_address.h>
21#include <asm/sched_clock.h> 21#include <linux/sched_clock.h>
22#include <asm/mach/time.h> 22#include <asm/mach/time.h>
23 23
24#define SIRFSOC_TIMER_COUNTER_LO 0x0000 24#define SIRFSOC_TIMER_COUNTER_LO 0x0000
diff --git a/drivers/clocksource/vf_pit_timer.c b/drivers/clocksource/vf_pit_timer.c
new file mode 100644
index 000000000000..587e0202a70b
--- /dev/null
+++ b/drivers/clocksource/vf_pit_timer.c
@@ -0,0 +1,194 @@
1/*
2 * Copyright 2012-2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 */
9
10#include <linux/interrupt.h>
11#include <linux/clockchips.h>
12#include <linux/clk.h>
13#include <linux/of_address.h>
14#include <linux/of_irq.h>
15#include <linux/sched_clock.h>
16
17/*
18 * Each pit takes 0x10 Bytes register space
19 */
20#define PITMCR 0x00
21#define PIT0_OFFSET 0x100
22#define PITn_OFFSET(n) (PIT0_OFFSET + 0x10 * (n))
23#define PITLDVAL 0x00
24#define PITCVAL 0x04
25#define PITTCTRL 0x08
26#define PITTFLG 0x0c
27
28#define PITMCR_MDIS (0x1 << 1)
29
30#define PITTCTRL_TEN (0x1 << 0)
31#define PITTCTRL_TIE (0x1 << 1)
32#define PITCTRL_CHN (0x1 << 2)
33
34#define PITTFLG_TIF 0x1
35
36static void __iomem *clksrc_base;
37static void __iomem *clkevt_base;
38static unsigned long cycle_per_jiffy;
39
40static inline void pit_timer_enable(void)
41{
42 __raw_writel(PITTCTRL_TEN | PITTCTRL_TIE, clkevt_base + PITTCTRL);
43}
44
45static inline void pit_timer_disable(void)
46{
47 __raw_writel(0, clkevt_base + PITTCTRL);
48}
49
50static inline void pit_irq_acknowledge(void)
51{
52 __raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG);
53}
54
55static unsigned int pit_read_sched_clock(void)
56{
57 return __raw_readl(clksrc_base + PITCVAL);
58}
59
60static int __init pit_clocksource_init(unsigned long rate)
61{
62 /* set the max load value and start the clock source counter */
63 __raw_writel(0, clksrc_base + PITTCTRL);
64 __raw_writel(~0UL, clksrc_base + PITLDVAL);
65 __raw_writel(PITTCTRL_TEN, clksrc_base + PITTCTRL);
66
67 setup_sched_clock(pit_read_sched_clock, 32, rate);
68 return clocksource_mmio_init(clksrc_base + PITCVAL, "vf-pit", rate,
69 300, 32, clocksource_mmio_readl_down);
70}
71
72static int pit_set_next_event(unsigned long delta,
73 struct clock_event_device *unused)
74{
75 /*
76 * set a new value to PITLDVAL register will not restart the timer,
77 * to abort the current cycle and start a timer period with the new
78 * value, the timer must be disabled and enabled again.
79 * and the PITLAVAL should be set to delta minus one according to pit
80 * hardware requirement.
81 */
82 pit_timer_disable();
83 __raw_writel(delta - 1, clkevt_base + PITLDVAL);
84 pit_timer_enable();
85
86 return 0;
87}
88
89static void pit_set_mode(enum clock_event_mode mode,
90 struct clock_event_device *evt)
91{
92 switch (mode) {
93 case CLOCK_EVT_MODE_PERIODIC:
94 pit_set_next_event(cycle_per_jiffy, evt);
95 break;
96 default:
97 break;
98 }
99}
100
101static irqreturn_t pit_timer_interrupt(int irq, void *dev_id)
102{
103 struct clock_event_device *evt = dev_id;
104
105 pit_irq_acknowledge();
106
107 /*
108 * pit hardware doesn't support oneshot, it will generate an interrupt
109 * and reload the counter value from PITLDVAL when PITCVAL reach zero,
110 * and start the counter again. So software need to disable the timer
111 * to stop the counter loop in ONESHOT mode.
112 */
113 if (likely(evt->mode == CLOCK_EVT_MODE_ONESHOT))
114 pit_timer_disable();
115
116 evt->event_handler(evt);
117
118 return IRQ_HANDLED;
119}
120
121static struct clock_event_device clockevent_pit = {
122 .name = "VF pit timer",
123 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
124 .set_mode = pit_set_mode,
125 .set_next_event = pit_set_next_event,
126 .rating = 300,
127};
128
129static struct irqaction pit_timer_irq = {
130 .name = "VF pit timer",
131 .flags = IRQF_TIMER | IRQF_IRQPOLL,
132 .handler = pit_timer_interrupt,
133 .dev_id = &clockevent_pit,
134};
135
136static int __init pit_clockevent_init(unsigned long rate, int irq)
137{
138 __raw_writel(0, clkevt_base + PITTCTRL);
139 __raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG);
140
141 BUG_ON(setup_irq(irq, &pit_timer_irq));
142
143 clockevent_pit.cpumask = cpumask_of(0);
144 clockevent_pit.irq = irq;
145 /*
146 * The value for the LDVAL register trigger is calculated as:
147 * LDVAL trigger = (period / clock period) - 1
148 * The pit is a 32-bit down count timer, when the conter value
149 * reaches 0, it will generate an interrupt, thus the minimal
150 * LDVAL trigger value is 1. And then the min_delta is
151 * minimal LDVAL trigger value + 1, and the max_delta is full 32-bit.
152 */
153 clockevents_config_and_register(&clockevent_pit, rate, 2, 0xffffffff);
154
155 return 0;
156}
157
158static void __init pit_timer_init(struct device_node *np)
159{
160 struct clk *pit_clk;
161 void __iomem *timer_base;
162 unsigned long clk_rate;
163 int irq;
164
165 timer_base = of_iomap(np, 0);
166 BUG_ON(!timer_base);
167
168 /*
169 * PIT0 and PIT1 can be chained to build a 64-bit timer,
170 * so choose PIT2 as clocksource, PIT3 as clockevent device,
171 * and leave PIT0 and PIT1 unused for anyone else who needs them.
172 */
173 clksrc_base = timer_base + PITn_OFFSET(2);
174 clkevt_base = timer_base + PITn_OFFSET(3);
175
176 irq = irq_of_parse_and_map(np, 0);
177 BUG_ON(irq <= 0);
178
179 pit_clk = of_clk_get(np, 0);
180 BUG_ON(IS_ERR(pit_clk));
181
182 BUG_ON(clk_prepare_enable(pit_clk));
183
184 clk_rate = clk_get_rate(pit_clk);
185 cycle_per_jiffy = clk_rate / (HZ);
186
187 /* enable the pit module */
188 __raw_writel(~PITMCR_MDIS, timer_base + PITMCR);
189
190 BUG_ON(pit_clocksource_init(clk_rate));
191
192 pit_clockevent_init(clk_rate, irq);
193}
194CLOCKSOURCE_OF_DECLARE(vf610, "fsl,vf610-pit", pit_timer_init);
diff --git a/drivers/clocksource/zevio-timer.c b/drivers/clocksource/zevio-timer.c
new file mode 100644
index 000000000000..ca81809d159d
--- /dev/null
+++ b/drivers/clocksource/zevio-timer.c
@@ -0,0 +1,215 @@
1/*
2 * linux/drivers/clocksource/zevio-timer.c
3 *
4 * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2, as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#include <linux/io.h>
13#include <linux/irq.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/of_irq.h>
17#include <linux/clk.h>
18#include <linux/clockchips.h>
19#include <linux/cpumask.h>
20#include <linux/interrupt.h>
21#include <linux/slab.h>
22
23#define IO_CURRENT_VAL 0x00
24#define IO_DIVIDER 0x04
25#define IO_CONTROL 0x08
26
27#define IO_TIMER1 0x00
28#define IO_TIMER2 0x0C
29
30#define IO_MATCH_BEGIN 0x18
31#define IO_MATCH(x) (IO_MATCH_BEGIN + ((x) << 2))
32
33#define IO_INTR_STS 0x00
34#define IO_INTR_ACK 0x00
35#define IO_INTR_MSK 0x04
36
37#define CNTL_STOP_TIMER (1 << 4)
38#define CNTL_RUN_TIMER (0 << 4)
39
40#define CNTL_INC (1 << 3)
41#define CNTL_DEC (0 << 3)
42
43#define CNTL_TOZERO 0
44#define CNTL_MATCH(x) ((x) + 1)
45#define CNTL_FOREVER 7
46
47/* There are 6 match registers but we only use one. */
48#define TIMER_MATCH 0
49
50#define TIMER_INTR_MSK (1 << (TIMER_MATCH))
51#define TIMER_INTR_ALL 0x3F
52
53struct zevio_timer {
54 void __iomem *base;
55 void __iomem *timer1, *timer2;
56 void __iomem *interrupt_regs;
57
58 struct clk *clk;
59 struct clock_event_device clkevt;
60 struct irqaction clkevt_irq;
61
62 char clocksource_name[64];
63 char clockevent_name[64];
64};
65
66static int zevio_timer_set_event(unsigned long delta,
67 struct clock_event_device *dev)
68{
69 struct zevio_timer *timer = container_of(dev, struct zevio_timer,
70 clkevt);
71
72 writel(delta, timer->timer1 + IO_CURRENT_VAL);
73 writel(CNTL_RUN_TIMER | CNTL_DEC | CNTL_MATCH(TIMER_MATCH),
74 timer->timer1 + IO_CONTROL);
75
76 return 0;
77}
78
79static void zevio_timer_set_mode(enum clock_event_mode mode,
80 struct clock_event_device *dev)
81{
82 struct zevio_timer *timer = container_of(dev, struct zevio_timer,
83 clkevt);
84
85 switch (mode) {
86 case CLOCK_EVT_MODE_RESUME:
87 case CLOCK_EVT_MODE_ONESHOT:
88 /* Enable timer interrupts */
89 writel(TIMER_INTR_MSK, timer->interrupt_regs + IO_INTR_MSK);
90 writel(TIMER_INTR_ALL, timer->interrupt_regs + IO_INTR_ACK);
91 break;
92 case CLOCK_EVT_MODE_SHUTDOWN:
93 case CLOCK_EVT_MODE_UNUSED:
94 /* Disable timer interrupts */
95 writel(0, timer->interrupt_regs + IO_INTR_MSK);
96 writel(TIMER_INTR_ALL, timer->interrupt_regs + IO_INTR_ACK);
97 /* Stop timer */
98 writel(CNTL_STOP_TIMER, timer->timer1 + IO_CONTROL);
99 break;
100 case CLOCK_EVT_MODE_PERIODIC:
101 default:
102 /* Unsupported */
103 break;
104 }
105}
106
107static irqreturn_t zevio_timer_interrupt(int irq, void *dev_id)
108{
109 struct zevio_timer *timer = dev_id;
110 u32 intr;
111
112 intr = readl(timer->interrupt_regs + IO_INTR_ACK);
113 if (!(intr & TIMER_INTR_MSK))
114 return IRQ_NONE;
115
116 writel(TIMER_INTR_MSK, timer->interrupt_regs + IO_INTR_ACK);
117 writel(CNTL_STOP_TIMER, timer->timer1 + IO_CONTROL);
118
119 if (timer->clkevt.event_handler)
120 timer->clkevt.event_handler(&timer->clkevt);
121
122 return IRQ_HANDLED;
123}
124
125static int __init zevio_timer_add(struct device_node *node)
126{
127 struct zevio_timer *timer;
128 struct resource res;
129 int irqnr, ret;
130
131 timer = kzalloc(sizeof(*timer), GFP_KERNEL);
132 if (!timer)
133 return -ENOMEM;
134
135 timer->base = of_iomap(node, 0);
136 if (!timer->base) {
137 ret = -EINVAL;
138 goto error_free;
139 }
140 timer->timer1 = timer->base + IO_TIMER1;
141 timer->timer2 = timer->base + IO_TIMER2;
142
143 timer->clk = of_clk_get(node, 0);
144 if (IS_ERR(timer->clk)) {
145 ret = PTR_ERR(timer->clk);
146 pr_err("Timer clock not found! (error %d)\n", ret);
147 goto error_unmap;
148 }
149
150 timer->interrupt_regs = of_iomap(node, 1);
151 irqnr = irq_of_parse_and_map(node, 0);
152
153 of_address_to_resource(node, 0, &res);
154 scnprintf(timer->clocksource_name, sizeof(timer->clocksource_name),
155 "%llx.%s_clocksource",
156 (unsigned long long)res.start, node->name);
157
158 scnprintf(timer->clockevent_name, sizeof(timer->clockevent_name),
159 "%llx.%s_clockevent",
160 (unsigned long long)res.start, node->name);
161
162 if (timer->interrupt_regs && irqnr) {
163 timer->clkevt.name = timer->clockevent_name;
164 timer->clkevt.set_next_event = zevio_timer_set_event;
165 timer->clkevt.set_mode = zevio_timer_set_mode;
166 timer->clkevt.rating = 200;
167 timer->clkevt.cpumask = cpu_all_mask;
168 timer->clkevt.features = CLOCK_EVT_FEAT_ONESHOT;
169 timer->clkevt.irq = irqnr;
170
171 writel(CNTL_STOP_TIMER, timer->timer1 + IO_CONTROL);
172 writel(0, timer->timer1 + IO_DIVIDER);
173
174 /* Start with timer interrupts disabled */
175 writel(0, timer->interrupt_regs + IO_INTR_MSK);
176 writel(TIMER_INTR_ALL, timer->interrupt_regs + IO_INTR_ACK);
177
178 /* Interrupt to occur when timer value matches 0 */
179 writel(0, timer->base + IO_MATCH(TIMER_MATCH));
180
181 timer->clkevt_irq.name = timer->clockevent_name;
182 timer->clkevt_irq.handler = zevio_timer_interrupt;
183 timer->clkevt_irq.dev_id = timer;
184 timer->clkevt_irq.flags = IRQF_TIMER | IRQF_IRQPOLL;
185
186 setup_irq(irqnr, &timer->clkevt_irq);
187
188 clockevents_config_and_register(&timer->clkevt,
189 clk_get_rate(timer->clk), 0x0001, 0xffff);
190 pr_info("Added %s as clockevent\n", timer->clockevent_name);
191 }
192
193 writel(CNTL_STOP_TIMER, timer->timer2 + IO_CONTROL);
194 writel(0, timer->timer2 + IO_CURRENT_VAL);
195 writel(0, timer->timer2 + IO_DIVIDER);
196 writel(CNTL_RUN_TIMER | CNTL_FOREVER | CNTL_INC,
197 timer->timer2 + IO_CONTROL);
198
199 clocksource_mmio_init(timer->timer2 + IO_CURRENT_VAL,
200 timer->clocksource_name,
201 clk_get_rate(timer->clk),
202 200, 16,
203 clocksource_mmio_readw_up);
204
205 pr_info("Added %s as clocksource\n", timer->clocksource_name);
206
207 return 0;
208error_unmap:
209 iounmap(timer->base);
210error_free:
211 kfree(timer);
212 return ret;
213}
214
215CLOCKSOURCE_OF_DECLARE(zevio_timer, "lsi,zevio-timer", zevio_timer_add);