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authorEzequiel Garcia <ezequiel.garcia@free-electrons.com>2014-02-19 15:05:25 -0500
committerDaniel Lezcano <daniel.lezcano@linaro.org>2014-03-11 18:05:02 -0400
commit0a54a069585bb875d37494c434f36a19bcc05df9 (patch)
tree7e1a5d74490aac2b4e6b0254bbcb261dac06237d /drivers/clocksource/time-orion.c
parente099d01eb221f4a1e713a7663ca143c05303947f (diff)
clocksource: orion: Use atomic access for shared registers
Replace the driver-specific thread-safe shared register API by the recently introduced atomic_io_clear_set(). Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Willy Tarreau <w@1wt.eu> Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Diffstat (limited to 'drivers/clocksource/time-orion.c')
-rw-r--r--drivers/clocksource/time-orion.c28
1 files changed, 10 insertions, 18 deletions
diff --git a/drivers/clocksource/time-orion.c b/drivers/clocksource/time-orion.c
index 20066222f3f2..0b3ce0399c51 100644
--- a/drivers/clocksource/time-orion.c
+++ b/drivers/clocksource/time-orion.c
@@ -35,20 +35,6 @@
35#define ORION_ONESHOT_MAX 0xfffffffe 35#define ORION_ONESHOT_MAX 0xfffffffe
36 36
37static void __iomem *timer_base; 37static void __iomem *timer_base;
38static DEFINE_SPINLOCK(timer_ctrl_lock);
39
40/*
41 * Thread-safe access to TIMER_CTRL register
42 * (shared with watchdog timer)
43 */
44void orion_timer_ctrl_clrset(u32 clr, u32 set)
45{
46 spin_lock(&timer_ctrl_lock);
47 writel((readl(timer_base + TIMER_CTRL) & ~clr) | set,
48 timer_base + TIMER_CTRL);
49 spin_unlock(&timer_ctrl_lock);
50}
51EXPORT_SYMBOL(orion_timer_ctrl_clrset);
52 38
53/* 39/*
54 * Free-running clocksource handling. 40 * Free-running clocksource handling.
@@ -68,7 +54,8 @@ static int orion_clkevt_next_event(unsigned long delta,
68{ 54{
69 /* setup and enable one-shot timer */ 55 /* setup and enable one-shot timer */
70 writel(delta, timer_base + TIMER1_VAL); 56 writel(delta, timer_base + TIMER1_VAL);
71 orion_timer_ctrl_clrset(TIMER1_RELOAD_EN, TIMER1_EN); 57 atomic_io_modify(timer_base + TIMER_CTRL,
58 TIMER1_RELOAD_EN | TIMER1_EN, TIMER1_EN);
72 59
73 return 0; 60 return 0;
74} 61}
@@ -80,10 +67,13 @@ static void orion_clkevt_mode(enum clock_event_mode mode,
80 /* setup and enable periodic timer at 1/HZ intervals */ 67 /* setup and enable periodic timer at 1/HZ intervals */
81 writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD); 68 writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD);
82 writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL); 69 writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL);
83 orion_timer_ctrl_clrset(0, TIMER1_RELOAD_EN | TIMER1_EN); 70 atomic_io_modify(timer_base + TIMER_CTRL,
71 TIMER1_RELOAD_EN | TIMER1_EN,
72 TIMER1_RELOAD_EN | TIMER1_EN);
84 } else { 73 } else {
85 /* disable timer */ 74 /* disable timer */
86 orion_timer_ctrl_clrset(TIMER1_RELOAD_EN | TIMER1_EN, 0); 75 atomic_io_modify(timer_base + TIMER_CTRL,
76 TIMER1_RELOAD_EN | TIMER1_EN, 0);
87 } 77 }
88} 78}
89 79
@@ -131,7 +121,9 @@ static void __init orion_timer_init(struct device_node *np)
131 /* setup timer0 as free-running clocksource */ 121 /* setup timer0 as free-running clocksource */
132 writel(~0, timer_base + TIMER0_VAL); 122 writel(~0, timer_base + TIMER0_VAL);
133 writel(~0, timer_base + TIMER0_RELOAD); 123 writel(~0, timer_base + TIMER0_RELOAD);
134 orion_timer_ctrl_clrset(0, TIMER0_RELOAD_EN | TIMER0_EN); 124 atomic_io_modify(timer_base + TIMER_CTRL,
125 TIMER0_RELOAD_EN | TIMER0_EN,
126 TIMER0_RELOAD_EN | TIMER0_EN);
135 clocksource_mmio_init(timer_base + TIMER0_VAL, "orion_clocksource", 127 clocksource_mmio_init(timer_base + TIMER0_VAL, "orion_clocksource",
136 clk_get_rate(clk), 300, 32, 128 clk_get_rate(clk), 300, 32,
137 clocksource_mmio_readl_down); 129 clocksource_mmio_readl_down);