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authorRob Herring <rob.herring@calxeda.com>2013-02-07 12:36:23 -0500
committerRob Herring <rob.herring@calxeda.com>2013-03-11 09:42:07 -0400
commit1d16cfb3aeba71bc6ecf2d19ccbabed0426e5c22 (patch)
treece8b8642fe5b0ab49213c64dc600e107104a532d /drivers/clocksource/tegra20_timer.c
parenteffbfdd7baf7babc73154b87a5ff940969cf6559 (diff)
clocksource: tegra20: use the device_node pointer passed to init
We've already matched the node, so use the node pointer passed in. The rtc init was intermingled with the timer init, so split this out to a separate init function. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: John Stultz <johnstul@us.ibm.com> Cc: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'drivers/clocksource/tegra20_timer.c')
-rw-r--r--drivers/clocksource/tegra20_timer.c67
1 files changed, 26 insertions, 41 deletions
diff --git a/drivers/clocksource/tegra20_timer.c b/drivers/clocksource/tegra20_timer.c
index b3396ab15f63..15cc723f699f 100644
--- a/drivers/clocksource/tegra20_timer.c
+++ b/drivers/clocksource/tegra20_timer.c
@@ -154,28 +154,12 @@ static struct irqaction tegra_timer_irq = {
154 .dev_id = &tegra_clockevent, 154 .dev_id = &tegra_clockevent,
155}; 155};
156 156
157static const struct of_device_id timer_match[] __initconst = {
158 { .compatible = "nvidia,tegra20-timer" },
159 {}
160};
161
162static const struct of_device_id rtc_match[] __initconst = {
163 { .compatible = "nvidia,tegra20-rtc" },
164 {}
165};
166
167static void __init tegra20_init_timer(struct device_node *np) 157static void __init tegra20_init_timer(struct device_node *np)
168{ 158{
169 struct clk *clk; 159 struct clk *clk;
170 unsigned long rate; 160 unsigned long rate;
171 int ret; 161 int ret;
172 162
173 np = of_find_matching_node(NULL, timer_match);
174 if (!np) {
175 pr_err("Failed to find timer DT node\n");
176 BUG();
177 }
178
179 timer_reg_base = of_iomap(np, 0); 163 timer_reg_base = of_iomap(np, 0);
180 if (!timer_reg_base) { 164 if (!timer_reg_base) {
181 pr_err("Can't map timer registers\n"); 165 pr_err("Can't map timer registers\n");
@@ -199,30 +183,6 @@ static void __init tegra20_init_timer(struct device_node *np)
199 183
200 of_node_put(np); 184 of_node_put(np);
201 185
202 np = of_find_matching_node(NULL, rtc_match);
203 if (!np) {
204 pr_err("Failed to find RTC DT node\n");
205 BUG();
206 }
207
208 rtc_base = of_iomap(np, 0);
209 if (!rtc_base) {
210 pr_err("Can't map RTC registers");
211 BUG();
212 }
213
214 /*
215 * rtc registers are used by read_persistent_clock, keep the rtc clock
216 * enabled
217 */
218 clk = clk_get_sys("rtc-tegra", NULL);
219 if (IS_ERR(clk))
220 pr_warn("Unable to get rtc-tegra clock\n");
221 else
222 clk_prepare_enable(clk);
223
224 of_node_put(np);
225
226 switch (rate) { 186 switch (rate) {
227 case 12000000: 187 case 12000000:
228 timer_writel(0x000b, TIMERUS_USEC_CFG); 188 timer_writel(0x000b, TIMERUS_USEC_CFG);
@@ -261,9 +221,34 @@ static void __init tegra20_init_timer(struct device_node *np)
261#ifdef CONFIG_HAVE_ARM_TWD 221#ifdef CONFIG_HAVE_ARM_TWD
262 twd_local_timer_of_register(); 222 twd_local_timer_of_register();
263#endif 223#endif
224}
225CLOCKSOURCE_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer);
226
227static void __init tegra20_init_rtc(struct device_node *np)
228{
229 struct clk *clk;
230
231 rtc_base = of_iomap(np, 0);
232 if (!rtc_base) {
233 pr_err("Can't map RTC registers");
234 BUG();
235 }
236
237 /*
238 * rtc registers are used by read_persistent_clock, keep the rtc clock
239 * enabled
240 */
241 clk = clk_get_sys("rtc-tegra", NULL);
242 if (IS_ERR(clk))
243 pr_warn("Unable to get rtc-tegra clock\n");
244 else
245 clk_prepare_enable(clk);
246
247 of_node_put(np);
248
264 register_persistent_clock(NULL, tegra_read_persistent_clock); 249 register_persistent_clock(NULL, tegra_read_persistent_clock);
265} 250}
266CLOCKSOURCE_OF_DECLARE(tegra20, "nvidia,tegra20-timer", tegra20_init_timer); 251CLOCKSOURCE_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);
267 252
268#ifdef CONFIG_PM 253#ifdef CONFIG_PM
269static u32 usec_config; 254static u32 usec_config;