diff options
author | Magnus Damm <damm@igel.co.jp> | 2009-04-29 10:50:37 -0400 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2009-04-29 23:57:30 -0400 |
commit | 3014f47460ecfb13d4169daae51f26a20bacfa17 (patch) | |
tree | 3c5c77d96a03f4c64437a984fa07ba857280f554 /drivers/clocksource/sh_cmt.c | |
parent | e6be3a25861429166f945499c7ee616875bc3db9 (diff) |
clocksource: sh_cmt 16-bit fixes
This patch contains various fixes for 16-bit cmt hardware.
With this applied periodic clockevents work fine on sh7203.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'drivers/clocksource/sh_cmt.c')
-rw-r--r-- | drivers/clocksource/sh_cmt.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c index bf3e4c11fd37..4ff1508e5ab7 100644 --- a/drivers/clocksource/sh_cmt.c +++ b/drivers/clocksource/sh_cmt.c | |||
@@ -158,16 +158,18 @@ static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate) | |||
158 | pr_err("sh_cmt: cannot enable clock \"%s\"\n", cfg->clk); | 158 | pr_err("sh_cmt: cannot enable clock \"%s\"\n", cfg->clk); |
159 | return ret; | 159 | return ret; |
160 | } | 160 | } |
161 | *rate = clk_get_rate(p->clk) / 8; | ||
162 | 161 | ||
163 | /* make sure channel is disabled */ | 162 | /* make sure channel is disabled */ |
164 | sh_cmt_start_stop_ch(p, 0); | 163 | sh_cmt_start_stop_ch(p, 0); |
165 | 164 | ||
166 | /* configure channel, periodic mode and maximum timeout */ | 165 | /* configure channel, periodic mode and maximum timeout */ |
167 | if (p->width == 16) | 166 | if (p->width == 16) { |
168 | sh_cmt_write(p, CMCSR, 0); | 167 | *rate = clk_get_rate(p->clk) / 512; |
169 | else | 168 | sh_cmt_write(p, CMCSR, 0x43); |
169 | } else { | ||
170 | *rate = clk_get_rate(p->clk) / 8; | ||
170 | sh_cmt_write(p, CMCSR, 0x01a4); | 171 | sh_cmt_write(p, CMCSR, 0x01a4); |
172 | } | ||
171 | 173 | ||
172 | sh_cmt_write(p, CMCOR, 0xffffffff); | 174 | sh_cmt_write(p, CMCOR, 0xffffffff); |
173 | sh_cmt_write(p, CMCNT, 0); | 175 | sh_cmt_write(p, CMCNT, 0); |
@@ -615,7 +617,7 @@ static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev) | |||
615 | if (resource_size(res) == 6) { | 617 | if (resource_size(res) == 6) { |
616 | p->width = 16; | 618 | p->width = 16; |
617 | p->overflow_bit = 0x80; | 619 | p->overflow_bit = 0x80; |
618 | p->clear_bits = ~0xc0; | 620 | p->clear_bits = ~0x80; |
619 | } else { | 621 | } else { |
620 | p->width = 32; | 622 | p->width = 32; |
621 | p->overflow_bit = 0x8000; | 623 | p->overflow_bit = 0x8000; |