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authorIngo Molnar <mingo@elte.hu>2010-06-18 04:53:12 -0400
committerIngo Molnar <mingo@elte.hu>2010-06-18 04:53:19 -0400
commit646b1db4956ba8bf748b835b5eba211133d91c2e (patch)
tree061166d873d9da9cf83044a7593ad111787076c5 /drivers/clocksource/sh_cmt.c
parent0f2c3de2ba110626515234d5d584fb1b0c0749a2 (diff)
parent7e27d6e778cd87b6f2415515d7127eba53fe5d02 (diff)
Merge commit 'v2.6.35-rc3' into perf/core
Merge reason: Go from -rc1 base to -rc3 base, merge in fixes.
Diffstat (limited to 'drivers/clocksource/sh_cmt.c')
-rw-r--r--drivers/clocksource/sh_cmt.c22
1 files changed, 13 insertions, 9 deletions
diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c
index f6677cb19789..f3d3898898ed 100644
--- a/drivers/clocksource/sh_cmt.c
+++ b/drivers/clocksource/sh_cmt.c
@@ -412,18 +412,10 @@ static cycle_t sh_cmt_clocksource_read(struct clocksource *cs)
412static int sh_cmt_clocksource_enable(struct clocksource *cs) 412static int sh_cmt_clocksource_enable(struct clocksource *cs)
413{ 413{
414 struct sh_cmt_priv *p = cs_to_sh_cmt(cs); 414 struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
415 int ret;
416 415
417 p->total_cycles = 0; 416 p->total_cycles = 0;
418 417
419 ret = sh_cmt_start(p, FLAG_CLOCKSOURCE); 418 return sh_cmt_start(p, FLAG_CLOCKSOURCE);
420 if (ret)
421 return ret;
422
423 /* TODO: calculate good shift from rate and counter bit width */
424 cs->shift = 0;
425 cs->mult = clocksource_hz2mult(p->rate, cs->shift);
426 return 0;
427} 419}
428 420
429static void sh_cmt_clocksource_disable(struct clocksource *cs) 421static void sh_cmt_clocksource_disable(struct clocksource *cs)
@@ -450,8 +442,20 @@ static int sh_cmt_register_clocksource(struct sh_cmt_priv *p,
450 cs->resume = sh_cmt_clocksource_resume; 442 cs->resume = sh_cmt_clocksource_resume;
451 cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8); 443 cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
452 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; 444 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
445
446 /* clk_get_rate() needs an enabled clock */
447 clk_enable(p->clk);
448 p->rate = clk_get_rate(p->clk) / (p->width == 16) ? 512 : 8;
449 clk_disable(p->clk);
450
451 /* TODO: calculate good shift from rate and counter bit width */
452 cs->shift = 10;
453 cs->mult = clocksource_hz2mult(p->rate, cs->shift);
454
453 dev_info(&p->pdev->dev, "used as clock source\n"); 455 dev_info(&p->pdev->dev, "used as clock source\n");
456
454 clocksource_register(cs); 457 clocksource_register(cs);
458
455 return 0; 459 return 0;
456} 460}
457 461