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authorHeiko Stuebner <heiko@sntech.de>2014-12-18 14:06:57 -0500
committerHeiko Stuebner <heiko@sntech.de>2014-12-28 17:31:44 -0500
commit9880d4277f6aab6b21404c824f9d9c652ba518ac (patch)
tree92e89a273fa90bc42e59750673e88285e84d8d47 /drivers/clk
parent12551f0239b50c88352e3292dd7703382addbf5e (diff)
clk: rockchip: fix rk3288 cpuclk core dividers
Commit 0e5bdb3f9fa5 (clk: rockchip: switch to using the new cpuclk type for armclk) didn't take into account that the divider used on rk3288 are of the (n+1) type. The rk3066 and rk3188 socs use more complex divider types making it necessary for the list-elements to be the real register-values to write. Therefore reduce divider values in the table accordingly so that they really are the values that should be written to the registers and match the dividers actually specified for the rk3288. Reported-by: Sonny Rao <sonnyrao@chromium.org> Fixes: 0e5bdb3f9fa5 ("clk: rockchip: switch to using the new cpuclk type for armclk") Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Doug Anderson <dianders@chromium.org> Cc: stable@vger.kernel.org
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/rockchip/clk-rk3288.c28
1 files changed, 14 insertions, 14 deletions
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index ac6be7c0132d..11194b8329fe 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -145,20 +145,20 @@ struct rockchip_pll_rate_table rk3288_pll_rates[] = {
145 } 145 }
146 146
147static struct rockchip_cpuclk_rate_table rk3288_cpuclk_rates[] __initdata = { 147static struct rockchip_cpuclk_rate_table rk3288_cpuclk_rates[] __initdata = {
148 RK3288_CPUCLK_RATE(1800000000, 2, 4, 2, 4, 4), 148 RK3288_CPUCLK_RATE(1800000000, 1, 3, 1, 3, 3),
149 RK3288_CPUCLK_RATE(1704000000, 2, 4, 2, 4, 4), 149 RK3288_CPUCLK_RATE(1704000000, 1, 3, 1, 3, 3),
150 RK3288_CPUCLK_RATE(1608000000, 2, 4, 2, 4, 4), 150 RK3288_CPUCLK_RATE(1608000000, 1, 3, 1, 3, 3),
151 RK3288_CPUCLK_RATE(1512000000, 2, 4, 2, 4, 4), 151 RK3288_CPUCLK_RATE(1512000000, 1, 3, 1, 3, 3),
152 RK3288_CPUCLK_RATE(1416000000, 2, 4, 2, 4, 4), 152 RK3288_CPUCLK_RATE(1416000000, 1, 3, 1, 3, 3),
153 RK3288_CPUCLK_RATE(1200000000, 2, 4, 2, 4, 4), 153 RK3288_CPUCLK_RATE(1200000000, 1, 3, 1, 3, 3),
154 RK3288_CPUCLK_RATE(1008000000, 2, 4, 2, 4, 4), 154 RK3288_CPUCLK_RATE(1008000000, 1, 3, 1, 3, 3),
155 RK3288_CPUCLK_RATE( 816000000, 2, 4, 2, 4, 4), 155 RK3288_CPUCLK_RATE( 816000000, 1, 3, 1, 3, 3),
156 RK3288_CPUCLK_RATE( 696000000, 2, 4, 2, 4, 4), 156 RK3288_CPUCLK_RATE( 696000000, 1, 3, 1, 3, 3),
157 RK3288_CPUCLK_RATE( 600000000, 2, 4, 2, 4, 4), 157 RK3288_CPUCLK_RATE( 600000000, 1, 3, 1, 3, 3),
158 RK3288_CPUCLK_RATE( 408000000, 2, 4, 2, 4, 4), 158 RK3288_CPUCLK_RATE( 408000000, 1, 3, 1, 3, 3),
159 RK3288_CPUCLK_RATE( 312000000, 2, 4, 2, 4, 4), 159 RK3288_CPUCLK_RATE( 312000000, 1, 3, 1, 3, 3),
160 RK3288_CPUCLK_RATE( 216000000, 2, 4, 2, 4, 4), 160 RK3288_CPUCLK_RATE( 216000000, 1, 3, 1, 3, 3),
161 RK3288_CPUCLK_RATE( 126000000, 2, 4, 2, 4, 4), 161 RK3288_CPUCLK_RATE( 126000000, 1, 3, 1, 3, 3),
162}; 162};
163 163
164static const struct rockchip_cpuclk_reg_data rk3288_cpuclk_data = { 164static const struct rockchip_cpuclk_reg_data rk3288_cpuclk_data = {