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authorLee Jones <lee.jones@linaro.org>2013-09-17 05:11:53 -0400
committerLinus Walleij <linus.walleij@linaro.org>2013-09-26 05:05:26 -0400
commit82b0f4b7c576d22c764239662cedc63c21f02d8d (patch)
tree825d5eca2a7363327578f4732551498c80aada8d /drivers/clk
parent0473b177c3dd5abdb2a7b54eec1921283928a17b (diff)
clk: ux500: Copy u8500_clk_init() ready for DT enablement
Here we're using the old clock initialisation function as a template. It's necessary to remove all of the clk_register_clkdev() calls as they don't make sense when booting with Device Tree. Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/ux500/Makefile1
-rw-r--r--drivers/clk/ux500/u8500_of_clk.c381
2 files changed, 382 insertions, 0 deletions
diff --git a/drivers/clk/ux500/Makefile b/drivers/clk/ux500/Makefile
index c6a806ed0e8c..521483f0ba33 100644
--- a/drivers/clk/ux500/Makefile
+++ b/drivers/clk/ux500/Makefile
@@ -8,6 +8,7 @@ obj-y += clk-prcmu.o
8obj-y += clk-sysctrl.o 8obj-y += clk-sysctrl.o
9 9
10# Clock definitions 10# Clock definitions
11obj-y += u8500_of_clk.o
11obj-y += u8500_clk.o 12obj-y += u8500_clk.o
12obj-y += u9540_clk.o 13obj-y += u9540_clk.o
13obj-y += u8540_clk.o 14obj-y += u8540_clk.o
diff --git a/drivers/clk/ux500/u8500_of_clk.c b/drivers/clk/ux500/u8500_of_clk.c
new file mode 100644
index 000000000000..ceebce6a624f
--- /dev/null
+++ b/drivers/clk/ux500/u8500_of_clk.c
@@ -0,0 +1,381 @@
1/*
2 * Clock definitions for u8500 platform.
3 *
4 * Copyright (C) 2012 ST-Ericsson SA
5 * Author: Ulf Hansson <ulf.hansson@linaro.org>
6 *
7 * License terms: GNU General Public License (GPL) version 2
8 */
9
10#include <linux/clk.h>
11#include <linux/clkdev.h>
12#include <linux/clk-provider.h>
13#include <linux/mfd/dbx500-prcmu.h>
14#include <linux/platform_data/clk-ux500.h>
15#include "clk.h"
16
17void u8500_of_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
18 u32 clkrst5_base, u32 clkrst6_base)
19{
20 struct prcmu_fw_version *fw_version;
21 const char *sgaclk_parent = NULL;
22 struct clk *clk;
23
24 /* Clock sources */
25 clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
26 CLK_IS_ROOT|CLK_IGNORE_UNUSED);
27
28 clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
29 CLK_IS_ROOT|CLK_IGNORE_UNUSED);
30
31 clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR,
32 CLK_IS_ROOT|CLK_IGNORE_UNUSED);
33
34 /* FIXME: Add sys, ulp and int clocks here. */
35
36 clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL",
37 CLK_IS_ROOT|CLK_IGNORE_UNUSED,
38 32768);
39
40 /* PRCMU clocks */
41 fw_version = prcmu_get_fw_version();
42 if (fw_version != NULL) {
43 switch (fw_version->project) {
44 case PRCMU_FW_PROJECT_U8500_C2:
45 case PRCMU_FW_PROJECT_U8520:
46 case PRCMU_FW_PROJECT_U8420:
47 sgaclk_parent = "soc0_pll";
48 break;
49 default:
50 break;
51 }
52 }
53
54 if (sgaclk_parent)
55 clk = clk_reg_prcmu_gate("sgclk", sgaclk_parent,
56 PRCMU_SGACLK, 0);
57 else
58 clk = clk_reg_prcmu_gate("sgclk", NULL,
59 PRCMU_SGACLK, CLK_IS_ROOT);
60
61 clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, CLK_IS_ROOT);
62
63 clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, CLK_IS_ROOT);
64
65 clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, CLK_IS_ROOT);
66
67 clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, CLK_IS_ROOT);
68
69 clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, CLK_IS_ROOT);
70
71 clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, CLK_IS_ROOT);
72
73 clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, CLK_IS_ROOT);
74
75 clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, CLK_IS_ROOT);
76
77 clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, CLK_IS_ROOT);
78
79 clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, CLK_IS_ROOT);
80
81 clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, CLK_IS_ROOT);
82
83 clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0,
84 CLK_IS_ROOT|CLK_SET_RATE_GATE);
85
86 clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, CLK_IS_ROOT);
87
88 clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0,
89 CLK_IS_ROOT|CLK_SET_RATE_GATE);
90
91 clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0,
92 CLK_IS_ROOT|CLK_SET_RATE_GATE);
93
94 clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0,
95 CLK_IS_ROOT|CLK_SET_RATE_GATE);
96
97 clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, CLK_IS_ROOT);
98
99 clk = clk_reg_prcmu_gate("apetraceclk", NULL, PRCMU_APETRACECLK,
100 CLK_IS_ROOT);
101
102 clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, CLK_IS_ROOT);
103
104 clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK,
105 CLK_IS_ROOT);
106
107 clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK,
108 CLK_IS_ROOT);
109
110 clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, CLK_IS_ROOT);
111
112 clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, CLK_IS_ROOT);
113
114 clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0,
115 CLK_IS_ROOT|CLK_SET_RATE_GATE);
116
117 clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, CLK_IS_ROOT);
118
119 clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, CLK_IS_ROOT);
120
121 clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT);
122
123 clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT);
124
125 clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK,
126 100000000,
127 CLK_IS_ROOT|CLK_SET_RATE_GATE);
128
129 clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",
130 PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);
131
132
133 clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll",
134 PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE);
135
136 clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll",
137 PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE);
138
139 clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk",
140 PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE);
141
142 clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk",
143 PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE);
144
145 clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk",
146 PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE);
147
148 clk = clk_reg_prcmu_scalable_rate("armss", NULL,
149 PRCMU_ARMSS, 0, CLK_IS_ROOT|CLK_IGNORE_UNUSED);
150
151 clk = clk_register_fixed_factor(NULL, "smp_twd", "armss",
152 CLK_IGNORE_UNUSED, 1, 2);
153
154 /*
155 * FIXME: Add special handled PRCMU clocks here:
156 * 1. clkout0yuv, use PRCMU as parent + need regulator + pinctrl.
157 * 2. ab9540_clkout1yuv, see clkout0yuv
158 */
159
160 /* PRCC P-clocks */
161 clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", clkrst1_base,
162 BIT(0), 0);
163
164 clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", clkrst1_base,
165 BIT(1), 0);
166
167 clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", clkrst1_base,
168 BIT(2), 0);
169
170 clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", clkrst1_base,
171 BIT(3), 0);
172
173 clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", clkrst1_base,
174 BIT(4), 0);
175
176 clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", clkrst1_base,
177 BIT(5), 0);
178
179 clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", clkrst1_base,
180 BIT(6), 0);
181
182 clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", clkrst1_base,
183 BIT(7), 0);
184
185 clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", clkrst1_base,
186 BIT(8), 0);
187
188 clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", clkrst1_base,
189 BIT(9), 0);
190
191 clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", clkrst1_base,
192 BIT(10), 0);
193
194 clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", clkrst1_base,
195 BIT(11), 0);
196
197 clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", clkrst2_base,
198 BIT(0), 0);
199
200 clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", clkrst2_base,
201 BIT(1), 0);
202
203 clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", clkrst2_base,
204 BIT(2), 0);
205
206 clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", clkrst2_base,
207 BIT(3), 0);
208
209 clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", clkrst2_base,
210 BIT(4), 0);
211
212 clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", clkrst2_base,
213 BIT(5), 0);
214
215 clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", clkrst2_base,
216 BIT(6), 0);
217
218 clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", clkrst2_base,
219 BIT(7), 0);
220
221 clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", clkrst2_base,
222 BIT(8), 0);
223
224 clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", clkrst2_base,
225 BIT(9), 0);
226
227 clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", clkrst2_base,
228 BIT(10), 0);
229
230 clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", clkrst2_base,
231 BIT(11), 0);
232
233 clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", clkrst2_base,
234 BIT(12), 0);
235
236 clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", clkrst3_base,
237 BIT(0), 0);
238
239 clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base,
240 BIT(1), 0);
241
242 clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", clkrst3_base,
243 BIT(2), 0);
244
245 clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", clkrst3_base,
246 BIT(3), 0);
247
248 clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", clkrst3_base,
249 BIT(4), 0);
250
251 clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", clkrst3_base,
252 BIT(5), 0);
253
254 clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", clkrst3_base,
255 BIT(6), 0);
256
257 clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", clkrst3_base,
258 BIT(7), 0);
259
260 clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", clkrst3_base,
261 BIT(8), 0);
262
263 clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", clkrst5_base,
264 BIT(0), 0);
265
266 clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", clkrst5_base,
267 BIT(1), 0);
268
269 clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", clkrst6_base,
270 BIT(0), 0);
271
272 clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", clkrst6_base,
273 BIT(1), 0);
274
275 clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", clkrst6_base,
276 BIT(2), 0);
277
278 clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", clkrst6_base,
279 BIT(3), 0);
280
281 clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", clkrst6_base,
282 BIT(4), 0);
283
284 clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", clkrst6_base,
285 BIT(5), 0);
286
287 clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", clkrst6_base,
288 BIT(6), 0);
289
290 clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", clkrst6_base,
291 BIT(7), 0);
292
293 /* PRCC K-clocks
294 *
295 * FIXME: Some drivers requires PERPIH[n| to be automatically enabled
296 * by enabling just the K-clock, even if it is not a valid parent to
297 * the K-clock. Until drivers get fixed we might need some kind of
298 * "parent muxed join".
299 */
300
301 /* Periph1 */
302 clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk",
303 clkrst1_base, BIT(0), CLK_SET_RATE_GATE);
304
305 clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk",
306 clkrst1_base, BIT(1), CLK_SET_RATE_GATE);
307
308 clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk",
309 clkrst1_base, BIT(2), CLK_SET_RATE_GATE);
310
311 clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",
312 clkrst1_base, BIT(3), CLK_SET_RATE_GATE);
313
314 clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",
315 clkrst1_base, BIT(4), CLK_SET_RATE_GATE);
316
317 clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk",
318 clkrst1_base, BIT(5), CLK_SET_RATE_GATE);
319
320 clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk",
321 clkrst1_base, BIT(6), CLK_SET_RATE_GATE);
322
323 clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
324 clkrst1_base, BIT(8), CLK_SET_RATE_GATE);
325
326 clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
327 clkrst1_base, BIT(9), CLK_SET_RATE_GATE);
328
329 clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",
330 clkrst1_base, BIT(10), CLK_SET_RATE_GATE);
331
332 /* Periph2 */
333 clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",
334 clkrst2_base, BIT(0), CLK_SET_RATE_GATE);
335
336 clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk",
337 clkrst2_base, BIT(2), CLK_SET_RATE_GATE);
338
339 clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk",
340 clkrst2_base, BIT(3), CLK_SET_RATE_GATE);
341
342 clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk",
343 clkrst2_base, BIT(4), CLK_SET_RATE_GATE);
344
345 clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk",
346 clkrst2_base, BIT(5), CLK_SET_RATE_GATE);
347
348 /* Note that rate is received from parent. */
349 clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk",
350 clkrst2_base, BIT(6),
351 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
352 clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk",
353 clkrst2_base, BIT(7),
354 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
355
356 /* Periph3 */
357 clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",
358 clkrst3_base, BIT(1), CLK_SET_RATE_GATE);
359
360 clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",
361 clkrst3_base, BIT(2), CLK_SET_RATE_GATE);
362
363 clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",
364 clkrst3_base, BIT(3), CLK_SET_RATE_GATE);
365
366 clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk",
367 clkrst3_base, BIT(4), CLK_SET_RATE_GATE);
368
369 clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k",
370 clkrst3_base, BIT(5), CLK_SET_RATE_GATE);
371
372 clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk",
373 clkrst3_base, BIT(6), CLK_SET_RATE_GATE);
374
375 clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk",
376 clkrst3_base, BIT(7), CLK_SET_RATE_GATE);
377
378 /* Periph6 */
379 clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk",
380 clkrst6_base, BIT(0), CLK_SET_RATE_GATE);
381}
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