clk/exynos5250: add mout_hdmi mux clock for hdmi

hdmi driver needs to change the parent of hdmi clock
frequently between pixel clock and hdmiphy clock. hdmiphy is
not stable after power on and for a short interval while changing
the phy configuration. For this duration pixel clock is used to
clock hdmi.

This patch is exposing the mux for changing parent.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

1 files changed, 4 insertions, 1 deletions

diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index e6a4be16272a..397f1ca41b97 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -102,6 +102,9 @@ enum exynos5250_clks {
         tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
         wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d,
 
+        /* mux clocks */
+        mout_hdmi = 1024,
+
         nr_clks,
 };
 
@@ -234,7 +237,7 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
         MUX(none, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4),
         MUX(none, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4),
         MUX(none, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4),
-        MUX(none, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1),
+        MUX(mout_hdmi, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1),
         MUX(none, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4),
         MUX(none, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4),
         MUX(none, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4),