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authorMike Turquette <mturquette@linaro.org>2014-01-16 16:13:46 -0500
committerMike Turquette <mturquette@linaro.org>2014-01-16 16:13:46 -0500
commit0099d8851681a550065e36fe89719616ab5f63d4 (patch)
tree8881a7064ff68cc97c71abd4b5bd1a67de314871 /drivers/clk
parentd6e0a2dd12f4067a5bcefb8bbd8ddbeff800afbc (diff)
parent2e84d75116c17c2034e917b411250d2d11755435 (diff)
Merge remote-tracking branch 'linaro/clk-next' into clk-next
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/Kconfig22
-rw-r--r--drivers/clk/Makefile6
-rw-r--r--drivers/clk/clk-composite.c28
-rw-r--r--drivers/clk/clk-fixed-rate.c43
-rw-r--r--drivers/clk/clk-max77686.c97
-rw-r--r--drivers/clk/clk-si570.c531
-rw-r--r--drivers/clk/clk-vt8500.c2
-rw-r--r--drivers/clk/clk.c371
-rw-r--r--drivers/clk/clk.h16
-rw-r--r--drivers/clk/clkdev.c12
-rw-r--r--drivers/clk/hisilicon/Makefile5
-rw-r--r--drivers/clk/hisilicon/clk-hi3620.c242
-rw-r--r--drivers/clk/hisilicon/clk.c171
-rw-r--r--drivers/clk/hisilicon/clk.h103
-rw-r--r--drivers/clk/hisilicon/clkgate-separated.c130
-rw-r--r--drivers/clk/keystone/gate.c12
-rw-r--r--drivers/clk/keystone/pll.c24
-rw-r--r--drivers/clk/mvebu/Kconfig5
-rw-r--r--drivers/clk/mvebu/Makefile1
-rw-r--r--drivers/clk/mvebu/clk-corediv.c223
-rw-r--r--drivers/clk/mvebu/clk-cpu.c2
-rw-r--r--drivers/clk/qcom/Kconfig47
-rw-r--r--drivers/clk/qcom/Makefile14
-rw-r--r--drivers/clk/qcom/clk-branch.c159
-rw-r--r--drivers/clk/qcom/clk-branch.h56
-rw-r--r--drivers/clk/qcom/clk-pll.c222
-rw-r--r--drivers/clk/qcom/clk-pll.h66
-rw-r--r--drivers/clk/qcom/clk-rcg.c517
-rw-r--r--drivers/clk/qcom/clk-rcg.h159
-rw-r--r--drivers/clk/qcom/clk-rcg2.c291
-rw-r--r--drivers/clk/qcom/clk-regmap.c114
-rw-r--r--drivers/clk/qcom/clk-regmap.h45
-rw-r--r--drivers/clk/qcom/gcc-msm8660.c2819
-rw-r--r--drivers/clk/qcom/gcc-msm8960.c2993
-rw-r--r--drivers/clk/qcom/gcc-msm8974.c2694
-rw-r--r--drivers/clk/qcom/mmcc-msm8960.c2321
-rw-r--r--drivers/clk/qcom/mmcc-msm8974.c2625
-rw-r--r--drivers/clk/qcom/reset.c63
-rw-r--r--drivers/clk/qcom/reset.h37
-rw-r--r--drivers/clk/samsung/clk-exynos-audss.c161
-rw-r--r--drivers/clk/samsung/clk-exynos4.c859
-rw-r--r--drivers/clk/samsung/clk-exynos5250.c697
-rw-r--r--drivers/clk/samsung/clk-exynos5420.c650
-rw-r--r--drivers/clk/samsung/clk-exynos5440.c81
-rw-r--r--drivers/clk/shmobile/Makefile7
-rw-r--r--drivers/clk/shmobile/clk-div6.c185
-rw-r--r--drivers/clk/shmobile/clk-emev2.c104
-rw-r--r--drivers/clk/shmobile/clk-mstp.c233
-rw-r--r--drivers/clk/shmobile/clk-rcar-gen2.c298
-rw-r--r--drivers/clk/sirf/Makefile5
-rw-r--r--drivers/clk/sirf/atlas6.h31
-rw-r--r--drivers/clk/sirf/clk-atlas6.c152
-rw-r--r--drivers/clk/sirf/clk-common.c (renamed from drivers/clk/clk-prima2.c)264
-rw-r--r--drivers/clk/sirf/clk-prima2.c151
-rw-r--r--drivers/clk/sirf/prima2.h25
-rw-r--r--drivers/clk/socfpga/clk.c6
-rw-r--r--drivers/clk/spear/clk-frac-synth.c2
-rw-r--r--drivers/clk/sunxi/clk-factors.c67
-rw-r--r--drivers/clk/sunxi/clk-factors.h16
-rw-r--r--drivers/clk/sunxi/clk-sunxi.c493
-rw-r--r--drivers/clk/tegra/Makefile7
-rw-r--r--drivers/clk/tegra/clk-id.h235
-rw-r--r--drivers/clk/tegra/clk-periph-gate.c8
-rw-r--r--drivers/clk/tegra/clk-periph.c34
-rw-r--r--drivers/clk/tegra/clk-pll.c417
-rw-r--r--drivers/clk/tegra/clk-tegra-audio.c215
-rw-r--r--drivers/clk/tegra/clk-tegra-fixed.c111
-rw-r--r--drivers/clk/tegra/clk-tegra-periph.c674
-rw-r--r--drivers/clk/tegra/clk-tegra-pmc.c132
-rw-r--r--drivers/clk/tegra/clk-tegra-super-gen4.c149
-rw-r--r--drivers/clk/tegra/clk-tegra114.c1687
-rw-r--r--drivers/clk/tegra/clk-tegra124.c1424
-rw-r--r--drivers/clk/tegra/clk-tegra20.c818
-rw-r--r--drivers/clk/tegra/clk-tegra30.c1506
-rw-r--r--drivers/clk/tegra/clk.c166
-rw-r--r--drivers/clk/tegra/clk.h115
-rw-r--r--drivers/clk/ux500/clk-prcmu.c2
-rw-r--r--drivers/clk/versatile/clk-sp810.c2
-rw-r--r--drivers/clk/zynq/clkc.c18
79 files changed, 24939 insertions, 4556 deletions
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 5c51115081b3..7641965d208d 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -23,16 +23,6 @@ config COMMON_CLK
23menu "Common Clock Framework" 23menu "Common Clock Framework"
24 depends on COMMON_CLK 24 depends on COMMON_CLK
25 25
26config COMMON_CLK_DEBUG
27 bool "DebugFS representation of clock tree"
28 select DEBUG_FS
29 ---help---
30 Creates a directory hierarchy in debugfs for visualizing the clk
31 tree structure. Each directory contains read-only members
32 that export information specific to that clk node: clk_rate,
33 clk_flags, clk_prepare_count, clk_enable_count &
34 clk_notifier_count.
35
36config COMMON_CLK_WM831X 26config COMMON_CLK_WM831X
37 tristate "Clock driver for WM831x/2x PMICs" 27 tristate "Clock driver for WM831x/2x PMICs"
38 depends on MFD_WM831X 28 depends on MFD_WM831X
@@ -64,6 +54,16 @@ config COMMON_CLK_SI5351
64 This driver supports Silicon Labs 5351A/B/C programmable clock 54 This driver supports Silicon Labs 5351A/B/C programmable clock
65 generators. 55 generators.
66 56
57config COMMON_CLK_SI570
58 tristate "Clock driver for SiLabs 570 and compatible devices"
59 depends on I2C
60 depends on OF
61 select REGMAP_I2C
62 help
63 ---help---
64 This driver supports Silicon Labs 570/571/598/599 programmable
65 clock generators.
66
67config COMMON_CLK_S2MPS11 67config COMMON_CLK_S2MPS11
68 tristate "Clock driver for S2MPS11 MFD" 68 tristate "Clock driver for S2MPS11 MFD"
69 depends on MFD_SEC_CORE 69 depends on MFD_SEC_CORE
@@ -107,6 +107,8 @@ config COMMON_CLK_KEYSTONE
107 Supports clock drivers for Keystone based SOCs. These SOCs have local 107 Supports clock drivers for Keystone based SOCs. These SOCs have local
108 a power sleep control module that gate the clock to the IPs and PLLs. 108 a power sleep control module that gate the clock to the IPs and PLLs.
109 109
110source "drivers/clk/qcom/Kconfig"
111
110endmenu 112endmenu
111 113
112source "drivers/clk/mvebu/Kconfig" 114source "drivers/clk/mvebu/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 7a10bc9a23e7..972da894baa1 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -14,13 +14,14 @@ obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o
14obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o 14obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o
15obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o 15obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
16obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o 16obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
17obj-$(CONFIG_ARCH_HI3xxx) += hisilicon/
17obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o 18obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o
18obj-$(CONFIG_ARCH_MXS) += mxs/ 19obj-$(CONFIG_ARCH_MXS) += mxs/
19obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/ 20obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/
20obj-$(CONFIG_PLAT_SPEAR) += spear/ 21obj-$(CONFIG_PLAT_SPEAR) += spear/
21obj-$(CONFIG_ARCH_U300) += clk-u300.o 22obj-$(CONFIG_ARCH_U300) += clk-u300.o
22obj-$(CONFIG_COMMON_CLK_VERSATILE) += versatile/ 23obj-$(CONFIG_COMMON_CLK_VERSATILE) += versatile/
23obj-$(CONFIG_ARCH_SIRF) += clk-prima2.o 24obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/
24obj-$(CONFIG_PLAT_ORION) += mvebu/ 25obj-$(CONFIG_PLAT_ORION) += mvebu/
25ifeq ($(CONFIG_COMMON_CLK), y) 26ifeq ($(CONFIG_COMMON_CLK), y)
26obj-$(CONFIG_ARCH_MMP) += mmp/ 27obj-$(CONFIG_ARCH_MMP) += mmp/
@@ -30,11 +31,13 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
30obj-$(CONFIG_ARCH_SUNXI) += sunxi/ 31obj-$(CONFIG_ARCH_SUNXI) += sunxi/
31obj-$(CONFIG_ARCH_U8500) += ux500/ 32obj-$(CONFIG_ARCH_U8500) += ux500/
32obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o 33obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
34obj-$(CONFIG_ARCH_SIRF) += sirf/
33obj-$(CONFIG_ARCH_ZYNQ) += zynq/ 35obj-$(CONFIG_ARCH_ZYNQ) += zynq/
34obj-$(CONFIG_ARCH_TEGRA) += tegra/ 36obj-$(CONFIG_ARCH_TEGRA) += tegra/
35obj-$(CONFIG_PLAT_SAMSUNG) += samsung/ 37obj-$(CONFIG_PLAT_SAMSUNG) += samsung/
36obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o 38obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o
37obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/ 39obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/
40obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += shmobile/
38 41
39obj-$(CONFIG_X86) += x86/ 42obj-$(CONFIG_X86) += x86/
40 43
@@ -43,6 +46,7 @@ obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o
43obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o 46obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
44obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o 47obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
45obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o 48obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o
49obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o
46obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o 50obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o
47obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o 51obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o
48obj-$(CONFIG_CLK_PPC_CORENET) += clk-ppc-corenet.o 52obj-$(CONFIG_CLK_PPC_CORENET) += clk-ppc-corenet.o
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index a33f46f20a41..57a078e06efe 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -55,6 +55,30 @@ static unsigned long clk_composite_recalc_rate(struct clk_hw *hw,
55 return rate_ops->recalc_rate(rate_hw, parent_rate); 55 return rate_ops->recalc_rate(rate_hw, parent_rate);
56} 56}
57 57
58static long clk_composite_determine_rate(struct clk_hw *hw, unsigned long rate,
59 unsigned long *best_parent_rate,
60 struct clk **best_parent_p)
61{
62 struct clk_composite *composite = to_clk_composite(hw);
63 const struct clk_ops *rate_ops = composite->rate_ops;
64 const struct clk_ops *mux_ops = composite->mux_ops;
65 struct clk_hw *rate_hw = composite->rate_hw;
66 struct clk_hw *mux_hw = composite->mux_hw;
67
68 if (rate_hw && rate_ops && rate_ops->determine_rate) {
69 rate_hw->clk = hw->clk;
70 return rate_ops->determine_rate(rate_hw, rate, best_parent_rate,
71 best_parent_p);
72 } else if (mux_hw && mux_ops && mux_ops->determine_rate) {
73 mux_hw->clk = hw->clk;
74 return mux_ops->determine_rate(mux_hw, rate, best_parent_rate,
75 best_parent_p);
76 } else {
77 pr_err("clk: clk_composite_determine_rate function called, but no mux or rate callback set!\n");
78 return 0;
79 }
80}
81
58static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate, 82static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate,
59 unsigned long *prate) 83 unsigned long *prate)
60{ 84{
@@ -147,6 +171,8 @@ struct clk *clk_register_composite(struct device *dev, const char *name,
147 composite->mux_ops = mux_ops; 171 composite->mux_ops = mux_ops;
148 clk_composite_ops->get_parent = clk_composite_get_parent; 172 clk_composite_ops->get_parent = clk_composite_get_parent;
149 clk_composite_ops->set_parent = clk_composite_set_parent; 173 clk_composite_ops->set_parent = clk_composite_set_parent;
174 if (mux_ops->determine_rate)
175 clk_composite_ops->determine_rate = clk_composite_determine_rate;
150 } 176 }
151 177
152 if (rate_hw && rate_ops) { 178 if (rate_hw && rate_ops) {
@@ -170,6 +196,8 @@ struct clk *clk_register_composite(struct device *dev, const char *name,
170 composite->rate_hw = rate_hw; 196 composite->rate_hw = rate_hw;
171 composite->rate_ops = rate_ops; 197 composite->rate_ops = rate_ops;
172 clk_composite_ops->recalc_rate = clk_composite_recalc_rate; 198 clk_composite_ops->recalc_rate = clk_composite_recalc_rate;
199 if (rate_ops->determine_rate)
200 clk_composite_ops->determine_rate = clk_composite_determine_rate;
173 } 201 }
174 202
175 if (gate_hw && gate_ops) { 203 if (gate_hw && gate_ops) {
diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
index 1ed591ab8b1d..0fc56ab6e844 100644
--- a/drivers/clk/clk-fixed-rate.c
+++ b/drivers/clk/clk-fixed-rate.c
@@ -34,22 +34,31 @@ static unsigned long clk_fixed_rate_recalc_rate(struct clk_hw *hw,
34 return to_clk_fixed_rate(hw)->fixed_rate; 34 return to_clk_fixed_rate(hw)->fixed_rate;
35} 35}
36 36
37static unsigned long clk_fixed_rate_recalc_accuracy(struct clk_hw *hw,
38 unsigned long parent_accuracy)
39{
40 return to_clk_fixed_rate(hw)->fixed_accuracy;
41}
42
37const struct clk_ops clk_fixed_rate_ops = { 43const struct clk_ops clk_fixed_rate_ops = {
38 .recalc_rate = clk_fixed_rate_recalc_rate, 44 .recalc_rate = clk_fixed_rate_recalc_rate,
45 .recalc_accuracy = clk_fixed_rate_recalc_accuracy,
39}; 46};
40EXPORT_SYMBOL_GPL(clk_fixed_rate_ops); 47EXPORT_SYMBOL_GPL(clk_fixed_rate_ops);
41 48
42/** 49/**
43 * clk_register_fixed_rate - register fixed-rate clock with the clock framework 50 * clk_register_fixed_rate_with_accuracy - register fixed-rate clock with the
51 * clock framework
44 * @dev: device that is registering this clock 52 * @dev: device that is registering this clock
45 * @name: name of this clock 53 * @name: name of this clock
46 * @parent_name: name of clock's parent 54 * @parent_name: name of clock's parent
47 * @flags: framework-specific flags 55 * @flags: framework-specific flags
48 * @fixed_rate: non-adjustable clock rate 56 * @fixed_rate: non-adjustable clock rate
57 * @fixed_accuracy: non-adjustable clock rate
49 */ 58 */
50struct clk *clk_register_fixed_rate(struct device *dev, const char *name, 59struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev,
51 const char *parent_name, unsigned long flags, 60 const char *name, const char *parent_name, unsigned long flags,
52 unsigned long fixed_rate) 61 unsigned long fixed_rate, unsigned long fixed_accuracy)
53{ 62{
54 struct clk_fixed_rate *fixed; 63 struct clk_fixed_rate *fixed;
55 struct clk *clk; 64 struct clk *clk;
@@ -70,16 +79,33 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
70 79
71 /* struct clk_fixed_rate assignments */ 80 /* struct clk_fixed_rate assignments */
72 fixed->fixed_rate = fixed_rate; 81 fixed->fixed_rate = fixed_rate;
82 fixed->fixed_accuracy = fixed_accuracy;
73 fixed->hw.init = &init; 83 fixed->hw.init = &init;
74 84
75 /* register the clock */ 85 /* register the clock */
76 clk = clk_register(dev, &fixed->hw); 86 clk = clk_register(dev, &fixed->hw);
77
78 if (IS_ERR(clk)) 87 if (IS_ERR(clk))
79 kfree(fixed); 88 kfree(fixed);
80 89
81 return clk; 90 return clk;
82} 91}
92EXPORT_SYMBOL_GPL(clk_register_fixed_rate_with_accuracy);
93
94/**
95 * clk_register_fixed_rate - register fixed-rate clock with the clock framework
96 * @dev: device that is registering this clock
97 * @name: name of this clock
98 * @parent_name: name of clock's parent
99 * @flags: framework-specific flags
100 * @fixed_rate: non-adjustable clock rate
101 */
102struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
103 const char *parent_name, unsigned long flags,
104 unsigned long fixed_rate)
105{
106 return clk_register_fixed_rate_with_accuracy(dev, name, parent_name,
107 flags, fixed_rate, 0);
108}
83EXPORT_SYMBOL_GPL(clk_register_fixed_rate); 109EXPORT_SYMBOL_GPL(clk_register_fixed_rate);
84 110
85#ifdef CONFIG_OF 111#ifdef CONFIG_OF
@@ -91,13 +117,18 @@ void of_fixed_clk_setup(struct device_node *node)
91 struct clk *clk; 117 struct clk *clk;
92 const char *clk_name = node->name; 118 const char *clk_name = node->name;
93 u32 rate; 119 u32 rate;
120 u32 accuracy = 0;
94 121
95 if (of_property_read_u32(node, "clock-frequency", &rate)) 122 if (of_property_read_u32(node, "clock-frequency", &rate))
96 return; 123 return;
97 124
125 of_property_read_u32(node, "clock-accuracy", &accuracy);
126
98 of_property_read_string(node, "clock-output-names", &clk_name); 127 of_property_read_string(node, "clock-output-names", &clk_name);
99 128
100 clk = clk_register_fixed_rate(NULL, clk_name, NULL, CLK_IS_ROOT, rate); 129 clk = clk_register_fixed_rate_with_accuracy(NULL, clk_name, NULL,
130 CLK_IS_ROOT, rate,
131 accuracy);
101 if (!IS_ERR(clk)) 132 if (!IS_ERR(clk))
102 of_clk_add_provider(node, of_clk_src_simple_get, clk); 133 of_clk_add_provider(node, of_clk_src_simple_get, clk);
103} 134}
diff --git a/drivers/clk/clk-max77686.c b/drivers/clk/clk-max77686.c
index 9f57bc37cd60..3d7e8dd8fd58 100644
--- a/drivers/clk/clk-max77686.c
+++ b/drivers/clk/clk-max77686.c
@@ -66,7 +66,7 @@ static void max77686_clk_unprepare(struct clk_hw *hw)
66 MAX77686_REG_32KHZ, max77686->mask, ~max77686->mask); 66 MAX77686_REG_32KHZ, max77686->mask, ~max77686->mask);
67} 67}
68 68
69static int max77686_clk_is_enabled(struct clk_hw *hw) 69static int max77686_clk_is_prepared(struct clk_hw *hw)
70{ 70{
71 struct max77686_clk *max77686 = to_max77686_clk(hw); 71 struct max77686_clk *max77686 = to_max77686_clk(hw);
72 int ret; 72 int ret;
@@ -81,10 +81,17 @@ static int max77686_clk_is_enabled(struct clk_hw *hw)
81 return val & max77686->mask; 81 return val & max77686->mask;
82} 82}
83 83
84static unsigned long max77686_recalc_rate(struct clk_hw *hw,
85 unsigned long parent_rate)
86{
87 return 32768;
88}
89
84static struct clk_ops max77686_clk_ops = { 90static struct clk_ops max77686_clk_ops = {
85 .prepare = max77686_clk_prepare, 91 .prepare = max77686_clk_prepare,
86 .unprepare = max77686_clk_unprepare, 92 .unprepare = max77686_clk_unprepare,
87 .is_enabled = max77686_clk_is_enabled, 93 .is_prepared = max77686_clk_is_prepared,
94 .recalc_rate = max77686_recalc_rate,
88}; 95};
89 96
90static struct clk_init_data max77686_clks_init[MAX77686_CLKS_NUM] = { 97static struct clk_init_data max77686_clks_init[MAX77686_CLKS_NUM] = {
@@ -105,38 +112,38 @@ static struct clk_init_data max77686_clks_init[MAX77686_CLKS_NUM] = {
105 }, 112 },
106}; 113};
107 114
108static int max77686_clk_register(struct device *dev, 115static struct clk *max77686_clk_register(struct device *dev,
109 struct max77686_clk *max77686) 116 struct max77686_clk *max77686)
110{ 117{
111 struct clk *clk; 118 struct clk *clk;
112 struct clk_hw *hw = &max77686->hw; 119 struct clk_hw *hw = &max77686->hw;
113 120
114 clk = clk_register(dev, hw); 121 clk = clk_register(dev, hw);
115
116 if (IS_ERR(clk)) 122 if (IS_ERR(clk))
117 return -ENOMEM; 123 return clk;
118 124
119 max77686->lookup = kzalloc(sizeof(struct clk_lookup), GFP_KERNEL); 125 max77686->lookup = kzalloc(sizeof(struct clk_lookup), GFP_KERNEL);
120 if (!max77686->lookup) 126 if (!max77686->lookup)
121 return -ENOMEM; 127 return ERR_PTR(-ENOMEM);
122 128
123 max77686->lookup->con_id = hw->init->name; 129 max77686->lookup->con_id = hw->init->name;
124 max77686->lookup->clk = clk; 130 max77686->lookup->clk = clk;
125 131
126 clkdev_add(max77686->lookup); 132 clkdev_add(max77686->lookup);
127 133
128 return 0; 134 return clk;
129} 135}
130 136
131static int max77686_clk_probe(struct platform_device *pdev) 137static int max77686_clk_probe(struct platform_device *pdev)
132{ 138{
133 struct max77686_dev *iodev = dev_get_drvdata(pdev->dev.parent); 139 struct max77686_dev *iodev = dev_get_drvdata(pdev->dev.parent);
134 struct max77686_clk **max77686_clks; 140 struct max77686_clk *max77686_clks[MAX77686_CLKS_NUM];
141 struct clk **clocks;
135 int i, ret; 142 int i, ret;
136 143
137 max77686_clks = devm_kzalloc(&pdev->dev, sizeof(struct max77686_clk *) 144 clocks = devm_kzalloc(&pdev->dev, sizeof(struct clk *)
138 * MAX77686_CLKS_NUM, GFP_KERNEL); 145 * MAX77686_CLKS_NUM, GFP_KERNEL);
139 if (!max77686_clks) 146 if (!clocks)
140 return -ENOMEM; 147 return -ENOMEM;
141 148
142 for (i = 0; i < MAX77686_CLKS_NUM; i++) { 149 for (i = 0; i < MAX77686_CLKS_NUM; i++) {
@@ -151,47 +158,63 @@ static int max77686_clk_probe(struct platform_device *pdev)
151 max77686_clks[i]->mask = 1 << i; 158 max77686_clks[i]->mask = 1 << i;
152 max77686_clks[i]->hw.init = &max77686_clks_init[i]; 159 max77686_clks[i]->hw.init = &max77686_clks_init[i];
153 160
154 ret = max77686_clk_register(&pdev->dev, max77686_clks[i]); 161 clocks[i] = max77686_clk_register(&pdev->dev, max77686_clks[i]);
162 if (IS_ERR(clocks[i])) {
163 ret = PTR_ERR(clocks[i]);
164 dev_err(&pdev->dev, "failed to register %s\n",
165 max77686_clks[i]->hw.init->name);
166 goto err_clocks;
167 }
168 }
169
170 platform_set_drvdata(pdev, clocks);
171
172 if (iodev->dev->of_node) {
173 struct clk_onecell_data *of_data;
174
175 of_data = devm_kzalloc(&pdev->dev,
176 sizeof(*of_data), GFP_KERNEL);
177 if (!of_data) {
178 ret = -ENOMEM;
179 goto err_clocks;
180 }
181
182 of_data->clks = clocks;
183 of_data->clk_num = MAX77686_CLKS_NUM;
184 ret = of_clk_add_provider(iodev->dev->of_node,
185 of_clk_src_onecell_get, of_data);
155 if (ret) { 186 if (ret) {
156 switch (i) { 187 dev_err(&pdev->dev, "failed to register OF clock provider\n");
157 case MAX77686_CLK_AP: 188 goto err_clocks;
158 dev_err(&pdev->dev, "Fail to register CLK_AP\n");
159 goto err_clk_ap;
160 break;
161 case MAX77686_CLK_CP:
162 dev_err(&pdev->dev, "Fail to register CLK_CP\n");
163 goto err_clk_cp;
164 break;
165 case MAX77686_CLK_PMIC:
166 dev_err(&pdev->dev, "Fail to register CLK_PMIC\n");
167 goto err_clk_pmic;
168 }
169 } 189 }
170 } 190 }
171 191
172 platform_set_drvdata(pdev, max77686_clks); 192 return 0;
173 193
174 goto out; 194err_clocks:
195 for (--i; i >= 0; --i) {
196 clkdev_drop(max77686_clks[i]->lookup);
197 clk_unregister(max77686_clks[i]->hw.clk);
198 }
175 199
176err_clk_pmic:
177 clkdev_drop(max77686_clks[MAX77686_CLK_CP]->lookup);
178 kfree(max77686_clks[MAX77686_CLK_CP]->hw.clk);
179err_clk_cp:
180 clkdev_drop(max77686_clks[MAX77686_CLK_AP]->lookup);
181 kfree(max77686_clks[MAX77686_CLK_AP]->hw.clk);
182err_clk_ap:
183out:
184 return ret; 200 return ret;
185} 201}
186 202
187static int max77686_clk_remove(struct platform_device *pdev) 203static int max77686_clk_remove(struct platform_device *pdev)
188{ 204{
189 struct max77686_clk **max77686_clks = platform_get_drvdata(pdev); 205 struct max77686_dev *iodev = dev_get_drvdata(pdev->dev.parent);
206 struct clk **clocks = platform_get_drvdata(pdev);
190 int i; 207 int i;
191 208
209 if (iodev->dev->of_node)
210 of_clk_del_provider(iodev->dev->of_node);
211
192 for (i = 0; i < MAX77686_CLKS_NUM; i++) { 212 for (i = 0; i < MAX77686_CLKS_NUM; i++) {
193 clkdev_drop(max77686_clks[i]->lookup); 213 struct clk_hw *hw = __clk_get_hw(clocks[i]);
194 kfree(max77686_clks[i]->hw.clk); 214 struct max77686_clk *max77686 = to_max77686_clk(hw);
215
216 clkdev_drop(max77686->lookup);
217 clk_unregister(clocks[i]);
195 } 218 }
196 return 0; 219 return 0;
197} 220}
diff --git a/drivers/clk/clk-si570.c b/drivers/clk/clk-si570.c
new file mode 100644
index 000000000000..4bbbe32585ec
--- /dev/null
+++ b/drivers/clk/clk-si570.c
@@ -0,0 +1,531 @@
1/*
2 * Driver for Silicon Labs Si570/Si571 Programmable XO/VCXO
3 *
4 * Copyright (C) 2010, 2011 Ericsson AB.
5 * Copyright (C) 2011 Guenter Roeck.
6 * Copyright (C) 2011 - 2013 Xilinx Inc.
7 *
8 * Author: Guenter Roeck <guenter.roeck@ericsson.com>
9 * Sören Brinkmann <soren.brinkmann@xilinx.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 */
21
22#include <linux/clk-provider.h>
23#include <linux/delay.h>
24#include <linux/module.h>
25#include <linux/i2c.h>
26#include <linux/regmap.h>
27#include <linux/slab.h>
28
29/* Si570 registers */
30#define SI570_REG_HS_N1 7
31#define SI570_REG_N1_RFREQ0 8
32#define SI570_REG_RFREQ1 9
33#define SI570_REG_RFREQ2 10
34#define SI570_REG_RFREQ3 11
35#define SI570_REG_RFREQ4 12
36#define SI570_REG_CONTROL 135
37#define SI570_REG_FREEZE_DCO 137
38#define SI570_DIV_OFFSET_7PPM 6
39
40#define HS_DIV_SHIFT 5
41#define HS_DIV_MASK 0xe0
42#define HS_DIV_OFFSET 4
43#define N1_6_2_MASK 0x1f
44#define N1_1_0_MASK 0xc0
45#define RFREQ_37_32_MASK 0x3f
46
47#define SI570_MIN_FREQ 10000000L
48#define SI570_MAX_FREQ 1417500000L
49#define SI598_MAX_FREQ 525000000L
50
51#define FDCO_MIN 4850000000LL
52#define FDCO_MAX 5670000000LL
53
54#define SI570_CNTRL_RECALL (1 << 0)
55#define SI570_CNTRL_FREEZE_M (1 << 5)
56#define SI570_CNTRL_NEWFREQ (1 << 6)
57
58#define SI570_FREEZE_DCO (1 << 4)
59
60/**
61 * struct clk_si570:
62 * @hw: Clock hw struct
63 * @regmap: Device's regmap
64 * @div_offset: Rgister offset for dividers
65 * @max_freq: Maximum frequency for this device
66 * @fxtal: Factory xtal frequency
67 * @n1: Clock divider N1
68 * @hs_div: Clock divider HSDIV
69 * @rfreq: Clock multiplier RFREQ
70 * @frequency: Current output frequency
71 * @i2c_client: I2C client pointer
72 */
73struct clk_si570 {
74 struct clk_hw hw;
75 struct regmap *regmap;
76 unsigned int div_offset;
77 u64 max_freq;
78 u64 fxtal;
79 unsigned int n1;
80 unsigned int hs_div;
81 u64 rfreq;
82 u64 frequency;
83 struct i2c_client *i2c_client;
84};
85#define to_clk_si570(_hw) container_of(_hw, struct clk_si570, hw)
86
87enum clk_si570_variant {
88 si57x,
89 si59x
90};
91
92/**
93 * si570_get_divs() - Read clock dividers from HW
94 * @data: Pointer to struct clk_si570
95 * @rfreq: Fractional multiplier (output)
96 * @n1: Divider N1 (output)
97 * @hs_div: Divider HSDIV (output)
98 * Returns 0 on success, negative errno otherwise.
99 *
100 * Retrieve clock dividers and multipliers from the HW.
101 */
102static int si570_get_divs(struct clk_si570 *data, u64 *rfreq,
103 unsigned int *n1, unsigned int *hs_div)
104{
105 int err;
106 u8 reg[6];
107 u64 tmp;
108
109 err = regmap_bulk_read(data->regmap, SI570_REG_HS_N1 + data->div_offset,
110 reg, ARRAY_SIZE(reg));
111 if (err)
112 return err;
113
114 *hs_div = ((reg[0] & HS_DIV_MASK) >> HS_DIV_SHIFT) + HS_DIV_OFFSET;
115 *n1 = ((reg[0] & N1_6_2_MASK) << 2) + ((reg[1] & N1_1_0_MASK) >> 6) + 1;
116 /* Handle invalid cases */
117 if (*n1 > 1)
118 *n1 &= ~1;
119
120 tmp = reg[1] & RFREQ_37_32_MASK;
121 tmp = (tmp << 8) + reg[2];
122 tmp = (tmp << 8) + reg[3];
123 tmp = (tmp << 8) + reg[4];
124 tmp = (tmp << 8) + reg[5];
125 *rfreq = tmp;
126
127 return 0;
128}
129
130/**
131 * si570_get_defaults() - Get default values
132 * @data: Driver data structure
133 * @fout: Factory frequency output
134 * Returns 0 on success, negative errno otherwise.
135 */
136static int si570_get_defaults(struct clk_si570 *data, u64 fout)
137{
138 int err;
139 u64 fdco;
140
141 regmap_write(data->regmap, SI570_REG_CONTROL, SI570_CNTRL_RECALL);
142
143 err = si570_get_divs(data, &data->rfreq, &data->n1, &data->hs_div);
144 if (err)
145 return err;
146
147 /*
148 * Accept optional precision loss to avoid arithmetic overflows.
149 * Acceptable per Silicon Labs Application Note AN334.
150 */
151 fdco = fout * data->n1 * data->hs_div;
152 if (fdco >= (1LL << 36))
153 data->fxtal = div64_u64(fdco << 24, data->rfreq >> 4);
154 else
155 data->fxtal = div64_u64(fdco << 28, data->rfreq);
156
157 data->frequency = fout;
158
159 return 0;
160}
161
162/**
163 * si570_update_rfreq() - Update clock multiplier
164 * @data: Driver data structure
165 * Passes on regmap_bulk_write() return value.
166 */
167static int si570_update_rfreq(struct clk_si570 *data)
168{
169 u8 reg[5];
170
171 reg[0] = ((data->n1 - 1) << 6) |
172 ((data->rfreq >> 32) & RFREQ_37_32_MASK);
173 reg[1] = (data->rfreq >> 24) & 0xff;
174 reg[2] = (data->rfreq >> 16) & 0xff;
175 reg[3] = (data->rfreq >> 8) & 0xff;
176 reg[4] = data->rfreq & 0xff;
177
178 return regmap_bulk_write(data->regmap, SI570_REG_N1_RFREQ0 +
179 data->div_offset, reg, ARRAY_SIZE(reg));
180}
181
182/**
183 * si570_calc_divs() - Caluclate clock dividers
184 * @frequency: Target frequency
185 * @data: Driver data structure
186 * @out_rfreq: RFREG fractional multiplier (output)
187 * @out_n1: Clock divider N1 (output)
188 * @out_hs_div: Clock divider HSDIV (output)
189 * Returns 0 on success, negative errno otherwise.
190 *
191 * Calculate the clock dividers (@out_hs_div, @out_n1) and clock multiplier
192 * (@out_rfreq) for a given target @frequency.
193 */
194static int si570_calc_divs(unsigned long frequency, struct clk_si570 *data,
195 u64 *out_rfreq, unsigned int *out_n1, unsigned int *out_hs_div)
196{
197 int i;
198 unsigned int n1, hs_div;
199 u64 fdco, best_fdco = ULLONG_MAX;
200 static const uint8_t si570_hs_div_values[] = { 11, 9, 7, 6, 5, 4 };
201
202 for (i = 0; i < ARRAY_SIZE(si570_hs_div_values); i++) {
203 hs_div = si570_hs_div_values[i];
204 /* Calculate lowest possible value for n1 */
205 n1 = div_u64(div_u64(FDCO_MIN, hs_div), frequency);
206 if (!n1 || (n1 & 1))
207 n1++;
208 while (n1 <= 128) {
209 fdco = (u64)frequency * (u64)hs_div * (u64)n1;
210 if (fdco > FDCO_MAX)
211 break;
212 if (fdco >= FDCO_MIN && fdco < best_fdco) {
213 *out_n1 = n1;
214 *out_hs_div = hs_div;
215 *out_rfreq = div64_u64(fdco << 28, data->fxtal);
216 best_fdco = fdco;
217 }
218 n1 += (n1 == 1 ? 1 : 2);
219 }
220 }
221
222 if (best_fdco == ULLONG_MAX)
223 return -EINVAL;
224
225 return 0;
226}
227
228static unsigned long si570_recalc_rate(struct clk_hw *hw,
229 unsigned long parent_rate)
230{
231 int err;
232 u64 rfreq, rate;
233 unsigned int n1, hs_div;
234 struct clk_si570 *data = to_clk_si570(hw);
235
236 err = si570_get_divs(data, &rfreq, &n1, &hs_div);
237 if (err) {
238 dev_err(&data->i2c_client->dev, "unable to recalc rate\n");
239 return data->frequency;
240 }
241
242 rfreq = div_u64(rfreq, hs_div * n1);
243 rate = (data->fxtal * rfreq) >> 28;
244
245 return rate;
246}
247
248static long si570_round_rate(struct clk_hw *hw, unsigned long rate,
249 unsigned long *parent_rate)
250{
251 int err;
252 u64 rfreq;
253 unsigned int n1, hs_div;
254 struct clk_si570 *data = to_clk_si570(hw);
255
256 if (!rate)
257 return 0;
258
259 if (div64_u64(abs(rate - data->frequency) * 10000LL,
260 data->frequency) < 35) {
261 rfreq = div64_u64((data->rfreq * rate) +
262 div64_u64(data->frequency, 2), data->frequency);
263 n1 = data->n1;
264 hs_div = data->hs_div;
265
266 } else {
267 err = si570_calc_divs(rate, data, &rfreq, &n1, &hs_div);
268 if (err) {
269 dev_err(&data->i2c_client->dev,
270 "unable to round rate\n");
271 return 0;
272 }
273 }
274
275 return rate;
276}
277
278/**
279 * si570_set_frequency() - Adjust output frequency
280 * @data: Driver data structure
281 * @frequency: Target frequency
282 * Returns 0 on success.
283 *
284 * Update output frequency for big frequency changes (> 3,500 ppm).
285 */
286static int si570_set_frequency(struct clk_si570 *data, unsigned long frequency)
287{
288 int err;
289
290 err = si570_calc_divs(frequency, data, &data->rfreq, &data->n1,
291 &data->hs_div);
292 if (err)
293 return err;
294
295 /*
296 * The DCO reg should be accessed with a read-modify-write operation
297 * per AN334
298 */
299 regmap_write(data->regmap, SI570_REG_FREEZE_DCO, SI570_FREEZE_DCO);
300 regmap_write(data->regmap, SI570_REG_HS_N1 + data->div_offset,
301 ((data->hs_div - HS_DIV_OFFSET) << HS_DIV_SHIFT) |
302 (((data->n1 - 1) >> 2) & N1_6_2_MASK));
303 si570_update_rfreq(data);
304 regmap_write(data->regmap, SI570_REG_FREEZE_DCO, 0);
305 regmap_write(data->regmap, SI570_REG_CONTROL, SI570_CNTRL_NEWFREQ);
306
307 /* Applying a new frequency can take up to 10ms */
308 usleep_range(10000, 12000);
309
310 return 0;
311}
312
313/**
314 * si570_set_frequency_small() - Adjust output frequency
315 * @data: Driver data structure
316 * @frequency: Target frequency
317 * Returns 0 on success.
318 *
319 * Update output frequency for small frequency changes (< 3,500 ppm).
320 */
321static int si570_set_frequency_small(struct clk_si570 *data,
322 unsigned long frequency)
323{
324 /*
325 * This is a re-implementation of DIV_ROUND_CLOSEST
326 * using the div64_u64 function lieu of letting the compiler
327 * insert EABI calls
328 */
329 data->rfreq = div64_u64((data->rfreq * frequency) +
330 div_u64(data->frequency, 2), data->frequency);
331 regmap_write(data->regmap, SI570_REG_CONTROL, SI570_CNTRL_FREEZE_M);
332 si570_update_rfreq(data);
333 regmap_write(data->regmap, SI570_REG_CONTROL, 0);
334
335 /* Applying a new frequency (small change) can take up to 100us */
336 usleep_range(100, 200);
337
338 return 0;
339}
340
341static int si570_set_rate(struct clk_hw *hw, unsigned long rate,
342 unsigned long parent_rate)
343{
344 struct clk_si570 *data = to_clk_si570(hw);
345 struct i2c_client *client = data->i2c_client;
346 int err;
347
348 if (rate < SI570_MIN_FREQ || rate > data->max_freq) {
349 dev_err(&client->dev,
350 "requested frequency %lu Hz is out of range\n", rate);
351 return -EINVAL;
352 }
353
354 if (div64_u64(abs(rate - data->frequency) * 10000LL,
355 data->frequency) < 35)
356 err = si570_set_frequency_small(data, rate);
357 else
358 err = si570_set_frequency(data, rate);
359
360 if (err)
361 return err;
362
363 data->frequency = rate;
364
365 return 0;
366}
367
368static const struct clk_ops si570_clk_ops = {
369 .recalc_rate = si570_recalc_rate,
370 .round_rate = si570_round_rate,
371 .set_rate = si570_set_rate,
372};
373
374static bool si570_regmap_is_volatile(struct device *dev, unsigned int reg)
375{
376 switch (reg) {
377 case SI570_REG_CONTROL:
378 return true;
379 default:
380 return false;
381 }
382}
383
384static bool si570_regmap_is_writeable(struct device *dev, unsigned int reg)
385{
386 switch (reg) {
387 case SI570_REG_HS_N1 ... (SI570_REG_RFREQ4 + SI570_DIV_OFFSET_7PPM):
388 case SI570_REG_CONTROL:
389 case SI570_REG_FREEZE_DCO:
390 return true;
391 default:
392 return false;
393 }
394}
395
396static struct regmap_config si570_regmap_config = {
397 .reg_bits = 8,
398 .val_bits = 8,
399 .cache_type = REGCACHE_RBTREE,
400 .max_register = 137,
401 .writeable_reg = si570_regmap_is_writeable,
402 .volatile_reg = si570_regmap_is_volatile,
403};
404
405static int si570_probe(struct i2c_client *client,
406 const struct i2c_device_id *id)
407{
408 struct clk_si570 *data;
409 struct clk_init_data init;
410 struct clk *clk;
411 u32 initial_fout, factory_fout, stability;
412 int err;
413 enum clk_si570_variant variant = id->driver_data;
414
415 data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
416 if (!data)
417 return -ENOMEM;
418
419 init.ops = &si570_clk_ops;
420 init.flags = CLK_IS_ROOT;
421 init.num_parents = 0;
422 data->hw.init = &init;
423 data->i2c_client = client;
424
425 if (variant == si57x) {
426 err = of_property_read_u32(client->dev.of_node,
427 "temperature-stability", &stability);
428 if (err) {
429 dev_err(&client->dev,
430 "'temperature-stability' property missing\n");
431 return err;
432 }
433 /* adjust register offsets for 7ppm devices */
434 if (stability == 7)
435 data->div_offset = SI570_DIV_OFFSET_7PPM;
436
437 data->max_freq = SI570_MAX_FREQ;
438 } else {
439 data->max_freq = SI598_MAX_FREQ;
440 }
441
442 if (of_property_read_string(client->dev.of_node, "clock-output-names",
443 &init.name))
444 init.name = client->dev.of_node->name;
445
446 err = of_property_read_u32(client->dev.of_node, "factory-fout",
447 &factory_fout);
448 if (err) {
449 dev_err(&client->dev, "'factory-fout' property missing\n");
450 return err;
451 }
452
453 data->regmap = devm_regmap_init_i2c(client, &si570_regmap_config);
454 if (IS_ERR(data->regmap)) {
455 dev_err(&client->dev, "failed to allocate register map\n");
456 return PTR_ERR(data->regmap);
457 }
458
459 i2c_set_clientdata(client, data);
460 err = si570_get_defaults(data, factory_fout);
461 if (err)
462 return err;
463
464 clk = devm_clk_register(&client->dev, &data->hw);
465 if (IS_ERR(clk)) {
466 dev_err(&client->dev, "clock registration failed\n");
467 return PTR_ERR(clk);
468 }
469 err = of_clk_add_provider(client->dev.of_node, of_clk_src_simple_get,
470 clk);
471 if (err) {
472 dev_err(&client->dev, "unable to add clk provider\n");
473 return err;
474 }
475
476 /* Read the requested initial output frequency from device tree */
477 if (!of_property_read_u32(client->dev.of_node, "clock-frequency",
478 &initial_fout)) {
479 err = clk_set_rate(clk, initial_fout);
480 if (err) {
481 of_clk_del_provider(client->dev.of_node);
482 return err;
483 }
484 }
485
486 /* Display a message indicating that we've successfully registered */
487 dev_info(&client->dev, "registered, current frequency %llu Hz\n",
488 data->frequency);
489
490 return 0;
491}
492
493static int si570_remove(struct i2c_client *client)
494{
495 of_clk_del_provider(client->dev.of_node);
496 return 0;
497}
498
499static const struct i2c_device_id si570_id[] = {
500 { "si570", si57x },
501 { "si571", si57x },
502 { "si598", si59x },
503 { "si599", si59x },
504 { }
505};
506MODULE_DEVICE_TABLE(i2c, si570_id);
507
508static const struct of_device_id clk_si570_of_match[] = {
509 { .compatible = "silabs,si570" },
510 { .compatible = "silabs,si571" },
511 { .compatible = "silabs,si598" },
512 { .compatible = "silabs,si599" },
513 { },
514};
515MODULE_DEVICE_TABLE(of, clk_si570_of_match);
516
517static struct i2c_driver si570_driver = {
518 .driver = {
519 .name = "si570",
520 .of_match_table = clk_si570_of_match,
521 },
522 .probe = si570_probe,
523 .remove = si570_remove,
524 .id_table = si570_id,
525};
526module_i2c_driver(si570_driver);
527
528MODULE_AUTHOR("Guenter Roeck <guenter.roeck@ericsson.com>");
529MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com");
530MODULE_DESCRIPTION("Si570 driver");
531MODULE_LICENSE("GPL");
diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c
index 7fd5c5e9e25d..37e928846ec5 100644
--- a/drivers/clk/clk-vt8500.c
+++ b/drivers/clk/clk-vt8500.c
@@ -641,7 +641,7 @@ static unsigned long vtwm_pll_recalc_rate(struct clk_hw *hw,
641 return pll_freq; 641 return pll_freq;
642} 642}
643 643
644const struct clk_ops vtwm_pll_ops = { 644static const struct clk_ops vtwm_pll_ops = {
645 .round_rate = vtwm_pll_round_rate, 645 .round_rate = vtwm_pll_round_rate,
646 .set_rate = vtwm_pll_set_rate, 646 .set_rate = vtwm_pll_set_rate,
647 .recalc_rate = vtwm_pll_recalc_rate, 647 .recalc_rate = vtwm_pll_recalc_rate,
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 2cf2ea6b77a1..2b38dc99063f 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -21,6 +21,8 @@
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/sched.h> 22#include <linux/sched.h>
23 23
24#include "clk.h"
25
24static DEFINE_SPINLOCK(enable_lock); 26static DEFINE_SPINLOCK(enable_lock);
25static DEFINE_MUTEX(prepare_lock); 27static DEFINE_MUTEX(prepare_lock);
26 28
@@ -92,7 +94,7 @@ static void clk_enable_unlock(unsigned long flags)
92 94
93/*** debugfs support ***/ 95/*** debugfs support ***/
94 96
95#ifdef CONFIG_COMMON_CLK_DEBUG 97#ifdef CONFIG_DEBUG_FS
96#include <linux/debugfs.h> 98#include <linux/debugfs.h>
97 99
98static struct dentry *rootdir; 100static struct dentry *rootdir;
@@ -104,10 +106,11 @@ static void clk_summary_show_one(struct seq_file *s, struct clk *c, int level)
104 if (!c) 106 if (!c)
105 return; 107 return;
106 108
107 seq_printf(s, "%*s%-*s %-11d %-12d %-10lu", 109 seq_printf(s, "%*s%-*s %-11d %-12d %-10lu %-11lu",
108 level * 3 + 1, "", 110 level * 3 + 1, "",
109 30 - level * 3, c->name, 111 30 - level * 3, c->name,
110 c->enable_count, c->prepare_count, clk_get_rate(c)); 112 c->enable_count, c->prepare_count, clk_get_rate(c),
113 clk_get_accuracy(c));
111 seq_printf(s, "\n"); 114 seq_printf(s, "\n");
112} 115}
113 116
@@ -129,8 +132,8 @@ static int clk_summary_show(struct seq_file *s, void *data)
129{ 132{
130 struct clk *c; 133 struct clk *c;
131 134
132 seq_printf(s, " clock enable_cnt prepare_cnt rate\n"); 135 seq_printf(s, " clock enable_cnt prepare_cnt rate accuracy\n");
133 seq_printf(s, "---------------------------------------------------------------------\n"); 136 seq_printf(s, "---------------------------------------------------------------------------------\n");
134 137
135 clk_prepare_lock(); 138 clk_prepare_lock();
136 139
@@ -167,6 +170,7 @@ static void clk_dump_one(struct seq_file *s, struct clk *c, int level)
167 seq_printf(s, "\"enable_count\": %d,", c->enable_count); 170 seq_printf(s, "\"enable_count\": %d,", c->enable_count);
168 seq_printf(s, "\"prepare_count\": %d,", c->prepare_count); 171 seq_printf(s, "\"prepare_count\": %d,", c->prepare_count);
169 seq_printf(s, "\"rate\": %lu", clk_get_rate(c)); 172 seq_printf(s, "\"rate\": %lu", clk_get_rate(c));
173 seq_printf(s, "\"accuracy\": %lu", clk_get_accuracy(c));
170} 174}
171 175
172static void clk_dump_subtree(struct seq_file *s, struct clk *c, int level) 176static void clk_dump_subtree(struct seq_file *s, struct clk *c, int level)
@@ -248,6 +252,11 @@ static int clk_debug_create_one(struct clk *clk, struct dentry *pdentry)
248 if (!d) 252 if (!d)
249 goto err_out; 253 goto err_out;
250 254
255 d = debugfs_create_u32("clk_accuracy", S_IRUGO, clk->dentry,
256 (u32 *)&clk->accuracy);
257 if (!d)
258 goto err_out;
259
251 d = debugfs_create_x32("clk_flags", S_IRUGO, clk->dentry, 260 d = debugfs_create_x32("clk_flags", S_IRUGO, clk->dentry,
252 (u32 *)&clk->flags); 261 (u32 *)&clk->flags);
253 if (!d) 262 if (!d)
@@ -272,7 +281,8 @@ static int clk_debug_create_one(struct clk *clk, struct dentry *pdentry)
272 goto out; 281 goto out;
273 282
274err_out: 283err_out:
275 debugfs_remove(clk->dentry); 284 debugfs_remove_recursive(clk->dentry);
285 clk->dentry = NULL;
276out: 286out:
277 return ret; 287 return ret;
278} 288}
@@ -342,6 +352,21 @@ out:
342 return ret; 352 return ret;
343} 353}
344 354
355 /**
356 * clk_debug_unregister - remove a clk node from the debugfs clk tree
357 * @clk: the clk being removed from the debugfs clk tree
358 *
359 * Dynamically removes a clk and all it's children clk nodes from the
360 * debugfs clk tree if clk->dentry points to debugfs created by
361 * clk_debug_register in __clk_init.
362 *
363 * Caller must hold prepare_lock.
364 */
365static void clk_debug_unregister(struct clk *clk)
366{
367 debugfs_remove_recursive(clk->dentry);
368}
369
345/** 370/**
346 * clk_debug_reparent - reparent clk node in the debugfs clk tree 371 * clk_debug_reparent - reparent clk node in the debugfs clk tree
347 * @clk: the clk being reparented 372 * @clk: the clk being reparented
@@ -432,6 +457,9 @@ static inline int clk_debug_register(struct clk *clk) { return 0; }
432static inline void clk_debug_reparent(struct clk *clk, struct clk *new_parent) 457static inline void clk_debug_reparent(struct clk *clk, struct clk *new_parent)
433{ 458{
434} 459}
460static inline void clk_debug_unregister(struct clk *clk)
461{
462}
435#endif 463#endif
436 464
437/* caller must hold prepare_lock */ 465/* caller must hold prepare_lock */
@@ -602,6 +630,14 @@ out:
602 return ret; 630 return ret;
603} 631}
604 632
633unsigned long __clk_get_accuracy(struct clk *clk)
634{
635 if (!clk)
636 return 0;
637
638 return clk->accuracy;
639}
640
605unsigned long __clk_get_flags(struct clk *clk) 641unsigned long __clk_get_flags(struct clk *clk)
606{ 642{
607 return !clk ? 0 : clk->flags; 643 return !clk ? 0 : clk->flags;
@@ -1016,6 +1052,59 @@ static int __clk_notify(struct clk *clk, unsigned long msg,
1016} 1052}
1017 1053
1018/** 1054/**
1055 * __clk_recalc_accuracies
1056 * @clk: first clk in the subtree
1057 *
1058 * Walks the subtree of clks starting with clk and recalculates accuracies as
1059 * it goes. Note that if a clk does not implement the .recalc_accuracy
1060 * callback then it is assumed that the clock will take on the accuracy of it's
1061 * parent.
1062 *
1063 * Caller must hold prepare_lock.
1064 */
1065static void __clk_recalc_accuracies(struct clk *clk)
1066{
1067 unsigned long parent_accuracy = 0;
1068 struct clk *child;
1069
1070 if (clk->parent)
1071 parent_accuracy = clk->parent->accuracy;
1072
1073 if (clk->ops->recalc_accuracy)
1074 clk->accuracy = clk->ops->recalc_accuracy(clk->hw,
1075 parent_accuracy);
1076 else
1077 clk->accuracy = parent_accuracy;
1078
1079 hlist_for_each_entry(child, &clk->children, child_node)
1080 __clk_recalc_accuracies(child);
1081}
1082
1083/**
1084 * clk_get_accuracy - return the accuracy of clk
1085 * @clk: the clk whose accuracy is being returned
1086 *
1087 * Simply returns the cached accuracy of the clk, unless
1088 * CLK_GET_ACCURACY_NOCACHE flag is set, which means a recalc_rate will be
1089 * issued.
1090 * If clk is NULL then returns 0.
1091 */
1092long clk_get_accuracy(struct clk *clk)
1093{
1094 unsigned long accuracy;
1095
1096 clk_prepare_lock();
1097 if (clk && (clk->flags & CLK_GET_ACCURACY_NOCACHE))
1098 __clk_recalc_accuracies(clk);
1099
1100 accuracy = __clk_get_accuracy(clk);
1101 clk_prepare_unlock();
1102
1103 return accuracy;
1104}
1105EXPORT_SYMBOL_GPL(clk_get_accuracy);
1106
1107/**
1019 * __clk_recalc_rates 1108 * __clk_recalc_rates
1020 * @clk: first clk in the subtree 1109 * @clk: first clk in the subtree
1021 * @msg: notification type (see include/linux/clk.h) 1110 * @msg: notification type (see include/linux/clk.h)
@@ -1129,10 +1218,9 @@ static void clk_reparent(struct clk *clk, struct clk *new_parent)
1129 clk->parent = new_parent; 1218 clk->parent = new_parent;
1130} 1219}
1131 1220
1132static int __clk_set_parent(struct clk *clk, struct clk *parent, u8 p_index) 1221static struct clk *__clk_set_parent_before(struct clk *clk, struct clk *parent)
1133{ 1222{
1134 unsigned long flags; 1223 unsigned long flags;
1135 int ret = 0;
1136 struct clk *old_parent = clk->parent; 1224 struct clk *old_parent = clk->parent;
1137 1225
1138 /* 1226 /*
@@ -1163,6 +1251,34 @@ static int __clk_set_parent(struct clk *clk, struct clk *parent, u8 p_index)
1163 clk_reparent(clk, parent); 1251 clk_reparent(clk, parent);
1164 clk_enable_unlock(flags); 1252 clk_enable_unlock(flags);
1165 1253
1254 return old_parent;
1255}
1256
1257static void __clk_set_parent_after(struct clk *clk, struct clk *parent,
1258 struct clk *old_parent)
1259{
1260 /*
1261 * Finish the migration of prepare state and undo the changes done
1262 * for preventing a race with clk_enable().
1263 */
1264 if (clk->prepare_count) {
1265 clk_disable(clk);
1266 clk_disable(old_parent);
1267 __clk_unprepare(old_parent);
1268 }
1269
1270 /* update debugfs with new clk tree topology */
1271 clk_debug_reparent(clk, parent);
1272}
1273
1274static int __clk_set_parent(struct clk *clk, struct clk *parent, u8 p_index)
1275{
1276 unsigned long flags;
1277 int ret = 0;
1278 struct clk *old_parent;
1279
1280 old_parent = __clk_set_parent_before(clk, parent);
1281
1166 /* change clock input source */ 1282 /* change clock input source */
1167 if (parent && clk->ops->set_parent) 1283 if (parent && clk->ops->set_parent)
1168 ret = clk->ops->set_parent(clk->hw, p_index); 1284 ret = clk->ops->set_parent(clk->hw, p_index);
@@ -1180,18 +1296,8 @@ static int __clk_set_parent(struct clk *clk, struct clk *parent, u8 p_index)
1180 return ret; 1296 return ret;
1181 } 1297 }
1182 1298
1183 /* 1299 __clk_set_parent_after(clk, parent, old_parent);
1184 * Finish the migration of prepare state and undo the changes done
1185 * for preventing a race with clk_enable().
1186 */
1187 if (clk->prepare_count) {
1188 clk_disable(clk);
1189 clk_disable(old_parent);
1190 __clk_unprepare(old_parent);
1191 }
1192 1300
1193 /* update debugfs with new clk tree topology */
1194 clk_debug_reparent(clk, parent);
1195 return 0; 1301 return 0;
1196} 1302}
1197 1303
@@ -1376,17 +1482,32 @@ static void clk_change_rate(struct clk *clk)
1376 struct clk *child; 1482 struct clk *child;
1377 unsigned long old_rate; 1483 unsigned long old_rate;
1378 unsigned long best_parent_rate = 0; 1484 unsigned long best_parent_rate = 0;
1485 bool skip_set_rate = false;
1486 struct clk *old_parent;
1379 1487
1380 old_rate = clk->rate; 1488 old_rate = clk->rate;
1381 1489
1382 /* set parent */ 1490 if (clk->new_parent)
1383 if (clk->new_parent && clk->new_parent != clk->parent) 1491 best_parent_rate = clk->new_parent->rate;
1384 __clk_set_parent(clk, clk->new_parent, clk->new_parent_index); 1492 else if (clk->parent)
1385
1386 if (clk->parent)
1387 best_parent_rate = clk->parent->rate; 1493 best_parent_rate = clk->parent->rate;
1388 1494
1389 if (clk->ops->set_rate) 1495 if (clk->new_parent && clk->new_parent != clk->parent) {
1496 old_parent = __clk_set_parent_before(clk, clk->new_parent);
1497
1498 if (clk->ops->set_rate_and_parent) {
1499 skip_set_rate = true;
1500 clk->ops->set_rate_and_parent(clk->hw, clk->new_rate,
1501 best_parent_rate,
1502 clk->new_parent_index);
1503 } else if (clk->ops->set_parent) {
1504 clk->ops->set_parent(clk->hw, clk->new_parent_index);
1505 }
1506
1507 __clk_set_parent_after(clk, clk->new_parent, old_parent);
1508 }
1509
1510 if (!skip_set_rate && clk->ops->set_rate)
1390 clk->ops->set_rate(clk->hw, clk->new_rate, best_parent_rate); 1511 clk->ops->set_rate(clk->hw, clk->new_rate, best_parent_rate);
1391 1512
1392 if (clk->ops->recalc_rate) 1513 if (clk->ops->recalc_rate)
@@ -1551,6 +1672,7 @@ void __clk_reparent(struct clk *clk, struct clk *new_parent)
1551{ 1672{
1552 clk_reparent(clk, new_parent); 1673 clk_reparent(clk, new_parent);
1553 clk_debug_reparent(clk, new_parent); 1674 clk_debug_reparent(clk, new_parent);
1675 __clk_recalc_accuracies(clk);
1554 __clk_recalc_rates(clk, POST_RATE_CHANGE); 1676 __clk_recalc_rates(clk, POST_RATE_CHANGE);
1555} 1677}
1556 1678
@@ -1621,11 +1743,13 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
1621 /* do the re-parent */ 1743 /* do the re-parent */
1622 ret = __clk_set_parent(clk, parent, p_index); 1744 ret = __clk_set_parent(clk, parent, p_index);
1623 1745
1624 /* propagate rate recalculation accordingly */ 1746 /* propagate rate an accuracy recalculation accordingly */
1625 if (ret) 1747 if (ret) {
1626 __clk_recalc_rates(clk, ABORT_RATE_CHANGE); 1748 __clk_recalc_rates(clk, ABORT_RATE_CHANGE);
1627 else 1749 } else {
1628 __clk_recalc_rates(clk, POST_RATE_CHANGE); 1750 __clk_recalc_rates(clk, POST_RATE_CHANGE);
1751 __clk_recalc_accuracies(clk);
1752 }
1629 1753
1630out: 1754out:
1631 clk_prepare_unlock(); 1755 clk_prepare_unlock();
@@ -1678,6 +1802,14 @@ int __clk_init(struct device *dev, struct clk *clk)
1678 goto out; 1802 goto out;
1679 } 1803 }
1680 1804
1805 if (clk->ops->set_rate_and_parent &&
1806 !(clk->ops->set_parent && clk->ops->set_rate)) {
1807 pr_warn("%s: %s must implement .set_parent & .set_rate\n",
1808 __func__, clk->name);
1809 ret = -EINVAL;
1810 goto out;
1811 }
1812
1681 /* throw a WARN if any entries in parent_names are NULL */ 1813 /* throw a WARN if any entries in parent_names are NULL */
1682 for (i = 0; i < clk->num_parents; i++) 1814 for (i = 0; i < clk->num_parents; i++)
1683 WARN(!clk->parent_names[i], 1815 WARN(!clk->parent_names[i],
@@ -1730,6 +1862,21 @@ int __clk_init(struct device *dev, struct clk *clk)
1730 hlist_add_head(&clk->child_node, &clk_orphan_list); 1862 hlist_add_head(&clk->child_node, &clk_orphan_list);
1731 1863
1732 /* 1864 /*
1865 * Set clk's accuracy. The preferred method is to use
1866 * .recalc_accuracy. For simple clocks and lazy developers the default
1867 * fallback is to use the parent's accuracy. If a clock doesn't have a
1868 * parent (or is orphaned) then accuracy is set to zero (perfect
1869 * clock).
1870 */
1871 if (clk->ops->recalc_accuracy)
1872 clk->accuracy = clk->ops->recalc_accuracy(clk->hw,
1873 __clk_get_accuracy(clk->parent));
1874 else if (clk->parent)
1875 clk->accuracy = clk->parent->accuracy;
1876 else
1877 clk->accuracy = 0;
1878
1879 /*
1733 * Set clk's rate. The preferred method is to use .recalc_rate. For 1880 * Set clk's rate. The preferred method is to use .recalc_rate. For
1734 * simple clocks and lazy developers the default fallback is to use the 1881 * simple clocks and lazy developers the default fallback is to use the
1735 * parent's rate. If a clock doesn't have a parent (or is orphaned) 1882 * parent's rate. If a clock doesn't have a parent (or is orphaned)
@@ -1743,6 +1890,7 @@ int __clk_init(struct device *dev, struct clk *clk)
1743 else 1890 else
1744 clk->rate = 0; 1891 clk->rate = 0;
1745 1892
1893 clk_debug_register(clk);
1746 /* 1894 /*
1747 * walk the list of orphan clocks and reparent any that are children of 1895 * walk the list of orphan clocks and reparent any that are children of
1748 * this clock 1896 * this clock
@@ -1773,8 +1921,7 @@ int __clk_init(struct device *dev, struct clk *clk)
1773 if (clk->ops->init) 1921 if (clk->ops->init)
1774 clk->ops->init(clk->hw); 1922 clk->ops->init(clk->hw);
1775 1923
1776 clk_debug_register(clk); 1924 kref_init(&clk->ref);
1777
1778out: 1925out:
1779 clk_prepare_unlock(); 1926 clk_prepare_unlock();
1780 1927
@@ -1810,6 +1957,10 @@ struct clk *__clk_register(struct device *dev, struct clk_hw *hw)
1810 clk->flags = hw->init->flags; 1957 clk->flags = hw->init->flags;
1811 clk->parent_names = hw->init->parent_names; 1958 clk->parent_names = hw->init->parent_names;
1812 clk->num_parents = hw->init->num_parents; 1959 clk->num_parents = hw->init->num_parents;
1960 if (dev && dev->driver)
1961 clk->owner = dev->driver->owner;
1962 else
1963 clk->owner = NULL;
1813 1964
1814 ret = __clk_init(dev, clk); 1965 ret = __clk_init(dev, clk);
1815 if (ret) 1966 if (ret)
@@ -1830,6 +1981,8 @@ static int _clk_register(struct device *dev, struct clk_hw *hw, struct clk *clk)
1830 goto fail_name; 1981 goto fail_name;
1831 } 1982 }
1832 clk->ops = hw->init->ops; 1983 clk->ops = hw->init->ops;
1984 if (dev && dev->driver)
1985 clk->owner = dev->driver->owner;
1833 clk->hw = hw; 1986 clk->hw = hw;
1834 clk->flags = hw->init->flags; 1987 clk->flags = hw->init->flags;
1835 clk->num_parents = hw->init->num_parents; 1988 clk->num_parents = hw->init->num_parents;
@@ -1904,13 +2057,104 @@ fail_out:
1904} 2057}
1905EXPORT_SYMBOL_GPL(clk_register); 2058EXPORT_SYMBOL_GPL(clk_register);
1906 2059
2060/*
2061 * Free memory allocated for a clock.
2062 * Caller must hold prepare_lock.
2063 */
2064static void __clk_release(struct kref *ref)
2065{
2066 struct clk *clk = container_of(ref, struct clk, ref);
2067 int i = clk->num_parents;
2068
2069 kfree(clk->parents);
2070 while (--i >= 0)
2071 kfree(clk->parent_names[i]);
2072
2073 kfree(clk->parent_names);
2074 kfree(clk->name);
2075 kfree(clk);
2076}
2077
2078/*
2079 * Empty clk_ops for unregistered clocks. These are used temporarily
2080 * after clk_unregister() was called on a clock and until last clock
2081 * consumer calls clk_put() and the struct clk object is freed.
2082 */
2083static int clk_nodrv_prepare_enable(struct clk_hw *hw)
2084{
2085 return -ENXIO;
2086}
2087
2088static void clk_nodrv_disable_unprepare(struct clk_hw *hw)
2089{
2090 WARN_ON_ONCE(1);
2091}
2092
2093static int clk_nodrv_set_rate(struct clk_hw *hw, unsigned long rate,
2094 unsigned long parent_rate)
2095{
2096 return -ENXIO;
2097}
2098
2099static int clk_nodrv_set_parent(struct clk_hw *hw, u8 index)
2100{
2101 return -ENXIO;
2102}
2103
2104static const struct clk_ops clk_nodrv_ops = {
2105 .enable = clk_nodrv_prepare_enable,
2106 .disable = clk_nodrv_disable_unprepare,
2107 .prepare = clk_nodrv_prepare_enable,
2108 .unprepare = clk_nodrv_disable_unprepare,
2109 .set_rate = clk_nodrv_set_rate,
2110 .set_parent = clk_nodrv_set_parent,
2111};
2112
1907/** 2113/**
1908 * clk_unregister - unregister a currently registered clock 2114 * clk_unregister - unregister a currently registered clock
1909 * @clk: clock to unregister 2115 * @clk: clock to unregister
1910 *
1911 * Currently unimplemented.
1912 */ 2116 */
1913void clk_unregister(struct clk *clk) {} 2117void clk_unregister(struct clk *clk)
2118{
2119 unsigned long flags;
2120
2121 if (!clk || WARN_ON_ONCE(IS_ERR(clk)))
2122 return;
2123
2124 clk_prepare_lock();
2125
2126 if (clk->ops == &clk_nodrv_ops) {
2127 pr_err("%s: unregistered clock: %s\n", __func__, clk->name);
2128 goto out;
2129 }
2130 /*
2131 * Assign empty clock ops for consumers that might still hold
2132 * a reference to this clock.
2133 */
2134 flags = clk_enable_lock();
2135 clk->ops = &clk_nodrv_ops;
2136 clk_enable_unlock(flags);
2137
2138 if (!hlist_empty(&clk->children)) {
2139 struct clk *child;
2140
2141 /* Reparent all children to the orphan list. */
2142 hlist_for_each_entry(child, &clk->children, child_node)
2143 clk_set_parent(child, NULL);
2144 }
2145
2146 clk_debug_unregister(clk);
2147
2148 hlist_del_init(&clk->child_node);
2149
2150 if (clk->prepare_count)
2151 pr_warn("%s: unregistering prepared clock: %s\n",
2152 __func__, clk->name);
2153
2154 kref_put(&clk->ref, __clk_release);
2155out:
2156 clk_prepare_unlock();
2157}
1914EXPORT_SYMBOL_GPL(clk_unregister); 2158EXPORT_SYMBOL_GPL(clk_unregister);
1915 2159
1916static void devm_clk_release(struct device *dev, void *res) 2160static void devm_clk_release(struct device *dev, void *res)
@@ -1970,6 +2214,31 @@ void devm_clk_unregister(struct device *dev, struct clk *clk)
1970} 2214}
1971EXPORT_SYMBOL_GPL(devm_clk_unregister); 2215EXPORT_SYMBOL_GPL(devm_clk_unregister);
1972 2216
2217/*
2218 * clkdev helpers
2219 */
2220int __clk_get(struct clk *clk)
2221{
2222 if (clk && !try_module_get(clk->owner))
2223 return 0;
2224
2225 kref_get(&clk->ref);
2226 return 1;
2227}
2228
2229void __clk_put(struct clk *clk)
2230{
2231 if (WARN_ON_ONCE(IS_ERR(clk)))
2232 return;
2233
2234 clk_prepare_lock();
2235 kref_put(&clk->ref, __clk_release);
2236 clk_prepare_unlock();
2237
2238 if (clk)
2239 module_put(clk->owner);
2240}
2241
1973/*** clk rate change notifiers ***/ 2242/*** clk rate change notifiers ***/
1974 2243
1975/** 2244/**
@@ -2110,7 +2379,18 @@ static const struct of_device_id __clk_of_table_sentinel
2110 __used __section(__clk_of_table_end); 2379 __used __section(__clk_of_table_end);
2111 2380
2112static LIST_HEAD(of_clk_providers); 2381static LIST_HEAD(of_clk_providers);
2113static DEFINE_MUTEX(of_clk_lock); 2382static DEFINE_MUTEX(of_clk_mutex);
2383
2384/* of_clk_provider list locking helpers */
2385void of_clk_lock(void)
2386{
2387 mutex_lock(&of_clk_mutex);
2388}
2389
2390void of_clk_unlock(void)
2391{
2392 mutex_unlock(&of_clk_mutex);
2393}
2114 2394
2115struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, 2395struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
2116 void *data) 2396 void *data)
@@ -2154,9 +2434,9 @@ int of_clk_add_provider(struct device_node *np,
2154 cp->data = data; 2434 cp->data = data;
2155 cp->get = clk_src_get; 2435 cp->get = clk_src_get;
2156 2436
2157 mutex_lock(&of_clk_lock); 2437 mutex_lock(&of_clk_mutex);
2158 list_add(&cp->link, &of_clk_providers); 2438 list_add(&cp->link, &of_clk_providers);
2159 mutex_unlock(&of_clk_lock); 2439 mutex_unlock(&of_clk_mutex);
2160 pr_debug("Added clock from %s\n", np->full_name); 2440 pr_debug("Added clock from %s\n", np->full_name);
2161 2441
2162 return 0; 2442 return 0;
@@ -2171,7 +2451,7 @@ void of_clk_del_provider(struct device_node *np)
2171{ 2451{
2172 struct of_clk_provider *cp; 2452 struct of_clk_provider *cp;
2173 2453
2174 mutex_lock(&of_clk_lock); 2454 mutex_lock(&of_clk_mutex);
2175 list_for_each_entry(cp, &of_clk_providers, link) { 2455 list_for_each_entry(cp, &of_clk_providers, link) {
2176 if (cp->node == np) { 2456 if (cp->node == np) {
2177 list_del(&cp->link); 2457 list_del(&cp->link);
@@ -2180,24 +2460,33 @@ void of_clk_del_provider(struct device_node *np)
2180 break; 2460 break;
2181 } 2461 }
2182 } 2462 }
2183 mutex_unlock(&of_clk_lock); 2463 mutex_unlock(&of_clk_mutex);
2184} 2464}
2185EXPORT_SYMBOL_GPL(of_clk_del_provider); 2465EXPORT_SYMBOL_GPL(of_clk_del_provider);
2186 2466
2187struct clk *of_clk_get_from_provider(struct of_phandle_args *clkspec) 2467struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec)
2188{ 2468{
2189 struct of_clk_provider *provider; 2469 struct of_clk_provider *provider;
2190 struct clk *clk = ERR_PTR(-ENOENT); 2470 struct clk *clk = ERR_PTR(-ENOENT);
2191 2471
2192 /* Check if we have such a provider in our array */ 2472 /* Check if we have such a provider in our array */
2193 mutex_lock(&of_clk_lock);
2194 list_for_each_entry(provider, &of_clk_providers, link) { 2473 list_for_each_entry(provider, &of_clk_providers, link) {
2195 if (provider->node == clkspec->np) 2474 if (provider->node == clkspec->np)
2196 clk = provider->get(clkspec, provider->data); 2475 clk = provider->get(clkspec, provider->data);
2197 if (!IS_ERR(clk)) 2476 if (!IS_ERR(clk))
2198 break; 2477 break;
2199 } 2478 }
2200 mutex_unlock(&of_clk_lock); 2479
2480 return clk;
2481}
2482
2483struct clk *of_clk_get_from_provider(struct of_phandle_args *clkspec)
2484{
2485 struct clk *clk;
2486
2487 mutex_lock(&of_clk_mutex);
2488 clk = __of_clk_get_from_provider(clkspec);
2489 mutex_unlock(&of_clk_mutex);
2201 2490
2202 return clk; 2491 return clk;
2203} 2492}
diff --git a/drivers/clk/clk.h b/drivers/clk/clk.h
new file mode 100644
index 000000000000..795cc9f0dac0
--- /dev/null
+++ b/drivers/clk/clk.h
@@ -0,0 +1,16 @@
1/*
2 * linux/drivers/clk/clk.h
3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * Sylwester Nawrocki <s.nawrocki@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK)
13struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec);
14void of_clk_lock(void);
15void of_clk_unlock(void);
16#endif
diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
index 442a31363873..48f67218247c 100644
--- a/drivers/clk/clkdev.c
+++ b/drivers/clk/clkdev.c
@@ -21,6 +21,8 @@
21#include <linux/clkdev.h> 21#include <linux/clkdev.h>
22#include <linux/of.h> 22#include <linux/of.h>
23 23
24#include "clk.h"
25
24static LIST_HEAD(clocks); 26static LIST_HEAD(clocks);
25static DEFINE_MUTEX(clocks_mutex); 27static DEFINE_MUTEX(clocks_mutex);
26 28
@@ -39,7 +41,13 @@ struct clk *of_clk_get(struct device_node *np, int index)
39 if (rc) 41 if (rc)
40 return ERR_PTR(rc); 42 return ERR_PTR(rc);
41 43
42 clk = of_clk_get_from_provider(&clkspec); 44 of_clk_lock();
45 clk = __of_clk_get_from_provider(&clkspec);
46
47 if (!IS_ERR(clk) && !__clk_get(clk))
48 clk = ERR_PTR(-ENOENT);
49
50 of_clk_unlock();
43 of_node_put(clkspec.np); 51 of_node_put(clkspec.np);
44 return clk; 52 return clk;
45} 53}
@@ -157,7 +165,7 @@ struct clk *clk_get(struct device *dev, const char *con_id)
157 165
158 if (dev) { 166 if (dev) {
159 clk = of_clk_get_by_name(dev->of_node, con_id); 167 clk = of_clk_get_by_name(dev->of_node, con_id);
160 if (!IS_ERR(clk) && __clk_get(clk)) 168 if (!IS_ERR(clk))
161 return clk; 169 return clk;
162 } 170 }
163 171
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
new file mode 100644
index 000000000000..a049108341fc
--- /dev/null
+++ b/drivers/clk/hisilicon/Makefile
@@ -0,0 +1,5 @@
1#
2# Hisilicon Clock specific Makefile
3#
4
5obj-y += clk.o clkgate-separated.o clk-hi3620.o
diff --git a/drivers/clk/hisilicon/clk-hi3620.c b/drivers/clk/hisilicon/clk-hi3620.c
new file mode 100644
index 000000000000..f24ad6a3a797
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi3620.c
@@ -0,0 +1,242 @@
1/*
2 * Hisilicon Hi3620 clock driver
3 *
4 * Copyright (c) 2012-2013 Hisilicon Limited.
5 * Copyright (c) 2012-2013 Linaro Limited.
6 *
7 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
8 * Xin Li <li.xin@linaro.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
23 *
24 */
25
26#include <linux/kernel.h>
27#include <linux/clk-provider.h>
28#include <linux/clkdev.h>
29#include <linux/io.h>
30#include <linux/of.h>
31#include <linux/of_address.h>
32#include <linux/of_device.h>
33#include <linux/slab.h>
34#include <linux/clk.h>
35
36#include <dt-bindings/clock/hi3620-clock.h>
37
38#include "clk.h"
39
40/* clock parent list */
41static const char *timer0_mux_p[] __initdata = { "osc32k", "timerclk01", };
42static const char *timer1_mux_p[] __initdata = { "osc32k", "timerclk01", };
43static const char *timer2_mux_p[] __initdata = { "osc32k", "timerclk23", };
44static const char *timer3_mux_p[] __initdata = { "osc32k", "timerclk23", };
45static const char *timer4_mux_p[] __initdata = { "osc32k", "timerclk45", };
46static const char *timer5_mux_p[] __initdata = { "osc32k", "timerclk45", };
47static const char *timer6_mux_p[] __initdata = { "osc32k", "timerclk67", };
48static const char *timer7_mux_p[] __initdata = { "osc32k", "timerclk67", };
49static const char *timer8_mux_p[] __initdata = { "osc32k", "timerclk89", };
50static const char *timer9_mux_p[] __initdata = { "osc32k", "timerclk89", };
51static const char *uart0_mux_p[] __initdata = { "osc26m", "pclk", };
52static const char *uart1_mux_p[] __initdata = { "osc26m", "pclk", };
53static const char *uart2_mux_p[] __initdata = { "osc26m", "pclk", };
54static const char *uart3_mux_p[] __initdata = { "osc26m", "pclk", };
55static const char *uart4_mux_p[] __initdata = { "osc26m", "pclk", };
56static const char *spi0_mux_p[] __initdata = { "osc26m", "rclk_cfgaxi", };
57static const char *spi1_mux_p[] __initdata = { "osc26m", "rclk_cfgaxi", };
58static const char *spi2_mux_p[] __initdata = { "osc26m", "rclk_cfgaxi", };
59/* share axi parent */
60static const char *saxi_mux_p[] __initdata = { "armpll3", "armpll2", };
61static const char *pwm0_mux_p[] __initdata = { "osc32k", "osc26m", };
62static const char *pwm1_mux_p[] __initdata = { "osc32k", "osc26m", };
63static const char *sd_mux_p[] __initdata = { "armpll2", "armpll3", };
64static const char *mmc1_mux_p[] __initdata = { "armpll2", "armpll3", };
65static const char *mmc1_mux2_p[] __initdata = { "osc26m", "mmc1_div", };
66static const char *g2d_mux_p[] __initdata = { "armpll2", "armpll3", };
67static const char *venc_mux_p[] __initdata = { "armpll2", "armpll3", };
68static const char *vdec_mux_p[] __initdata = { "armpll2", "armpll3", };
69static const char *vpp_mux_p[] __initdata = { "armpll2", "armpll3", };
70static const char *edc0_mux_p[] __initdata = { "armpll2", "armpll3", };
71static const char *ldi0_mux_p[] __initdata = { "armpll2", "armpll4",
72 "armpll3", "armpll5", };
73static const char *edc1_mux_p[] __initdata = { "armpll2", "armpll3", };
74static const char *ldi1_mux_p[] __initdata = { "armpll2", "armpll4",
75 "armpll3", "armpll5", };
76static const char *rclk_hsic_p[] __initdata = { "armpll3", "armpll2", };
77static const char *mmc2_mux_p[] __initdata = { "armpll2", "armpll3", };
78static const char *mmc3_mux_p[] __initdata = { "armpll2", "armpll3", };
79
80
81/* fixed rate clocks */
82static struct hisi_fixed_rate_clock hi3620_fixed_rate_clks[] __initdata = {
83 { HI3620_OSC32K, "osc32k", NULL, CLK_IS_ROOT, 32768, },
84 { HI3620_OSC26M, "osc26m", NULL, CLK_IS_ROOT, 26000000, },
85 { HI3620_PCLK, "pclk", NULL, CLK_IS_ROOT, 26000000, },
86 { HI3620_PLL_ARM0, "armpll0", NULL, CLK_IS_ROOT, 1600000000, },
87 { HI3620_PLL_ARM1, "armpll1", NULL, CLK_IS_ROOT, 1600000000, },
88 { HI3620_PLL_PERI, "armpll2", NULL, CLK_IS_ROOT, 1440000000, },
89 { HI3620_PLL_USB, "armpll3", NULL, CLK_IS_ROOT, 1440000000, },
90 { HI3620_PLL_HDMI, "armpll4", NULL, CLK_IS_ROOT, 1188000000, },
91 { HI3620_PLL_GPU, "armpll5", NULL, CLK_IS_ROOT, 1300000000, },
92};
93
94/* fixed factor clocks */
95static struct hisi_fixed_factor_clock hi3620_fixed_factor_clks[] __initdata = {
96 { HI3620_RCLK_TCXO, "rclk_tcxo", "osc26m", 1, 4, 0, },
97 { HI3620_RCLK_CFGAXI, "rclk_cfgaxi", "armpll2", 1, 30, 0, },
98 { HI3620_RCLK_PICO, "rclk_pico", "hsic_div", 1, 40, 0, },
99};
100
101static struct hisi_mux_clock hi3620_mux_clks[] __initdata = {
102 { HI3620_TIMER0_MUX, "timer0_mux", timer0_mux_p, ARRAY_SIZE(timer0_mux_p), CLK_SET_RATE_PARENT, 0, 15, 2, 0, },
103 { HI3620_TIMER1_MUX, "timer1_mux", timer1_mux_p, ARRAY_SIZE(timer1_mux_p), CLK_SET_RATE_PARENT, 0, 17, 2, 0, },
104 { HI3620_TIMER2_MUX, "timer2_mux", timer2_mux_p, ARRAY_SIZE(timer2_mux_p), CLK_SET_RATE_PARENT, 0, 19, 2, 0, },
105 { HI3620_TIMER3_MUX, "timer3_mux", timer3_mux_p, ARRAY_SIZE(timer3_mux_p), CLK_SET_RATE_PARENT, 0, 21, 2, 0, },
106 { HI3620_TIMER4_MUX, "timer4_mux", timer4_mux_p, ARRAY_SIZE(timer4_mux_p), CLK_SET_RATE_PARENT, 0x18, 0, 2, 0, },
107 { HI3620_TIMER5_MUX, "timer5_mux", timer5_mux_p, ARRAY_SIZE(timer5_mux_p), CLK_SET_RATE_PARENT, 0x18, 2, 2, 0, },
108 { HI3620_TIMER6_MUX, "timer6_mux", timer6_mux_p, ARRAY_SIZE(timer6_mux_p), CLK_SET_RATE_PARENT, 0x18, 4, 2, 0, },
109 { HI3620_TIMER7_MUX, "timer7_mux", timer7_mux_p, ARRAY_SIZE(timer7_mux_p), CLK_SET_RATE_PARENT, 0x18, 6, 2, 0, },
110 { HI3620_TIMER8_MUX, "timer8_mux", timer8_mux_p, ARRAY_SIZE(timer8_mux_p), CLK_SET_RATE_PARENT, 0x18, 8, 2, 0, },
111 { HI3620_TIMER9_MUX, "timer9_mux", timer9_mux_p, ARRAY_SIZE(timer9_mux_p), CLK_SET_RATE_PARENT, 0x18, 10, 2, 0, },
112 { HI3620_UART0_MUX, "uart0_mux", uart0_mux_p, ARRAY_SIZE(uart0_mux_p), CLK_SET_RATE_PARENT, 0x100, 7, 1, CLK_MUX_HIWORD_MASK, },
113 { HI3620_UART1_MUX, "uart1_mux", uart1_mux_p, ARRAY_SIZE(uart1_mux_p), CLK_SET_RATE_PARENT, 0x100, 8, 1, CLK_MUX_HIWORD_MASK, },
114 { HI3620_UART2_MUX, "uart2_mux", uart2_mux_p, ARRAY_SIZE(uart2_mux_p), CLK_SET_RATE_PARENT, 0x100, 9, 1, CLK_MUX_HIWORD_MASK, },
115 { HI3620_UART3_MUX, "uart3_mux", uart3_mux_p, ARRAY_SIZE(uart3_mux_p), CLK_SET_RATE_PARENT, 0x100, 10, 1, CLK_MUX_HIWORD_MASK, },
116 { HI3620_UART4_MUX, "uart4_mux", uart4_mux_p, ARRAY_SIZE(uart4_mux_p), CLK_SET_RATE_PARENT, 0x100, 11, 1, CLK_MUX_HIWORD_MASK, },
117 { HI3620_SPI0_MUX, "spi0_mux", spi0_mux_p, ARRAY_SIZE(spi0_mux_p), CLK_SET_RATE_PARENT, 0x100, 12, 1, CLK_MUX_HIWORD_MASK, },
118 { HI3620_SPI1_MUX, "spi1_mux", spi1_mux_p, ARRAY_SIZE(spi1_mux_p), CLK_SET_RATE_PARENT, 0x100, 13, 1, CLK_MUX_HIWORD_MASK, },
119 { HI3620_SPI2_MUX, "spi2_mux", spi2_mux_p, ARRAY_SIZE(spi2_mux_p), CLK_SET_RATE_PARENT, 0x100, 14, 1, CLK_MUX_HIWORD_MASK, },
120 { HI3620_SAXI_MUX, "saxi_mux", saxi_mux_p, ARRAY_SIZE(saxi_mux_p), CLK_SET_RATE_PARENT, 0x100, 15, 1, CLK_MUX_HIWORD_MASK, },
121 { HI3620_PWM0_MUX, "pwm0_mux", pwm0_mux_p, ARRAY_SIZE(pwm0_mux_p), CLK_SET_RATE_PARENT, 0x104, 10, 1, CLK_MUX_HIWORD_MASK, },
122 { HI3620_PWM1_MUX, "pwm1_mux", pwm1_mux_p, ARRAY_SIZE(pwm1_mux_p), CLK_SET_RATE_PARENT, 0x104, 11, 1, CLK_MUX_HIWORD_MASK, },
123 { HI3620_SD_MUX, "sd_mux", sd_mux_p, ARRAY_SIZE(sd_mux_p), CLK_SET_RATE_PARENT, 0x108, 4, 1, CLK_MUX_HIWORD_MASK, },
124 { HI3620_MMC1_MUX, "mmc1_mux", mmc1_mux_p, ARRAY_SIZE(mmc1_mux_p), CLK_SET_RATE_PARENT, 0x108, 9, 1, CLK_MUX_HIWORD_MASK, },
125 { HI3620_MMC1_MUX2, "mmc1_mux2", mmc1_mux2_p, ARRAY_SIZE(mmc1_mux2_p), CLK_SET_RATE_PARENT, 0x108, 10, 1, CLK_MUX_HIWORD_MASK, },
126 { HI3620_G2D_MUX, "g2d_mux", g2d_mux_p, ARRAY_SIZE(g2d_mux_p), CLK_SET_RATE_PARENT, 0x10c, 5, 1, CLK_MUX_HIWORD_MASK, },
127 { HI3620_VENC_MUX, "venc_mux", venc_mux_p, ARRAY_SIZE(venc_mux_p), CLK_SET_RATE_PARENT, 0x10c, 11, 1, CLK_MUX_HIWORD_MASK, },
128 { HI3620_VDEC_MUX, "vdec_mux", vdec_mux_p, ARRAY_SIZE(vdec_mux_p), CLK_SET_RATE_PARENT, 0x110, 5, 1, CLK_MUX_HIWORD_MASK, },
129 { HI3620_VPP_MUX, "vpp_mux", vpp_mux_p, ARRAY_SIZE(vpp_mux_p), CLK_SET_RATE_PARENT, 0x110, 11, 1, CLK_MUX_HIWORD_MASK, },
130 { HI3620_EDC0_MUX, "edc0_mux", edc0_mux_p, ARRAY_SIZE(edc0_mux_p), CLK_SET_RATE_PARENT, 0x114, 6, 1, CLK_MUX_HIWORD_MASK, },
131 { HI3620_LDI0_MUX, "ldi0_mux", ldi0_mux_p, ARRAY_SIZE(ldi0_mux_p), CLK_SET_RATE_PARENT, 0x114, 13, 2, CLK_MUX_HIWORD_MASK, },
132 { HI3620_EDC1_MUX, "edc1_mux", edc1_mux_p, ARRAY_SIZE(edc1_mux_p), CLK_SET_RATE_PARENT, 0x118, 6, 1, CLK_MUX_HIWORD_MASK, },
133 { HI3620_LDI1_MUX, "ldi1_mux", ldi1_mux_p, ARRAY_SIZE(ldi1_mux_p), CLK_SET_RATE_PARENT, 0x118, 14, 2, CLK_MUX_HIWORD_MASK, },
134 { HI3620_RCLK_HSIC, "rclk_hsic", rclk_hsic_p, ARRAY_SIZE(rclk_hsic_p), CLK_SET_RATE_PARENT, 0x130, 2, 1, CLK_MUX_HIWORD_MASK, },
135 { HI3620_MMC2_MUX, "mmc2_mux", mmc2_mux_p, ARRAY_SIZE(mmc2_mux_p), CLK_SET_RATE_PARENT, 0x140, 4, 1, CLK_MUX_HIWORD_MASK, },
136 { HI3620_MMC3_MUX, "mmc3_mux", mmc3_mux_p, ARRAY_SIZE(mmc3_mux_p), CLK_SET_RATE_PARENT, 0x140, 9, 1, CLK_MUX_HIWORD_MASK, },
137};
138
139static struct hisi_divider_clock hi3620_div_clks[] __initdata = {
140 { HI3620_SHAREAXI_DIV, "saxi_div", "saxi_mux", 0, 0x100, 0, 5, CLK_DIVIDER_HIWORD_MASK, NULL, },
141 { HI3620_CFGAXI_DIV, "cfgaxi_div", "saxi_div", 0, 0x100, 5, 2, CLK_DIVIDER_HIWORD_MASK, NULL, },
142 { HI3620_SD_DIV, "sd_div", "sd_mux", 0, 0x108, 0, 4, CLK_DIVIDER_HIWORD_MASK, NULL, },
143 { HI3620_MMC1_DIV, "mmc1_div", "mmc1_mux", 0, 0x108, 5, 4, CLK_DIVIDER_HIWORD_MASK, NULL, },
144 { HI3620_HSIC_DIV, "hsic_div", "rclk_hsic", 0, 0x130, 0, 2, CLK_DIVIDER_HIWORD_MASK, NULL, },
145 { HI3620_MMC2_DIV, "mmc2_div", "mmc2_mux", 0, 0x140, 0, 4, CLK_DIVIDER_HIWORD_MASK, NULL, },
146 { HI3620_MMC3_DIV, "mmc3_div", "mmc3_mux", 0, 0x140, 5, 4, CLK_DIVIDER_HIWORD_MASK, NULL, },
147};
148
149static struct hisi_gate_clock hi3620_seperated_gate_clks[] __initdata = {
150 { HI3620_TIMERCLK01, "timerclk01", "timer_rclk01", CLK_SET_RATE_PARENT, 0x20, 0, 0, },
151 { HI3620_TIMER_RCLK01, "timer_rclk01", "rclk_tcxo", CLK_SET_RATE_PARENT, 0x20, 1, 0, },
152 { HI3620_TIMERCLK23, "timerclk23", "timer_rclk23", CLK_SET_RATE_PARENT, 0x20, 2, 0, },
153 { HI3620_TIMER_RCLK23, "timer_rclk23", "rclk_tcxo", CLK_SET_RATE_PARENT, 0x20, 3, 0, },
154 { HI3620_RTCCLK, "rtcclk", "pclk", CLK_SET_RATE_PARENT, 0x20, 5, 0, },
155 { HI3620_KPC_CLK, "kpc_clk", "pclk", CLK_SET_RATE_PARENT, 0x20, 6, 0, },
156 { HI3620_GPIOCLK0, "gpioclk0", "pclk", CLK_SET_RATE_PARENT, 0x20, 8, 0, },
157 { HI3620_GPIOCLK1, "gpioclk1", "pclk", CLK_SET_RATE_PARENT, 0x20, 9, 0, },
158 { HI3620_GPIOCLK2, "gpioclk2", "pclk", CLK_SET_RATE_PARENT, 0x20, 10, 0, },
159 { HI3620_GPIOCLK3, "gpioclk3", "pclk", CLK_SET_RATE_PARENT, 0x20, 11, 0, },
160 { HI3620_GPIOCLK4, "gpioclk4", "pclk", CLK_SET_RATE_PARENT, 0x20, 12, 0, },
161 { HI3620_GPIOCLK5, "gpioclk5", "pclk", CLK_SET_RATE_PARENT, 0x20, 13, 0, },
162 { HI3620_GPIOCLK6, "gpioclk6", "pclk", CLK_SET_RATE_PARENT, 0x20, 14, 0, },
163 { HI3620_GPIOCLK7, "gpioclk7", "pclk", CLK_SET_RATE_PARENT, 0x20, 15, 0, },
164 { HI3620_GPIOCLK8, "gpioclk8", "pclk", CLK_SET_RATE_PARENT, 0x20, 16, 0, },
165 { HI3620_GPIOCLK9, "gpioclk9", "pclk", CLK_SET_RATE_PARENT, 0x20, 17, 0, },
166 { HI3620_GPIOCLK10, "gpioclk10", "pclk", CLK_SET_RATE_PARENT, 0x20, 18, 0, },
167 { HI3620_GPIOCLK11, "gpioclk11", "pclk", CLK_SET_RATE_PARENT, 0x20, 19, 0, },
168 { HI3620_GPIOCLK12, "gpioclk12", "pclk", CLK_SET_RATE_PARENT, 0x20, 20, 0, },
169 { HI3620_GPIOCLK13, "gpioclk13", "pclk", CLK_SET_RATE_PARENT, 0x20, 21, 0, },
170 { HI3620_GPIOCLK14, "gpioclk14", "pclk", CLK_SET_RATE_PARENT, 0x20, 22, 0, },
171 { HI3620_GPIOCLK15, "gpioclk15", "pclk", CLK_SET_RATE_PARENT, 0x20, 23, 0, },
172 { HI3620_GPIOCLK16, "gpioclk16", "pclk", CLK_SET_RATE_PARENT, 0x20, 24, 0, },
173 { HI3620_GPIOCLK17, "gpioclk17", "pclk", CLK_SET_RATE_PARENT, 0x20, 25, 0, },
174 { HI3620_GPIOCLK18, "gpioclk18", "pclk", CLK_SET_RATE_PARENT, 0x20, 26, 0, },
175 { HI3620_GPIOCLK19, "gpioclk19", "pclk", CLK_SET_RATE_PARENT, 0x20, 27, 0, },
176 { HI3620_GPIOCLK20, "gpioclk20", "pclk", CLK_SET_RATE_PARENT, 0x20, 28, 0, },
177 { HI3620_GPIOCLK21, "gpioclk21", "pclk", CLK_SET_RATE_PARENT, 0x20, 29, 0, },
178 { HI3620_DPHY0_CLK, "dphy0_clk", "osc26m", CLK_SET_RATE_PARENT, 0x30, 15, 0, },
179 { HI3620_DPHY1_CLK, "dphy1_clk", "osc26m", CLK_SET_RATE_PARENT, 0x30, 16, 0, },
180 { HI3620_DPHY2_CLK, "dphy2_clk", "osc26m", CLK_SET_RATE_PARENT, 0x30, 17, 0, },
181 { HI3620_USBPHY_CLK, "usbphy_clk", "rclk_pico", CLK_SET_RATE_PARENT, 0x30, 24, 0, },
182 { HI3620_ACP_CLK, "acp_clk", "rclk_cfgaxi", CLK_SET_RATE_PARENT, 0x30, 28, 0, },
183 { HI3620_TIMERCLK45, "timerclk45", "rclk_tcxo", CLK_SET_RATE_PARENT, 0x40, 3, 0, },
184 { HI3620_TIMERCLK67, "timerclk67", "rclk_tcxo", CLK_SET_RATE_PARENT, 0x40, 4, 0, },
185 { HI3620_TIMERCLK89, "timerclk89", "rclk_tcxo", CLK_SET_RATE_PARENT, 0x40, 5, 0, },
186 { HI3620_PWMCLK0, "pwmclk0", "pwm0_mux", CLK_SET_RATE_PARENT, 0x40, 7, 0, },
187 { HI3620_PWMCLK1, "pwmclk1", "pwm1_mux", CLK_SET_RATE_PARENT, 0x40, 8, 0, },
188 { HI3620_UARTCLK0, "uartclk0", "uart0_mux", CLK_SET_RATE_PARENT, 0x40, 16, 0, },
189 { HI3620_UARTCLK1, "uartclk1", "uart1_mux", CLK_SET_RATE_PARENT, 0x40, 17, 0, },
190 { HI3620_UARTCLK2, "uartclk2", "uart2_mux", CLK_SET_RATE_PARENT, 0x40, 18, 0, },
191 { HI3620_UARTCLK3, "uartclk3", "uart3_mux", CLK_SET_RATE_PARENT, 0x40, 19, 0, },
192 { HI3620_UARTCLK4, "uartclk4", "uart4_mux", CLK_SET_RATE_PARENT, 0x40, 20, 0, },
193 { HI3620_SPICLK0, "spiclk0", "spi0_mux", CLK_SET_RATE_PARENT, 0x40, 21, 0, },
194 { HI3620_SPICLK1, "spiclk1", "spi1_mux", CLK_SET_RATE_PARENT, 0x40, 22, 0, },
195 { HI3620_SPICLK2, "spiclk2", "spi2_mux", CLK_SET_RATE_PARENT, 0x40, 23, 0, },
196 { HI3620_I2CCLK0, "i2cclk0", "pclk", CLK_SET_RATE_PARENT, 0x40, 24, 0, },
197 { HI3620_I2CCLK1, "i2cclk1", "pclk", CLK_SET_RATE_PARENT, 0x40, 25, 0, },
198 { HI3620_SCI_CLK, "sci_clk", "osc26m", CLK_SET_RATE_PARENT, 0x40, 26, 0, },
199 { HI3620_I2CCLK2, "i2cclk2", "pclk", CLK_SET_RATE_PARENT, 0x40, 28, 0, },
200 { HI3620_I2CCLK3, "i2cclk3", "pclk", CLK_SET_RATE_PARENT, 0x40, 29, 0, },
201 { HI3620_DDRC_PER_CLK, "ddrc_per_clk", "rclk_cfgaxi", CLK_SET_RATE_PARENT, 0x50, 9, 0, },
202 { HI3620_DMAC_CLK, "dmac_clk", "rclk_cfgaxi", CLK_SET_RATE_PARENT, 0x50, 10, 0, },
203 { HI3620_USB2DVC_CLK, "usb2dvc_clk", "rclk_cfgaxi", CLK_SET_RATE_PARENT, 0x50, 17, 0, },
204 { HI3620_SD_CLK, "sd_clk", "sd_div", CLK_SET_RATE_PARENT, 0x50, 20, 0, },
205 { HI3620_MMC_CLK1, "mmc_clk1", "mmc1_mux2", CLK_SET_RATE_PARENT, 0x50, 21, 0, },
206 { HI3620_MMC_CLK2, "mmc_clk2", "mmc2_div", CLK_SET_RATE_PARENT, 0x50, 22, 0, },
207 { HI3620_MMC_CLK3, "mmc_clk3", "mmc3_div", CLK_SET_RATE_PARENT, 0x50, 23, 0, },
208 { HI3620_MCU_CLK, "mcu_clk", "acp_clk", CLK_SET_RATE_PARENT, 0x50, 24, 0, },
209};
210
211static void __init hi3620_clk_init(struct device_node *np)
212{
213 void __iomem *base;
214
215 if (np) {
216 base = of_iomap(np, 0);
217 if (!base) {
218 pr_err("failed to map Hi3620 clock registers\n");
219 return;
220 }
221 } else {
222 pr_err("failed to find Hi3620 clock node in DTS\n");
223 return;
224 }
225
226 hisi_clk_init(np, HI3620_NR_CLKS);
227
228 hisi_clk_register_fixed_rate(hi3620_fixed_rate_clks,
229 ARRAY_SIZE(hi3620_fixed_rate_clks),
230 base);
231 hisi_clk_register_fixed_factor(hi3620_fixed_factor_clks,
232 ARRAY_SIZE(hi3620_fixed_factor_clks),
233 base);
234 hisi_clk_register_mux(hi3620_mux_clks, ARRAY_SIZE(hi3620_mux_clks),
235 base);
236 hisi_clk_register_divider(hi3620_div_clks, ARRAY_SIZE(hi3620_div_clks),
237 base);
238 hisi_clk_register_gate_sep(hi3620_seperated_gate_clks,
239 ARRAY_SIZE(hi3620_seperated_gate_clks),
240 base);
241}
242CLK_OF_DECLARE(hi3620_clk, "hisilicon,hi3620-clock", hi3620_clk_init);
diff --git a/drivers/clk/hisilicon/clk.c b/drivers/clk/hisilicon/clk.c
new file mode 100644
index 000000000000..a3a7152c92d9
--- /dev/null
+++ b/drivers/clk/hisilicon/clk.c
@@ -0,0 +1,171 @@
1/*
2 * Hisilicon clock driver
3 *
4 * Copyright (c) 2012-2013 Hisilicon Limited.
5 * Copyright (c) 2012-2013 Linaro Limited.
6 *
7 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
8 * Xin Li <li.xin@linaro.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
23 *
24 */
25
26#include <linux/kernel.h>
27#include <linux/clk-provider.h>
28#include <linux/clkdev.h>
29#include <linux/delay.h>
30#include <linux/io.h>
31#include <linux/of.h>
32#include <linux/of_address.h>
33#include <linux/of_device.h>
34#include <linux/slab.h>
35#include <linux/clk.h>
36
37#include "clk.h"
38
39static DEFINE_SPINLOCK(hisi_clk_lock);
40static struct clk **clk_table;
41static struct clk_onecell_data clk_data;
42
43void __init hisi_clk_init(struct device_node *np, int nr_clks)
44{
45 clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL);
46 if (!clk_table) {
47 pr_err("%s: could not allocate clock lookup table\n", __func__);
48 return;
49 }
50 clk_data.clks = clk_table;
51 clk_data.clk_num = nr_clks;
52 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
53}
54
55void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *clks,
56 int nums, void __iomem *base)
57{
58 struct clk *clk;
59 int i;
60
61 for (i = 0; i < nums; i++) {
62 clk = clk_register_fixed_rate(NULL, clks[i].name,
63 clks[i].parent_name,
64 clks[i].flags,
65 clks[i].fixed_rate);
66 if (IS_ERR(clk)) {
67 pr_err("%s: failed to register clock %s\n",
68 __func__, clks[i].name);
69 continue;
70 }
71 }
72}
73
74void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *clks,
75 int nums, void __iomem *base)
76{
77 struct clk *clk;
78 int i;
79
80 for (i = 0; i < nums; i++) {
81 clk = clk_register_fixed_factor(NULL, clks[i].name,
82 clks[i].parent_name,
83 clks[i].flags, clks[i].mult,
84 clks[i].div);
85 if (IS_ERR(clk)) {
86 pr_err("%s: failed to register clock %s\n",
87 __func__, clks[i].name);
88 continue;
89 }
90 }
91}
92
93void __init hisi_clk_register_mux(struct hisi_mux_clock *clks,
94 int nums, void __iomem *base)
95{
96 struct clk *clk;
97 int i;
98
99 for (i = 0; i < nums; i++) {
100 clk = clk_register_mux(NULL, clks[i].name, clks[i].parent_names,
101 clks[i].num_parents, clks[i].flags,
102 base + clks[i].offset, clks[i].shift,
103 clks[i].width, clks[i].mux_flags,
104 &hisi_clk_lock);
105 if (IS_ERR(clk)) {
106 pr_err("%s: failed to register clock %s\n",
107 __func__, clks[i].name);
108 continue;
109 }
110
111 if (clks[i].alias)
112 clk_register_clkdev(clk, clks[i].alias, NULL);
113
114 clk_table[clks[i].id] = clk;
115 }
116}
117
118void __init hisi_clk_register_divider(struct hisi_divider_clock *clks,
119 int nums, void __iomem *base)
120{
121 struct clk *clk;
122 int i;
123
124 for (i = 0; i < nums; i++) {
125 clk = clk_register_divider_table(NULL, clks[i].name,
126 clks[i].parent_name,
127 clks[i].flags,
128 base + clks[i].offset,
129 clks[i].shift, clks[i].width,
130 clks[i].div_flags,
131 clks[i].table,
132 &hisi_clk_lock);
133 if (IS_ERR(clk)) {
134 pr_err("%s: failed to register clock %s\n",
135 __func__, clks[i].name);
136 continue;
137 }
138
139 if (clks[i].alias)
140 clk_register_clkdev(clk, clks[i].alias, NULL);
141
142 clk_table[clks[i].id] = clk;
143 }
144}
145
146void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *clks,
147 int nums, void __iomem *base)
148{
149 struct clk *clk;
150 int i;
151
152 for (i = 0; i < nums; i++) {
153 clk = hisi_register_clkgate_sep(NULL, clks[i].name,
154 clks[i].parent_name,
155 clks[i].flags,
156 base + clks[i].offset,
157 clks[i].bit_idx,
158 clks[i].gate_flags,
159 &hisi_clk_lock);
160 if (IS_ERR(clk)) {
161 pr_err("%s: failed to register clock %s\n",
162 __func__, clks[i].name);
163 continue;
164 }
165
166 if (clks[i].alias)
167 clk_register_clkdev(clk, clks[i].alias, NULL);
168
169 clk_table[clks[i].id] = clk;
170 }
171}
diff --git a/drivers/clk/hisilicon/clk.h b/drivers/clk/hisilicon/clk.h
new file mode 100644
index 000000000000..4a6beebefb7a
--- /dev/null
+++ b/drivers/clk/hisilicon/clk.h
@@ -0,0 +1,103 @@
1/*
2 * Hisilicon Hi3620 clock gate driver
3 *
4 * Copyright (c) 2012-2013 Hisilicon Limited.
5 * Copyright (c) 2012-2013 Linaro Limited.
6 *
7 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
8 * Xin Li <li.xin@linaro.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
23 *
24 */
25
26#ifndef __HISI_CLK_H
27#define __HISI_CLK_H
28
29#include <linux/clk-provider.h>
30#include <linux/io.h>
31#include <linux/spinlock.h>
32
33struct hisi_fixed_rate_clock {
34 unsigned int id;
35 char *name;
36 const char *parent_name;
37 unsigned long flags;
38 unsigned long fixed_rate;
39};
40
41struct hisi_fixed_factor_clock {
42 unsigned int id;
43 char *name;
44 const char *parent_name;
45 unsigned long mult;
46 unsigned long div;
47 unsigned long flags;
48};
49
50struct hisi_mux_clock {
51 unsigned int id;
52 const char *name;
53 const char **parent_names;
54 u8 num_parents;
55 unsigned long flags;
56 unsigned long offset;
57 u8 shift;
58 u8 width;
59 u8 mux_flags;
60 const char *alias;
61};
62
63struct hisi_divider_clock {
64 unsigned int id;
65 const char *name;
66 const char *parent_name;
67 unsigned long flags;
68 unsigned long offset;
69 u8 shift;
70 u8 width;
71 u8 div_flags;
72 struct clk_div_table *table;
73 const char *alias;
74};
75
76struct hisi_gate_clock {
77 unsigned int id;
78 const char *name;
79 const char *parent_name;
80 unsigned long flags;
81 unsigned long offset;
82 u8 bit_idx;
83 u8 gate_flags;
84 const char *alias;
85};
86
87struct clk *hisi_register_clkgate_sep(struct device *, const char *,
88 const char *, unsigned long,
89 void __iomem *, u8,
90 u8, spinlock_t *);
91
92void __init hisi_clk_init(struct device_node *, int);
93void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *,
94 int, void __iomem *);
95void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *,
96 int, void __iomem *);
97void __init hisi_clk_register_mux(struct hisi_mux_clock *, int,
98 void __iomem *);
99void __init hisi_clk_register_divider(struct hisi_divider_clock *,
100 int, void __iomem *);
101void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *,
102 int, void __iomem *);
103#endif /* __HISI_CLK_H */
diff --git a/drivers/clk/hisilicon/clkgate-separated.c b/drivers/clk/hisilicon/clkgate-separated.c
new file mode 100644
index 000000000000..b03d5a7246f9
--- /dev/null
+++ b/drivers/clk/hisilicon/clkgate-separated.c
@@ -0,0 +1,130 @@
1/*
2 * Hisilicon clock separated gate driver
3 *
4 * Copyright (c) 2012-2013 Hisilicon Limited.
5 * Copyright (c) 2012-2013 Linaro Limited.
6 *
7 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
8 * Xin Li <li.xin@linaro.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
23 *
24 */
25
26#include <linux/kernel.h>
27#include <linux/clk-provider.h>
28#include <linux/clkdev.h>
29#include <linux/io.h>
30#include <linux/slab.h>
31#include <linux/clk.h>
32
33#include "clk.h"
34
35/* clock separated gate register offset */
36#define CLKGATE_SEPERATED_ENABLE 0x0
37#define CLKGATE_SEPERATED_DISABLE 0x4
38#define CLKGATE_SEPERATED_STATUS 0x8
39
40struct clkgate_separated {
41 struct clk_hw hw;
42 void __iomem *enable; /* enable register */
43 u8 bit_idx; /* bits in enable/disable register */
44 u8 flags;
45 spinlock_t *lock;
46};
47
48static int clkgate_separated_enable(struct clk_hw *hw)
49{
50 struct clkgate_separated *sclk;
51 unsigned long flags = 0;
52 u32 reg;
53
54 sclk = container_of(hw, struct clkgate_separated, hw);
55 if (sclk->lock)
56 spin_lock_irqsave(sclk->lock, flags);
57 reg = BIT(sclk->bit_idx);
58 writel_relaxed(reg, sclk->enable);
59 readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS);
60 if (sclk->lock)
61 spin_unlock_irqrestore(sclk->lock, flags);
62 return 0;
63}
64
65static void clkgate_separated_disable(struct clk_hw *hw)
66{
67 struct clkgate_separated *sclk;
68 unsigned long flags = 0;
69 u32 reg;
70
71 sclk = container_of(hw, struct clkgate_separated, hw);
72 if (sclk->lock)
73 spin_lock_irqsave(sclk->lock, flags);
74 reg = BIT(sclk->bit_idx);
75 writel_relaxed(reg, sclk->enable + CLKGATE_SEPERATED_DISABLE);
76 readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS);
77 if (sclk->lock)
78 spin_unlock_irqrestore(sclk->lock, flags);
79}
80
81static int clkgate_separated_is_enabled(struct clk_hw *hw)
82{
83 struct clkgate_separated *sclk;
84 u32 reg;
85
86 sclk = container_of(hw, struct clkgate_separated, hw);
87 reg = readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS);
88 reg &= BIT(sclk->bit_idx);
89
90 return reg ? 1 : 0;
91}
92
93static struct clk_ops clkgate_separated_ops = {
94 .enable = clkgate_separated_enable,
95 .disable = clkgate_separated_disable,
96 .is_enabled = clkgate_separated_is_enabled,
97};
98
99struct clk *hisi_register_clkgate_sep(struct device *dev, const char *name,
100 const char *parent_name,
101 unsigned long flags,
102 void __iomem *reg, u8 bit_idx,
103 u8 clk_gate_flags, spinlock_t *lock)
104{
105 struct clkgate_separated *sclk;
106 struct clk *clk;
107 struct clk_init_data init;
108
109 sclk = kzalloc(sizeof(*sclk), GFP_KERNEL);
110 if (!sclk) {
111 pr_err("%s: fail to allocate separated gated clk\n", __func__);
112 return ERR_PTR(-ENOMEM);
113 }
114
115 init.name = name;
116 init.ops = &clkgate_separated_ops;
117 init.flags = flags | CLK_IS_BASIC;
118 init.parent_names = (parent_name ? &parent_name : NULL);
119 init.num_parents = (parent_name ? 1 : 0);
120
121 sclk->enable = reg + CLKGATE_SEPERATED_ENABLE;
122 sclk->bit_idx = bit_idx;
123 sclk->flags = clk_gate_flags;
124 sclk->hw.init = &init;
125
126 clk = clk_register(dev, &sclk->hw);
127 if (IS_ERR(clk))
128 kfree(sclk);
129 return clk;
130}
diff --git a/drivers/clk/keystone/gate.c b/drivers/clk/keystone/gate.c
index 1f333bcfc22e..17a598398a53 100644
--- a/drivers/clk/keystone/gate.c
+++ b/drivers/clk/keystone/gate.c
@@ -223,8 +223,7 @@ static void __init of_psc_clk_init(struct device_node *node, spinlock_t *lock)
223 data->domain_base = of_iomap(node, i); 223 data->domain_base = of_iomap(node, i);
224 if (!data->domain_base) { 224 if (!data->domain_base) {
225 pr_err("%s: domain ioremap failed\n", __func__); 225 pr_err("%s: domain ioremap failed\n", __func__);
226 iounmap(data->control_base); 226 goto unmap_ctrl;
227 goto out;
228 } 227 }
229 228
230 of_property_read_u32(node, "domain-id", &data->domain_id); 229 of_property_read_u32(node, "domain-id", &data->domain_id);
@@ -237,16 +236,21 @@ static void __init of_psc_clk_init(struct device_node *node, spinlock_t *lock)
237 parent_name = of_clk_get_parent_name(node, 0); 236 parent_name = of_clk_get_parent_name(node, 0);
238 if (!parent_name) { 237 if (!parent_name) {
239 pr_err("%s: Parent clock not found\n", __func__); 238 pr_err("%s: Parent clock not found\n", __func__);
240 goto out; 239 goto unmap_domain;
241 } 240 }
242 241
243 clk = clk_register_psc(NULL, clk_name, parent_name, data, lock); 242 clk = clk_register_psc(NULL, clk_name, parent_name, data, lock);
244 if (clk) { 243 if (!IS_ERR(clk)) {
245 of_clk_add_provider(node, of_clk_src_simple_get, clk); 244 of_clk_add_provider(node, of_clk_src_simple_get, clk);
246 return; 245 return;
247 } 246 }
248 247
249 pr_err("%s: error registering clk %s\n", __func__, node->name); 248 pr_err("%s: error registering clk %s\n", __func__, node->name);
249
250unmap_domain:
251 iounmap(data->domain_base);
252unmap_ctrl:
253 iounmap(data->control_base);
250out: 254out:
251 kfree(data); 255 kfree(data);
252 return; 256 return;
diff --git a/drivers/clk/keystone/pll.c b/drivers/clk/keystone/pll.c
index 47a1bd9f1726..0dd8a4b12747 100644
--- a/drivers/clk/keystone/pll.c
+++ b/drivers/clk/keystone/pll.c
@@ -24,6 +24,8 @@
24#define MAIN_PLLM_HIGH_MASK 0x7f000 24#define MAIN_PLLM_HIGH_MASK 0x7f000
25#define PLLM_HIGH_SHIFT 6 25#define PLLM_HIGH_SHIFT 6
26#define PLLD_MASK 0x3f 26#define PLLD_MASK 0x3f
27#define CLKOD_MASK 0x780000
28#define CLKOD_SHIFT 19
27 29
28/** 30/**
29 * struct clk_pll_data - pll data structure 31 * struct clk_pll_data - pll data structure
@@ -41,7 +43,10 @@
41 * @pllm_upper_mask: multiplier upper mask 43 * @pllm_upper_mask: multiplier upper mask
42 * @pllm_upper_shift: multiplier upper shift 44 * @pllm_upper_shift: multiplier upper shift
43 * @plld_mask: divider mask 45 * @plld_mask: divider mask
44 * @postdiv: Post divider 46 * @clkod_mask: output divider mask
47 * @clkod_shift: output divider shift
48 * @plld_mask: divider mask
49 * @postdiv: Fixed post divider
45 */ 50 */
46struct clk_pll_data { 51struct clk_pll_data {
47 bool has_pllctrl; 52 bool has_pllctrl;
@@ -53,6 +58,8 @@ struct clk_pll_data {
53 u32 pllm_upper_mask; 58 u32 pllm_upper_mask;
54 u32 pllm_upper_shift; 59 u32 pllm_upper_shift;
55 u32 plld_mask; 60 u32 plld_mask;
61 u32 clkod_mask;
62 u32 clkod_shift;
56 u32 postdiv; 63 u32 postdiv;
57}; 64};
58 65
@@ -90,7 +97,13 @@ static unsigned long clk_pllclk_recalc(struct clk_hw *hw,
90 mult |= ((val & pll_data->pllm_upper_mask) 97 mult |= ((val & pll_data->pllm_upper_mask)
91 >> pll_data->pllm_upper_shift); 98 >> pll_data->pllm_upper_shift);
92 prediv = (val & pll_data->plld_mask); 99 prediv = (val & pll_data->plld_mask);
93 postdiv = pll_data->postdiv; 100
101 if (!pll_data->has_pllctrl)
102 /* read post divider from od bits*/
103 postdiv = ((val & pll_data->clkod_mask) >>
104 pll_data->clkod_shift) + 1;
105 else
106 postdiv = pll_data->postdiv;
94 107
95 rate /= (prediv + 1); 108 rate /= (prediv + 1);
96 rate = (rate * (mult + 1)); 109 rate = (rate * (mult + 1));
@@ -155,8 +168,11 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl)
155 } 168 }
156 169
157 parent_name = of_clk_get_parent_name(node, 0); 170 parent_name = of_clk_get_parent_name(node, 0);
158 if (of_property_read_u32(node, "fixed-postdiv", &pll_data->postdiv)) 171 if (of_property_read_u32(node, "fixed-postdiv", &pll_data->postdiv)) {
159 goto out; 172 /* assume the PLL has output divider register bits */
173 pll_data->clkod_mask = CLKOD_MASK;
174 pll_data->clkod_shift = CLKOD_SHIFT;
175 }
160 176
161 i = of_property_match_string(node, "reg-names", "control"); 177 i = of_property_match_string(node, "reg-names", "control");
162 pll_data->pll_ctl0 = of_iomap(node, i); 178 pll_data->pll_ctl0 = of_iomap(node, i);
diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index 0b0f3e729cf7..c339b829d3e3 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -4,15 +4,20 @@ config MVEBU_CLK_COMMON
4config MVEBU_CLK_CPU 4config MVEBU_CLK_CPU
5 bool 5 bool
6 6
7config MVEBU_CLK_COREDIV
8 bool
9
7config ARMADA_370_CLK 10config ARMADA_370_CLK
8 bool 11 bool
9 select MVEBU_CLK_COMMON 12 select MVEBU_CLK_COMMON
10 select MVEBU_CLK_CPU 13 select MVEBU_CLK_CPU
14 select MVEBU_CLK_COREDIV
11 15
12config ARMADA_XP_CLK 16config ARMADA_XP_CLK
13 bool 17 bool
14 select MVEBU_CLK_COMMON 18 select MVEBU_CLK_COMMON
15 select MVEBU_CLK_CPU 19 select MVEBU_CLK_CPU
20 select MVEBU_CLK_COREDIV
16 21
17config DOVE_CLK 22config DOVE_CLK
18 bool 23 bool
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index 1c7e70c63fb2..21bbfb4a9f42 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -1,5 +1,6 @@
1obj-$(CONFIG_MVEBU_CLK_COMMON) += common.o 1obj-$(CONFIG_MVEBU_CLK_COMMON) += common.o
2obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o 2obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o
3obj-$(CONFIG_MVEBU_CLK_COREDIV) += clk-corediv.o
3 4
4obj-$(CONFIG_ARMADA_370_CLK) += armada-370.o 5obj-$(CONFIG_ARMADA_370_CLK) += armada-370.o
5obj-$(CONFIG_ARMADA_XP_CLK) += armada-xp.o 6obj-$(CONFIG_ARMADA_XP_CLK) += armada-xp.o
diff --git a/drivers/clk/mvebu/clk-corediv.c b/drivers/clk/mvebu/clk-corediv.c
new file mode 100644
index 000000000000..7162615bcdcd
--- /dev/null
+++ b/drivers/clk/mvebu/clk-corediv.c
@@ -0,0 +1,223 @@
1/*
2 * MVEBU Core divider clock
3 *
4 * Copyright (C) 2013 Marvell
5 *
6 * Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/kernel.h>
14#include <linux/clk-provider.h>
15#include <linux/of_address.h>
16#include <linux/slab.h>
17#include <linux/delay.h>
18#include "common.h"
19
20#define CORE_CLK_DIV_RATIO_MASK 0xff
21#define CORE_CLK_DIV_RATIO_RELOAD BIT(8)
22#define CORE_CLK_DIV_ENABLE_OFFSET 24
23#define CORE_CLK_DIV_RATIO_OFFSET 0x8
24
25struct clk_corediv_desc {
26 unsigned int mask;
27 unsigned int offset;
28 unsigned int fieldbit;
29};
30
31struct clk_corediv {
32 struct clk_hw hw;
33 void __iomem *reg;
34 struct clk_corediv_desc desc;
35 spinlock_t lock;
36};
37
38static struct clk_onecell_data clk_data;
39
40static const struct clk_corediv_desc mvebu_corediv_desc[] __initconst = {
41 { .mask = 0x3f, .offset = 8, .fieldbit = 1 }, /* NAND clock */
42};
43
44#define to_corediv_clk(p) container_of(p, struct clk_corediv, hw)
45
46static int clk_corediv_is_enabled(struct clk_hw *hwclk)
47{
48 struct clk_corediv *corediv = to_corediv_clk(hwclk);
49 struct clk_corediv_desc *desc = &corediv->desc;
50 u32 enable_mask = BIT(desc->fieldbit) << CORE_CLK_DIV_ENABLE_OFFSET;
51
52 return !!(readl(corediv->reg) & enable_mask);
53}
54
55static int clk_corediv_enable(struct clk_hw *hwclk)
56{
57 struct clk_corediv *corediv = to_corediv_clk(hwclk);
58 struct clk_corediv_desc *desc = &corediv->desc;
59 unsigned long flags = 0;
60 u32 reg;
61
62 spin_lock_irqsave(&corediv->lock, flags);
63
64 reg = readl(corediv->reg);
65 reg |= (BIT(desc->fieldbit) << CORE_CLK_DIV_ENABLE_OFFSET);
66 writel(reg, corediv->reg);
67
68 spin_unlock_irqrestore(&corediv->lock, flags);
69
70 return 0;
71}
72
73static void clk_corediv_disable(struct clk_hw *hwclk)
74{
75 struct clk_corediv *corediv = to_corediv_clk(hwclk);
76 struct clk_corediv_desc *desc = &corediv->desc;
77 unsigned long flags = 0;
78 u32 reg;
79
80 spin_lock_irqsave(&corediv->lock, flags);
81
82 reg = readl(corediv->reg);
83 reg &= ~(BIT(desc->fieldbit) << CORE_CLK_DIV_ENABLE_OFFSET);
84 writel(reg, corediv->reg);
85
86 spin_unlock_irqrestore(&corediv->lock, flags);
87}
88
89static unsigned long clk_corediv_recalc_rate(struct clk_hw *hwclk,
90 unsigned long parent_rate)
91{
92 struct clk_corediv *corediv = to_corediv_clk(hwclk);
93 struct clk_corediv_desc *desc = &corediv->desc;
94 u32 reg, div;
95
96 reg = readl(corediv->reg + CORE_CLK_DIV_RATIO_OFFSET);
97 div = (reg >> desc->offset) & desc->mask;
98 return parent_rate / div;
99}
100
101static long clk_corediv_round_rate(struct clk_hw *hwclk, unsigned long rate,
102 unsigned long *parent_rate)
103{
104 /* Valid ratio are 1:4, 1:5, 1:6 and 1:8 */
105 u32 div;
106
107 div = *parent_rate / rate;
108 if (div < 4)
109 div = 4;
110 else if (div > 6)
111 div = 8;
112
113 return *parent_rate / div;
114}
115
116static int clk_corediv_set_rate(struct clk_hw *hwclk, unsigned long rate,
117 unsigned long parent_rate)
118{
119 struct clk_corediv *corediv = to_corediv_clk(hwclk);
120 struct clk_corediv_desc *desc = &corediv->desc;
121 unsigned long flags = 0;
122 u32 reg, div;
123
124 div = parent_rate / rate;
125
126 spin_lock_irqsave(&corediv->lock, flags);
127
128 /* Write new divider to the divider ratio register */
129 reg = readl(corediv->reg + CORE_CLK_DIV_RATIO_OFFSET);
130 reg &= ~(desc->mask << desc->offset);
131 reg |= (div & desc->mask) << desc->offset;
132 writel(reg, corediv->reg + CORE_CLK_DIV_RATIO_OFFSET);
133
134 /* Set reload-force for this clock */
135 reg = readl(corediv->reg) | BIT(desc->fieldbit);
136 writel(reg, corediv->reg);
137
138 /* Now trigger the clock update */
139 reg = readl(corediv->reg) | CORE_CLK_DIV_RATIO_RELOAD;
140 writel(reg, corediv->reg);
141
142 /*
143 * Wait for clocks to settle down, and then clear all the
144 * ratios request and the reload request.
145 */
146 udelay(1000);
147 reg &= ~(CORE_CLK_DIV_RATIO_MASK | CORE_CLK_DIV_RATIO_RELOAD);
148 writel(reg, corediv->reg);
149 udelay(1000);
150
151 spin_unlock_irqrestore(&corediv->lock, flags);
152
153 return 0;
154}
155
156static const struct clk_ops corediv_ops = {
157 .enable = clk_corediv_enable,
158 .disable = clk_corediv_disable,
159 .is_enabled = clk_corediv_is_enabled,
160 .recalc_rate = clk_corediv_recalc_rate,
161 .round_rate = clk_corediv_round_rate,
162 .set_rate = clk_corediv_set_rate,
163};
164
165static void __init mvebu_corediv_clk_init(struct device_node *node)
166{
167 struct clk_init_data init;
168 struct clk_corediv *corediv;
169 struct clk **clks;
170 void __iomem *base;
171 const char *parent_name;
172 const char *clk_name;
173 int i;
174
175 base = of_iomap(node, 0);
176 if (WARN_ON(!base))
177 return;
178
179 parent_name = of_clk_get_parent_name(node, 0);
180
181 clk_data.clk_num = ARRAY_SIZE(mvebu_corediv_desc);
182
183 /* clks holds the clock array */
184 clks = kcalloc(clk_data.clk_num, sizeof(struct clk *),
185 GFP_KERNEL);
186 if (WARN_ON(!clks))
187 goto err_unmap;
188 /* corediv holds the clock specific array */
189 corediv = kcalloc(clk_data.clk_num, sizeof(struct clk_corediv),
190 GFP_KERNEL);
191 if (WARN_ON(!corediv))
192 goto err_free_clks;
193
194 spin_lock_init(&corediv->lock);
195
196 for (i = 0; i < clk_data.clk_num; i++) {
197 of_property_read_string_index(node, "clock-output-names",
198 i, &clk_name);
199 init.num_parents = 1;
200 init.parent_names = &parent_name;
201 init.name = clk_name;
202 init.ops = &corediv_ops;
203 init.flags = 0;
204
205 corediv[i].desc = mvebu_corediv_desc[i];
206 corediv[i].reg = base;
207 corediv[i].hw.init = &init;
208
209 clks[i] = clk_register(NULL, &corediv[i].hw);
210 WARN_ON(IS_ERR(clks[i]));
211 }
212
213 clk_data.clks = clks;
214 of_clk_add_provider(node, of_clk_src_onecell_get, &clk_data);
215 return;
216
217err_free_clks:
218 kfree(clks);
219err_unmap:
220 iounmap(base);
221}
222CLK_OF_DECLARE(mvebu_corediv_clk, "marvell,armada-370-corediv-clock",
223 mvebu_corediv_clk_init);
diff --git a/drivers/clk/mvebu/clk-cpu.c b/drivers/clk/mvebu/clk-cpu.c
index 1466865b0743..8ebf757d29e2 100644
--- a/drivers/clk/mvebu/clk-cpu.c
+++ b/drivers/clk/mvebu/clk-cpu.c
@@ -101,7 +101,7 @@ static const struct clk_ops cpu_ops = {
101 .set_rate = clk_cpu_set_rate, 101 .set_rate = clk_cpu_set_rate,
102}; 102};
103 103
104void __init of_cpu_clk_setup(struct device_node *node) 104static void __init of_cpu_clk_setup(struct device_node *node)
105{ 105{
106 struct cpu_clk *cpuclk; 106 struct cpu_clk *cpuclk;
107 void __iomem *clock_complex_base = of_iomap(node, 0); 107 void __iomem *clock_complex_base = of_iomap(node, 0);
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
new file mode 100644
index 000000000000..995bcfa021a4
--- /dev/null
+++ b/drivers/clk/qcom/Kconfig
@@ -0,0 +1,47 @@
1config COMMON_CLK_QCOM
2 tristate "Support for Qualcomm's clock controllers"
3 depends on OF
4 select REGMAP_MMIO
5 select RESET_CONTROLLER
6
7config MSM_GCC_8660
8 tristate "MSM8660 Global Clock Controller"
9 depends on COMMON_CLK_QCOM
10 help
11 Support for the global clock controller on msm8660 devices.
12 Say Y if you want to use peripheral devices such as UART, SPI,
13 i2c, USB, SD/eMMC, etc.
14
15config MSM_GCC_8960
16 tristate "MSM8960 Global Clock Controller"
17 depends on COMMON_CLK_QCOM
18 help
19 Support for the global clock controller on msm8960 devices.
20 Say Y if you want to use peripheral devices such as UART, SPI,
21 i2c, USB, SD/eMMC, SATA, PCIe, etc.
22
23config MSM_MMCC_8960
24 tristate "MSM8960 Multimedia Clock Controller"
25 select MSM_GCC_8960
26 depends on COMMON_CLK_QCOM
27 help
28 Support for the multimedia clock controller on msm8960 devices.
29 Say Y if you want to support multimedia devices such as display,
30 graphics, video encode/decode, camera, etc.
31
32config MSM_GCC_8974
33 tristate "MSM8974 Global Clock Controller"
34 depends on COMMON_CLK_QCOM
35 help
36 Support for the global clock controller on msm8974 devices.
37 Say Y if you want to use peripheral devices such as UART, SPI,
38 i2c, USB, SD/eMMC, SATA, PCIe, etc.
39
40config MSM_MMCC_8974
41 tristate "MSM8974 Multimedia Clock Controller"
42 select MSM_GCC_8974
43 depends on COMMON_CLK_QCOM
44 help
45 Support for the multimedia clock controller on msm8974 devices.
46 Say Y if you want to support multimedia devices such as display,
47 graphics, video encode/decode, camera, etc.
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
new file mode 100644
index 000000000000..190d38433202
--- /dev/null
+++ b/drivers/clk/qcom/Makefile
@@ -0,0 +1,14 @@
1obj-$(CONFIG_COMMON_CLK_QCOM) += clk-qcom.o
2
3clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-regmap.o
4clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-pll.o
5clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-rcg.o
6clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-rcg2.o
7clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-branch.o
8clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += reset.o
9
10obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o
11obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o
12obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
13obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
14obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c
new file mode 100644
index 000000000000..6b4d2bcb1a53
--- /dev/null
+++ b/drivers/clk/qcom/clk-branch.c
@@ -0,0 +1,159 @@
1/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/bitops.h>
16#include <linux/err.h>
17#include <linux/delay.h>
18#include <linux/export.h>
19#include <linux/clk-provider.h>
20#include <linux/regmap.h>
21
22#include "clk-branch.h"
23
24static bool clk_branch_in_hwcg_mode(const struct clk_branch *br)
25{
26 u32 val;
27
28 if (!br->hwcg_reg)
29 return 0;
30
31 regmap_read(br->clkr.regmap, br->hwcg_reg, &val);
32
33 return !!(val & BIT(br->hwcg_bit));
34}
35
36static bool clk_branch_check_halt(const struct clk_branch *br, bool enabling)
37{
38 bool invert = (br->halt_check == BRANCH_HALT_ENABLE);
39 u32 val;
40
41 regmap_read(br->clkr.regmap, br->halt_reg, &val);
42
43 val &= BIT(br->halt_bit);
44 if (invert)
45 val = !val;
46
47 return !!val == !enabling;
48}
49
50#define BRANCH_CLK_OFF BIT(31)
51#define BRANCH_NOC_FSM_STATUS_SHIFT 28
52#define BRANCH_NOC_FSM_STATUS_MASK 0x7
53#define BRANCH_NOC_FSM_STATUS_ON (0x2 << BRANCH_NOC_FSM_STATUS_SHIFT)
54
55static bool clk_branch2_check_halt(const struct clk_branch *br, bool enabling)
56{
57 u32 val;
58 u32 mask;
59
60 mask = BRANCH_NOC_FSM_STATUS_MASK << BRANCH_NOC_FSM_STATUS_SHIFT;
61 mask |= BRANCH_CLK_OFF;
62
63 regmap_read(br->clkr.regmap, br->halt_reg, &val);
64
65 if (enabling) {
66 val &= mask;
67 return (val & BRANCH_CLK_OFF) == 0 ||
68 val == BRANCH_NOC_FSM_STATUS_ON;
69 } else {
70 return val & BRANCH_CLK_OFF;
71 }
72}
73
74static int clk_branch_wait(const struct clk_branch *br, bool enabling,
75 bool (check_halt)(const struct clk_branch *, bool))
76{
77 bool voted = br->halt_check & BRANCH_VOTED;
78 const char *name = __clk_get_name(br->clkr.hw.clk);
79
80 /* Skip checking halt bit if the clock is in hardware gated mode */
81 if (clk_branch_in_hwcg_mode(br))
82 return 0;
83
84 if (br->halt_check == BRANCH_HALT_DELAY || (!enabling && voted)) {
85 udelay(10);
86 } else if (br->halt_check == BRANCH_HALT_ENABLE ||
87 br->halt_check == BRANCH_HALT ||
88 (enabling && voted)) {
89 int count = 200;
90
91 while (count-- > 0) {
92 if (check_halt(br, enabling))
93 return 0;
94 udelay(1);
95 }
96 WARN(1, "%s status stuck at 'o%s'", name,
97 enabling ? "ff" : "n");
98 return -EBUSY;
99 }
100 return 0;
101}
102
103static int clk_branch_toggle(struct clk_hw *hw, bool en,
104 bool (check_halt)(const struct clk_branch *, bool))
105{
106 struct clk_branch *br = to_clk_branch(hw);
107 int ret;
108
109 if (en) {
110 ret = clk_enable_regmap(hw);
111 if (ret)
112 return ret;
113 } else {
114 clk_disable_regmap(hw);
115 }
116
117 return clk_branch_wait(br, en, check_halt);
118}
119
120static int clk_branch_enable(struct clk_hw *hw)
121{
122 return clk_branch_toggle(hw, true, clk_branch_check_halt);
123}
124
125static void clk_branch_disable(struct clk_hw *hw)
126{
127 clk_branch_toggle(hw, false, clk_branch_check_halt);
128}
129
130const struct clk_ops clk_branch_ops = {
131 .enable = clk_branch_enable,
132 .disable = clk_branch_disable,
133 .is_enabled = clk_is_enabled_regmap,
134};
135EXPORT_SYMBOL_GPL(clk_branch_ops);
136
137static int clk_branch2_enable(struct clk_hw *hw)
138{
139 return clk_branch_toggle(hw, true, clk_branch2_check_halt);
140}
141
142static void clk_branch2_disable(struct clk_hw *hw)
143{
144 clk_branch_toggle(hw, false, clk_branch2_check_halt);
145}
146
147const struct clk_ops clk_branch2_ops = {
148 .enable = clk_branch2_enable,
149 .disable = clk_branch2_disable,
150 .is_enabled = clk_is_enabled_regmap,
151};
152EXPORT_SYMBOL_GPL(clk_branch2_ops);
153
154const struct clk_ops clk_branch_simple_ops = {
155 .enable = clk_enable_regmap,
156 .disable = clk_disable_regmap,
157 .is_enabled = clk_is_enabled_regmap,
158};
159EXPORT_SYMBOL_GPL(clk_branch_simple_ops);
diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h
new file mode 100644
index 000000000000..284df3f3c55f
--- /dev/null
+++ b/drivers/clk/qcom/clk-branch.h
@@ -0,0 +1,56 @@
1/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef __QCOM_CLK_BRANCH_H__
15#define __QCOM_CLK_BRANCH_H__
16
17#include <linux/clk-provider.h>
18
19#include "clk-regmap.h"
20
21/**
22 * struct clk_branch - gating clock with status bit and dynamic hardware gating
23 *
24 * @hwcg_reg: dynamic hardware clock gating register
25 * @hwcg_bit: ORed with @hwcg_reg to enable dynamic hardware clock gating
26 * @halt_reg: halt register
27 * @halt_bit: ANDed with @halt_reg to test for clock halted
28 * @halt_check: type of halt checking to perform
29 * @clkr: handle between common and hardware-specific interfaces
30 *
31 * Clock which can gate its output.
32 */
33struct clk_branch {
34 u32 hwcg_reg;
35 u32 halt_reg;
36 u8 hwcg_bit;
37 u8 halt_bit;
38 u8 halt_check;
39#define BRANCH_VOTED BIT(7) /* Delay on disable */
40#define BRANCH_HALT 0 /* pol: 1 = halt */
41#define BRANCH_HALT_VOTED (BRANCH_HALT | BRANCH_VOTED)
42#define BRANCH_HALT_ENABLE 1 /* pol: 0 = halt */
43#define BRANCH_HALT_ENABLE_VOTED (BRANCH_HALT_ENABLE | BRANCH_VOTED)
44#define BRANCH_HALT_DELAY 2 /* No bit to check; just delay */
45
46 struct clk_regmap clkr;
47};
48
49extern const struct clk_ops clk_branch_ops;
50extern const struct clk_ops clk_branch2_ops;
51extern const struct clk_ops clk_branch_simple_ops;
52
53#define to_clk_branch(_hw) \
54 container_of(to_clk_regmap(_hw), struct clk_branch, clkr)
55
56#endif
diff --git a/drivers/clk/qcom/clk-pll.c b/drivers/clk/qcom/clk-pll.c
new file mode 100644
index 000000000000..0f927c538613
--- /dev/null
+++ b/drivers/clk/qcom/clk-pll.c
@@ -0,0 +1,222 @@
1/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/bitops.h>
16#include <linux/err.h>
17#include <linux/bug.h>
18#include <linux/delay.h>
19#include <linux/export.h>
20#include <linux/clk-provider.h>
21#include <linux/regmap.h>
22
23#include <asm/div64.h>
24
25#include "clk-pll.h"
26
27#define PLL_OUTCTRL BIT(0)
28#define PLL_BYPASSNL BIT(1)
29#define PLL_RESET_N BIT(2)
30#define PLL_LOCK_COUNT_SHIFT 8
31#define PLL_LOCK_COUNT_MASK 0x3f
32#define PLL_BIAS_COUNT_SHIFT 14
33#define PLL_BIAS_COUNT_MASK 0x3f
34#define PLL_VOTE_FSM_ENA BIT(20)
35#define PLL_VOTE_FSM_RESET BIT(21)
36
37static int clk_pll_enable(struct clk_hw *hw)
38{
39 struct clk_pll *pll = to_clk_pll(hw);
40 int ret;
41 u32 mask, val;
42
43 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
44 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val);
45 if (ret)
46 return ret;
47
48 /* Skip if already enabled or in FSM mode */
49 if ((val & mask) == mask || val & PLL_VOTE_FSM_ENA)
50 return 0;
51
52 /* Disable PLL bypass mode. */
53 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL,
54 PLL_BYPASSNL);
55 if (ret)
56 return ret;
57
58 /*
59 * H/W requires a 5us delay between disabling the bypass and
60 * de-asserting the reset. Delay 10us just to be safe.
61 */
62 udelay(10);
63
64 /* De-assert active-low PLL reset. */
65 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N,
66 PLL_RESET_N);
67 if (ret)
68 return ret;
69
70 /* Wait until PLL is locked. */
71 udelay(50);
72
73 /* Enable PLL output. */
74 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL,
75 PLL_OUTCTRL);
76 if (ret)
77 return ret;
78
79 return 0;
80}
81
82static void clk_pll_disable(struct clk_hw *hw)
83{
84 struct clk_pll *pll = to_clk_pll(hw);
85 u32 mask;
86 u32 val;
87
88 regmap_read(pll->clkr.regmap, pll->mode_reg, &val);
89 /* Skip if in FSM mode */
90 if (val & PLL_VOTE_FSM_ENA)
91 return;
92 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
93 regmap_update_bits(pll->clkr.regmap, pll->mode_reg, mask, 0);
94}
95
96static unsigned long
97clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
98{
99 struct clk_pll *pll = to_clk_pll(hw);
100 u32 l, m, n;
101 unsigned long rate;
102 u64 tmp;
103
104 regmap_read(pll->clkr.regmap, pll->l_reg, &l);
105 regmap_read(pll->clkr.regmap, pll->m_reg, &m);
106 regmap_read(pll->clkr.regmap, pll->n_reg, &n);
107
108 l &= 0x3ff;
109 m &= 0x7ffff;
110 n &= 0x7ffff;
111
112 rate = parent_rate * l;
113 if (n) {
114 tmp = parent_rate;
115 tmp *= m;
116 do_div(tmp, n);
117 rate += tmp;
118 }
119 return rate;
120}
121
122const struct clk_ops clk_pll_ops = {
123 .enable = clk_pll_enable,
124 .disable = clk_pll_disable,
125 .recalc_rate = clk_pll_recalc_rate,
126};
127EXPORT_SYMBOL_GPL(clk_pll_ops);
128
129static int wait_for_pll(struct clk_pll *pll)
130{
131 u32 val;
132 int count;
133 int ret;
134 const char *name = __clk_get_name(pll->clkr.hw.clk);
135
136 /* Wait for pll to enable. */
137 for (count = 200; count > 0; count--) {
138 ret = regmap_read(pll->clkr.regmap, pll->status_reg, &val);
139 if (ret)
140 return ret;
141 if (val & BIT(pll->status_bit))
142 return 0;
143 udelay(1);
144 }
145
146 WARN(1, "%s didn't enable after voting for it!\n", name);
147 return -ETIMEDOUT;
148}
149
150static int clk_pll_vote_enable(struct clk_hw *hw)
151{
152 int ret;
153 struct clk_pll *p = to_clk_pll(__clk_get_hw(__clk_get_parent(hw->clk)));
154
155 ret = clk_enable_regmap(hw);
156 if (ret)
157 return ret;
158
159 return wait_for_pll(p);
160}
161
162const struct clk_ops clk_pll_vote_ops = {
163 .enable = clk_pll_vote_enable,
164 .disable = clk_disable_regmap,
165};
166EXPORT_SYMBOL_GPL(clk_pll_vote_ops);
167
168static void
169clk_pll_set_fsm_mode(struct clk_pll *pll, struct regmap *regmap)
170{
171 u32 val;
172 u32 mask;
173
174 /* De-assert reset to FSM */
175 regmap_update_bits(regmap, pll->mode_reg, PLL_VOTE_FSM_RESET, 0);
176
177 /* Program bias count and lock count */
178 val = 1 << PLL_BIAS_COUNT_SHIFT;
179 mask = PLL_BIAS_COUNT_MASK << PLL_BIAS_COUNT_SHIFT;
180 mask |= PLL_LOCK_COUNT_MASK << PLL_LOCK_COUNT_SHIFT;
181 regmap_update_bits(regmap, pll->mode_reg, mask, val);
182
183 /* Enable PLL FSM voting */
184 regmap_update_bits(regmap, pll->mode_reg, PLL_VOTE_FSM_ENA,
185 PLL_VOTE_FSM_ENA);
186}
187
188static void clk_pll_configure(struct clk_pll *pll, struct regmap *regmap,
189 const struct pll_config *config)
190{
191 u32 val;
192 u32 mask;
193
194 regmap_write(regmap, pll->l_reg, config->l);
195 regmap_write(regmap, pll->m_reg, config->m);
196 regmap_write(regmap, pll->n_reg, config->n);
197
198 val = config->vco_val;
199 val |= config->pre_div_val;
200 val |= config->post_div_val;
201 val |= config->mn_ena_mask;
202 val |= config->main_output_mask;
203 val |= config->aux_output_mask;
204
205 mask = config->vco_mask;
206 mask |= config->pre_div_mask;
207 mask |= config->post_div_mask;
208 mask |= config->mn_ena_mask;
209 mask |= config->main_output_mask;
210 mask |= config->aux_output_mask;
211
212 regmap_update_bits(regmap, pll->config_reg, mask, val);
213}
214
215void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
216 const struct pll_config *config, bool fsm_mode)
217{
218 clk_pll_configure(pll, regmap, config);
219 if (fsm_mode)
220 clk_pll_set_fsm_mode(pll, regmap);
221}
222EXPORT_SYMBOL_GPL(clk_pll_configure_sr_hpm_lp);
diff --git a/drivers/clk/qcom/clk-pll.h b/drivers/clk/qcom/clk-pll.h
new file mode 100644
index 000000000000..0775a99ca768
--- /dev/null
+++ b/drivers/clk/qcom/clk-pll.h
@@ -0,0 +1,66 @@
1/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef __QCOM_CLK_PLL_H__
15#define __QCOM_CLK_PLL_H__
16
17#include <linux/clk-provider.h>
18#include "clk-regmap.h"
19
20/**
21 * struct clk_pll - phase locked loop (PLL)
22 * @l_reg: L register
23 * @m_reg: M register
24 * @n_reg: N register
25 * @config_reg: config register
26 * @mode_reg: mode register
27 * @status_reg: status register
28 * @status_bit: ANDed with @status_reg to determine if PLL is enabled
29 * @hw: handle between common and hardware-specific interfaces
30 */
31struct clk_pll {
32 u32 l_reg;
33 u32 m_reg;
34 u32 n_reg;
35 u32 config_reg;
36 u32 mode_reg;
37 u32 status_reg;
38 u8 status_bit;
39
40 struct clk_regmap clkr;
41};
42
43extern const struct clk_ops clk_pll_ops;
44extern const struct clk_ops clk_pll_vote_ops;
45
46#define to_clk_pll(_hw) container_of(to_clk_regmap(_hw), struct clk_pll, clkr)
47
48struct pll_config {
49 u16 l;
50 u32 m;
51 u32 n;
52 u32 vco_val;
53 u32 vco_mask;
54 u32 pre_div_val;
55 u32 pre_div_mask;
56 u32 post_div_val;
57 u32 post_div_mask;
58 u32 mn_ena_mask;
59 u32 main_output_mask;
60 u32 aux_output_mask;
61};
62
63void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
64 const struct pll_config *config, bool fsm_mode);
65
66#endif
diff --git a/drivers/clk/qcom/clk-rcg.c b/drivers/clk/qcom/clk-rcg.c
new file mode 100644
index 000000000000..abfc2b675aea
--- /dev/null
+++ b/drivers/clk/qcom/clk-rcg.c
@@ -0,0 +1,517 @@
1/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/bitops.h>
16#include <linux/err.h>
17#include <linux/export.h>
18#include <linux/clk-provider.h>
19#include <linux/regmap.h>
20
21#include <asm/div64.h>
22
23#include "clk-rcg.h"
24
25static u32 ns_to_src(struct src_sel *s, u32 ns)
26{
27 ns >>= s->src_sel_shift;
28 ns &= SRC_SEL_MASK;
29 return ns;
30}
31
32static u32 src_to_ns(struct src_sel *s, u8 src, u32 ns)
33{
34 u32 mask;
35
36 mask = SRC_SEL_MASK;
37 mask <<= s->src_sel_shift;
38 ns &= ~mask;
39
40 ns |= src << s->src_sel_shift;
41 return ns;
42}
43
44static u8 clk_rcg_get_parent(struct clk_hw *hw)
45{
46 struct clk_rcg *rcg = to_clk_rcg(hw);
47 int num_parents = __clk_get_num_parents(hw->clk);
48 u32 ns;
49 int i;
50
51 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
52 ns = ns_to_src(&rcg->s, ns);
53 for (i = 0; i < num_parents; i++)
54 if (ns == rcg->s.parent_map[i])
55 return i;
56
57 return -EINVAL;
58}
59
60static int reg_to_bank(struct clk_dyn_rcg *rcg, u32 bank)
61{
62 bank &= BIT(rcg->mux_sel_bit);
63 return !!bank;
64}
65
66static u8 clk_dyn_rcg_get_parent(struct clk_hw *hw)
67{
68 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
69 int num_parents = __clk_get_num_parents(hw->clk);
70 u32 ns, ctl;
71 int bank;
72 int i;
73 struct src_sel *s;
74
75 regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl);
76 bank = reg_to_bank(rcg, ctl);
77 s = &rcg->s[bank];
78
79 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
80 ns = ns_to_src(s, ns);
81
82 for (i = 0; i < num_parents; i++)
83 if (ns == s->parent_map[i])
84 return i;
85
86 return -EINVAL;
87}
88
89static int clk_rcg_set_parent(struct clk_hw *hw, u8 index)
90{
91 struct clk_rcg *rcg = to_clk_rcg(hw);
92 u32 ns;
93
94 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
95 ns = src_to_ns(&rcg->s, rcg->s.parent_map[index], ns);
96 regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
97
98 return 0;
99}
100
101static u32 md_to_m(struct mn *mn, u32 md)
102{
103 md >>= mn->m_val_shift;
104 md &= BIT(mn->width) - 1;
105 return md;
106}
107
108static u32 ns_to_pre_div(struct pre_div *p, u32 ns)
109{
110 ns >>= p->pre_div_shift;
111 ns &= BIT(p->pre_div_width) - 1;
112 return ns;
113}
114
115static u32 pre_div_to_ns(struct pre_div *p, u8 pre_div, u32 ns)
116{
117 u32 mask;
118
119 mask = BIT(p->pre_div_width) - 1;
120 mask <<= p->pre_div_shift;
121 ns &= ~mask;
122
123 ns |= pre_div << p->pre_div_shift;
124 return ns;
125}
126
127static u32 mn_to_md(struct mn *mn, u32 m, u32 n, u32 md)
128{
129 u32 mask, mask_w;
130
131 mask_w = BIT(mn->width) - 1;
132 mask = (mask_w << mn->m_val_shift) | mask_w;
133 md &= ~mask;
134
135 if (n) {
136 m <<= mn->m_val_shift;
137 md |= m;
138 md |= ~n & mask_w;
139 }
140
141 return md;
142}
143
144static u32 ns_m_to_n(struct mn *mn, u32 ns, u32 m)
145{
146 ns = ~ns >> mn->n_val_shift;
147 ns &= BIT(mn->width) - 1;
148 return ns + m;
149}
150
151static u32 reg_to_mnctr_mode(struct mn *mn, u32 val)
152{
153 val >>= mn->mnctr_mode_shift;
154 val &= MNCTR_MODE_MASK;
155 return val;
156}
157
158static u32 mn_to_ns(struct mn *mn, u32 m, u32 n, u32 ns)
159{
160 u32 mask;
161
162 mask = BIT(mn->width) - 1;
163 mask <<= mn->n_val_shift;
164 ns &= ~mask;
165
166 if (n) {
167 n = n - m;
168 n = ~n;
169 n &= BIT(mn->width) - 1;
170 n <<= mn->n_val_shift;
171 ns |= n;
172 }
173
174 return ns;
175}
176
177static u32 mn_to_reg(struct mn *mn, u32 m, u32 n, u32 val)
178{
179 u32 mask;
180
181 mask = MNCTR_MODE_MASK << mn->mnctr_mode_shift;
182 mask |= BIT(mn->mnctr_en_bit);
183 val &= ~mask;
184
185 if (n) {
186 val |= BIT(mn->mnctr_en_bit);
187 val |= MNCTR_MODE_DUAL << mn->mnctr_mode_shift;
188 }
189
190 return val;
191}
192
193static void configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)
194{
195 u32 ns, md, ctl, *regp;
196 int bank, new_bank;
197 struct mn *mn;
198 struct pre_div *p;
199 struct src_sel *s;
200 bool enabled;
201 u32 md_reg;
202 u32 bank_reg;
203 bool banked_mn = !!rcg->mn[1].width;
204 struct clk_hw *hw = &rcg->clkr.hw;
205
206 enabled = __clk_is_enabled(hw->clk);
207
208 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
209 regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl);
210
211 if (banked_mn) {
212 regp = &ctl;
213 bank_reg = rcg->clkr.enable_reg;
214 } else {
215 regp = &ns;
216 bank_reg = rcg->ns_reg;
217 }
218
219 bank = reg_to_bank(rcg, *regp);
220 new_bank = enabled ? !bank : bank;
221
222 if (banked_mn) {
223 mn = &rcg->mn[new_bank];
224 md_reg = rcg->md_reg[new_bank];
225
226 ns |= BIT(mn->mnctr_reset_bit);
227 regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
228
229 regmap_read(rcg->clkr.regmap, md_reg, &md);
230 md = mn_to_md(mn, f->m, f->n, md);
231 regmap_write(rcg->clkr.regmap, md_reg, md);
232
233 ns = mn_to_ns(mn, f->m, f->n, ns);
234 regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
235
236 ctl = mn_to_reg(mn, f->m, f->n, ctl);
237 regmap_write(rcg->clkr.regmap, rcg->clkr.enable_reg, ctl);
238
239 ns &= ~BIT(mn->mnctr_reset_bit);
240 regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
241 } else {
242 p = &rcg->p[new_bank];
243 ns = pre_div_to_ns(p, f->pre_div - 1, ns);
244 }
245
246 s = &rcg->s[new_bank];
247 ns = src_to_ns(s, s->parent_map[f->src], ns);
248 regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
249
250 if (enabled) {
251 *regp ^= BIT(rcg->mux_sel_bit);
252 regmap_write(rcg->clkr.regmap, bank_reg, *regp);
253 }
254}
255
256static int clk_dyn_rcg_set_parent(struct clk_hw *hw, u8 index)
257{
258 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
259 u32 ns, ctl, md, reg;
260 int bank;
261 struct freq_tbl f = { 0 };
262 bool banked_mn = !!rcg->mn[1].width;
263
264 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
265 regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl);
266 reg = banked_mn ? ctl : ns;
267
268 bank = reg_to_bank(rcg, reg);
269
270 if (banked_mn) {
271 regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);
272 f.m = md_to_m(&rcg->mn[bank], md);
273 f.n = ns_m_to_n(&rcg->mn[bank], ns, f.m);
274 } else {
275 f.pre_div = ns_to_pre_div(&rcg->p[bank], ns) + 1;
276 }
277 f.src = index;
278
279 configure_bank(rcg, &f);
280
281 return 0;
282}
283
284/*
285 * Calculate m/n:d rate
286 *
287 * parent_rate m
288 * rate = ----------- x ---
289 * pre_div n
290 */
291static unsigned long
292calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 pre_div)
293{
294 if (pre_div)
295 rate /= pre_div + 1;
296
297 if (mode) {
298 u64 tmp = rate;
299 tmp *= m;
300 do_div(tmp, n);
301 rate = tmp;
302 }
303
304 return rate;
305}
306
307static unsigned long
308clk_rcg_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
309{
310 struct clk_rcg *rcg = to_clk_rcg(hw);
311 u32 pre_div, m = 0, n = 0, ns, md, mode = 0;
312 struct mn *mn = &rcg->mn;
313
314 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
315 pre_div = ns_to_pre_div(&rcg->p, ns);
316
317 if (rcg->mn.width) {
318 regmap_read(rcg->clkr.regmap, rcg->md_reg, &md);
319 m = md_to_m(mn, md);
320 n = ns_m_to_n(mn, ns, m);
321 /* MN counter mode is in hw.enable_reg sometimes */
322 if (rcg->clkr.enable_reg != rcg->ns_reg)
323 regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &mode);
324 else
325 mode = ns;
326 mode = reg_to_mnctr_mode(mn, mode);
327 }
328
329 return calc_rate(parent_rate, m, n, mode, pre_div);
330}
331
332static unsigned long
333clk_dyn_rcg_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
334{
335 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
336 u32 m, n, pre_div, ns, md, mode, reg;
337 int bank;
338 struct mn *mn;
339 bool banked_mn = !!rcg->mn[1].width;
340
341 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
342
343 if (banked_mn)
344 regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &reg);
345 else
346 reg = ns;
347
348 bank = reg_to_bank(rcg, reg);
349
350 if (banked_mn) {
351 mn = &rcg->mn[bank];
352 regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);
353 m = md_to_m(mn, md);
354 n = ns_m_to_n(mn, ns, m);
355 mode = reg_to_mnctr_mode(mn, reg);
356 return calc_rate(parent_rate, m, n, mode, 0);
357 } else {
358 pre_div = ns_to_pre_div(&rcg->p[bank], ns);
359 return calc_rate(parent_rate, 0, 0, 0, pre_div);
360 }
361}
362
363static const
364struct freq_tbl *find_freq(const struct freq_tbl *f, unsigned long rate)
365{
366 if (!f)
367 return NULL;
368
369 for (; f->freq; f++)
370 if (rate <= f->freq)
371 return f;
372
373 return NULL;
374}
375
376static long _freq_tbl_determine_rate(struct clk_hw *hw,
377 const struct freq_tbl *f, unsigned long rate,
378 unsigned long *p_rate, struct clk **p)
379{
380 unsigned long clk_flags;
381
382 f = find_freq(f, rate);
383 if (!f)
384 return -EINVAL;
385
386 clk_flags = __clk_get_flags(hw->clk);
387 *p = clk_get_parent_by_index(hw->clk, f->src);
388 if (clk_flags & CLK_SET_RATE_PARENT) {
389 rate = rate * f->pre_div;
390 if (f->n) {
391 u64 tmp = rate;
392 tmp = tmp * f->n;
393 do_div(tmp, f->m);
394 rate = tmp;
395 }
396 } else {
397 rate = __clk_get_rate(*p);
398 }
399 *p_rate = rate;
400
401 return f->freq;
402}
403
404static long clk_rcg_determine_rate(struct clk_hw *hw, unsigned long rate,
405 unsigned long *p_rate, struct clk **p)
406{
407 struct clk_rcg *rcg = to_clk_rcg(hw);
408
409 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, p_rate, p);
410}
411
412static long clk_dyn_rcg_determine_rate(struct clk_hw *hw, unsigned long rate,
413 unsigned long *p_rate, struct clk **p)
414{
415 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
416
417 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, p_rate, p);
418}
419
420static int clk_rcg_set_rate(struct clk_hw *hw, unsigned long rate,
421 unsigned long parent_rate)
422{
423 struct clk_rcg *rcg = to_clk_rcg(hw);
424 const struct freq_tbl *f;
425 u32 ns, md, ctl;
426 struct mn *mn = &rcg->mn;
427 u32 mask = 0;
428 unsigned int reset_reg;
429
430 f = find_freq(rcg->freq_tbl, rate);
431 if (!f)
432 return -EINVAL;
433
434 if (rcg->mn.reset_in_cc)
435 reset_reg = rcg->clkr.enable_reg;
436 else
437 reset_reg = rcg->ns_reg;
438
439 if (rcg->mn.width) {
440 mask = BIT(mn->mnctr_reset_bit);
441 regmap_update_bits(rcg->clkr.regmap, reset_reg, mask, mask);
442
443 regmap_read(rcg->clkr.regmap, rcg->md_reg, &md);
444 md = mn_to_md(mn, f->m, f->n, md);
445 regmap_write(rcg->clkr.regmap, rcg->md_reg, md);
446
447 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
448 /* MN counter mode is in hw.enable_reg sometimes */
449 if (rcg->clkr.enable_reg != rcg->ns_reg) {
450 regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl);
451 ctl = mn_to_reg(mn, f->m, f->n, ctl);
452 regmap_write(rcg->clkr.regmap, rcg->clkr.enable_reg, ctl);
453 } else {
454 ns = mn_to_reg(mn, f->m, f->n, ns);
455 }
456 ns = mn_to_ns(mn, f->m, f->n, ns);
457 } else {
458 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
459 }
460
461 ns = pre_div_to_ns(&rcg->p, f->pre_div - 1, ns);
462 regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
463
464 regmap_update_bits(rcg->clkr.regmap, reset_reg, mask, 0);
465
466 return 0;
467}
468
469static int __clk_dyn_rcg_set_rate(struct clk_hw *hw, unsigned long rate)
470{
471 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
472 const struct freq_tbl *f;
473
474 f = find_freq(rcg->freq_tbl, rate);
475 if (!f)
476 return -EINVAL;
477
478 configure_bank(rcg, f);
479
480 return 0;
481}
482
483static int clk_dyn_rcg_set_rate(struct clk_hw *hw, unsigned long rate,
484 unsigned long parent_rate)
485{
486 return __clk_dyn_rcg_set_rate(hw, rate);
487}
488
489static int clk_dyn_rcg_set_rate_and_parent(struct clk_hw *hw,
490 unsigned long rate, unsigned long parent_rate, u8 index)
491{
492 return __clk_dyn_rcg_set_rate(hw, rate);
493}
494
495const struct clk_ops clk_rcg_ops = {
496 .enable = clk_enable_regmap,
497 .disable = clk_disable_regmap,
498 .get_parent = clk_rcg_get_parent,
499 .set_parent = clk_rcg_set_parent,
500 .recalc_rate = clk_rcg_recalc_rate,
501 .determine_rate = clk_rcg_determine_rate,
502 .set_rate = clk_rcg_set_rate,
503};
504EXPORT_SYMBOL_GPL(clk_rcg_ops);
505
506const struct clk_ops clk_dyn_rcg_ops = {
507 .enable = clk_enable_regmap,
508 .is_enabled = clk_is_enabled_regmap,
509 .disable = clk_disable_regmap,
510 .get_parent = clk_dyn_rcg_get_parent,
511 .set_parent = clk_dyn_rcg_set_parent,
512 .recalc_rate = clk_dyn_rcg_recalc_rate,
513 .determine_rate = clk_dyn_rcg_determine_rate,
514 .set_rate = clk_dyn_rcg_set_rate,
515 .set_rate_and_parent = clk_dyn_rcg_set_rate_and_parent,
516};
517EXPORT_SYMBOL_GPL(clk_dyn_rcg_ops);
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
new file mode 100644
index 000000000000..1d6b6dece328
--- /dev/null
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -0,0 +1,159 @@
1/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef __QCOM_CLK_RCG_H__
15#define __QCOM_CLK_RCG_H__
16
17#include <linux/clk-provider.h>
18#include "clk-regmap.h"
19
20struct freq_tbl {
21 unsigned long freq;
22 u8 src;
23 u8 pre_div;
24 u16 m;
25 u16 n;
26};
27
28/**
29 * struct mn - M/N:D counter
30 * @mnctr_en_bit: bit to enable mn counter
31 * @mnctr_reset_bit: bit to assert mn counter reset
32 * @mnctr_mode_shift: lowest bit of mn counter mode field
33 * @n_val_shift: lowest bit of n value field
34 * @m_val_shift: lowest bit of m value field
35 * @width: number of bits in m/n/d values
36 * @reset_in_cc: true if the mnctr_reset_bit is in the CC register
37 */
38struct mn {
39 u8 mnctr_en_bit;
40 u8 mnctr_reset_bit;
41 u8 mnctr_mode_shift;
42#define MNCTR_MODE_DUAL 0x2
43#define MNCTR_MODE_MASK 0x3
44 u8 n_val_shift;
45 u8 m_val_shift;
46 u8 width;
47 bool reset_in_cc;
48};
49
50/**
51 * struct pre_div - pre-divider
52 * @pre_div_shift: lowest bit of pre divider field
53 * @pre_div_width: number of bits in predivider
54 */
55struct pre_div {
56 u8 pre_div_shift;
57 u8 pre_div_width;
58};
59
60/**
61 * struct src_sel - source selector
62 * @src_sel_shift: lowest bit of source selection field
63 * @parent_map: map from software's parent index to hardware's src_sel field
64 */
65struct src_sel {
66 u8 src_sel_shift;
67#define SRC_SEL_MASK 0x7
68 const u8 *parent_map;
69};
70
71/**
72 * struct clk_rcg - root clock generator
73 *
74 * @ns_reg: NS register
75 * @md_reg: MD register
76 * @mn: mn counter
77 * @p: pre divider
78 * @s: source selector
79 * @freq_tbl: frequency table
80 * @clkr: regmap clock handle
81 * @lock: register lock
82 *
83 */
84struct clk_rcg {
85 u32 ns_reg;
86 u32 md_reg;
87
88 struct mn mn;
89 struct pre_div p;
90 struct src_sel s;
91
92 const struct freq_tbl *freq_tbl;
93
94 struct clk_regmap clkr;
95};
96
97extern const struct clk_ops clk_rcg_ops;
98
99#define to_clk_rcg(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg, clkr)
100
101/**
102 * struct clk_dyn_rcg - root clock generator with glitch free mux
103 *
104 * @mux_sel_bit: bit to switch glitch free mux
105 * @ns_reg: NS register
106 * @md_reg: MD0 and MD1 register
107 * @mn: mn counter (banked)
108 * @s: source selector (banked)
109 * @freq_tbl: frequency table
110 * @clkr: regmap clock handle
111 * @lock: register lock
112 *
113 */
114struct clk_dyn_rcg {
115 u32 ns_reg;
116 u32 md_reg[2];
117
118 u8 mux_sel_bit;
119
120 struct mn mn[2];
121 struct pre_div p[2];
122 struct src_sel s[2];
123
124 const struct freq_tbl *freq_tbl;
125
126 struct clk_regmap clkr;
127};
128
129extern const struct clk_ops clk_dyn_rcg_ops;
130
131#define to_clk_dyn_rcg(_hw) \
132 container_of(to_clk_regmap(_hw), struct clk_dyn_rcg, clkr)
133
134/**
135 * struct clk_rcg2 - root clock generator
136 *
137 * @cmd_rcgr: corresponds to *_CMD_RCGR
138 * @mnd_width: number of bits in m/n/d values
139 * @hid_width: number of bits in half integer divider
140 * @parent_map: map from software's parent index to hardware's src_sel field
141 * @freq_tbl: frequency table
142 * @clkr: regmap clock handle
143 * @lock: register lock
144 *
145 */
146struct clk_rcg2 {
147 u32 cmd_rcgr;
148 u8 mnd_width;
149 u8 hid_width;
150 const u8 *parent_map;
151 const struct freq_tbl *freq_tbl;
152 struct clk_regmap clkr;
153};
154
155#define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr)
156
157extern const struct clk_ops clk_rcg2_ops;
158
159#endif
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
new file mode 100644
index 000000000000..00f878a04d3f
--- /dev/null
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -0,0 +1,291 @@
1/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/bitops.h>
16#include <linux/err.h>
17#include <linux/bug.h>
18#include <linux/export.h>
19#include <linux/clk-provider.h>
20#include <linux/delay.h>
21#include <linux/regmap.h>
22
23#include <asm/div64.h>
24
25#include "clk-rcg.h"
26
27#define CMD_REG 0x0
28#define CMD_UPDATE BIT(0)
29#define CMD_ROOT_EN BIT(1)
30#define CMD_DIRTY_CFG BIT(4)
31#define CMD_DIRTY_N BIT(5)
32#define CMD_DIRTY_M BIT(6)
33#define CMD_DIRTY_D BIT(7)
34#define CMD_ROOT_OFF BIT(31)
35
36#define CFG_REG 0x4
37#define CFG_SRC_DIV_SHIFT 0
38#define CFG_SRC_SEL_SHIFT 8
39#define CFG_SRC_SEL_MASK (0x7 << CFG_SRC_SEL_SHIFT)
40#define CFG_MODE_SHIFT 12
41#define CFG_MODE_MASK (0x3 << CFG_MODE_SHIFT)
42#define CFG_MODE_DUAL_EDGE (0x2 << CFG_MODE_SHIFT)
43
44#define M_REG 0x8
45#define N_REG 0xc
46#define D_REG 0x10
47
48static int clk_rcg2_is_enabled(struct clk_hw *hw)
49{
50 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
51 u32 cmd;
52 int ret;
53
54 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);
55 if (ret)
56 return ret;
57
58 return (cmd & CMD_ROOT_OFF) != 0;
59}
60
61static u8 clk_rcg2_get_parent(struct clk_hw *hw)
62{
63 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
64 int num_parents = __clk_get_num_parents(hw->clk);
65 u32 cfg;
66 int i, ret;
67
68 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
69 if (ret)
70 return ret;
71
72 cfg &= CFG_SRC_SEL_MASK;
73 cfg >>= CFG_SRC_SEL_SHIFT;
74
75 for (i = 0; i < num_parents; i++)
76 if (cfg == rcg->parent_map[i])
77 return i;
78
79 return -EINVAL;
80}
81
82static int update_config(struct clk_rcg2 *rcg)
83{
84 int count, ret;
85 u32 cmd;
86 struct clk_hw *hw = &rcg->clkr.hw;
87 const char *name = __clk_get_name(hw->clk);
88
89 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
90 CMD_UPDATE, CMD_UPDATE);
91 if (ret)
92 return ret;
93
94 /* Wait for update to take effect */
95 for (count = 500; count > 0; count--) {
96 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);
97 if (ret)
98 return ret;
99 if (!(cmd & CMD_UPDATE))
100 return 0;
101 udelay(1);
102 }
103
104 WARN(1, "%s: rcg didn't update its configuration.", name);
105 return 0;
106}
107
108static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
109{
110 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
111 int ret;
112
113 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
114 CFG_SRC_SEL_MASK,
115 rcg->parent_map[index] << CFG_SRC_SEL_SHIFT);
116 if (ret)
117 return ret;
118
119 return update_config(rcg);
120}
121
122/*
123 * Calculate m/n:d rate
124 *
125 * parent_rate m
126 * rate = ----------- x ---
127 * hid_div n
128 */
129static unsigned long
130calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div)
131{
132 if (hid_div) {
133 rate *= 2;
134 rate /= hid_div + 1;
135 }
136
137 if (mode) {
138 u64 tmp = rate;
139 tmp *= m;
140 do_div(tmp, n);
141 rate = tmp;
142 }
143
144 return rate;
145}
146
147static unsigned long
148clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
149{
150 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
151 u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask;
152
153 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
154
155 if (rcg->mnd_width) {
156 mask = BIT(rcg->mnd_width) - 1;
157 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + M_REG, &m);
158 m &= mask;
159 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + N_REG, &n);
160 n = ~n;
161 n &= mask;
162 n += m;
163 mode = cfg & CFG_MODE_MASK;
164 mode >>= CFG_MODE_SHIFT;
165 }
166
167 mask = BIT(rcg->hid_width) - 1;
168 hid_div = cfg >> CFG_SRC_DIV_SHIFT;
169 hid_div &= mask;
170
171 return calc_rate(parent_rate, m, n, mode, hid_div);
172}
173
174static const
175struct freq_tbl *find_freq(const struct freq_tbl *f, unsigned long rate)
176{
177 if (!f)
178 return NULL;
179
180 for (; f->freq; f++)
181 if (rate <= f->freq)
182 return f;
183
184 return NULL;
185}
186
187static long _freq_tbl_determine_rate(struct clk_hw *hw,
188 const struct freq_tbl *f, unsigned long rate,
189 unsigned long *p_rate, struct clk **p)
190{
191 unsigned long clk_flags;
192
193 f = find_freq(f, rate);
194 if (!f)
195 return -EINVAL;
196
197 clk_flags = __clk_get_flags(hw->clk);
198 *p = clk_get_parent_by_index(hw->clk, f->src);
199 if (clk_flags & CLK_SET_RATE_PARENT) {
200 if (f->pre_div) {
201 rate /= 2;
202 rate *= f->pre_div + 1;
203 }
204
205 if (f->n) {
206 u64 tmp = rate;
207 tmp = tmp * f->n;
208 do_div(tmp, f->m);
209 rate = tmp;
210 }
211 } else {
212 rate = __clk_get_rate(*p);
213 }
214 *p_rate = rate;
215
216 return f->freq;
217}
218
219static long clk_rcg2_determine_rate(struct clk_hw *hw, unsigned long rate,
220 unsigned long *p_rate, struct clk **p)
221{
222 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
223
224 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, p_rate, p);
225}
226
227static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate)
228{
229 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
230 const struct freq_tbl *f;
231 u32 cfg, mask;
232 int ret;
233
234 f = find_freq(rcg->freq_tbl, rate);
235 if (!f)
236 return -EINVAL;
237
238 if (rcg->mnd_width && f->n) {
239 mask = BIT(rcg->mnd_width) - 1;
240 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + M_REG,
241 mask, f->m);
242 if (ret)
243 return ret;
244
245 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + N_REG,
246 mask, ~(f->n - f->m));
247 if (ret)
248 return ret;
249
250 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + D_REG,
251 mask, ~f->n);
252 if (ret)
253 return ret;
254 }
255
256 mask = BIT(rcg->hid_width) - 1;
257 mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK;
258 cfg = f->pre_div << CFG_SRC_DIV_SHIFT;
259 cfg |= rcg->parent_map[f->src] << CFG_SRC_SEL_SHIFT;
260 if (rcg->mnd_width && f->n)
261 cfg |= CFG_MODE_DUAL_EDGE;
262 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, mask,
263 cfg);
264 if (ret)
265 return ret;
266
267 return update_config(rcg);
268}
269
270static int clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
271 unsigned long parent_rate)
272{
273 return __clk_rcg2_set_rate(hw, rate);
274}
275
276static int clk_rcg2_set_rate_and_parent(struct clk_hw *hw,
277 unsigned long rate, unsigned long parent_rate, u8 index)
278{
279 return __clk_rcg2_set_rate(hw, rate);
280}
281
282const struct clk_ops clk_rcg2_ops = {
283 .is_enabled = clk_rcg2_is_enabled,
284 .get_parent = clk_rcg2_get_parent,
285 .set_parent = clk_rcg2_set_parent,
286 .recalc_rate = clk_rcg2_recalc_rate,
287 .determine_rate = clk_rcg2_determine_rate,
288 .set_rate = clk_rcg2_set_rate,
289 .set_rate_and_parent = clk_rcg2_set_rate_and_parent,
290};
291EXPORT_SYMBOL_GPL(clk_rcg2_ops);
diff --git a/drivers/clk/qcom/clk-regmap.c b/drivers/clk/qcom/clk-regmap.c
new file mode 100644
index 000000000000..a58ba39a900c
--- /dev/null
+++ b/drivers/clk/qcom/clk-regmap.c
@@ -0,0 +1,114 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/device.h>
15#include <linux/clk-provider.h>
16#include <linux/regmap.h>
17#include <linux/export.h>
18
19#include "clk-regmap.h"
20
21/**
22 * clk_is_enabled_regmap - standard is_enabled() for regmap users
23 *
24 * @hw: clk to operate on
25 *
26 * Clocks that use regmap for their register I/O can set the
27 * enable_reg and enable_mask fields in their struct clk_regmap and then use
28 * this as their is_enabled operation, saving some code.
29 */
30int clk_is_enabled_regmap(struct clk_hw *hw)
31{
32 struct clk_regmap *rclk = to_clk_regmap(hw);
33 unsigned int val;
34 int ret;
35
36 ret = regmap_read(rclk->regmap, rclk->enable_reg, &val);
37 if (ret != 0)
38 return ret;
39
40 if (rclk->enable_is_inverted)
41 return (val & rclk->enable_mask) == 0;
42 else
43 return (val & rclk->enable_mask) != 0;
44}
45EXPORT_SYMBOL_GPL(clk_is_enabled_regmap);
46
47/**
48 * clk_enable_regmap - standard enable() for regmap users
49 *
50 * @hw: clk to operate on
51 *
52 * Clocks that use regmap for their register I/O can set the
53 * enable_reg and enable_mask fields in their struct clk_regmap and then use
54 * this as their enable() operation, saving some code.
55 */
56int clk_enable_regmap(struct clk_hw *hw)
57{
58 struct clk_regmap *rclk = to_clk_regmap(hw);
59 unsigned int val;
60
61 if (rclk->enable_is_inverted)
62 val = 0;
63 else
64 val = rclk->enable_mask;
65
66 return regmap_update_bits(rclk->regmap, rclk->enable_reg,
67 rclk->enable_mask, val);
68}
69EXPORT_SYMBOL_GPL(clk_enable_regmap);
70
71/**
72 * clk_disable_regmap - standard disable() for regmap users
73 *
74 * @hw: clk to operate on
75 *
76 * Clocks that use regmap for their register I/O can set the
77 * enable_reg and enable_mask fields in their struct clk_regmap and then use
78 * this as their disable() operation, saving some code.
79 */
80void clk_disable_regmap(struct clk_hw *hw)
81{
82 struct clk_regmap *rclk = to_clk_regmap(hw);
83 unsigned int val;
84
85 if (rclk->enable_is_inverted)
86 val = rclk->enable_mask;
87 else
88 val = 0;
89
90 regmap_update_bits(rclk->regmap, rclk->enable_reg, rclk->enable_mask,
91 val);
92}
93EXPORT_SYMBOL_GPL(clk_disable_regmap);
94
95/**
96 * devm_clk_register_regmap - register a clk_regmap clock
97 *
98 * @rclk: clk to operate on
99 *
100 * Clocks that use regmap for their register I/O should register their
101 * clk_regmap struct via this function so that the regmap is initialized
102 * and so that the clock is registered with the common clock framework.
103 */
104struct clk *devm_clk_register_regmap(struct device *dev,
105 struct clk_regmap *rclk)
106{
107 if (dev && dev_get_regmap(dev, NULL))
108 rclk->regmap = dev_get_regmap(dev, NULL);
109 else if (dev && dev->parent)
110 rclk->regmap = dev_get_regmap(dev->parent, NULL);
111
112 return devm_clk_register(dev, &rclk->hw);
113}
114EXPORT_SYMBOL_GPL(devm_clk_register_regmap);
diff --git a/drivers/clk/qcom/clk-regmap.h b/drivers/clk/qcom/clk-regmap.h
new file mode 100644
index 000000000000..491a63d537df
--- /dev/null
+++ b/drivers/clk/qcom/clk-regmap.h
@@ -0,0 +1,45 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef __QCOM_CLK_REGMAP_H__
15#define __QCOM_CLK_REGMAP_H__
16
17#include <linux/clk-provider.h>
18
19struct regmap;
20
21/**
22 * struct clk_regmap - regmap supporting clock
23 * @hw: handle between common and hardware-specific interfaces
24 * @regmap: regmap to use for regmap helpers and/or by providers
25 * @enable_reg: register when using regmap enable/disable ops
26 * @enable_mask: mask when using regmap enable/disable ops
27 * @enable_is_inverted: flag to indicate set enable_mask bits to disable
28 * when using clock_enable_regmap and friends APIs.
29 */
30struct clk_regmap {
31 struct clk_hw hw;
32 struct regmap *regmap;
33 unsigned int enable_reg;
34 unsigned int enable_mask;
35 bool enable_is_inverted;
36};
37#define to_clk_regmap(_hw) container_of(_hw, struct clk_regmap, hw)
38
39int clk_is_enabled_regmap(struct clk_hw *hw);
40int clk_enable_regmap(struct clk_hw *hw);
41void clk_disable_regmap(struct clk_hw *hw);
42struct clk *
43devm_clk_register_regmap(struct device *dev, struct clk_regmap *rclk);
44
45#endif
diff --git a/drivers/clk/qcom/gcc-msm8660.c b/drivers/clk/qcom/gcc-msm8660.c
new file mode 100644
index 000000000000..bc0b7f1fcfbe
--- /dev/null
+++ b/drivers/clk/qcom/gcc-msm8660.c
@@ -0,0 +1,2819 @@
1/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/bitops.h>
16#include <linux/err.h>
17#include <linux/platform_device.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/clk-provider.h>
22#include <linux/regmap.h>
23#include <linux/reset-controller.h>
24
25#include <dt-bindings/clock/qcom,gcc-msm8660.h>
26#include <dt-bindings/reset/qcom,gcc-msm8660.h>
27
28#include "clk-regmap.h"
29#include "clk-pll.h"
30#include "clk-rcg.h"
31#include "clk-branch.h"
32#include "reset.h"
33
34static struct clk_pll pll8 = {
35 .l_reg = 0x3144,
36 .m_reg = 0x3148,
37 .n_reg = 0x314c,
38 .config_reg = 0x3154,
39 .mode_reg = 0x3140,
40 .status_reg = 0x3158,
41 .status_bit = 16,
42 .clkr.hw.init = &(struct clk_init_data){
43 .name = "pll8",
44 .parent_names = (const char *[]){ "pxo" },
45 .num_parents = 1,
46 .ops = &clk_pll_ops,
47 },
48};
49
50static struct clk_regmap pll8_vote = {
51 .enable_reg = 0x34c0,
52 .enable_mask = BIT(8),
53 .hw.init = &(struct clk_init_data){
54 .name = "pll8_vote",
55 .parent_names = (const char *[]){ "pll8" },
56 .num_parents = 1,
57 .ops = &clk_pll_vote_ops,
58 },
59};
60
61#define P_PXO 0
62#define P_PLL8 1
63#define P_CXO 2
64
65static const u8 gcc_pxo_pll8_map[] = {
66 [P_PXO] = 0,
67 [P_PLL8] = 3,
68};
69
70static const char *gcc_pxo_pll8[] = {
71 "pxo",
72 "pll8_vote",
73};
74
75static const u8 gcc_pxo_pll8_cxo_map[] = {
76 [P_PXO] = 0,
77 [P_PLL8] = 3,
78 [P_CXO] = 5,
79};
80
81static const char *gcc_pxo_pll8_cxo[] = {
82 "pxo",
83 "pll8_vote",
84 "cxo",
85};
86
87static struct freq_tbl clk_tbl_gsbi_uart[] = {
88 { 1843200, P_PLL8, 2, 6, 625 },
89 { 3686400, P_PLL8, 2, 12, 625 },
90 { 7372800, P_PLL8, 2, 24, 625 },
91 { 14745600, P_PLL8, 2, 48, 625 },
92 { 16000000, P_PLL8, 4, 1, 6 },
93 { 24000000, P_PLL8, 4, 1, 4 },
94 { 32000000, P_PLL8, 4, 1, 3 },
95 { 40000000, P_PLL8, 1, 5, 48 },
96 { 46400000, P_PLL8, 1, 29, 240 },
97 { 48000000, P_PLL8, 4, 1, 2 },
98 { 51200000, P_PLL8, 1, 2, 15 },
99 { 56000000, P_PLL8, 1, 7, 48 },
100 { 58982400, P_PLL8, 1, 96, 625 },
101 { 64000000, P_PLL8, 2, 1, 3 },
102 { }
103};
104
105static struct clk_rcg gsbi1_uart_src = {
106 .ns_reg = 0x29d4,
107 .md_reg = 0x29d0,
108 .mn = {
109 .mnctr_en_bit = 8,
110 .mnctr_reset_bit = 7,
111 .mnctr_mode_shift = 5,
112 .n_val_shift = 16,
113 .m_val_shift = 16,
114 .width = 16,
115 },
116 .p = {
117 .pre_div_shift = 3,
118 .pre_div_width = 2,
119 },
120 .s = {
121 .src_sel_shift = 0,
122 .parent_map = gcc_pxo_pll8_map,
123 },
124 .freq_tbl = clk_tbl_gsbi_uart,
125 .clkr = {
126 .enable_reg = 0x29d4,
127 .enable_mask = BIT(11),
128 .hw.init = &(struct clk_init_data){
129 .name = "gsbi1_uart_src",
130 .parent_names = gcc_pxo_pll8,
131 .num_parents = 2,
132 .ops = &clk_rcg_ops,
133 .flags = CLK_SET_PARENT_GATE,
134 },
135 },
136};
137
138static struct clk_branch gsbi1_uart_clk = {
139 .halt_reg = 0x2fcc,
140 .halt_bit = 10,
141 .clkr = {
142 .enable_reg = 0x29d4,
143 .enable_mask = BIT(9),
144 .hw.init = &(struct clk_init_data){
145 .name = "gsbi1_uart_clk",
146 .parent_names = (const char *[]){
147 "gsbi1_uart_src",
148 },
149 .num_parents = 1,
150 .ops = &clk_branch_ops,
151 .flags = CLK_SET_RATE_PARENT,
152 },
153 },
154};
155
156static struct clk_rcg gsbi2_uart_src = {
157 .ns_reg = 0x29f4,
158 .md_reg = 0x29f0,
159 .mn = {
160 .mnctr_en_bit = 8,
161 .mnctr_reset_bit = 7,
162 .mnctr_mode_shift = 5,
163 .n_val_shift = 16,
164 .m_val_shift = 16,
165 .width = 16,
166 },
167 .p = {
168 .pre_div_shift = 3,
169 .pre_div_width = 2,
170 },
171 .s = {
172 .src_sel_shift = 0,
173 .parent_map = gcc_pxo_pll8_map,
174 },
175 .freq_tbl = clk_tbl_gsbi_uart,
176 .clkr = {
177 .enable_reg = 0x29f4,
178 .enable_mask = BIT(11),
179 .hw.init = &(struct clk_init_data){
180 .name = "gsbi2_uart_src",
181 .parent_names = gcc_pxo_pll8,
182 .num_parents = 2,
183 .ops = &clk_rcg_ops,
184 .flags = CLK_SET_PARENT_GATE,
185 },
186 },
187};
188
189static struct clk_branch gsbi2_uart_clk = {
190 .halt_reg = 0x2fcc,
191 .halt_bit = 6,
192 .clkr = {
193 .enable_reg = 0x29f4,
194 .enable_mask = BIT(9),
195 .hw.init = &(struct clk_init_data){
196 .name = "gsbi2_uart_clk",
197 .parent_names = (const char *[]){
198 "gsbi2_uart_src",
199 },
200 .num_parents = 1,
201 .ops = &clk_branch_ops,
202 .flags = CLK_SET_RATE_PARENT,
203 },
204 },
205};
206
207static struct clk_rcg gsbi3_uart_src = {
208 .ns_reg = 0x2a14,
209 .md_reg = 0x2a10,
210 .mn = {
211 .mnctr_en_bit = 8,
212 .mnctr_reset_bit = 7,
213 .mnctr_mode_shift = 5,
214 .n_val_shift = 16,
215 .m_val_shift = 16,
216 .width = 16,
217 },
218 .p = {
219 .pre_div_shift = 3,
220 .pre_div_width = 2,
221 },
222 .s = {
223 .src_sel_shift = 0,
224 .parent_map = gcc_pxo_pll8_map,
225 },
226 .freq_tbl = clk_tbl_gsbi_uart,
227 .clkr = {
228 .enable_reg = 0x2a14,
229 .enable_mask = BIT(11),
230 .hw.init = &(struct clk_init_data){
231 .name = "gsbi3_uart_src",
232 .parent_names = gcc_pxo_pll8,
233 .num_parents = 2,
234 .ops = &clk_rcg_ops,
235 .flags = CLK_SET_PARENT_GATE,
236 },
237 },
238};
239
240static struct clk_branch gsbi3_uart_clk = {
241 .halt_reg = 0x2fcc,
242 .halt_bit = 2,
243 .clkr = {
244 .enable_reg = 0x2a14,
245 .enable_mask = BIT(9),
246 .hw.init = &(struct clk_init_data){
247 .name = "gsbi3_uart_clk",
248 .parent_names = (const char *[]){
249 "gsbi3_uart_src",
250 },
251 .num_parents = 1,
252 .ops = &clk_branch_ops,
253 .flags = CLK_SET_RATE_PARENT,
254 },
255 },
256};
257
258static struct clk_rcg gsbi4_uart_src = {
259 .ns_reg = 0x2a34,
260 .md_reg = 0x2a30,
261 .mn = {
262 .mnctr_en_bit = 8,
263 .mnctr_reset_bit = 7,
264 .mnctr_mode_shift = 5,
265 .n_val_shift = 16,
266 .m_val_shift = 16,
267 .width = 16,
268 },
269 .p = {
270 .pre_div_shift = 3,
271 .pre_div_width = 2,
272 },
273 .s = {
274 .src_sel_shift = 0,
275 .parent_map = gcc_pxo_pll8_map,
276 },
277 .freq_tbl = clk_tbl_gsbi_uart,
278 .clkr = {
279 .enable_reg = 0x2a34,
280 .enable_mask = BIT(11),
281 .hw.init = &(struct clk_init_data){
282 .name = "gsbi4_uart_src",
283 .parent_names = gcc_pxo_pll8,
284 .num_parents = 2,
285 .ops = &clk_rcg_ops,
286 .flags = CLK_SET_PARENT_GATE,
287 },
288 },
289};
290
291static struct clk_branch gsbi4_uart_clk = {
292 .halt_reg = 0x2fd0,
293 .halt_bit = 26,
294 .clkr = {
295 .enable_reg = 0x2a34,
296 .enable_mask = BIT(9),
297 .hw.init = &(struct clk_init_data){
298 .name = "gsbi4_uart_clk",
299 .parent_names = (const char *[]){
300 "gsbi4_uart_src",
301 },
302 .num_parents = 1,
303 .ops = &clk_branch_ops,
304 .flags = CLK_SET_RATE_PARENT,
305 },
306 },
307};
308
309static struct clk_rcg gsbi5_uart_src = {
310 .ns_reg = 0x2a54,
311 .md_reg = 0x2a50,
312 .mn = {
313 .mnctr_en_bit = 8,
314 .mnctr_reset_bit = 7,
315 .mnctr_mode_shift = 5,
316 .n_val_shift = 16,
317 .m_val_shift = 16,
318 .width = 16,
319 },
320 .p = {
321 .pre_div_shift = 3,
322 .pre_div_width = 2,
323 },
324 .s = {
325 .src_sel_shift = 0,
326 .parent_map = gcc_pxo_pll8_map,
327 },
328 .freq_tbl = clk_tbl_gsbi_uart,
329 .clkr = {
330 .enable_reg = 0x2a54,
331 .enable_mask = BIT(11),
332 .hw.init = &(struct clk_init_data){
333 .name = "gsbi5_uart_src",
334 .parent_names = gcc_pxo_pll8,
335 .num_parents = 2,
336 .ops = &clk_rcg_ops,
337 .flags = CLK_SET_PARENT_GATE,
338 },
339 },
340};
341
342static struct clk_branch gsbi5_uart_clk = {
343 .halt_reg = 0x2fd0,
344 .halt_bit = 22,
345 .clkr = {
346 .enable_reg = 0x2a54,
347 .enable_mask = BIT(9),
348 .hw.init = &(struct clk_init_data){
349 .name = "gsbi5_uart_clk",
350 .parent_names = (const char *[]){
351 "gsbi5_uart_src",
352 },
353 .num_parents = 1,
354 .ops = &clk_branch_ops,
355 .flags = CLK_SET_RATE_PARENT,
356 },
357 },
358};
359
360static struct clk_rcg gsbi6_uart_src = {
361 .ns_reg = 0x2a74,
362 .md_reg = 0x2a70,
363 .mn = {
364 .mnctr_en_bit = 8,
365 .mnctr_reset_bit = 7,
366 .mnctr_mode_shift = 5,
367 .n_val_shift = 16,
368 .m_val_shift = 16,
369 .width = 16,
370 },
371 .p = {
372 .pre_div_shift = 3,
373 .pre_div_width = 2,
374 },
375 .s = {
376 .src_sel_shift = 0,
377 .parent_map = gcc_pxo_pll8_map,
378 },
379 .freq_tbl = clk_tbl_gsbi_uart,
380 .clkr = {
381 .enable_reg = 0x2a74,
382 .enable_mask = BIT(11),
383 .hw.init = &(struct clk_init_data){
384 .name = "gsbi6_uart_src",
385 .parent_names = gcc_pxo_pll8,
386 .num_parents = 2,
387 .ops = &clk_rcg_ops,
388 .flags = CLK_SET_PARENT_GATE,
389 },
390 },
391};
392
393static struct clk_branch gsbi6_uart_clk = {
394 .halt_reg = 0x2fd0,
395 .halt_bit = 18,
396 .clkr = {
397 .enable_reg = 0x2a74,
398 .enable_mask = BIT(9),
399 .hw.init = &(struct clk_init_data){
400 .name = "gsbi6_uart_clk",
401 .parent_names = (const char *[]){
402 "gsbi6_uart_src",
403 },
404 .num_parents = 1,
405 .ops = &clk_branch_ops,
406 .flags = CLK_SET_RATE_PARENT,
407 },
408 },
409};
410
411static struct clk_rcg gsbi7_uart_src = {
412 .ns_reg = 0x2a94,
413 .md_reg = 0x2a90,
414 .mn = {
415 .mnctr_en_bit = 8,
416 .mnctr_reset_bit = 7,
417 .mnctr_mode_shift = 5,
418 .n_val_shift = 16,
419 .m_val_shift = 16,
420 .width = 16,
421 },
422 .p = {
423 .pre_div_shift = 3,
424 .pre_div_width = 2,
425 },
426 .s = {
427 .src_sel_shift = 0,
428 .parent_map = gcc_pxo_pll8_map,
429 },
430 .freq_tbl = clk_tbl_gsbi_uart,
431 .clkr = {
432 .enable_reg = 0x2a94,
433 .enable_mask = BIT(11),
434 .hw.init = &(struct clk_init_data){
435 .name = "gsbi7_uart_src",
436 .parent_names = gcc_pxo_pll8,
437 .num_parents = 2,
438 .ops = &clk_rcg_ops,
439 .flags = CLK_SET_PARENT_GATE,
440 },
441 },
442};
443
444static struct clk_branch gsbi7_uart_clk = {
445 .halt_reg = 0x2fd0,
446 .halt_bit = 14,
447 .clkr = {
448 .enable_reg = 0x2a94,
449 .enable_mask = BIT(9),
450 .hw.init = &(struct clk_init_data){
451 .name = "gsbi7_uart_clk",
452 .parent_names = (const char *[]){
453 "gsbi7_uart_src",
454 },
455 .num_parents = 1,
456 .ops = &clk_branch_ops,
457 .flags = CLK_SET_RATE_PARENT,
458 },
459 },
460};
461
462static struct clk_rcg gsbi8_uart_src = {
463 .ns_reg = 0x2ab4,
464 .md_reg = 0x2ab0,
465 .mn = {
466 .mnctr_en_bit = 8,
467 .mnctr_reset_bit = 7,
468 .mnctr_mode_shift = 5,
469 .n_val_shift = 16,
470 .m_val_shift = 16,
471 .width = 16,
472 },
473 .p = {
474 .pre_div_shift = 3,
475 .pre_div_width = 2,
476 },
477 .s = {
478 .src_sel_shift = 0,
479 .parent_map = gcc_pxo_pll8_map,
480 },
481 .freq_tbl = clk_tbl_gsbi_uart,
482 .clkr = {
483 .enable_reg = 0x2ab4,
484 .enable_mask = BIT(11),
485 .hw.init = &(struct clk_init_data){
486 .name = "gsbi8_uart_src",
487 .parent_names = gcc_pxo_pll8,
488 .num_parents = 2,
489 .ops = &clk_rcg_ops,
490 .flags = CLK_SET_PARENT_GATE,
491 },
492 },
493};
494
495static struct clk_branch gsbi8_uart_clk = {
496 .halt_reg = 0x2fd0,
497 .halt_bit = 10,
498 .clkr = {
499 .enable_reg = 0x2ab4,
500 .enable_mask = BIT(9),
501 .hw.init = &(struct clk_init_data){
502 .name = "gsbi8_uart_clk",
503 .parent_names = (const char *[]){ "gsbi8_uart_src" },
504 .num_parents = 1,
505 .ops = &clk_branch_ops,
506 .flags = CLK_SET_RATE_PARENT,
507 },
508 },
509};
510
511static struct clk_rcg gsbi9_uart_src = {
512 .ns_reg = 0x2ad4,
513 .md_reg = 0x2ad0,
514 .mn = {
515 .mnctr_en_bit = 8,
516 .mnctr_reset_bit = 7,
517 .mnctr_mode_shift = 5,
518 .n_val_shift = 16,
519 .m_val_shift = 16,
520 .width = 16,
521 },
522 .p = {
523 .pre_div_shift = 3,
524 .pre_div_width = 2,
525 },
526 .s = {
527 .src_sel_shift = 0,
528 .parent_map = gcc_pxo_pll8_map,
529 },
530 .freq_tbl = clk_tbl_gsbi_uart,
531 .clkr = {
532 .enable_reg = 0x2ad4,
533 .enable_mask = BIT(11),
534 .hw.init = &(struct clk_init_data){
535 .name = "gsbi9_uart_src",
536 .parent_names = gcc_pxo_pll8,
537 .num_parents = 2,
538 .ops = &clk_rcg_ops,
539 .flags = CLK_SET_PARENT_GATE,
540 },
541 },
542};
543
544static struct clk_branch gsbi9_uart_clk = {
545 .halt_reg = 0x2fd0,
546 .halt_bit = 6,
547 .clkr = {
548 .enable_reg = 0x2ad4,
549 .enable_mask = BIT(9),
550 .hw.init = &(struct clk_init_data){
551 .name = "gsbi9_uart_clk",
552 .parent_names = (const char *[]){ "gsbi9_uart_src" },
553 .num_parents = 1,
554 .ops = &clk_branch_ops,
555 .flags = CLK_SET_RATE_PARENT,
556 },
557 },
558};
559
560static struct clk_rcg gsbi10_uart_src = {
561 .ns_reg = 0x2af4,
562 .md_reg = 0x2af0,
563 .mn = {
564 .mnctr_en_bit = 8,
565 .mnctr_reset_bit = 7,
566 .mnctr_mode_shift = 5,
567 .n_val_shift = 16,
568 .m_val_shift = 16,
569 .width = 16,
570 },
571 .p = {
572 .pre_div_shift = 3,
573 .pre_div_width = 2,
574 },
575 .s = {
576 .src_sel_shift = 0,
577 .parent_map = gcc_pxo_pll8_map,
578 },
579 .freq_tbl = clk_tbl_gsbi_uart,
580 .clkr = {
581 .enable_reg = 0x2af4,
582 .enable_mask = BIT(11),
583 .hw.init = &(struct clk_init_data){
584 .name = "gsbi10_uart_src",
585 .parent_names = gcc_pxo_pll8,
586 .num_parents = 2,
587 .ops = &clk_rcg_ops,
588 .flags = CLK_SET_PARENT_GATE,
589 },
590 },
591};
592
593static struct clk_branch gsbi10_uart_clk = {
594 .halt_reg = 0x2fd0,
595 .halt_bit = 2,
596 .clkr = {
597 .enable_reg = 0x2af4,
598 .enable_mask = BIT(9),
599 .hw.init = &(struct clk_init_data){
600 .name = "gsbi10_uart_clk",
601 .parent_names = (const char *[]){ "gsbi10_uart_src" },
602 .num_parents = 1,
603 .ops = &clk_branch_ops,
604 .flags = CLK_SET_RATE_PARENT,
605 },
606 },
607};
608
609static struct clk_rcg gsbi11_uart_src = {
610 .ns_reg = 0x2b14,
611 .md_reg = 0x2b10,
612 .mn = {
613 .mnctr_en_bit = 8,
614 .mnctr_reset_bit = 7,
615 .mnctr_mode_shift = 5,
616 .n_val_shift = 16,
617 .m_val_shift = 16,
618 .width = 16,
619 },
620 .p = {
621 .pre_div_shift = 3,
622 .pre_div_width = 2,
623 },
624 .s = {
625 .src_sel_shift = 0,
626 .parent_map = gcc_pxo_pll8_map,
627 },
628 .freq_tbl = clk_tbl_gsbi_uart,
629 .clkr = {
630 .enable_reg = 0x2b14,
631 .enable_mask = BIT(11),
632 .hw.init = &(struct clk_init_data){
633 .name = "gsbi11_uart_src",
634 .parent_names = gcc_pxo_pll8,
635 .num_parents = 2,
636 .ops = &clk_rcg_ops,
637 .flags = CLK_SET_PARENT_GATE,
638 },
639 },
640};
641
642static struct clk_branch gsbi11_uart_clk = {
643 .halt_reg = 0x2fd4,
644 .halt_bit = 17,
645 .clkr = {
646 .enable_reg = 0x2b14,
647 .enable_mask = BIT(9),
648 .hw.init = &(struct clk_init_data){
649 .name = "gsbi11_uart_clk",
650 .parent_names = (const char *[]){ "gsbi11_uart_src" },
651 .num_parents = 1,
652 .ops = &clk_branch_ops,
653 .flags = CLK_SET_RATE_PARENT,
654 },
655 },
656};
657
658static struct clk_rcg gsbi12_uart_src = {
659 .ns_reg = 0x2b34,
660 .md_reg = 0x2b30,
661 .mn = {
662 .mnctr_en_bit = 8,
663 .mnctr_reset_bit = 7,
664 .mnctr_mode_shift = 5,
665 .n_val_shift = 16,
666 .m_val_shift = 16,
667 .width = 16,
668 },
669 .p = {
670 .pre_div_shift = 3,
671 .pre_div_width = 2,
672 },
673 .s = {
674 .src_sel_shift = 0,
675 .parent_map = gcc_pxo_pll8_map,
676 },
677 .freq_tbl = clk_tbl_gsbi_uart,
678 .clkr = {
679 .enable_reg = 0x2b34,
680 .enable_mask = BIT(11),
681 .hw.init = &(struct clk_init_data){
682 .name = "gsbi12_uart_src",
683 .parent_names = gcc_pxo_pll8,
684 .num_parents = 2,
685 .ops = &clk_rcg_ops,
686 .flags = CLK_SET_PARENT_GATE,
687 },
688 },
689};
690
691static struct clk_branch gsbi12_uart_clk = {
692 .halt_reg = 0x2fd4,
693 .halt_bit = 13,
694 .clkr = {
695 .enable_reg = 0x2b34,
696 .enable_mask = BIT(9),
697 .hw.init = &(struct clk_init_data){
698 .name = "gsbi12_uart_clk",
699 .parent_names = (const char *[]){ "gsbi12_uart_src" },
700 .num_parents = 1,
701 .ops = &clk_branch_ops,
702 .flags = CLK_SET_RATE_PARENT,
703 },
704 },
705};
706
707static struct freq_tbl clk_tbl_gsbi_qup[] = {
708 { 1100000, P_PXO, 1, 2, 49 },
709 { 5400000, P_PXO, 1, 1, 5 },
710 { 10800000, P_PXO, 1, 2, 5 },
711 { 15060000, P_PLL8, 1, 2, 51 },
712 { 24000000, P_PLL8, 4, 1, 4 },
713 { 25600000, P_PLL8, 1, 1, 15 },
714 { 27000000, P_PXO, 1, 0, 0 },
715 { 48000000, P_PLL8, 4, 1, 2 },
716 { 51200000, P_PLL8, 1, 2, 15 },
717 { }
718};
719
720static struct clk_rcg gsbi1_qup_src = {
721 .ns_reg = 0x29cc,
722 .md_reg = 0x29c8,
723 .mn = {
724 .mnctr_en_bit = 8,
725 .mnctr_reset_bit = 7,
726 .mnctr_mode_shift = 5,
727 .n_val_shift = 16,
728 .m_val_shift = 16,
729 .width = 8,
730 },
731 .p = {
732 .pre_div_shift = 3,
733 .pre_div_width = 2,
734 },
735 .s = {
736 .src_sel_shift = 0,
737 .parent_map = gcc_pxo_pll8_map,
738 },
739 .freq_tbl = clk_tbl_gsbi_qup,
740 .clkr = {
741 .enable_reg = 0x29cc,
742 .enable_mask = BIT(11),
743 .hw.init = &(struct clk_init_data){
744 .name = "gsbi1_qup_src",
745 .parent_names = gcc_pxo_pll8,
746 .num_parents = 2,
747 .ops = &clk_rcg_ops,
748 .flags = CLK_SET_PARENT_GATE,
749 },
750 },
751};
752
753static struct clk_branch gsbi1_qup_clk = {
754 .halt_reg = 0x2fcc,
755 .halt_bit = 9,
756 .clkr = {
757 .enable_reg = 0x29cc,
758 .enable_mask = BIT(9),
759 .hw.init = &(struct clk_init_data){
760 .name = "gsbi1_qup_clk",
761 .parent_names = (const char *[]){ "gsbi1_qup_src" },
762 .num_parents = 1,
763 .ops = &clk_branch_ops,
764 .flags = CLK_SET_RATE_PARENT,
765 },
766 },
767};
768
769static struct clk_rcg gsbi2_qup_src = {
770 .ns_reg = 0x29ec,
771 .md_reg = 0x29e8,
772 .mn = {
773 .mnctr_en_bit = 8,
774 .mnctr_reset_bit = 7,
775 .mnctr_mode_shift = 5,
776 .n_val_shift = 16,
777 .m_val_shift = 16,
778 .width = 8,
779 },
780 .p = {
781 .pre_div_shift = 3,
782 .pre_div_width = 2,
783 },
784 .s = {
785 .src_sel_shift = 0,
786 .parent_map = gcc_pxo_pll8_map,
787 },
788 .freq_tbl = clk_tbl_gsbi_qup,
789 .clkr = {
790 .enable_reg = 0x29ec,
791 .enable_mask = BIT(11),
792 .hw.init = &(struct clk_init_data){
793 .name = "gsbi2_qup_src",
794 .parent_names = gcc_pxo_pll8,
795 .num_parents = 2,
796 .ops = &clk_rcg_ops,
797 .flags = CLK_SET_PARENT_GATE,
798 },
799 },
800};
801
802static struct clk_branch gsbi2_qup_clk = {
803 .halt_reg = 0x2fcc,
804 .halt_bit = 4,
805 .clkr = {
806 .enable_reg = 0x29ec,
807 .enable_mask = BIT(9),
808 .hw.init = &(struct clk_init_data){
809 .name = "gsbi2_qup_clk",
810 .parent_names = (const char *[]){ "gsbi2_qup_src" },
811 .num_parents = 1,
812 .ops = &clk_branch_ops,
813 .flags = CLK_SET_RATE_PARENT,
814 },
815 },
816};
817
818static struct clk_rcg gsbi3_qup_src = {
819 .ns_reg = 0x2a0c,
820 .md_reg = 0x2a08,
821 .mn = {
822 .mnctr_en_bit = 8,
823 .mnctr_reset_bit = 7,
824 .mnctr_mode_shift = 5,
825 .n_val_shift = 16,
826 .m_val_shift = 16,
827 .width = 8,
828 },
829 .p = {
830 .pre_div_shift = 3,
831 .pre_div_width = 2,
832 },
833 .s = {
834 .src_sel_shift = 0,
835 .parent_map = gcc_pxo_pll8_map,
836 },
837 .freq_tbl = clk_tbl_gsbi_qup,
838 .clkr = {
839 .enable_reg = 0x2a0c,
840 .enable_mask = BIT(11),
841 .hw.init = &(struct clk_init_data){
842 .name = "gsbi3_qup_src",
843 .parent_names = gcc_pxo_pll8,
844 .num_parents = 2,
845 .ops = &clk_rcg_ops,
846 .flags = CLK_SET_PARENT_GATE,
847 },
848 },
849};
850
851static struct clk_branch gsbi3_qup_clk = {
852 .halt_reg = 0x2fcc,
853 .halt_bit = 0,
854 .clkr = {
855 .enable_reg = 0x2a0c,
856 .enable_mask = BIT(9),
857 .hw.init = &(struct clk_init_data){
858 .name = "gsbi3_qup_clk",
859 .parent_names = (const char *[]){ "gsbi3_qup_src" },
860 .num_parents = 1,
861 .ops = &clk_branch_ops,
862 .flags = CLK_SET_RATE_PARENT,
863 },
864 },
865};
866
867static struct clk_rcg gsbi4_qup_src = {
868 .ns_reg = 0x2a2c,
869 .md_reg = 0x2a28,
870 .mn = {
871 .mnctr_en_bit = 8,
872 .mnctr_reset_bit = 7,
873 .mnctr_mode_shift = 5,
874 .n_val_shift = 16,
875 .m_val_shift = 16,
876 .width = 8,
877 },
878 .p = {
879 .pre_div_shift = 3,
880 .pre_div_width = 2,
881 },
882 .s = {
883 .src_sel_shift = 0,
884 .parent_map = gcc_pxo_pll8_map,
885 },
886 .freq_tbl = clk_tbl_gsbi_qup,
887 .clkr = {
888 .enable_reg = 0x2a2c,
889 .enable_mask = BIT(11),
890 .hw.init = &(struct clk_init_data){
891 .name = "gsbi4_qup_src",
892 .parent_names = gcc_pxo_pll8,
893 .num_parents = 2,
894 .ops = &clk_rcg_ops,
895 .flags = CLK_SET_PARENT_GATE,
896 },
897 },
898};
899
900static struct clk_branch gsbi4_qup_clk = {
901 .halt_reg = 0x2fd0,
902 .halt_bit = 24,
903 .clkr = {
904 .enable_reg = 0x2a2c,
905 .enable_mask = BIT(9),
906 .hw.init = &(struct clk_init_data){
907 .name = "gsbi4_qup_clk",
908 .parent_names = (const char *[]){ "gsbi4_qup_src" },
909 .num_parents = 1,
910 .ops = &clk_branch_ops,
911 .flags = CLK_SET_RATE_PARENT,
912 },
913 },
914};
915
916static struct clk_rcg gsbi5_qup_src = {
917 .ns_reg = 0x2a4c,
918 .md_reg = 0x2a48,
919 .mn = {
920 .mnctr_en_bit = 8,
921 .mnctr_reset_bit = 7,
922 .mnctr_mode_shift = 5,
923 .n_val_shift = 16,
924 .m_val_shift = 16,
925 .width = 8,
926 },
927 .p = {
928 .pre_div_shift = 3,
929 .pre_div_width = 2,
930 },
931 .s = {
932 .src_sel_shift = 0,
933 .parent_map = gcc_pxo_pll8_map,
934 },
935 .freq_tbl = clk_tbl_gsbi_qup,
936 .clkr = {
937 .enable_reg = 0x2a4c,
938 .enable_mask = BIT(11),
939 .hw.init = &(struct clk_init_data){
940 .name = "gsbi5_qup_src",
941 .parent_names = gcc_pxo_pll8,
942 .num_parents = 2,
943 .ops = &clk_rcg_ops,
944 .flags = CLK_SET_PARENT_GATE,
945 },
946 },
947};
948
949static struct clk_branch gsbi5_qup_clk = {
950 .halt_reg = 0x2fd0,
951 .halt_bit = 20,
952 .clkr = {
953 .enable_reg = 0x2a4c,
954 .enable_mask = BIT(9),
955 .hw.init = &(struct clk_init_data){
956 .name = "gsbi5_qup_clk",
957 .parent_names = (const char *[]){ "gsbi5_qup_src" },
958 .num_parents = 1,
959 .ops = &clk_branch_ops,
960 .flags = CLK_SET_RATE_PARENT,
961 },
962 },
963};
964
965static struct clk_rcg gsbi6_qup_src = {
966 .ns_reg = 0x2a6c,
967 .md_reg = 0x2a68,
968 .mn = {
969 .mnctr_en_bit = 8,
970 .mnctr_reset_bit = 7,
971 .mnctr_mode_shift = 5,
972 .n_val_shift = 16,
973 .m_val_shift = 16,
974 .width = 8,
975 },
976 .p = {
977 .pre_div_shift = 3,
978 .pre_div_width = 2,
979 },
980 .s = {
981 .src_sel_shift = 0,
982 .parent_map = gcc_pxo_pll8_map,
983 },
984 .freq_tbl = clk_tbl_gsbi_qup,
985 .clkr = {
986 .enable_reg = 0x2a6c,
987 .enable_mask = BIT(11),
988 .hw.init = &(struct clk_init_data){
989 .name = "gsbi6_qup_src",
990 .parent_names = gcc_pxo_pll8,
991 .num_parents = 2,
992 .ops = &clk_rcg_ops,
993 .flags = CLK_SET_PARENT_GATE,
994 },
995 },
996};
997
998static struct clk_branch gsbi6_qup_clk = {
999 .halt_reg = 0x2fd0,
1000 .halt_bit = 16,
1001 .clkr = {
1002 .enable_reg = 0x2a6c,
1003 .enable_mask = BIT(9),
1004 .hw.init = &(struct clk_init_data){
1005 .name = "gsbi6_qup_clk",
1006 .parent_names = (const char *[]){ "gsbi6_qup_src" },
1007 .num_parents = 1,
1008 .ops = &clk_branch_ops,
1009 .flags = CLK_SET_RATE_PARENT,
1010 },
1011 },
1012};
1013
1014static struct clk_rcg gsbi7_qup_src = {
1015 .ns_reg = 0x2a8c,
1016 .md_reg = 0x2a88,
1017 .mn = {
1018 .mnctr_en_bit = 8,
1019 .mnctr_reset_bit = 7,
1020 .mnctr_mode_shift = 5,
1021 .n_val_shift = 16,
1022 .m_val_shift = 16,
1023 .width = 8,
1024 },
1025 .p = {
1026 .pre_div_shift = 3,
1027 .pre_div_width = 2,
1028 },
1029 .s = {
1030 .src_sel_shift = 0,
1031 .parent_map = gcc_pxo_pll8_map,
1032 },
1033 .freq_tbl = clk_tbl_gsbi_qup,
1034 .clkr = {
1035 .enable_reg = 0x2a8c,
1036 .enable_mask = BIT(11),
1037 .hw.init = &(struct clk_init_data){
1038 .name = "gsbi7_qup_src",
1039 .parent_names = gcc_pxo_pll8,
1040 .num_parents = 2,
1041 .ops = &clk_rcg_ops,
1042 .flags = CLK_SET_PARENT_GATE,
1043 },
1044 },
1045};
1046
1047static struct clk_branch gsbi7_qup_clk = {
1048 .halt_reg = 0x2fd0,
1049 .halt_bit = 12,
1050 .clkr = {
1051 .enable_reg = 0x2a8c,
1052 .enable_mask = BIT(9),
1053 .hw.init = &(struct clk_init_data){
1054 .name = "gsbi7_qup_clk",
1055 .parent_names = (const char *[]){ "gsbi7_qup_src" },
1056 .num_parents = 1,
1057 .ops = &clk_branch_ops,
1058 .flags = CLK_SET_RATE_PARENT,
1059 },
1060 },
1061};
1062
1063static struct clk_rcg gsbi8_qup_src = {
1064 .ns_reg = 0x2aac,
1065 .md_reg = 0x2aa8,
1066 .mn = {
1067 .mnctr_en_bit = 8,
1068 .mnctr_reset_bit = 7,
1069 .mnctr_mode_shift = 5,
1070 .n_val_shift = 16,
1071 .m_val_shift = 16,
1072 .width = 8,
1073 },
1074 .p = {
1075 .pre_div_shift = 3,
1076 .pre_div_width = 2,
1077 },
1078 .s = {
1079 .src_sel_shift = 0,
1080 .parent_map = gcc_pxo_pll8_map,
1081 },
1082 .freq_tbl = clk_tbl_gsbi_qup,
1083 .clkr = {
1084 .enable_reg = 0x2aac,
1085 .enable_mask = BIT(11),
1086 .hw.init = &(struct clk_init_data){
1087 .name = "gsbi8_qup_src",
1088 .parent_names = gcc_pxo_pll8,
1089 .num_parents = 2,
1090 .ops = &clk_rcg_ops,
1091 .flags = CLK_SET_PARENT_GATE,
1092 },
1093 },
1094};
1095
1096static struct clk_branch gsbi8_qup_clk = {
1097 .halt_reg = 0x2fd0,
1098 .halt_bit = 8,
1099 .clkr = {
1100 .enable_reg = 0x2aac,
1101 .enable_mask = BIT(9),
1102 .hw.init = &(struct clk_init_data){
1103 .name = "gsbi8_qup_clk",
1104 .parent_names = (const char *[]){ "gsbi8_qup_src" },
1105 .num_parents = 1,
1106 .ops = &clk_branch_ops,
1107 .flags = CLK_SET_RATE_PARENT,
1108 },
1109 },
1110};
1111
1112static struct clk_rcg gsbi9_qup_src = {
1113 .ns_reg = 0x2acc,
1114 .md_reg = 0x2ac8,
1115 .mn = {
1116 .mnctr_en_bit = 8,
1117 .mnctr_reset_bit = 7,
1118 .mnctr_mode_shift = 5,
1119 .n_val_shift = 16,
1120 .m_val_shift = 16,
1121 .width = 8,
1122 },
1123 .p = {
1124 .pre_div_shift = 3,
1125 .pre_div_width = 2,
1126 },
1127 .s = {
1128 .src_sel_shift = 0,
1129 .parent_map = gcc_pxo_pll8_map,
1130 },
1131 .freq_tbl = clk_tbl_gsbi_qup,
1132 .clkr = {
1133 .enable_reg = 0x2acc,
1134 .enable_mask = BIT(11),
1135 .hw.init = &(struct clk_init_data){
1136 .name = "gsbi9_qup_src",
1137 .parent_names = gcc_pxo_pll8,
1138 .num_parents = 2,
1139 .ops = &clk_rcg_ops,
1140 .flags = CLK_SET_PARENT_GATE,
1141 },
1142 },
1143};
1144
1145static struct clk_branch gsbi9_qup_clk = {
1146 .halt_reg = 0x2fd0,
1147 .halt_bit = 4,
1148 .clkr = {
1149 .enable_reg = 0x2acc,
1150 .enable_mask = BIT(9),
1151 .hw.init = &(struct clk_init_data){
1152 .name = "gsbi9_qup_clk",
1153 .parent_names = (const char *[]){ "gsbi9_qup_src" },
1154 .num_parents = 1,
1155 .ops = &clk_branch_ops,
1156 .flags = CLK_SET_RATE_PARENT,
1157 },
1158 },
1159};
1160
1161static struct clk_rcg gsbi10_qup_src = {
1162 .ns_reg = 0x2aec,
1163 .md_reg = 0x2ae8,
1164 .mn = {
1165 .mnctr_en_bit = 8,
1166 .mnctr_reset_bit = 7,
1167 .mnctr_mode_shift = 5,
1168 .n_val_shift = 16,
1169 .m_val_shift = 16,
1170 .width = 8,
1171 },
1172 .p = {
1173 .pre_div_shift = 3,
1174 .pre_div_width = 2,
1175 },
1176 .s = {
1177 .src_sel_shift = 0,
1178 .parent_map = gcc_pxo_pll8_map,
1179 },
1180 .freq_tbl = clk_tbl_gsbi_qup,
1181 .clkr = {
1182 .enable_reg = 0x2aec,
1183 .enable_mask = BIT(11),
1184 .hw.init = &(struct clk_init_data){
1185 .name = "gsbi10_qup_src",
1186 .parent_names = gcc_pxo_pll8,
1187 .num_parents = 2,
1188 .ops = &clk_rcg_ops,
1189 .flags = CLK_SET_PARENT_GATE,
1190 },
1191 },
1192};
1193
1194static struct clk_branch gsbi10_qup_clk = {
1195 .halt_reg = 0x2fd0,
1196 .halt_bit = 0,
1197 .clkr = {
1198 .enable_reg = 0x2aec,
1199 .enable_mask = BIT(9),
1200 .hw.init = &(struct clk_init_data){
1201 .name = "gsbi10_qup_clk",
1202 .parent_names = (const char *[]){ "gsbi10_qup_src" },
1203 .num_parents = 1,
1204 .ops = &clk_branch_ops,
1205 .flags = CLK_SET_RATE_PARENT,
1206 },
1207 },
1208};
1209
1210static struct clk_rcg gsbi11_qup_src = {
1211 .ns_reg = 0x2b0c,
1212 .md_reg = 0x2b08,
1213 .mn = {
1214 .mnctr_en_bit = 8,
1215 .mnctr_reset_bit = 7,
1216 .mnctr_mode_shift = 5,
1217 .n_val_shift = 16,
1218 .m_val_shift = 16,
1219 .width = 8,
1220 },
1221 .p = {
1222 .pre_div_shift = 3,
1223 .pre_div_width = 2,
1224 },
1225 .s = {
1226 .src_sel_shift = 0,
1227 .parent_map = gcc_pxo_pll8_map,
1228 },
1229 .freq_tbl = clk_tbl_gsbi_qup,
1230 .clkr = {
1231 .enable_reg = 0x2b0c,
1232 .enable_mask = BIT(11),
1233 .hw.init = &(struct clk_init_data){
1234 .name = "gsbi11_qup_src",
1235 .parent_names = gcc_pxo_pll8,
1236 .num_parents = 2,
1237 .ops = &clk_rcg_ops,
1238 .flags = CLK_SET_PARENT_GATE,
1239 },
1240 },
1241};
1242
1243static struct clk_branch gsbi11_qup_clk = {
1244 .halt_reg = 0x2fd4,
1245 .halt_bit = 15,
1246 .clkr = {
1247 .enable_reg = 0x2b0c,
1248 .enable_mask = BIT(9),
1249 .hw.init = &(struct clk_init_data){
1250 .name = "gsbi11_qup_clk",
1251 .parent_names = (const char *[]){ "gsbi11_qup_src" },
1252 .num_parents = 1,
1253 .ops = &clk_branch_ops,
1254 .flags = CLK_SET_RATE_PARENT,
1255 },
1256 },
1257};
1258
1259static struct clk_rcg gsbi12_qup_src = {
1260 .ns_reg = 0x2b2c,
1261 .md_reg = 0x2b28,
1262 .mn = {
1263 .mnctr_en_bit = 8,
1264 .mnctr_reset_bit = 7,
1265 .mnctr_mode_shift = 5,
1266 .n_val_shift = 16,
1267 .m_val_shift = 16,
1268 .width = 8,
1269 },
1270 .p = {
1271 .pre_div_shift = 3,
1272 .pre_div_width = 2,
1273 },
1274 .s = {
1275 .src_sel_shift = 0,
1276 .parent_map = gcc_pxo_pll8_map,
1277 },
1278 .freq_tbl = clk_tbl_gsbi_qup,
1279 .clkr = {
1280 .enable_reg = 0x2b2c,
1281 .enable_mask = BIT(11),
1282 .hw.init = &(struct clk_init_data){
1283 .name = "gsbi12_qup_src",
1284 .parent_names = gcc_pxo_pll8,
1285 .num_parents = 2,
1286 .ops = &clk_rcg_ops,
1287 .flags = CLK_SET_PARENT_GATE,
1288 },
1289 },
1290};
1291
1292static struct clk_branch gsbi12_qup_clk = {
1293 .halt_reg = 0x2fd4,
1294 .halt_bit = 11,
1295 .clkr = {
1296 .enable_reg = 0x2b2c,
1297 .enable_mask = BIT(9),
1298 .hw.init = &(struct clk_init_data){
1299 .name = "gsbi12_qup_clk",
1300 .parent_names = (const char *[]){ "gsbi12_qup_src" },
1301 .num_parents = 1,
1302 .ops = &clk_branch_ops,
1303 .flags = CLK_SET_RATE_PARENT,
1304 },
1305 },
1306};
1307
1308static const struct freq_tbl clk_tbl_gp[] = {
1309 { 9600000, P_CXO, 2, 0, 0 },
1310 { 13500000, P_PXO, 2, 0, 0 },
1311 { 19200000, P_CXO, 1, 0, 0 },
1312 { 27000000, P_PXO, 1, 0, 0 },
1313 { 64000000, P_PLL8, 2, 1, 3 },
1314 { 76800000, P_PLL8, 1, 1, 5 },
1315 { 96000000, P_PLL8, 4, 0, 0 },
1316 { 128000000, P_PLL8, 3, 0, 0 },
1317 { 192000000, P_PLL8, 2, 0, 0 },
1318 { }
1319};
1320
1321static struct clk_rcg gp0_src = {
1322 .ns_reg = 0x2d24,
1323 .md_reg = 0x2d00,
1324 .mn = {
1325 .mnctr_en_bit = 8,
1326 .mnctr_reset_bit = 7,
1327 .mnctr_mode_shift = 5,
1328 .n_val_shift = 16,
1329 .m_val_shift = 16,
1330 .width = 8,
1331 },
1332 .p = {
1333 .pre_div_shift = 3,
1334 .pre_div_width = 2,
1335 },
1336 .s = {
1337 .src_sel_shift = 0,
1338 .parent_map = gcc_pxo_pll8_cxo_map,
1339 },
1340 .freq_tbl = clk_tbl_gp,
1341 .clkr = {
1342 .enable_reg = 0x2d24,
1343 .enable_mask = BIT(11),
1344 .hw.init = &(struct clk_init_data){
1345 .name = "gp0_src",
1346 .parent_names = gcc_pxo_pll8_cxo,
1347 .num_parents = 3,
1348 .ops = &clk_rcg_ops,
1349 .flags = CLK_SET_PARENT_GATE,
1350 },
1351 }
1352};
1353
1354static struct clk_branch gp0_clk = {
1355 .halt_reg = 0x2fd8,
1356 .halt_bit = 7,
1357 .clkr = {
1358 .enable_reg = 0x2d24,
1359 .enable_mask = BIT(9),
1360 .hw.init = &(struct clk_init_data){
1361 .name = "gp0_clk",
1362 .parent_names = (const char *[]){ "gp0_src" },
1363 .num_parents = 1,
1364 .ops = &clk_branch_ops,
1365 .flags = CLK_SET_RATE_PARENT,
1366 },
1367 },
1368};
1369
1370static struct clk_rcg gp1_src = {
1371 .ns_reg = 0x2d44,
1372 .md_reg = 0x2d40,
1373 .mn = {
1374 .mnctr_en_bit = 8,
1375 .mnctr_reset_bit = 7,
1376 .mnctr_mode_shift = 5,
1377 .n_val_shift = 16,
1378 .m_val_shift = 16,
1379 .width = 8,
1380 },
1381 .p = {
1382 .pre_div_shift = 3,
1383 .pre_div_width = 2,
1384 },
1385 .s = {
1386 .src_sel_shift = 0,
1387 .parent_map = gcc_pxo_pll8_cxo_map,
1388 },
1389 .freq_tbl = clk_tbl_gp,
1390 .clkr = {
1391 .enable_reg = 0x2d44,
1392 .enable_mask = BIT(11),
1393 .hw.init = &(struct clk_init_data){
1394 .name = "gp1_src",
1395 .parent_names = gcc_pxo_pll8_cxo,
1396 .num_parents = 3,
1397 .ops = &clk_rcg_ops,
1398 .flags = CLK_SET_RATE_GATE,
1399 },
1400 }
1401};
1402
1403static struct clk_branch gp1_clk = {
1404 .halt_reg = 0x2fd8,
1405 .halt_bit = 6,
1406 .clkr = {
1407 .enable_reg = 0x2d44,
1408 .enable_mask = BIT(9),
1409 .hw.init = &(struct clk_init_data){
1410 .name = "gp1_clk",
1411 .parent_names = (const char *[]){ "gp1_src" },
1412 .num_parents = 1,
1413 .ops = &clk_branch_ops,
1414 .flags = CLK_SET_RATE_PARENT,
1415 },
1416 },
1417};
1418
1419static struct clk_rcg gp2_src = {
1420 .ns_reg = 0x2d64,
1421 .md_reg = 0x2d60,
1422 .mn = {
1423 .mnctr_en_bit = 8,
1424 .mnctr_reset_bit = 7,
1425 .mnctr_mode_shift = 5,
1426 .n_val_shift = 16,
1427 .m_val_shift = 16,
1428 .width = 8,
1429 },
1430 .p = {
1431 .pre_div_shift = 3,
1432 .pre_div_width = 2,
1433 },
1434 .s = {
1435 .src_sel_shift = 0,
1436 .parent_map = gcc_pxo_pll8_cxo_map,
1437 },
1438 .freq_tbl = clk_tbl_gp,
1439 .clkr = {
1440 .enable_reg = 0x2d64,
1441 .enable_mask = BIT(11),
1442 .hw.init = &(struct clk_init_data){
1443 .name = "gp2_src",
1444 .parent_names = gcc_pxo_pll8_cxo,
1445 .num_parents = 3,
1446 .ops = &clk_rcg_ops,
1447 .flags = CLK_SET_RATE_GATE,
1448 },
1449 }
1450};
1451
1452static struct clk_branch gp2_clk = {
1453 .halt_reg = 0x2fd8,
1454 .halt_bit = 5,
1455 .clkr = {
1456 .enable_reg = 0x2d64,
1457 .enable_mask = BIT(9),
1458 .hw.init = &(struct clk_init_data){
1459 .name = "gp2_clk",
1460 .parent_names = (const char *[]){ "gp2_src" },
1461 .num_parents = 1,
1462 .ops = &clk_branch_ops,
1463 .flags = CLK_SET_RATE_PARENT,
1464 },
1465 },
1466};
1467
1468static struct clk_branch pmem_clk = {
1469 .hwcg_reg = 0x25a0,
1470 .hwcg_bit = 6,
1471 .halt_reg = 0x2fc8,
1472 .halt_bit = 20,
1473 .clkr = {
1474 .enable_reg = 0x25a0,
1475 .enable_mask = BIT(4),
1476 .hw.init = &(struct clk_init_data){
1477 .name = "pmem_clk",
1478 .ops = &clk_branch_ops,
1479 .flags = CLK_IS_ROOT,
1480 },
1481 },
1482};
1483
1484static struct clk_rcg prng_src = {
1485 .ns_reg = 0x2e80,
1486 .p = {
1487 .pre_div_shift = 3,
1488 .pre_div_width = 4,
1489 },
1490 .s = {
1491 .src_sel_shift = 0,
1492 .parent_map = gcc_pxo_pll8_map,
1493 },
1494 .clkr.hw = {
1495 .init = &(struct clk_init_data){
1496 .name = "prng_src",
1497 .parent_names = gcc_pxo_pll8,
1498 .num_parents = 2,
1499 .ops = &clk_rcg_ops,
1500 },
1501 },
1502};
1503
1504static struct clk_branch prng_clk = {
1505 .halt_reg = 0x2fd8,
1506 .halt_check = BRANCH_HALT_VOTED,
1507 .halt_bit = 10,
1508 .clkr = {
1509 .enable_reg = 0x3080,
1510 .enable_mask = BIT(10),
1511 .hw.init = &(struct clk_init_data){
1512 .name = "prng_clk",
1513 .parent_names = (const char *[]){ "prng_src" },
1514 .num_parents = 1,
1515 .ops = &clk_branch_ops,
1516 },
1517 },
1518};
1519
1520static const struct freq_tbl clk_tbl_sdc[] = {
1521 { 144000, P_PXO, 3, 2, 125 },
1522 { 400000, P_PLL8, 4, 1, 240 },
1523 { 16000000, P_PLL8, 4, 1, 6 },
1524 { 17070000, P_PLL8, 1, 2, 45 },
1525 { 20210000, P_PLL8, 1, 1, 19 },
1526 { 24000000, P_PLL8, 4, 1, 4 },
1527 { 48000000, P_PLL8, 4, 1, 2 },
1528 { }
1529};
1530
1531static struct clk_rcg sdc1_src = {
1532 .ns_reg = 0x282c,
1533 .md_reg = 0x2828,
1534 .mn = {
1535 .mnctr_en_bit = 8,
1536 .mnctr_reset_bit = 7,
1537 .mnctr_mode_shift = 5,
1538 .n_val_shift = 16,
1539 .m_val_shift = 16,
1540 .width = 8,
1541 },
1542 .p = {
1543 .pre_div_shift = 3,
1544 .pre_div_width = 2,
1545 },
1546 .s = {
1547 .src_sel_shift = 0,
1548 .parent_map = gcc_pxo_pll8_map,
1549 },
1550 .freq_tbl = clk_tbl_sdc,
1551 .clkr = {
1552 .enable_reg = 0x282c,
1553 .enable_mask = BIT(11),
1554 .hw.init = &(struct clk_init_data){
1555 .name = "sdc1_src",
1556 .parent_names = gcc_pxo_pll8,
1557 .num_parents = 2,
1558 .ops = &clk_rcg_ops,
1559 .flags = CLK_SET_RATE_GATE,
1560 },
1561 }
1562};
1563
1564static struct clk_branch sdc1_clk = {
1565 .halt_reg = 0x2fc8,
1566 .halt_bit = 6,
1567 .clkr = {
1568 .enable_reg = 0x282c,
1569 .enable_mask = BIT(9),
1570 .hw.init = &(struct clk_init_data){
1571 .name = "sdc1_clk",
1572 .parent_names = (const char *[]){ "sdc1_src" },
1573 .num_parents = 1,
1574 .ops = &clk_branch_ops,
1575 .flags = CLK_SET_RATE_PARENT,
1576 },
1577 },
1578};
1579
1580static struct clk_rcg sdc2_src = {
1581 .ns_reg = 0x284c,
1582 .md_reg = 0x2848,
1583 .mn = {
1584 .mnctr_en_bit = 8,
1585 .mnctr_reset_bit = 7,
1586 .mnctr_mode_shift = 5,
1587 .n_val_shift = 16,
1588 .m_val_shift = 16,
1589 .width = 8,
1590 },
1591 .p = {
1592 .pre_div_shift = 3,
1593 .pre_div_width = 2,
1594 },
1595 .s = {
1596 .src_sel_shift = 0,
1597 .parent_map = gcc_pxo_pll8_map,
1598 },
1599 .freq_tbl = clk_tbl_sdc,
1600 .clkr = {
1601 .enable_reg = 0x284c,
1602 .enable_mask = BIT(11),
1603 .hw.init = &(struct clk_init_data){
1604 .name = "sdc2_src",
1605 .parent_names = gcc_pxo_pll8,
1606 .num_parents = 2,
1607 .ops = &clk_rcg_ops,
1608 .flags = CLK_SET_RATE_GATE,
1609 },
1610 }
1611};
1612
1613static struct clk_branch sdc2_clk = {
1614 .halt_reg = 0x2fc8,
1615 .halt_bit = 5,
1616 .clkr = {
1617 .enable_reg = 0x284c,
1618 .enable_mask = BIT(9),
1619 .hw.init = &(struct clk_init_data){
1620 .name = "sdc2_clk",
1621 .parent_names = (const char *[]){ "sdc2_src" },
1622 .num_parents = 1,
1623 .ops = &clk_branch_ops,
1624 .flags = CLK_SET_RATE_PARENT,
1625 },
1626 },
1627};
1628
1629static struct clk_rcg sdc3_src = {
1630 .ns_reg = 0x286c,
1631 .md_reg = 0x2868,
1632 .mn = {
1633 .mnctr_en_bit = 8,
1634 .mnctr_reset_bit = 7,
1635 .mnctr_mode_shift = 5,
1636 .n_val_shift = 16,
1637 .m_val_shift = 16,
1638 .width = 8,
1639 },
1640 .p = {
1641 .pre_div_shift = 3,
1642 .pre_div_width = 2,
1643 },
1644 .s = {
1645 .src_sel_shift = 0,
1646 .parent_map = gcc_pxo_pll8_map,
1647 },
1648 .freq_tbl = clk_tbl_sdc,
1649 .clkr = {
1650 .enable_reg = 0x286c,
1651 .enable_mask = BIT(11),
1652 .hw.init = &(struct clk_init_data){
1653 .name = "sdc3_src",
1654 .parent_names = gcc_pxo_pll8,
1655 .num_parents = 2,
1656 .ops = &clk_rcg_ops,
1657 .flags = CLK_SET_RATE_GATE,
1658 },
1659 }
1660};
1661
1662static struct clk_branch sdc3_clk = {
1663 .halt_reg = 0x2fc8,
1664 .halt_bit = 4,
1665 .clkr = {
1666 .enable_reg = 0x286c,
1667 .enable_mask = BIT(9),
1668 .hw.init = &(struct clk_init_data){
1669 .name = "sdc3_clk",
1670 .parent_names = (const char *[]){ "sdc3_src" },
1671 .num_parents = 1,
1672 .ops = &clk_branch_ops,
1673 .flags = CLK_SET_RATE_PARENT,
1674 },
1675 },
1676};
1677
1678static struct clk_rcg sdc4_src = {
1679 .ns_reg = 0x288c,
1680 .md_reg = 0x2888,
1681 .mn = {
1682 .mnctr_en_bit = 8,
1683 .mnctr_reset_bit = 7,
1684 .mnctr_mode_shift = 5,
1685 .n_val_shift = 16,
1686 .m_val_shift = 16,
1687 .width = 8,
1688 },
1689 .p = {
1690 .pre_div_shift = 3,
1691 .pre_div_width = 2,
1692 },
1693 .s = {
1694 .src_sel_shift = 0,
1695 .parent_map = gcc_pxo_pll8_map,
1696 },
1697 .freq_tbl = clk_tbl_sdc,
1698 .clkr = {
1699 .enable_reg = 0x288c,
1700 .enable_mask = BIT(11),
1701 .hw.init = &(struct clk_init_data){
1702 .name = "sdc4_src",
1703 .parent_names = gcc_pxo_pll8,
1704 .num_parents = 2,
1705 .ops = &clk_rcg_ops,
1706 .flags = CLK_SET_RATE_GATE,
1707 },
1708 }
1709};
1710
1711static struct clk_branch sdc4_clk = {
1712 .halt_reg = 0x2fc8,
1713 .halt_bit = 3,
1714 .clkr = {
1715 .enable_reg = 0x288c,
1716 .enable_mask = BIT(9),
1717 .hw.init = &(struct clk_init_data){
1718 .name = "sdc4_clk",
1719 .parent_names = (const char *[]){ "sdc4_src" },
1720 .num_parents = 1,
1721 .ops = &clk_branch_ops,
1722 .flags = CLK_SET_RATE_PARENT,
1723 },
1724 },
1725};
1726
1727static struct clk_rcg sdc5_src = {
1728 .ns_reg = 0x28ac,
1729 .md_reg = 0x28a8,
1730 .mn = {
1731 .mnctr_en_bit = 8,
1732 .mnctr_reset_bit = 7,
1733 .mnctr_mode_shift = 5,
1734 .n_val_shift = 16,
1735 .m_val_shift = 16,
1736 .width = 8,
1737 },
1738 .p = {
1739 .pre_div_shift = 3,
1740 .pre_div_width = 2,
1741 },
1742 .s = {
1743 .src_sel_shift = 0,
1744 .parent_map = gcc_pxo_pll8_map,
1745 },
1746 .freq_tbl = clk_tbl_sdc,
1747 .clkr = {
1748 .enable_reg = 0x28ac,
1749 .enable_mask = BIT(11),
1750 .hw.init = &(struct clk_init_data){
1751 .name = "sdc5_src",
1752 .parent_names = gcc_pxo_pll8,
1753 .num_parents = 2,
1754 .ops = &clk_rcg_ops,
1755 .flags = CLK_SET_RATE_GATE,
1756 },
1757 }
1758};
1759
1760static struct clk_branch sdc5_clk = {
1761 .halt_reg = 0x2fc8,
1762 .halt_bit = 2,
1763 .clkr = {
1764 .enable_reg = 0x28ac,
1765 .enable_mask = BIT(9),
1766 .hw.init = &(struct clk_init_data){
1767 .name = "sdc5_clk",
1768 .parent_names = (const char *[]){ "sdc5_src" },
1769 .num_parents = 1,
1770 .ops = &clk_branch_ops,
1771 .flags = CLK_SET_RATE_PARENT,
1772 },
1773 },
1774};
1775
1776static const struct freq_tbl clk_tbl_tsif_ref[] = {
1777 { 105000, P_PXO, 1, 1, 256 },
1778 { }
1779};
1780
1781static struct clk_rcg tsif_ref_src = {
1782 .ns_reg = 0x2710,
1783 .md_reg = 0x270c,
1784 .mn = {
1785 .mnctr_en_bit = 8,
1786 .mnctr_reset_bit = 7,
1787 .mnctr_mode_shift = 5,
1788 .n_val_shift = 16,
1789 .m_val_shift = 16,
1790 .width = 16,
1791 },
1792 .p = {
1793 .pre_div_shift = 3,
1794 .pre_div_width = 2,
1795 },
1796 .s = {
1797 .src_sel_shift = 0,
1798 .parent_map = gcc_pxo_pll8_map,
1799 },
1800 .freq_tbl = clk_tbl_tsif_ref,
1801 .clkr = {
1802 .enable_reg = 0x2710,
1803 .enable_mask = BIT(11),
1804 .hw.init = &(struct clk_init_data){
1805 .name = "tsif_ref_src",
1806 .parent_names = gcc_pxo_pll8,
1807 .num_parents = 2,
1808 .ops = &clk_rcg_ops,
1809 .flags = CLK_SET_RATE_GATE,
1810 },
1811 }
1812};
1813
1814static struct clk_branch tsif_ref_clk = {
1815 .halt_reg = 0x2fd4,
1816 .halt_bit = 5,
1817 .clkr = {
1818 .enable_reg = 0x2710,
1819 .enable_mask = BIT(9),
1820 .hw.init = &(struct clk_init_data){
1821 .name = "tsif_ref_clk",
1822 .parent_names = (const char *[]){ "tsif_ref_src" },
1823 .num_parents = 1,
1824 .ops = &clk_branch_ops,
1825 .flags = CLK_SET_RATE_PARENT,
1826 },
1827 },
1828};
1829
1830static const struct freq_tbl clk_tbl_usb[] = {
1831 { 60000000, P_PLL8, 1, 5, 32 },
1832 { }
1833};
1834
1835static struct clk_rcg usb_hs1_xcvr_src = {
1836 .ns_reg = 0x290c,
1837 .md_reg = 0x2908,
1838 .mn = {
1839 .mnctr_en_bit = 8,
1840 .mnctr_reset_bit = 7,
1841 .mnctr_mode_shift = 5,
1842 .n_val_shift = 16,
1843 .m_val_shift = 16,
1844 .width = 8,
1845 },
1846 .p = {
1847 .pre_div_shift = 3,
1848 .pre_div_width = 2,
1849 },
1850 .s = {
1851 .src_sel_shift = 0,
1852 .parent_map = gcc_pxo_pll8_map,
1853 },
1854 .freq_tbl = clk_tbl_usb,
1855 .clkr = {
1856 .enable_reg = 0x290c,
1857 .enable_mask = BIT(11),
1858 .hw.init = &(struct clk_init_data){
1859 .name = "usb_hs1_xcvr_src",
1860 .parent_names = gcc_pxo_pll8,
1861 .num_parents = 2,
1862 .ops = &clk_rcg_ops,
1863 .flags = CLK_SET_RATE_GATE,
1864 },
1865 }
1866};
1867
1868static struct clk_branch usb_hs1_xcvr_clk = {
1869 .halt_reg = 0x2fc8,
1870 .halt_bit = 0,
1871 .clkr = {
1872 .enable_reg = 0x290c,
1873 .enable_mask = BIT(9),
1874 .hw.init = &(struct clk_init_data){
1875 .name = "usb_hs1_xcvr_clk",
1876 .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
1877 .num_parents = 1,
1878 .ops = &clk_branch_ops,
1879 .flags = CLK_SET_RATE_PARENT,
1880 },
1881 },
1882};
1883
1884static struct clk_rcg usb_fs1_xcvr_fs_src = {
1885 .ns_reg = 0x2968,
1886 .md_reg = 0x2964,
1887 .mn = {
1888 .mnctr_en_bit = 8,
1889 .mnctr_reset_bit = 7,
1890 .mnctr_mode_shift = 5,
1891 .n_val_shift = 16,
1892 .m_val_shift = 16,
1893 .width = 8,
1894 },
1895 .p = {
1896 .pre_div_shift = 3,
1897 .pre_div_width = 2,
1898 },
1899 .s = {
1900 .src_sel_shift = 0,
1901 .parent_map = gcc_pxo_pll8_map,
1902 },
1903 .freq_tbl = clk_tbl_usb,
1904 .clkr = {
1905 .enable_reg = 0x2968,
1906 .enable_mask = BIT(11),
1907 .hw.init = &(struct clk_init_data){
1908 .name = "usb_fs1_xcvr_fs_src",
1909 .parent_names = gcc_pxo_pll8,
1910 .num_parents = 2,
1911 .ops = &clk_rcg_ops,
1912 .flags = CLK_SET_RATE_GATE,
1913 },
1914 }
1915};
1916
1917static const char *usb_fs1_xcvr_fs_src_p[] = { "usb_fs1_xcvr_fs_src" };
1918
1919static struct clk_branch usb_fs1_xcvr_fs_clk = {
1920 .halt_reg = 0x2fcc,
1921 .halt_bit = 15,
1922 .clkr = {
1923 .enable_reg = 0x2968,
1924 .enable_mask = BIT(9),
1925 .hw.init = &(struct clk_init_data){
1926 .name = "usb_fs1_xcvr_fs_clk",
1927 .parent_names = usb_fs1_xcvr_fs_src_p,
1928 .num_parents = 1,
1929 .ops = &clk_branch_ops,
1930 .flags = CLK_SET_RATE_PARENT,
1931 },
1932 },
1933};
1934
1935static struct clk_branch usb_fs1_system_clk = {
1936 .halt_reg = 0x2fcc,
1937 .halt_bit = 16,
1938 .clkr = {
1939 .enable_reg = 0x296c,
1940 .enable_mask = BIT(4),
1941 .hw.init = &(struct clk_init_data){
1942 .parent_names = usb_fs1_xcvr_fs_src_p,
1943 .num_parents = 1,
1944 .name = "usb_fs1_system_clk",
1945 .ops = &clk_branch_ops,
1946 .flags = CLK_SET_RATE_PARENT,
1947 },
1948 },
1949};
1950
1951static struct clk_rcg usb_fs2_xcvr_fs_src = {
1952 .ns_reg = 0x2988,
1953 .md_reg = 0x2984,
1954 .mn = {
1955 .mnctr_en_bit = 8,
1956 .mnctr_reset_bit = 7,
1957 .mnctr_mode_shift = 5,
1958 .n_val_shift = 16,
1959 .m_val_shift = 16,
1960 .width = 8,
1961 },
1962 .p = {
1963 .pre_div_shift = 3,
1964 .pre_div_width = 2,
1965 },
1966 .s = {
1967 .src_sel_shift = 0,
1968 .parent_map = gcc_pxo_pll8_map,
1969 },
1970 .freq_tbl = clk_tbl_usb,
1971 .clkr = {
1972 .enable_reg = 0x2988,
1973 .enable_mask = BIT(11),
1974 .hw.init = &(struct clk_init_data){
1975 .name = "usb_fs2_xcvr_fs_src",
1976 .parent_names = gcc_pxo_pll8,
1977 .num_parents = 2,
1978 .ops = &clk_rcg_ops,
1979 .flags = CLK_SET_RATE_GATE,
1980 },
1981 }
1982};
1983
1984static const char *usb_fs2_xcvr_fs_src_p[] = { "usb_fs2_xcvr_fs_src" };
1985
1986static struct clk_branch usb_fs2_xcvr_fs_clk = {
1987 .halt_reg = 0x2fcc,
1988 .halt_bit = 12,
1989 .clkr = {
1990 .enable_reg = 0x2988,
1991 .enable_mask = BIT(9),
1992 .hw.init = &(struct clk_init_data){
1993 .name = "usb_fs2_xcvr_fs_clk",
1994 .parent_names = usb_fs2_xcvr_fs_src_p,
1995 .num_parents = 1,
1996 .ops = &clk_branch_ops,
1997 .flags = CLK_SET_RATE_PARENT,
1998 },
1999 },
2000};
2001
2002static struct clk_branch usb_fs2_system_clk = {
2003 .halt_reg = 0x2fcc,
2004 .halt_bit = 13,
2005 .clkr = {
2006 .enable_reg = 0x298c,
2007 .enable_mask = BIT(4),
2008 .hw.init = &(struct clk_init_data){
2009 .name = "usb_fs2_system_clk",
2010 .parent_names = usb_fs2_xcvr_fs_src_p,
2011 .num_parents = 1,
2012 .ops = &clk_branch_ops,
2013 .flags = CLK_SET_RATE_PARENT,
2014 },
2015 },
2016};
2017
2018static struct clk_branch gsbi1_h_clk = {
2019 .halt_reg = 0x2fcc,
2020 .halt_bit = 11,
2021 .clkr = {
2022 .enable_reg = 0x29c0,
2023 .enable_mask = BIT(4),
2024 .hw.init = &(struct clk_init_data){
2025 .name = "gsbi1_h_clk",
2026 .ops = &clk_branch_ops,
2027 .flags = CLK_IS_ROOT,
2028 },
2029 },
2030};
2031
2032static struct clk_branch gsbi2_h_clk = {
2033 .halt_reg = 0x2fcc,
2034 .halt_bit = 7,
2035 .clkr = {
2036 .enable_reg = 0x29e0,
2037 .enable_mask = BIT(4),
2038 .hw.init = &(struct clk_init_data){
2039 .name = "gsbi2_h_clk",
2040 .ops = &clk_branch_ops,
2041 .flags = CLK_IS_ROOT,
2042 },
2043 },
2044};
2045
2046static struct clk_branch gsbi3_h_clk = {
2047 .halt_reg = 0x2fcc,
2048 .halt_bit = 3,
2049 .clkr = {
2050 .enable_reg = 0x2a00,
2051 .enable_mask = BIT(4),
2052 .hw.init = &(struct clk_init_data){
2053 .name = "gsbi3_h_clk",
2054 .ops = &clk_branch_ops,
2055 .flags = CLK_IS_ROOT,
2056 },
2057 },
2058};
2059
2060static struct clk_branch gsbi4_h_clk = {
2061 .halt_reg = 0x2fd0,
2062 .halt_bit = 27,
2063 .clkr = {
2064 .enable_reg = 0x2a20,
2065 .enable_mask = BIT(4),
2066 .hw.init = &(struct clk_init_data){
2067 .name = "gsbi4_h_clk",
2068 .ops = &clk_branch_ops,
2069 .flags = CLK_IS_ROOT,
2070 },
2071 },
2072};
2073
2074static struct clk_branch gsbi5_h_clk = {
2075 .halt_reg = 0x2fd0,
2076 .halt_bit = 23,
2077 .clkr = {
2078 .enable_reg = 0x2a40,
2079 .enable_mask = BIT(4),
2080 .hw.init = &(struct clk_init_data){
2081 .name = "gsbi5_h_clk",
2082 .ops = &clk_branch_ops,
2083 .flags = CLK_IS_ROOT,
2084 },
2085 },
2086};
2087
2088static struct clk_branch gsbi6_h_clk = {
2089 .halt_reg = 0x2fd0,
2090 .halt_bit = 19,
2091 .clkr = {
2092 .enable_reg = 0x2a60,
2093 .enable_mask = BIT(4),
2094 .hw.init = &(struct clk_init_data){
2095 .name = "gsbi6_h_clk",
2096 .ops = &clk_branch_ops,
2097 .flags = CLK_IS_ROOT,
2098 },
2099 },
2100};
2101
2102static struct clk_branch gsbi7_h_clk = {
2103 .halt_reg = 0x2fd0,
2104 .halt_bit = 15,
2105 .clkr = {
2106 .enable_reg = 0x2a80,
2107 .enable_mask = BIT(4),
2108 .hw.init = &(struct clk_init_data){
2109 .name = "gsbi7_h_clk",
2110 .ops = &clk_branch_ops,
2111 .flags = CLK_IS_ROOT,
2112 },
2113 },
2114};
2115
2116static struct clk_branch gsbi8_h_clk = {
2117 .halt_reg = 0x2fd0,
2118 .halt_bit = 11,
2119 .clkr = {
2120 .enable_reg = 0x2aa0,
2121 .enable_mask = BIT(4),
2122 .hw.init = &(struct clk_init_data){
2123 .name = "gsbi8_h_clk",
2124 .ops = &clk_branch_ops,
2125 .flags = CLK_IS_ROOT,
2126 },
2127 },
2128};
2129
2130static struct clk_branch gsbi9_h_clk = {
2131 .halt_reg = 0x2fd0,
2132 .halt_bit = 7,
2133 .clkr = {
2134 .enable_reg = 0x2ac0,
2135 .enable_mask = BIT(4),
2136 .hw.init = &(struct clk_init_data){
2137 .name = "gsbi9_h_clk",
2138 .ops = &clk_branch_ops,
2139 .flags = CLK_IS_ROOT,
2140 },
2141 },
2142};
2143
2144static struct clk_branch gsbi10_h_clk = {
2145 .halt_reg = 0x2fd0,
2146 .halt_bit = 3,
2147 .clkr = {
2148 .enable_reg = 0x2ae0,
2149 .enable_mask = BIT(4),
2150 .hw.init = &(struct clk_init_data){
2151 .name = "gsbi10_h_clk",
2152 .ops = &clk_branch_ops,
2153 .flags = CLK_IS_ROOT,
2154 },
2155 },
2156};
2157
2158static struct clk_branch gsbi11_h_clk = {
2159 .halt_reg = 0x2fd4,
2160 .halt_bit = 18,
2161 .clkr = {
2162 .enable_reg = 0x2b00,
2163 .enable_mask = BIT(4),
2164 .hw.init = &(struct clk_init_data){
2165 .name = "gsbi11_h_clk",
2166 .ops = &clk_branch_ops,
2167 .flags = CLK_IS_ROOT,
2168 },
2169 },
2170};
2171
2172static struct clk_branch gsbi12_h_clk = {
2173 .halt_reg = 0x2fd4,
2174 .halt_bit = 14,
2175 .clkr = {
2176 .enable_reg = 0x2b20,
2177 .enable_mask = BIT(4),
2178 .hw.init = &(struct clk_init_data){
2179 .name = "gsbi12_h_clk",
2180 .ops = &clk_branch_ops,
2181 .flags = CLK_IS_ROOT,
2182 },
2183 },
2184};
2185
2186static struct clk_branch tsif_h_clk = {
2187 .halt_reg = 0x2fd4,
2188 .halt_bit = 7,
2189 .clkr = {
2190 .enable_reg = 0x2700,
2191 .enable_mask = BIT(4),
2192 .hw.init = &(struct clk_init_data){
2193 .name = "tsif_h_clk",
2194 .ops = &clk_branch_ops,
2195 .flags = CLK_IS_ROOT,
2196 },
2197 },
2198};
2199
2200static struct clk_branch usb_fs1_h_clk = {
2201 .halt_reg = 0x2fcc,
2202 .halt_bit = 17,
2203 .clkr = {
2204 .enable_reg = 0x2960,
2205 .enable_mask = BIT(4),
2206 .hw.init = &(struct clk_init_data){
2207 .name = "usb_fs1_h_clk",
2208 .ops = &clk_branch_ops,
2209 .flags = CLK_IS_ROOT,
2210 },
2211 },
2212};
2213
2214static struct clk_branch usb_fs2_h_clk = {
2215 .halt_reg = 0x2fcc,
2216 .halt_bit = 14,
2217 .clkr = {
2218 .enable_reg = 0x2980,
2219 .enable_mask = BIT(4),
2220 .hw.init = &(struct clk_init_data){
2221 .name = "usb_fs2_h_clk",
2222 .ops = &clk_branch_ops,
2223 .flags = CLK_IS_ROOT,
2224 },
2225 },
2226};
2227
2228static struct clk_branch usb_hs1_h_clk = {
2229 .halt_reg = 0x2fc8,
2230 .halt_bit = 1,
2231 .clkr = {
2232 .enable_reg = 0x2900,
2233 .enable_mask = BIT(4),
2234 .hw.init = &(struct clk_init_data){
2235 .name = "usb_hs1_h_clk",
2236 .ops = &clk_branch_ops,
2237 .flags = CLK_IS_ROOT,
2238 },
2239 },
2240};
2241
2242static struct clk_branch sdc1_h_clk = {
2243 .halt_reg = 0x2fc8,
2244 .halt_bit = 11,
2245 .clkr = {
2246 .enable_reg = 0x2820,
2247 .enable_mask = BIT(4),
2248 .hw.init = &(struct clk_init_data){
2249 .name = "sdc1_h_clk",
2250 .ops = &clk_branch_ops,
2251 .flags = CLK_IS_ROOT,
2252 },
2253 },
2254};
2255
2256static struct clk_branch sdc2_h_clk = {
2257 .halt_reg = 0x2fc8,
2258 .halt_bit = 10,
2259 .clkr = {
2260 .enable_reg = 0x2840,
2261 .enable_mask = BIT(4),
2262 .hw.init = &(struct clk_init_data){
2263 .name = "sdc2_h_clk",
2264 .ops = &clk_branch_ops,
2265 .flags = CLK_IS_ROOT,
2266 },
2267 },
2268};
2269
2270static struct clk_branch sdc3_h_clk = {
2271 .halt_reg = 0x2fc8,
2272 .halt_bit = 9,
2273 .clkr = {
2274 .enable_reg = 0x2860,
2275 .enable_mask = BIT(4),
2276 .hw.init = &(struct clk_init_data){
2277 .name = "sdc3_h_clk",
2278 .ops = &clk_branch_ops,
2279 .flags = CLK_IS_ROOT,
2280 },
2281 },
2282};
2283
2284static struct clk_branch sdc4_h_clk = {
2285 .halt_reg = 0x2fc8,
2286 .halt_bit = 8,
2287 .clkr = {
2288 .enable_reg = 0x2880,
2289 .enable_mask = BIT(4),
2290 .hw.init = &(struct clk_init_data){
2291 .name = "sdc4_h_clk",
2292 .ops = &clk_branch_ops,
2293 .flags = CLK_IS_ROOT,
2294 },
2295 },
2296};
2297
2298static struct clk_branch sdc5_h_clk = {
2299 .halt_reg = 0x2fc8,
2300 .halt_bit = 7,
2301 .clkr = {
2302 .enable_reg = 0x28a0,
2303 .enable_mask = BIT(4),
2304 .hw.init = &(struct clk_init_data){
2305 .name = "sdc5_h_clk",
2306 .ops = &clk_branch_ops,
2307 .flags = CLK_IS_ROOT,
2308 },
2309 },
2310};
2311
2312static struct clk_branch adm0_clk = {
2313 .halt_reg = 0x2fdc,
2314 .halt_check = BRANCH_HALT_VOTED,
2315 .halt_bit = 14,
2316 .clkr = {
2317 .enable_reg = 0x3080,
2318 .enable_mask = BIT(2),
2319 .hw.init = &(struct clk_init_data){
2320 .name = "adm0_clk",
2321 .ops = &clk_branch_ops,
2322 .flags = CLK_IS_ROOT,
2323 },
2324 },
2325};
2326
2327static struct clk_branch adm0_pbus_clk = {
2328 .halt_reg = 0x2fdc,
2329 .halt_check = BRANCH_HALT_VOTED,
2330 .halt_bit = 13,
2331 .clkr = {
2332 .enable_reg = 0x3080,
2333 .enable_mask = BIT(3),
2334 .hw.init = &(struct clk_init_data){
2335 .name = "adm0_pbus_clk",
2336 .ops = &clk_branch_ops,
2337 .flags = CLK_IS_ROOT,
2338 },
2339 },
2340};
2341
2342static struct clk_branch adm1_clk = {
2343 .halt_reg = 0x2fdc,
2344 .halt_bit = 12,
2345 .halt_check = BRANCH_HALT_VOTED,
2346 .clkr = {
2347 .enable_reg = 0x3080,
2348 .enable_mask = BIT(4),
2349 .hw.init = &(struct clk_init_data){
2350 .name = "adm1_clk",
2351 .ops = &clk_branch_ops,
2352 .flags = CLK_IS_ROOT,
2353 },
2354 },
2355};
2356
2357static struct clk_branch adm1_pbus_clk = {
2358 .halt_reg = 0x2fdc,
2359 .halt_bit = 11,
2360 .halt_check = BRANCH_HALT_VOTED,
2361 .clkr = {
2362 .enable_reg = 0x3080,
2363 .enable_mask = BIT(5),
2364 .hw.init = &(struct clk_init_data){
2365 .name = "adm1_pbus_clk",
2366 .ops = &clk_branch_ops,
2367 .flags = CLK_IS_ROOT,
2368 },
2369 },
2370};
2371
2372static struct clk_branch modem_ahb1_h_clk = {
2373 .halt_reg = 0x2fdc,
2374 .halt_bit = 8,
2375 .halt_check = BRANCH_HALT_VOTED,
2376 .clkr = {
2377 .enable_reg = 0x3080,
2378 .enable_mask = BIT(0),
2379 .hw.init = &(struct clk_init_data){
2380 .name = "modem_ahb1_h_clk",
2381 .ops = &clk_branch_ops,
2382 .flags = CLK_IS_ROOT,
2383 },
2384 },
2385};
2386
2387static struct clk_branch modem_ahb2_h_clk = {
2388 .halt_reg = 0x2fdc,
2389 .halt_bit = 7,
2390 .halt_check = BRANCH_HALT_VOTED,
2391 .clkr = {
2392 .enable_reg = 0x3080,
2393 .enable_mask = BIT(1),
2394 .hw.init = &(struct clk_init_data){
2395 .name = "modem_ahb2_h_clk",
2396 .ops = &clk_branch_ops,
2397 .flags = CLK_IS_ROOT,
2398 },
2399 },
2400};
2401
2402static struct clk_branch pmic_arb0_h_clk = {
2403 .halt_reg = 0x2fd8,
2404 .halt_check = BRANCH_HALT_VOTED,
2405 .halt_bit = 22,
2406 .clkr = {
2407 .enable_reg = 0x3080,
2408 .enable_mask = BIT(8),
2409 .hw.init = &(struct clk_init_data){
2410 .name = "pmic_arb0_h_clk",
2411 .ops = &clk_branch_ops,
2412 .flags = CLK_IS_ROOT,
2413 },
2414 },
2415};
2416
2417static struct clk_branch pmic_arb1_h_clk = {
2418 .halt_reg = 0x2fd8,
2419 .halt_check = BRANCH_HALT_VOTED,
2420 .halt_bit = 21,
2421 .clkr = {
2422 .enable_reg = 0x3080,
2423 .enable_mask = BIT(9),
2424 .hw.init = &(struct clk_init_data){
2425 .name = "pmic_arb1_h_clk",
2426 .ops = &clk_branch_ops,
2427 .flags = CLK_IS_ROOT,
2428 },
2429 },
2430};
2431
2432static struct clk_branch pmic_ssbi2_clk = {
2433 .halt_reg = 0x2fd8,
2434 .halt_check = BRANCH_HALT_VOTED,
2435 .halt_bit = 23,
2436 .clkr = {
2437 .enable_reg = 0x3080,
2438 .enable_mask = BIT(7),
2439 .hw.init = &(struct clk_init_data){
2440 .name = "pmic_ssbi2_clk",
2441 .ops = &clk_branch_ops,
2442 .flags = CLK_IS_ROOT,
2443 },
2444 },
2445};
2446
2447static struct clk_branch rpm_msg_ram_h_clk = {
2448 .hwcg_reg = 0x27e0,
2449 .hwcg_bit = 6,
2450 .halt_reg = 0x2fd8,
2451 .halt_check = BRANCH_HALT_VOTED,
2452 .halt_bit = 12,
2453 .clkr = {
2454 .enable_reg = 0x3080,
2455 .enable_mask = BIT(6),
2456 .hw.init = &(struct clk_init_data){
2457 .name = "rpm_msg_ram_h_clk",
2458 .ops = &clk_branch_ops,
2459 .flags = CLK_IS_ROOT,
2460 },
2461 },
2462};
2463
2464static struct clk_regmap *gcc_msm8660_clks[] = {
2465 [PLL8] = &pll8.clkr,
2466 [PLL8_VOTE] = &pll8_vote,
2467 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
2468 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
2469 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
2470 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
2471 [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
2472 [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
2473 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
2474 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
2475 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
2476 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
2477 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
2478 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
2479 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
2480 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
2481 [GSBI8_UART_SRC] = &gsbi8_uart_src.clkr,
2482 [GSBI8_UART_CLK] = &gsbi8_uart_clk.clkr,
2483 [GSBI9_UART_SRC] = &gsbi9_uart_src.clkr,
2484 [GSBI9_UART_CLK] = &gsbi9_uart_clk.clkr,
2485 [GSBI10_UART_SRC] = &gsbi10_uart_src.clkr,
2486 [GSBI10_UART_CLK] = &gsbi10_uart_clk.clkr,
2487 [GSBI11_UART_SRC] = &gsbi11_uart_src.clkr,
2488 [GSBI11_UART_CLK] = &gsbi11_uart_clk.clkr,
2489 [GSBI12_UART_SRC] = &gsbi12_uart_src.clkr,
2490 [GSBI12_UART_CLK] = &gsbi12_uart_clk.clkr,
2491 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
2492 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
2493 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
2494 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
2495 [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
2496 [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
2497 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
2498 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
2499 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
2500 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
2501 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
2502 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
2503 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
2504 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
2505 [GSBI8_QUP_SRC] = &gsbi8_qup_src.clkr,
2506 [GSBI8_QUP_CLK] = &gsbi8_qup_clk.clkr,
2507 [GSBI9_QUP_SRC] = &gsbi9_qup_src.clkr,
2508 [GSBI9_QUP_CLK] = &gsbi9_qup_clk.clkr,
2509 [GSBI10_QUP_SRC] = &gsbi10_qup_src.clkr,
2510 [GSBI10_QUP_CLK] = &gsbi10_qup_clk.clkr,
2511 [GSBI11_QUP_SRC] = &gsbi11_qup_src.clkr,
2512 [GSBI11_QUP_CLK] = &gsbi11_qup_clk.clkr,
2513 [GSBI12_QUP_SRC] = &gsbi12_qup_src.clkr,
2514 [GSBI12_QUP_CLK] = &gsbi12_qup_clk.clkr,
2515 [GP0_SRC] = &gp0_src.clkr,
2516 [GP0_CLK] = &gp0_clk.clkr,
2517 [GP1_SRC] = &gp1_src.clkr,
2518 [GP1_CLK] = &gp1_clk.clkr,
2519 [GP2_SRC] = &gp2_src.clkr,
2520 [GP2_CLK] = &gp2_clk.clkr,
2521 [PMEM_CLK] = &pmem_clk.clkr,
2522 [PRNG_SRC] = &prng_src.clkr,
2523 [PRNG_CLK] = &prng_clk.clkr,
2524 [SDC1_SRC] = &sdc1_src.clkr,
2525 [SDC1_CLK] = &sdc1_clk.clkr,
2526 [SDC2_SRC] = &sdc2_src.clkr,
2527 [SDC2_CLK] = &sdc2_clk.clkr,
2528 [SDC3_SRC] = &sdc3_src.clkr,
2529 [SDC3_CLK] = &sdc3_clk.clkr,
2530 [SDC4_SRC] = &sdc4_src.clkr,
2531 [SDC4_CLK] = &sdc4_clk.clkr,
2532 [SDC5_SRC] = &sdc5_src.clkr,
2533 [SDC5_CLK] = &sdc5_clk.clkr,
2534 [TSIF_REF_SRC] = &tsif_ref_src.clkr,
2535 [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
2536 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
2537 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
2538 [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
2539 [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
2540 [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
2541 [USB_FS2_XCVR_FS_SRC] = &usb_fs2_xcvr_fs_src.clkr,
2542 [USB_FS2_XCVR_FS_CLK] = &usb_fs2_xcvr_fs_clk.clkr,
2543 [USB_FS2_SYSTEM_CLK] = &usb_fs2_system_clk.clkr,
2544 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
2545 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
2546 [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
2547 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
2548 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
2549 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
2550 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
2551 [GSBI8_H_CLK] = &gsbi8_h_clk.clkr,
2552 [GSBI9_H_CLK] = &gsbi9_h_clk.clkr,
2553 [GSBI10_H_CLK] = &gsbi10_h_clk.clkr,
2554 [GSBI11_H_CLK] = &gsbi11_h_clk.clkr,
2555 [GSBI12_H_CLK] = &gsbi12_h_clk.clkr,
2556 [TSIF_H_CLK] = &tsif_h_clk.clkr,
2557 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
2558 [USB_FS2_H_CLK] = &usb_fs2_h_clk.clkr,
2559 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
2560 [SDC1_H_CLK] = &sdc1_h_clk.clkr,
2561 [SDC2_H_CLK] = &sdc2_h_clk.clkr,
2562 [SDC3_H_CLK] = &sdc3_h_clk.clkr,
2563 [SDC4_H_CLK] = &sdc4_h_clk.clkr,
2564 [SDC5_H_CLK] = &sdc5_h_clk.clkr,
2565 [ADM0_CLK] = &adm0_clk.clkr,
2566 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
2567 [ADM1_CLK] = &adm1_clk.clkr,
2568 [ADM1_PBUS_CLK] = &adm1_pbus_clk.clkr,
2569 [MODEM_AHB1_H_CLK] = &modem_ahb1_h_clk.clkr,
2570 [MODEM_AHB2_H_CLK] = &modem_ahb2_h_clk.clkr,
2571 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
2572 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
2573 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
2574 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
2575};
2576
2577static const struct qcom_reset_map gcc_msm8660_resets[] = {
2578 [AFAB_CORE_RESET] = { 0x2080, 7 },
2579 [SCSS_SYS_RESET] = { 0x20b4, 1 },
2580 [SCSS_SYS_POR_RESET] = { 0x20b4 },
2581 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
2582 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
2583 [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
2584 [AFAB_EBI1_S_RESET] = { 0x20c0, 7 },
2585 [SFAB_CORE_RESET] = { 0x2120, 7 },
2586 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
2587 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
2588 [SFAB_ADM0_M2_RESET] = { 0x21e4, 7 },
2589 [ADM0_C2_RESET] = { 0x220c, 4 },
2590 [ADM0_C1_RESET] = { 0x220c, 3 },
2591 [ADM0_C0_RESET] = { 0x220c, 2 },
2592 [ADM0_PBUS_RESET] = { 0x220c, 1 },
2593 [ADM0_RESET] = { 0x220c },
2594 [SFAB_ADM1_M0_RESET] = { 0x2220, 7 },
2595 [SFAB_ADM1_M1_RESET] = { 0x2224, 7 },
2596 [SFAB_ADM1_M2_RESET] = { 0x2228, 7 },
2597 [MMFAB_ADM1_M3_RESET] = { 0x2240, 7 },
2598 [ADM1_C3_RESET] = { 0x226c, 5 },
2599 [ADM1_C2_RESET] = { 0x226c, 4 },
2600 [ADM1_C1_RESET] = { 0x226c, 3 },
2601 [ADM1_C0_RESET] = { 0x226c, 2 },
2602 [ADM1_PBUS_RESET] = { 0x226c, 1 },
2603 [ADM1_RESET] = { 0x226c },
2604 [IMEM0_RESET] = { 0x2280, 7 },
2605 [SFAB_LPASS_Q6_RESET] = { 0x23a0, 7 },
2606 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
2607 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
2608 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
2609 [DFAB_CORE_RESET] = { 0x24ac, 7 },
2610 [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
2611 [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
2612 [DFAB_SWAY0_RESET] = { 0x2540, 7 },
2613 [DFAB_SWAY1_RESET] = { 0x2544, 7 },
2614 [DFAB_ARB0_RESET] = { 0x2560, 7 },
2615 [DFAB_ARB1_RESET] = { 0x2564, 7 },
2616 [PPSS_PROC_RESET] = { 0x2594, 1 },
2617 [PPSS_RESET] = { 0x2594 },
2618 [PMEM_RESET] = { 0x25a0, 7 },
2619 [DMA_BAM_RESET] = { 0x25c0, 7 },
2620 [SIC_RESET] = { 0x25e0, 7 },
2621 [SPS_TIC_RESET] = { 0x2600, 7 },
2622 [CFBP0_RESET] = { 0x2650, 7 },
2623 [CFBP1_RESET] = { 0x2654, 7 },
2624 [CFBP2_RESET] = { 0x2658, 7 },
2625 [EBI2_RESET] = { 0x2664, 7 },
2626 [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
2627 [CFPB_MASTER_RESET] = { 0x26a0, 7 },
2628 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
2629 [CFPB_SPLITTER_RESET] = { 0x26e0, 7 },
2630 [TSIF_RESET] = { 0x2700, 7 },
2631 [CE1_RESET] = { 0x2720, 7 },
2632 [CE2_RESET] = { 0x2740, 7 },
2633 [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
2634 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
2635 [RPM_PROC_RESET] = { 0x27c0, 7 },
2636 [RPM_BUS_RESET] = { 0x27c4, 7 },
2637 [RPM_MSG_RAM_RESET] = { 0x27e0, 7 },
2638 [PMIC_ARB0_RESET] = { 0x2800, 7 },
2639 [PMIC_ARB1_RESET] = { 0x2804, 7 },
2640 [PMIC_SSBI2_RESET] = { 0x280c, 12 },
2641 [SDC1_RESET] = { 0x2830 },
2642 [SDC2_RESET] = { 0x2850 },
2643 [SDC3_RESET] = { 0x2870 },
2644 [SDC4_RESET] = { 0x2890 },
2645 [SDC5_RESET] = { 0x28b0 },
2646 [USB_HS1_RESET] = { 0x2910 },
2647 [USB_HS2_XCVR_RESET] = { 0x2934, 1 },
2648 [USB_HS2_RESET] = { 0x2934 },
2649 [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
2650 [USB_FS1_RESET] = { 0x2974 },
2651 [USB_FS2_XCVR_RESET] = { 0x2994, 1 },
2652 [USB_FS2_RESET] = { 0x2994 },
2653 [GSBI1_RESET] = { 0x29dc },
2654 [GSBI2_RESET] = { 0x29fc },
2655 [GSBI3_RESET] = { 0x2a1c },
2656 [GSBI4_RESET] = { 0x2a3c },
2657 [GSBI5_RESET] = { 0x2a5c },
2658 [GSBI6_RESET] = { 0x2a7c },
2659 [GSBI7_RESET] = { 0x2a9c },
2660 [GSBI8_RESET] = { 0x2abc },
2661 [GSBI9_RESET] = { 0x2adc },
2662 [GSBI10_RESET] = { 0x2afc },
2663 [GSBI11_RESET] = { 0x2b1c },
2664 [GSBI12_RESET] = { 0x2b3c },
2665 [SPDM_RESET] = { 0x2b6c },
2666 [SEC_CTRL_RESET] = { 0x2b80, 7 },
2667 [TLMM_H_RESET] = { 0x2ba0, 7 },
2668 [TLMM_RESET] = { 0x2ba4, 7 },
2669 [MARRM_PWRON_RESET] = { 0x2bd4, 1 },
2670 [MARM_RESET] = { 0x2bd4 },
2671 [MAHB1_RESET] = { 0x2be4, 7 },
2672 [SFAB_MSS_S_RESET] = { 0x2c00, 7 },
2673 [MAHB2_RESET] = { 0x2c20, 7 },
2674 [MODEM_SW_AHB_RESET] = { 0x2c48, 1 },
2675 [MODEM_RESET] = { 0x2c48 },
2676 [SFAB_MSS_MDM1_RESET] = { 0x2c4c, 1 },
2677 [SFAB_MSS_MDM0_RESET] = { 0x2c4c },
2678 [MSS_SLP_RESET] = { 0x2c60, 7 },
2679 [MSS_MARM_SAW_RESET] = { 0x2c68, 1 },
2680 [MSS_WDOG_RESET] = { 0x2c68 },
2681 [TSSC_RESET] = { 0x2ca0, 7 },
2682 [PDM_RESET] = { 0x2cc0, 12 },
2683 [SCSS_CORE0_RESET] = { 0x2d60, 1 },
2684 [SCSS_CORE0_POR_RESET] = { 0x2d60 },
2685 [SCSS_CORE1_RESET] = { 0x2d80, 1 },
2686 [SCSS_CORE1_POR_RESET] = { 0x2d80 },
2687 [MPM_RESET] = { 0x2da4, 1 },
2688 [EBI1_1X_DIV_RESET] = { 0x2dec, 9 },
2689 [EBI1_RESET] = { 0x2dec, 7 },
2690 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
2691 [USB_PHY0_RESET] = { 0x2e20 },
2692 [USB_PHY1_RESET] = { 0x2e40 },
2693 [PRNG_RESET] = { 0x2e80, 12 },
2694};
2695
2696static const struct regmap_config gcc_msm8660_regmap_config = {
2697 .reg_bits = 32,
2698 .reg_stride = 4,
2699 .val_bits = 32,
2700 .max_register = 0x363c,
2701 .fast_io = true,
2702};
2703
2704static const struct of_device_id gcc_msm8660_match_table[] = {
2705 { .compatible = "qcom,gcc-msm8660" },
2706 { }
2707};
2708MODULE_DEVICE_TABLE(of, gcc_msm8660_match_table);
2709
2710struct qcom_cc {
2711 struct qcom_reset_controller reset;
2712 struct clk_onecell_data data;
2713 struct clk *clks[];
2714};
2715
2716static int gcc_msm8660_probe(struct platform_device *pdev)
2717{
2718 void __iomem *base;
2719 struct resource *res;
2720 int i, ret;
2721 struct device *dev = &pdev->dev;
2722 struct clk *clk;
2723 struct clk_onecell_data *data;
2724 struct clk **clks;
2725 struct regmap *regmap;
2726 size_t num_clks;
2727 struct qcom_reset_controller *reset;
2728 struct qcom_cc *cc;
2729
2730 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2731 base = devm_ioremap_resource(dev, res);
2732 if (IS_ERR(base))
2733 return PTR_ERR(base);
2734
2735 regmap = devm_regmap_init_mmio(dev, base, &gcc_msm8660_regmap_config);
2736 if (IS_ERR(regmap))
2737 return PTR_ERR(regmap);
2738
2739 num_clks = ARRAY_SIZE(gcc_msm8660_clks);
2740 cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*clks) * num_clks,
2741 GFP_KERNEL);
2742 if (!cc)
2743 return -ENOMEM;
2744
2745 clks = cc->clks;
2746 data = &cc->data;
2747 data->clks = clks;
2748 data->clk_num = num_clks;
2749
2750 /* Temporary until RPM clocks supported */
2751 clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 19200000);
2752 if (IS_ERR(clk))
2753 return PTR_ERR(clk);
2754
2755 clk = clk_register_fixed_rate(dev, "pxo", NULL, CLK_IS_ROOT, 27000000);
2756 if (IS_ERR(clk))
2757 return PTR_ERR(clk);
2758
2759 for (i = 0; i < num_clks; i++) {
2760 if (!gcc_msm8660_clks[i])
2761 continue;
2762 clk = devm_clk_register_regmap(dev, gcc_msm8660_clks[i]);
2763 if (IS_ERR(clk))
2764 return PTR_ERR(clk);
2765 clks[i] = clk;
2766 }
2767
2768 ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, data);
2769 if (ret)
2770 return ret;
2771
2772 reset = &cc->reset;
2773 reset->rcdev.of_node = dev->of_node;
2774 reset->rcdev.ops = &qcom_reset_ops,
2775 reset->rcdev.owner = THIS_MODULE,
2776 reset->rcdev.nr_resets = ARRAY_SIZE(gcc_msm8660_resets),
2777 reset->regmap = regmap;
2778 reset->reset_map = gcc_msm8660_resets,
2779 platform_set_drvdata(pdev, &reset->rcdev);
2780
2781 ret = reset_controller_register(&reset->rcdev);
2782 if (ret)
2783 of_clk_del_provider(dev->of_node);
2784
2785 return ret;
2786}
2787
2788static int gcc_msm8660_remove(struct platform_device *pdev)
2789{
2790 of_clk_del_provider(pdev->dev.of_node);
2791 reset_controller_unregister(platform_get_drvdata(pdev));
2792 return 0;
2793}
2794
2795static struct platform_driver gcc_msm8660_driver = {
2796 .probe = gcc_msm8660_probe,
2797 .remove = gcc_msm8660_remove,
2798 .driver = {
2799 .name = "gcc-msm8660",
2800 .owner = THIS_MODULE,
2801 .of_match_table = gcc_msm8660_match_table,
2802 },
2803};
2804
2805static int __init gcc_msm8660_init(void)
2806{
2807 return platform_driver_register(&gcc_msm8660_driver);
2808}
2809core_initcall(gcc_msm8660_init);
2810
2811static void __exit gcc_msm8660_exit(void)
2812{
2813 platform_driver_unregister(&gcc_msm8660_driver);
2814}
2815module_exit(gcc_msm8660_exit);
2816
2817MODULE_DESCRIPTION("GCC MSM 8660 Driver");
2818MODULE_LICENSE("GPL v2");
2819MODULE_ALIAS("platform:gcc-msm8660");
diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c
new file mode 100644
index 000000000000..fd446ab2fd98
--- /dev/null
+++ b/drivers/clk/qcom/gcc-msm8960.c
@@ -0,0 +1,2993 @@
1/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/bitops.h>
16#include <linux/err.h>
17#include <linux/platform_device.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/clk-provider.h>
22#include <linux/regmap.h>
23#include <linux/reset-controller.h>
24
25#include <dt-bindings/clock/qcom,gcc-msm8960.h>
26#include <dt-bindings/reset/qcom,gcc-msm8960.h>
27
28#include "clk-regmap.h"
29#include "clk-pll.h"
30#include "clk-rcg.h"
31#include "clk-branch.h"
32#include "reset.h"
33
34static struct clk_pll pll3 = {
35 .l_reg = 0x3164,
36 .m_reg = 0x3168,
37 .n_reg = 0x316c,
38 .config_reg = 0x3174,
39 .mode_reg = 0x3160,
40 .status_reg = 0x3178,
41 .status_bit = 16,
42 .clkr.hw.init = &(struct clk_init_data){
43 .name = "pll3",
44 .parent_names = (const char *[]){ "pxo" },
45 .num_parents = 1,
46 .ops = &clk_pll_ops,
47 },
48};
49
50static struct clk_pll pll8 = {
51 .l_reg = 0x3144,
52 .m_reg = 0x3148,
53 .n_reg = 0x314c,
54 .config_reg = 0x3154,
55 .mode_reg = 0x3140,
56 .status_reg = 0x3158,
57 .status_bit = 16,
58 .clkr.hw.init = &(struct clk_init_data){
59 .name = "pll8",
60 .parent_names = (const char *[]){ "pxo" },
61 .num_parents = 1,
62 .ops = &clk_pll_ops,
63 },
64};
65
66static struct clk_regmap pll8_vote = {
67 .enable_reg = 0x34c0,
68 .enable_mask = BIT(8),
69 .hw.init = &(struct clk_init_data){
70 .name = "pll8_vote",
71 .parent_names = (const char *[]){ "pll8" },
72 .num_parents = 1,
73 .ops = &clk_pll_vote_ops,
74 },
75};
76
77static struct clk_pll pll14 = {
78 .l_reg = 0x31c4,
79 .m_reg = 0x31c8,
80 .n_reg = 0x31cc,
81 .config_reg = 0x31d4,
82 .mode_reg = 0x31c0,
83 .status_reg = 0x31d8,
84 .status_bit = 16,
85 .clkr.hw.init = &(struct clk_init_data){
86 .name = "pll14",
87 .parent_names = (const char *[]){ "pxo" },
88 .num_parents = 1,
89 .ops = &clk_pll_ops,
90 },
91};
92
93static struct clk_regmap pll14_vote = {
94 .enable_reg = 0x34c0,
95 .enable_mask = BIT(14),
96 .hw.init = &(struct clk_init_data){
97 .name = "pll14_vote",
98 .parent_names = (const char *[]){ "pll14" },
99 .num_parents = 1,
100 .ops = &clk_pll_vote_ops,
101 },
102};
103
104#define P_PXO 0
105#define P_PLL8 1
106#define P_CXO 2
107
108static const u8 gcc_pxo_pll8_map[] = {
109 [P_PXO] = 0,
110 [P_PLL8] = 3,
111};
112
113static const char *gcc_pxo_pll8[] = {
114 "pxo",
115 "pll8_vote",
116};
117
118static const u8 gcc_pxo_pll8_cxo_map[] = {
119 [P_PXO] = 0,
120 [P_PLL8] = 3,
121 [P_CXO] = 5,
122};
123
124static const char *gcc_pxo_pll8_cxo[] = {
125 "pxo",
126 "pll8_vote",
127 "cxo",
128};
129
130static struct freq_tbl clk_tbl_gsbi_uart[] = {
131 { 1843200, P_PLL8, 2, 6, 625 },
132 { 3686400, P_PLL8, 2, 12, 625 },
133 { 7372800, P_PLL8, 2, 24, 625 },
134 { 14745600, P_PLL8, 2, 48, 625 },
135 { 16000000, P_PLL8, 4, 1, 6 },
136 { 24000000, P_PLL8, 4, 1, 4 },
137 { 32000000, P_PLL8, 4, 1, 3 },
138 { 40000000, P_PLL8, 1, 5, 48 },
139 { 46400000, P_PLL8, 1, 29, 240 },
140 { 48000000, P_PLL8, 4, 1, 2 },
141 { 51200000, P_PLL8, 1, 2, 15 },
142 { 56000000, P_PLL8, 1, 7, 48 },
143 { 58982400, P_PLL8, 1, 96, 625 },
144 { 64000000, P_PLL8, 2, 1, 3 },
145 { }
146};
147
148static struct clk_rcg gsbi1_uart_src = {
149 .ns_reg = 0x29d4,
150 .md_reg = 0x29d0,
151 .mn = {
152 .mnctr_en_bit = 8,
153 .mnctr_reset_bit = 7,
154 .mnctr_mode_shift = 5,
155 .n_val_shift = 16,
156 .m_val_shift = 16,
157 .width = 16,
158 },
159 .p = {
160 .pre_div_shift = 3,
161 .pre_div_width = 2,
162 },
163 .s = {
164 .src_sel_shift = 0,
165 .parent_map = gcc_pxo_pll8_map,
166 },
167 .freq_tbl = clk_tbl_gsbi_uart,
168 .clkr = {
169 .enable_reg = 0x29d4,
170 .enable_mask = BIT(11),
171 .hw.init = &(struct clk_init_data){
172 .name = "gsbi1_uart_src",
173 .parent_names = gcc_pxo_pll8,
174 .num_parents = 2,
175 .ops = &clk_rcg_ops,
176 .flags = CLK_SET_PARENT_GATE,
177 },
178 },
179};
180
181static struct clk_branch gsbi1_uart_clk = {
182 .halt_reg = 0x2fcc,
183 .halt_bit = 10,
184 .clkr = {
185 .enable_reg = 0x29d4,
186 .enable_mask = BIT(9),
187 .hw.init = &(struct clk_init_data){
188 .name = "gsbi1_uart_clk",
189 .parent_names = (const char *[]){
190 "gsbi1_uart_src",
191 },
192 .num_parents = 1,
193 .ops = &clk_branch_ops,
194 .flags = CLK_SET_RATE_PARENT,
195 },
196 },
197};
198
199static struct clk_rcg gsbi2_uart_src = {
200 .ns_reg = 0x29f4,
201 .md_reg = 0x29f0,
202 .mn = {
203 .mnctr_en_bit = 8,
204 .mnctr_reset_bit = 7,
205 .mnctr_mode_shift = 5,
206 .n_val_shift = 16,
207 .m_val_shift = 16,
208 .width = 16,
209 },
210 .p = {
211 .pre_div_shift = 3,
212 .pre_div_width = 2,
213 },
214 .s = {
215 .src_sel_shift = 0,
216 .parent_map = gcc_pxo_pll8_map,
217 },
218 .freq_tbl = clk_tbl_gsbi_uart,
219 .clkr = {
220 .enable_reg = 0x29f4,
221 .enable_mask = BIT(11),
222 .hw.init = &(struct clk_init_data){
223 .name = "gsbi2_uart_src",
224 .parent_names = gcc_pxo_pll8,
225 .num_parents = 2,
226 .ops = &clk_rcg_ops,
227 .flags = CLK_SET_PARENT_GATE,
228 },
229 },
230};
231
232static struct clk_branch gsbi2_uart_clk = {
233 .halt_reg = 0x2fcc,
234 .halt_bit = 6,
235 .clkr = {
236 .enable_reg = 0x29f4,
237 .enable_mask = BIT(9),
238 .hw.init = &(struct clk_init_data){
239 .name = "gsbi2_uart_clk",
240 .parent_names = (const char *[]){
241 "gsbi2_uart_src",
242 },
243 .num_parents = 1,
244 .ops = &clk_branch_ops,
245 .flags = CLK_SET_RATE_PARENT,
246 },
247 },
248};
249
250static struct clk_rcg gsbi3_uart_src = {
251 .ns_reg = 0x2a14,
252 .md_reg = 0x2a10,
253 .mn = {
254 .mnctr_en_bit = 8,
255 .mnctr_reset_bit = 7,
256 .mnctr_mode_shift = 5,
257 .n_val_shift = 16,
258 .m_val_shift = 16,
259 .width = 16,
260 },
261 .p = {
262 .pre_div_shift = 3,
263 .pre_div_width = 2,
264 },
265 .s = {
266 .src_sel_shift = 0,
267 .parent_map = gcc_pxo_pll8_map,
268 },
269 .freq_tbl = clk_tbl_gsbi_uart,
270 .clkr = {
271 .enable_reg = 0x2a14,
272 .enable_mask = BIT(11),
273 .hw.init = &(struct clk_init_data){
274 .name = "gsbi3_uart_src",
275 .parent_names = gcc_pxo_pll8,
276 .num_parents = 2,
277 .ops = &clk_rcg_ops,
278 .flags = CLK_SET_PARENT_GATE,
279 },
280 },
281};
282
283static struct clk_branch gsbi3_uart_clk = {
284 .halt_reg = 0x2fcc,
285 .halt_bit = 2,
286 .clkr = {
287 .enable_reg = 0x2a14,
288 .enable_mask = BIT(9),
289 .hw.init = &(struct clk_init_data){
290 .name = "gsbi3_uart_clk",
291 .parent_names = (const char *[]){
292 "gsbi3_uart_src",
293 },
294 .num_parents = 1,
295 .ops = &clk_branch_ops,
296 .flags = CLK_SET_RATE_PARENT,
297 },
298 },
299};
300
301static struct clk_rcg gsbi4_uart_src = {
302 .ns_reg = 0x2a34,
303 .md_reg = 0x2a30,
304 .mn = {
305 .mnctr_en_bit = 8,
306 .mnctr_reset_bit = 7,
307 .mnctr_mode_shift = 5,
308 .n_val_shift = 16,
309 .m_val_shift = 16,
310 .width = 16,
311 },
312 .p = {
313 .pre_div_shift = 3,
314 .pre_div_width = 2,
315 },
316 .s = {
317 .src_sel_shift = 0,
318 .parent_map = gcc_pxo_pll8_map,
319 },
320 .freq_tbl = clk_tbl_gsbi_uart,
321 .clkr = {
322 .enable_reg = 0x2a34,
323 .enable_mask = BIT(11),
324 .hw.init = &(struct clk_init_data){
325 .name = "gsbi4_uart_src",
326 .parent_names = gcc_pxo_pll8,
327 .num_parents = 2,
328 .ops = &clk_rcg_ops,
329 .flags = CLK_SET_PARENT_GATE,
330 },
331 },
332};
333
334static struct clk_branch gsbi4_uart_clk = {
335 .halt_reg = 0x2fd0,
336 .halt_bit = 26,
337 .clkr = {
338 .enable_reg = 0x2a34,
339 .enable_mask = BIT(9),
340 .hw.init = &(struct clk_init_data){
341 .name = "gsbi4_uart_clk",
342 .parent_names = (const char *[]){
343 "gsbi4_uart_src",
344 },
345 .num_parents = 1,
346 .ops = &clk_branch_ops,
347 .flags = CLK_SET_RATE_PARENT,
348 },
349 },
350};
351
352static struct clk_rcg gsbi5_uart_src = {
353 .ns_reg = 0x2a54,
354 .md_reg = 0x2a50,
355 .mn = {
356 .mnctr_en_bit = 8,
357 .mnctr_reset_bit = 7,
358 .mnctr_mode_shift = 5,
359 .n_val_shift = 16,
360 .m_val_shift = 16,
361 .width = 16,
362 },
363 .p = {
364 .pre_div_shift = 3,
365 .pre_div_width = 2,
366 },
367 .s = {
368 .src_sel_shift = 0,
369 .parent_map = gcc_pxo_pll8_map,
370 },
371 .freq_tbl = clk_tbl_gsbi_uart,
372 .clkr = {
373 .enable_reg = 0x2a54,
374 .enable_mask = BIT(11),
375 .hw.init = &(struct clk_init_data){
376 .name = "gsbi5_uart_src",
377 .parent_names = gcc_pxo_pll8,
378 .num_parents = 2,
379 .ops = &clk_rcg_ops,
380 .flags = CLK_SET_PARENT_GATE,
381 },
382 },
383};
384
385static struct clk_branch gsbi5_uart_clk = {
386 .halt_reg = 0x2fd0,
387 .halt_bit = 22,
388 .clkr = {
389 .enable_reg = 0x2a54,
390 .enable_mask = BIT(9),
391 .hw.init = &(struct clk_init_data){
392 .name = "gsbi5_uart_clk",
393 .parent_names = (const char *[]){
394 "gsbi5_uart_src",
395 },
396 .num_parents = 1,
397 .ops = &clk_branch_ops,
398 .flags = CLK_SET_RATE_PARENT,
399 },
400 },
401};
402
403static struct clk_rcg gsbi6_uart_src = {
404 .ns_reg = 0x2a74,
405 .md_reg = 0x2a70,
406 .mn = {
407 .mnctr_en_bit = 8,
408 .mnctr_reset_bit = 7,
409 .mnctr_mode_shift = 5,
410 .n_val_shift = 16,
411 .m_val_shift = 16,
412 .width = 16,
413 },
414 .p = {
415 .pre_div_shift = 3,
416 .pre_div_width = 2,
417 },
418 .s = {
419 .src_sel_shift = 0,
420 .parent_map = gcc_pxo_pll8_map,
421 },
422 .freq_tbl = clk_tbl_gsbi_uart,
423 .clkr = {
424 .enable_reg = 0x2a74,
425 .enable_mask = BIT(11),
426 .hw.init = &(struct clk_init_data){
427 .name = "gsbi6_uart_src",
428 .parent_names = gcc_pxo_pll8,
429 .num_parents = 2,
430 .ops = &clk_rcg_ops,
431 .flags = CLK_SET_PARENT_GATE,
432 },
433 },
434};
435
436static struct clk_branch gsbi6_uart_clk = {
437 .halt_reg = 0x2fd0,
438 .halt_bit = 18,
439 .clkr = {
440 .enable_reg = 0x2a74,
441 .enable_mask = BIT(9),
442 .hw.init = &(struct clk_init_data){
443 .name = "gsbi6_uart_clk",
444 .parent_names = (const char *[]){
445 "gsbi6_uart_src",
446 },
447 .num_parents = 1,
448 .ops = &clk_branch_ops,
449 .flags = CLK_SET_RATE_PARENT,
450 },
451 },
452};
453
454static struct clk_rcg gsbi7_uart_src = {
455 .ns_reg = 0x2a94,
456 .md_reg = 0x2a90,
457 .mn = {
458 .mnctr_en_bit = 8,
459 .mnctr_reset_bit = 7,
460 .mnctr_mode_shift = 5,
461 .n_val_shift = 16,
462 .m_val_shift = 16,
463 .width = 16,
464 },
465 .p = {
466 .pre_div_shift = 3,
467 .pre_div_width = 2,
468 },
469 .s = {
470 .src_sel_shift = 0,
471 .parent_map = gcc_pxo_pll8_map,
472 },
473 .freq_tbl = clk_tbl_gsbi_uart,
474 .clkr = {
475 .enable_reg = 0x2a94,
476 .enable_mask = BIT(11),
477 .hw.init = &(struct clk_init_data){
478 .name = "gsbi7_uart_src",
479 .parent_names = gcc_pxo_pll8,
480 .num_parents = 2,
481 .ops = &clk_rcg_ops,
482 .flags = CLK_SET_PARENT_GATE,
483 },
484 },
485};
486
487static struct clk_branch gsbi7_uart_clk = {
488 .halt_reg = 0x2fd0,
489 .halt_bit = 14,
490 .clkr = {
491 .enable_reg = 0x2a94,
492 .enable_mask = BIT(9),
493 .hw.init = &(struct clk_init_data){
494 .name = "gsbi7_uart_clk",
495 .parent_names = (const char *[]){
496 "gsbi7_uart_src",
497 },
498 .num_parents = 1,
499 .ops = &clk_branch_ops,
500 .flags = CLK_SET_RATE_PARENT,
501 },
502 },
503};
504
505static struct clk_rcg gsbi8_uart_src = {
506 .ns_reg = 0x2ab4,
507 .md_reg = 0x2ab0,
508 .mn = {
509 .mnctr_en_bit = 8,
510 .mnctr_reset_bit = 7,
511 .mnctr_mode_shift = 5,
512 .n_val_shift = 16,
513 .m_val_shift = 16,
514 .width = 16,
515 },
516 .p = {
517 .pre_div_shift = 3,
518 .pre_div_width = 2,
519 },
520 .s = {
521 .src_sel_shift = 0,
522 .parent_map = gcc_pxo_pll8_map,
523 },
524 .freq_tbl = clk_tbl_gsbi_uart,
525 .clkr = {
526 .enable_reg = 0x2ab4,
527 .enable_mask = BIT(11),
528 .hw.init = &(struct clk_init_data){
529 .name = "gsbi8_uart_src",
530 .parent_names = gcc_pxo_pll8,
531 .num_parents = 2,
532 .ops = &clk_rcg_ops,
533 .flags = CLK_SET_PARENT_GATE,
534 },
535 },
536};
537
538static struct clk_branch gsbi8_uart_clk = {
539 .halt_reg = 0x2fd0,
540 .halt_bit = 10,
541 .clkr = {
542 .enable_reg = 0x2ab4,
543 .enable_mask = BIT(9),
544 .hw.init = &(struct clk_init_data){
545 .name = "gsbi8_uart_clk",
546 .parent_names = (const char *[]){ "gsbi8_uart_src" },
547 .num_parents = 1,
548 .ops = &clk_branch_ops,
549 .flags = CLK_SET_RATE_PARENT,
550 },
551 },
552};
553
554static struct clk_rcg gsbi9_uart_src = {
555 .ns_reg = 0x2ad4,
556 .md_reg = 0x2ad0,
557 .mn = {
558 .mnctr_en_bit = 8,
559 .mnctr_reset_bit = 7,
560 .mnctr_mode_shift = 5,
561 .n_val_shift = 16,
562 .m_val_shift = 16,
563 .width = 16,
564 },
565 .p = {
566 .pre_div_shift = 3,
567 .pre_div_width = 2,
568 },
569 .s = {
570 .src_sel_shift = 0,
571 .parent_map = gcc_pxo_pll8_map,
572 },
573 .freq_tbl = clk_tbl_gsbi_uart,
574 .clkr = {
575 .enable_reg = 0x2ad4,
576 .enable_mask = BIT(11),
577 .hw.init = &(struct clk_init_data){
578 .name = "gsbi9_uart_src",
579 .parent_names = gcc_pxo_pll8,
580 .num_parents = 2,
581 .ops = &clk_rcg_ops,
582 .flags = CLK_SET_PARENT_GATE,
583 },
584 },
585};
586
587static struct clk_branch gsbi9_uart_clk = {
588 .halt_reg = 0x2fd0,
589 .halt_bit = 6,
590 .clkr = {
591 .enable_reg = 0x2ad4,
592 .enable_mask = BIT(9),
593 .hw.init = &(struct clk_init_data){
594 .name = "gsbi9_uart_clk",
595 .parent_names = (const char *[]){ "gsbi9_uart_src" },
596 .num_parents = 1,
597 .ops = &clk_branch_ops,
598 .flags = CLK_SET_RATE_PARENT,
599 },
600 },
601};
602
603static struct clk_rcg gsbi10_uart_src = {
604 .ns_reg = 0x2af4,
605 .md_reg = 0x2af0,
606 .mn = {
607 .mnctr_en_bit = 8,
608 .mnctr_reset_bit = 7,
609 .mnctr_mode_shift = 5,
610 .n_val_shift = 16,
611 .m_val_shift = 16,
612 .width = 16,
613 },
614 .p = {
615 .pre_div_shift = 3,
616 .pre_div_width = 2,
617 },
618 .s = {
619 .src_sel_shift = 0,
620 .parent_map = gcc_pxo_pll8_map,
621 },
622 .freq_tbl = clk_tbl_gsbi_uart,
623 .clkr = {
624 .enable_reg = 0x2af4,
625 .enable_mask = BIT(11),
626 .hw.init = &(struct clk_init_data){
627 .name = "gsbi10_uart_src",
628 .parent_names = gcc_pxo_pll8,
629 .num_parents = 2,
630 .ops = &clk_rcg_ops,
631 .flags = CLK_SET_PARENT_GATE,
632 },
633 },
634};
635
636static struct clk_branch gsbi10_uart_clk = {
637 .halt_reg = 0x2fd0,
638 .halt_bit = 2,
639 .clkr = {
640 .enable_reg = 0x2af4,
641 .enable_mask = BIT(9),
642 .hw.init = &(struct clk_init_data){
643 .name = "gsbi10_uart_clk",
644 .parent_names = (const char *[]){ "gsbi10_uart_src" },
645 .num_parents = 1,
646 .ops = &clk_branch_ops,
647 .flags = CLK_SET_RATE_PARENT,
648 },
649 },
650};
651
652static struct clk_rcg gsbi11_uart_src = {
653 .ns_reg = 0x2b14,
654 .md_reg = 0x2b10,
655 .mn = {
656 .mnctr_en_bit = 8,
657 .mnctr_reset_bit = 7,
658 .mnctr_mode_shift = 5,
659 .n_val_shift = 16,
660 .m_val_shift = 16,
661 .width = 16,
662 },
663 .p = {
664 .pre_div_shift = 3,
665 .pre_div_width = 2,
666 },
667 .s = {
668 .src_sel_shift = 0,
669 .parent_map = gcc_pxo_pll8_map,
670 },
671 .freq_tbl = clk_tbl_gsbi_uart,
672 .clkr = {
673 .enable_reg = 0x2b14,
674 .enable_mask = BIT(11),
675 .hw.init = &(struct clk_init_data){
676 .name = "gsbi11_uart_src",
677 .parent_names = gcc_pxo_pll8,
678 .num_parents = 2,
679 .ops = &clk_rcg_ops,
680 .flags = CLK_SET_PARENT_GATE,
681 },
682 },
683};
684
685static struct clk_branch gsbi11_uart_clk = {
686 .halt_reg = 0x2fd4,
687 .halt_bit = 17,
688 .clkr = {
689 .enable_reg = 0x2b14,
690 .enable_mask = BIT(9),
691 .hw.init = &(struct clk_init_data){
692 .name = "gsbi11_uart_clk",
693 .parent_names = (const char *[]){ "gsbi11_uart_src" },
694 .num_parents = 1,
695 .ops = &clk_branch_ops,
696 .flags = CLK_SET_RATE_PARENT,
697 },
698 },
699};
700
701static struct clk_rcg gsbi12_uart_src = {
702 .ns_reg = 0x2b34,
703 .md_reg = 0x2b30,
704 .mn = {
705 .mnctr_en_bit = 8,
706 .mnctr_reset_bit = 7,
707 .mnctr_mode_shift = 5,
708 .n_val_shift = 16,
709 .m_val_shift = 16,
710 .width = 16,
711 },
712 .p = {
713 .pre_div_shift = 3,
714 .pre_div_width = 2,
715 },
716 .s = {
717 .src_sel_shift = 0,
718 .parent_map = gcc_pxo_pll8_map,
719 },
720 .freq_tbl = clk_tbl_gsbi_uart,
721 .clkr = {
722 .enable_reg = 0x2b34,
723 .enable_mask = BIT(11),
724 .hw.init = &(struct clk_init_data){
725 .name = "gsbi12_uart_src",
726 .parent_names = gcc_pxo_pll8,
727 .num_parents = 2,
728 .ops = &clk_rcg_ops,
729 .flags = CLK_SET_PARENT_GATE,
730 },
731 },
732};
733
734static struct clk_branch gsbi12_uart_clk = {
735 .halt_reg = 0x2fd4,
736 .halt_bit = 13,
737 .clkr = {
738 .enable_reg = 0x2b34,
739 .enable_mask = BIT(9),
740 .hw.init = &(struct clk_init_data){
741 .name = "gsbi12_uart_clk",
742 .parent_names = (const char *[]){ "gsbi12_uart_src" },
743 .num_parents = 1,
744 .ops = &clk_branch_ops,
745 .flags = CLK_SET_RATE_PARENT,
746 },
747 },
748};
749
750static struct freq_tbl clk_tbl_gsbi_qup[] = {
751 { 1100000, P_PXO, 1, 2, 49 },
752 { 5400000, P_PXO, 1, 1, 5 },
753 { 10800000, P_PXO, 1, 2, 5 },
754 { 15060000, P_PLL8, 1, 2, 51 },
755 { 24000000, P_PLL8, 4, 1, 4 },
756 { 25600000, P_PLL8, 1, 1, 15 },
757 { 27000000, P_PXO, 1, 0, 0 },
758 { 48000000, P_PLL8, 4, 1, 2 },
759 { 51200000, P_PLL8, 1, 2, 15 },
760 { }
761};
762
763static struct clk_rcg gsbi1_qup_src = {
764 .ns_reg = 0x29cc,
765 .md_reg = 0x29c8,
766 .mn = {
767 .mnctr_en_bit = 8,
768 .mnctr_reset_bit = 7,
769 .mnctr_mode_shift = 5,
770 .n_val_shift = 16,
771 .m_val_shift = 16,
772 .width = 8,
773 },
774 .p = {
775 .pre_div_shift = 3,
776 .pre_div_width = 2,
777 },
778 .s = {
779 .src_sel_shift = 0,
780 .parent_map = gcc_pxo_pll8_map,
781 },
782 .freq_tbl = clk_tbl_gsbi_qup,
783 .clkr = {
784 .enable_reg = 0x29cc,
785 .enable_mask = BIT(11),
786 .hw.init = &(struct clk_init_data){
787 .name = "gsbi1_qup_src",
788 .parent_names = gcc_pxo_pll8,
789 .num_parents = 2,
790 .ops = &clk_rcg_ops,
791 .flags = CLK_SET_PARENT_GATE,
792 },
793 },
794};
795
796static struct clk_branch gsbi1_qup_clk = {
797 .halt_reg = 0x2fcc,
798 .halt_bit = 9,
799 .clkr = {
800 .enable_reg = 0x29cc,
801 .enable_mask = BIT(9),
802 .hw.init = &(struct clk_init_data){
803 .name = "gsbi1_qup_clk",
804 .parent_names = (const char *[]){ "gsbi1_qup_src" },
805 .num_parents = 1,
806 .ops = &clk_branch_ops,
807 .flags = CLK_SET_RATE_PARENT,
808 },
809 },
810};
811
812static struct clk_rcg gsbi2_qup_src = {
813 .ns_reg = 0x29ec,
814 .md_reg = 0x29e8,
815 .mn = {
816 .mnctr_en_bit = 8,
817 .mnctr_reset_bit = 7,
818 .mnctr_mode_shift = 5,
819 .n_val_shift = 16,
820 .m_val_shift = 16,
821 .width = 8,
822 },
823 .p = {
824 .pre_div_shift = 3,
825 .pre_div_width = 2,
826 },
827 .s = {
828 .src_sel_shift = 0,
829 .parent_map = gcc_pxo_pll8_map,
830 },
831 .freq_tbl = clk_tbl_gsbi_qup,
832 .clkr = {
833 .enable_reg = 0x29ec,
834 .enable_mask = BIT(11),
835 .hw.init = &(struct clk_init_data){
836 .name = "gsbi2_qup_src",
837 .parent_names = gcc_pxo_pll8,
838 .num_parents = 2,
839 .ops = &clk_rcg_ops,
840 .flags = CLK_SET_PARENT_GATE,
841 },
842 },
843};
844
845static struct clk_branch gsbi2_qup_clk = {
846 .halt_reg = 0x2fcc,
847 .halt_bit = 4,
848 .clkr = {
849 .enable_reg = 0x29ec,
850 .enable_mask = BIT(9),
851 .hw.init = &(struct clk_init_data){
852 .name = "gsbi2_qup_clk",
853 .parent_names = (const char *[]){ "gsbi2_qup_src" },
854 .num_parents = 1,
855 .ops = &clk_branch_ops,
856 .flags = CLK_SET_RATE_PARENT,
857 },
858 },
859};
860
861static struct clk_rcg gsbi3_qup_src = {
862 .ns_reg = 0x2a0c,
863 .md_reg = 0x2a08,
864 .mn = {
865 .mnctr_en_bit = 8,
866 .mnctr_reset_bit = 7,
867 .mnctr_mode_shift = 5,
868 .n_val_shift = 16,
869 .m_val_shift = 16,
870 .width = 8,
871 },
872 .p = {
873 .pre_div_shift = 3,
874 .pre_div_width = 2,
875 },
876 .s = {
877 .src_sel_shift = 0,
878 .parent_map = gcc_pxo_pll8_map,
879 },
880 .freq_tbl = clk_tbl_gsbi_qup,
881 .clkr = {
882 .enable_reg = 0x2a0c,
883 .enable_mask = BIT(11),
884 .hw.init = &(struct clk_init_data){
885 .name = "gsbi3_qup_src",
886 .parent_names = gcc_pxo_pll8,
887 .num_parents = 2,
888 .ops = &clk_rcg_ops,
889 .flags = CLK_SET_PARENT_GATE,
890 },
891 },
892};
893
894static struct clk_branch gsbi3_qup_clk = {
895 .halt_reg = 0x2fcc,
896 .halt_bit = 0,
897 .clkr = {
898 .enable_reg = 0x2a0c,
899 .enable_mask = BIT(9),
900 .hw.init = &(struct clk_init_data){
901 .name = "gsbi3_qup_clk",
902 .parent_names = (const char *[]){ "gsbi3_qup_src" },
903 .num_parents = 1,
904 .ops = &clk_branch_ops,
905 .flags = CLK_SET_RATE_PARENT,
906 },
907 },
908};
909
910static struct clk_rcg gsbi4_qup_src = {
911 .ns_reg = 0x2a2c,
912 .md_reg = 0x2a28,
913 .mn = {
914 .mnctr_en_bit = 8,
915 .mnctr_reset_bit = 7,
916 .mnctr_mode_shift = 5,
917 .n_val_shift = 16,
918 .m_val_shift = 16,
919 .width = 8,
920 },
921 .p = {
922 .pre_div_shift = 3,
923 .pre_div_width = 2,
924 },
925 .s = {
926 .src_sel_shift = 0,
927 .parent_map = gcc_pxo_pll8_map,
928 },
929 .freq_tbl = clk_tbl_gsbi_qup,
930 .clkr = {
931 .enable_reg = 0x2a2c,
932 .enable_mask = BIT(11),
933 .hw.init = &(struct clk_init_data){
934 .name = "gsbi4_qup_src",
935 .parent_names = gcc_pxo_pll8,
936 .num_parents = 2,
937 .ops = &clk_rcg_ops,
938 .flags = CLK_SET_PARENT_GATE,
939 },
940 },
941};
942
943static struct clk_branch gsbi4_qup_clk = {
944 .halt_reg = 0x2fd0,
945 .halt_bit = 24,
946 .clkr = {
947 .enable_reg = 0x2a2c,
948 .enable_mask = BIT(9),
949 .hw.init = &(struct clk_init_data){
950 .name = "gsbi4_qup_clk",
951 .parent_names = (const char *[]){ "gsbi4_qup_src" },
952 .num_parents = 1,
953 .ops = &clk_branch_ops,
954 .flags = CLK_SET_RATE_PARENT,
955 },
956 },
957};
958
959static struct clk_rcg gsbi5_qup_src = {
960 .ns_reg = 0x2a4c,
961 .md_reg = 0x2a48,
962 .mn = {
963 .mnctr_en_bit = 8,
964 .mnctr_reset_bit = 7,
965 .mnctr_mode_shift = 5,
966 .n_val_shift = 16,
967 .m_val_shift = 16,
968 .width = 8,
969 },
970 .p = {
971 .pre_div_shift = 3,
972 .pre_div_width = 2,
973 },
974 .s = {
975 .src_sel_shift = 0,
976 .parent_map = gcc_pxo_pll8_map,
977 },
978 .freq_tbl = clk_tbl_gsbi_qup,
979 .clkr = {
980 .enable_reg = 0x2a4c,
981 .enable_mask = BIT(11),
982 .hw.init = &(struct clk_init_data){
983 .name = "gsbi5_qup_src",
984 .parent_names = gcc_pxo_pll8,
985 .num_parents = 2,
986 .ops = &clk_rcg_ops,
987 .flags = CLK_SET_PARENT_GATE,
988 },
989 },
990};
991
992static struct clk_branch gsbi5_qup_clk = {
993 .halt_reg = 0x2fd0,
994 .halt_bit = 20,
995 .clkr = {
996 .enable_reg = 0x2a4c,
997 .enable_mask = BIT(9),
998 .hw.init = &(struct clk_init_data){
999 .name = "gsbi5_qup_clk",
1000 .parent_names = (const char *[]){ "gsbi5_qup_src" },
1001 .num_parents = 1,
1002 .ops = &clk_branch_ops,
1003 .flags = CLK_SET_RATE_PARENT,
1004 },
1005 },
1006};
1007
1008static struct clk_rcg gsbi6_qup_src = {
1009 .ns_reg = 0x2a6c,
1010 .md_reg = 0x2a68,
1011 .mn = {
1012 .mnctr_en_bit = 8,
1013 .mnctr_reset_bit = 7,
1014 .mnctr_mode_shift = 5,
1015 .n_val_shift = 16,
1016 .m_val_shift = 16,
1017 .width = 8,
1018 },
1019 .p = {
1020 .pre_div_shift = 3,
1021 .pre_div_width = 2,
1022 },
1023 .s = {
1024 .src_sel_shift = 0,
1025 .parent_map = gcc_pxo_pll8_map,
1026 },
1027 .freq_tbl = clk_tbl_gsbi_qup,
1028 .clkr = {
1029 .enable_reg = 0x2a6c,
1030 .enable_mask = BIT(11),
1031 .hw.init = &(struct clk_init_data){
1032 .name = "gsbi6_qup_src",
1033 .parent_names = gcc_pxo_pll8,
1034 .num_parents = 2,
1035 .ops = &clk_rcg_ops,
1036 .flags = CLK_SET_PARENT_GATE,
1037 },
1038 },
1039};
1040
1041static struct clk_branch gsbi6_qup_clk = {
1042 .halt_reg = 0x2fd0,
1043 .halt_bit = 16,
1044 .clkr = {
1045 .enable_reg = 0x2a6c,
1046 .enable_mask = BIT(9),
1047 .hw.init = &(struct clk_init_data){
1048 .name = "gsbi6_qup_clk",
1049 .parent_names = (const char *[]){ "gsbi6_qup_src" },
1050 .num_parents = 1,
1051 .ops = &clk_branch_ops,
1052 .flags = CLK_SET_RATE_PARENT,
1053 },
1054 },
1055};
1056
1057static struct clk_rcg gsbi7_qup_src = {
1058 .ns_reg = 0x2a8c,
1059 .md_reg = 0x2a88,
1060 .mn = {
1061 .mnctr_en_bit = 8,
1062 .mnctr_reset_bit = 7,
1063 .mnctr_mode_shift = 5,
1064 .n_val_shift = 16,
1065 .m_val_shift = 16,
1066 .width = 8,
1067 },
1068 .p = {
1069 .pre_div_shift = 3,
1070 .pre_div_width = 2,
1071 },
1072 .s = {
1073 .src_sel_shift = 0,
1074 .parent_map = gcc_pxo_pll8_map,
1075 },
1076 .freq_tbl = clk_tbl_gsbi_qup,
1077 .clkr = {
1078 .enable_reg = 0x2a8c,
1079 .enable_mask = BIT(11),
1080 .hw.init = &(struct clk_init_data){
1081 .name = "gsbi7_qup_src",
1082 .parent_names = gcc_pxo_pll8,
1083 .num_parents = 2,
1084 .ops = &clk_rcg_ops,
1085 .flags = CLK_SET_PARENT_GATE,
1086 },
1087 },
1088};
1089
1090static struct clk_branch gsbi7_qup_clk = {
1091 .halt_reg = 0x2fd0,
1092 .halt_bit = 12,
1093 .clkr = {
1094 .enable_reg = 0x2a8c,
1095 .enable_mask = BIT(9),
1096 .hw.init = &(struct clk_init_data){
1097 .name = "gsbi7_qup_clk",
1098 .parent_names = (const char *[]){ "gsbi7_qup_src" },
1099 .num_parents = 1,
1100 .ops = &clk_branch_ops,
1101 .flags = CLK_SET_RATE_PARENT,
1102 },
1103 },
1104};
1105
1106static struct clk_rcg gsbi8_qup_src = {
1107 .ns_reg = 0x2aac,
1108 .md_reg = 0x2aa8,
1109 .mn = {
1110 .mnctr_en_bit = 8,
1111 .mnctr_reset_bit = 7,
1112 .mnctr_mode_shift = 5,
1113 .n_val_shift = 16,
1114 .m_val_shift = 16,
1115 .width = 8,
1116 },
1117 .p = {
1118 .pre_div_shift = 3,
1119 .pre_div_width = 2,
1120 },
1121 .s = {
1122 .src_sel_shift = 0,
1123 .parent_map = gcc_pxo_pll8_map,
1124 },
1125 .freq_tbl = clk_tbl_gsbi_qup,
1126 .clkr = {
1127 .enable_reg = 0x2aac,
1128 .enable_mask = BIT(11),
1129 .hw.init = &(struct clk_init_data){
1130 .name = "gsbi8_qup_src",
1131 .parent_names = gcc_pxo_pll8,
1132 .num_parents = 2,
1133 .ops = &clk_rcg_ops,
1134 .flags = CLK_SET_PARENT_GATE,
1135 },
1136 },
1137};
1138
1139static struct clk_branch gsbi8_qup_clk = {
1140 .halt_reg = 0x2fd0,
1141 .halt_bit = 8,
1142 .clkr = {
1143 .enable_reg = 0x2aac,
1144 .enable_mask = BIT(9),
1145 .hw.init = &(struct clk_init_data){
1146 .name = "gsbi8_qup_clk",
1147 .parent_names = (const char *[]){ "gsbi8_qup_src" },
1148 .num_parents = 1,
1149 .ops = &clk_branch_ops,
1150 .flags = CLK_SET_RATE_PARENT,
1151 },
1152 },
1153};
1154
1155static struct clk_rcg gsbi9_qup_src = {
1156 .ns_reg = 0x2acc,
1157 .md_reg = 0x2ac8,
1158 .mn = {
1159 .mnctr_en_bit = 8,
1160 .mnctr_reset_bit = 7,
1161 .mnctr_mode_shift = 5,
1162 .n_val_shift = 16,
1163 .m_val_shift = 16,
1164 .width = 8,
1165 },
1166 .p = {
1167 .pre_div_shift = 3,
1168 .pre_div_width = 2,
1169 },
1170 .s = {
1171 .src_sel_shift = 0,
1172 .parent_map = gcc_pxo_pll8_map,
1173 },
1174 .freq_tbl = clk_tbl_gsbi_qup,
1175 .clkr = {
1176 .enable_reg = 0x2acc,
1177 .enable_mask = BIT(11),
1178 .hw.init = &(struct clk_init_data){
1179 .name = "gsbi9_qup_src",
1180 .parent_names = gcc_pxo_pll8,
1181 .num_parents = 2,
1182 .ops = &clk_rcg_ops,
1183 .flags = CLK_SET_PARENT_GATE,
1184 },
1185 },
1186};
1187
1188static struct clk_branch gsbi9_qup_clk = {
1189 .halt_reg = 0x2fd0,
1190 .halt_bit = 4,
1191 .clkr = {
1192 .enable_reg = 0x2acc,
1193 .enable_mask = BIT(9),
1194 .hw.init = &(struct clk_init_data){
1195 .name = "gsbi9_qup_clk",
1196 .parent_names = (const char *[]){ "gsbi9_qup_src" },
1197 .num_parents = 1,
1198 .ops = &clk_branch_ops,
1199 .flags = CLK_SET_RATE_PARENT,
1200 },
1201 },
1202};
1203
1204static struct clk_rcg gsbi10_qup_src = {
1205 .ns_reg = 0x2aec,
1206 .md_reg = 0x2ae8,
1207 .mn = {
1208 .mnctr_en_bit = 8,
1209 .mnctr_reset_bit = 7,
1210 .mnctr_mode_shift = 5,
1211 .n_val_shift = 16,
1212 .m_val_shift = 16,
1213 .width = 8,
1214 },
1215 .p = {
1216 .pre_div_shift = 3,
1217 .pre_div_width = 2,
1218 },
1219 .s = {
1220 .src_sel_shift = 0,
1221 .parent_map = gcc_pxo_pll8_map,
1222 },
1223 .freq_tbl = clk_tbl_gsbi_qup,
1224 .clkr = {
1225 .enable_reg = 0x2aec,
1226 .enable_mask = BIT(11),
1227 .hw.init = &(struct clk_init_data){
1228 .name = "gsbi10_qup_src",
1229 .parent_names = gcc_pxo_pll8,
1230 .num_parents = 2,
1231 .ops = &clk_rcg_ops,
1232 .flags = CLK_SET_PARENT_GATE,
1233 },
1234 },
1235};
1236
1237static struct clk_branch gsbi10_qup_clk = {
1238 .halt_reg = 0x2fd0,
1239 .halt_bit = 0,
1240 .clkr = {
1241 .enable_reg = 0x2aec,
1242 .enable_mask = BIT(9),
1243 .hw.init = &(struct clk_init_data){
1244 .name = "gsbi10_qup_clk",
1245 .parent_names = (const char *[]){ "gsbi10_qup_src" },
1246 .num_parents = 1,
1247 .ops = &clk_branch_ops,
1248 .flags = CLK_SET_RATE_PARENT,
1249 },
1250 },
1251};
1252
1253static struct clk_rcg gsbi11_qup_src = {
1254 .ns_reg = 0x2b0c,
1255 .md_reg = 0x2b08,
1256 .mn = {
1257 .mnctr_en_bit = 8,
1258 .mnctr_reset_bit = 7,
1259 .mnctr_mode_shift = 5,
1260 .n_val_shift = 16,
1261 .m_val_shift = 16,
1262 .width = 8,
1263 },
1264 .p = {
1265 .pre_div_shift = 3,
1266 .pre_div_width = 2,
1267 },
1268 .s = {
1269 .src_sel_shift = 0,
1270 .parent_map = gcc_pxo_pll8_map,
1271 },
1272 .freq_tbl = clk_tbl_gsbi_qup,
1273 .clkr = {
1274 .enable_reg = 0x2b0c,
1275 .enable_mask = BIT(11),
1276 .hw.init = &(struct clk_init_data){
1277 .name = "gsbi11_qup_src",
1278 .parent_names = gcc_pxo_pll8,
1279 .num_parents = 2,
1280 .ops = &clk_rcg_ops,
1281 .flags = CLK_SET_PARENT_GATE,
1282 },
1283 },
1284};
1285
1286static struct clk_branch gsbi11_qup_clk = {
1287 .halt_reg = 0x2fd4,
1288 .halt_bit = 15,
1289 .clkr = {
1290 .enable_reg = 0x2b0c,
1291 .enable_mask = BIT(9),
1292 .hw.init = &(struct clk_init_data){
1293 .name = "gsbi11_qup_clk",
1294 .parent_names = (const char *[]){ "gsbi11_qup_src" },
1295 .num_parents = 1,
1296 .ops = &clk_branch_ops,
1297 .flags = CLK_SET_RATE_PARENT,
1298 },
1299 },
1300};
1301
1302static struct clk_rcg gsbi12_qup_src = {
1303 .ns_reg = 0x2b2c,
1304 .md_reg = 0x2b28,
1305 .mn = {
1306 .mnctr_en_bit = 8,
1307 .mnctr_reset_bit = 7,
1308 .mnctr_mode_shift = 5,
1309 .n_val_shift = 16,
1310 .m_val_shift = 16,
1311 .width = 8,
1312 },
1313 .p = {
1314 .pre_div_shift = 3,
1315 .pre_div_width = 2,
1316 },
1317 .s = {
1318 .src_sel_shift = 0,
1319 .parent_map = gcc_pxo_pll8_map,
1320 },
1321 .freq_tbl = clk_tbl_gsbi_qup,
1322 .clkr = {
1323 .enable_reg = 0x2b2c,
1324 .enable_mask = BIT(11),
1325 .hw.init = &(struct clk_init_data){
1326 .name = "gsbi12_qup_src",
1327 .parent_names = gcc_pxo_pll8,
1328 .num_parents = 2,
1329 .ops = &clk_rcg_ops,
1330 .flags = CLK_SET_PARENT_GATE,
1331 },
1332 },
1333};
1334
1335static struct clk_branch gsbi12_qup_clk = {
1336 .halt_reg = 0x2fd4,
1337 .halt_bit = 11,
1338 .clkr = {
1339 .enable_reg = 0x2b2c,
1340 .enable_mask = BIT(9),
1341 .hw.init = &(struct clk_init_data){
1342 .name = "gsbi12_qup_clk",
1343 .parent_names = (const char *[]){ "gsbi12_qup_src" },
1344 .num_parents = 1,
1345 .ops = &clk_branch_ops,
1346 .flags = CLK_SET_RATE_PARENT,
1347 },
1348 },
1349};
1350
1351static const struct freq_tbl clk_tbl_gp[] = {
1352 { 9600000, P_CXO, 2, 0, 0 },
1353 { 13500000, P_PXO, 2, 0, 0 },
1354 { 19200000, P_CXO, 1, 0, 0 },
1355 { 27000000, P_PXO, 1, 0, 0 },
1356 { 64000000, P_PLL8, 2, 1, 3 },
1357 { 76800000, P_PLL8, 1, 1, 5 },
1358 { 96000000, P_PLL8, 4, 0, 0 },
1359 { 128000000, P_PLL8, 3, 0, 0 },
1360 { 192000000, P_PLL8, 2, 0, 0 },
1361 { }
1362};
1363
1364static struct clk_rcg gp0_src = {
1365 .ns_reg = 0x2d24,
1366 .md_reg = 0x2d00,
1367 .mn = {
1368 .mnctr_en_bit = 8,
1369 .mnctr_reset_bit = 7,
1370 .mnctr_mode_shift = 5,
1371 .n_val_shift = 16,
1372 .m_val_shift = 16,
1373 .width = 8,
1374 },
1375 .p = {
1376 .pre_div_shift = 3,
1377 .pre_div_width = 2,
1378 },
1379 .s = {
1380 .src_sel_shift = 0,
1381 .parent_map = gcc_pxo_pll8_cxo_map,
1382 },
1383 .freq_tbl = clk_tbl_gp,
1384 .clkr = {
1385 .enable_reg = 0x2d24,
1386 .enable_mask = BIT(11),
1387 .hw.init = &(struct clk_init_data){
1388 .name = "gp0_src",
1389 .parent_names = gcc_pxo_pll8_cxo,
1390 .num_parents = 3,
1391 .ops = &clk_rcg_ops,
1392 .flags = CLK_SET_PARENT_GATE,
1393 },
1394 }
1395};
1396
1397static struct clk_branch gp0_clk = {
1398 .halt_reg = 0x2fd8,
1399 .halt_bit = 7,
1400 .clkr = {
1401 .enable_reg = 0x2d24,
1402 .enable_mask = BIT(9),
1403 .hw.init = &(struct clk_init_data){
1404 .name = "gp0_clk",
1405 .parent_names = (const char *[]){ "gp0_src" },
1406 .num_parents = 1,
1407 .ops = &clk_branch_ops,
1408 .flags = CLK_SET_RATE_PARENT,
1409 },
1410 },
1411};
1412
1413static struct clk_rcg gp1_src = {
1414 .ns_reg = 0x2d44,
1415 .md_reg = 0x2d40,
1416 .mn = {
1417 .mnctr_en_bit = 8,
1418 .mnctr_reset_bit = 7,
1419 .mnctr_mode_shift = 5,
1420 .n_val_shift = 16,
1421 .m_val_shift = 16,
1422 .width = 8,
1423 },
1424 .p = {
1425 .pre_div_shift = 3,
1426 .pre_div_width = 2,
1427 },
1428 .s = {
1429 .src_sel_shift = 0,
1430 .parent_map = gcc_pxo_pll8_cxo_map,
1431 },
1432 .freq_tbl = clk_tbl_gp,
1433 .clkr = {
1434 .enable_reg = 0x2d44,
1435 .enable_mask = BIT(11),
1436 .hw.init = &(struct clk_init_data){
1437 .name = "gp1_src",
1438 .parent_names = gcc_pxo_pll8_cxo,
1439 .num_parents = 3,
1440 .ops = &clk_rcg_ops,
1441 .flags = CLK_SET_RATE_GATE,
1442 },
1443 }
1444};
1445
1446static struct clk_branch gp1_clk = {
1447 .halt_reg = 0x2fd8,
1448 .halt_bit = 6,
1449 .clkr = {
1450 .enable_reg = 0x2d44,
1451 .enable_mask = BIT(9),
1452 .hw.init = &(struct clk_init_data){
1453 .name = "gp1_clk",
1454 .parent_names = (const char *[]){ "gp1_src" },
1455 .num_parents = 1,
1456 .ops = &clk_branch_ops,
1457 .flags = CLK_SET_RATE_PARENT,
1458 },
1459 },
1460};
1461
1462static struct clk_rcg gp2_src = {
1463 .ns_reg = 0x2d64,
1464 .md_reg = 0x2d60,
1465 .mn = {
1466 .mnctr_en_bit = 8,
1467 .mnctr_reset_bit = 7,
1468 .mnctr_mode_shift = 5,
1469 .n_val_shift = 16,
1470 .m_val_shift = 16,
1471 .width = 8,
1472 },
1473 .p = {
1474 .pre_div_shift = 3,
1475 .pre_div_width = 2,
1476 },
1477 .s = {
1478 .src_sel_shift = 0,
1479 .parent_map = gcc_pxo_pll8_cxo_map,
1480 },
1481 .freq_tbl = clk_tbl_gp,
1482 .clkr = {
1483 .enable_reg = 0x2d64,
1484 .enable_mask = BIT(11),
1485 .hw.init = &(struct clk_init_data){
1486 .name = "gp2_src",
1487 .parent_names = gcc_pxo_pll8_cxo,
1488 .num_parents = 3,
1489 .ops = &clk_rcg_ops,
1490 .flags = CLK_SET_RATE_GATE,
1491 },
1492 }
1493};
1494
1495static struct clk_branch gp2_clk = {
1496 .halt_reg = 0x2fd8,
1497 .halt_bit = 5,
1498 .clkr = {
1499 .enable_reg = 0x2d64,
1500 .enable_mask = BIT(9),
1501 .hw.init = &(struct clk_init_data){
1502 .name = "gp2_clk",
1503 .parent_names = (const char *[]){ "gp2_src" },
1504 .num_parents = 1,
1505 .ops = &clk_branch_ops,
1506 .flags = CLK_SET_RATE_PARENT,
1507 },
1508 },
1509};
1510
1511static struct clk_branch pmem_clk = {
1512 .hwcg_reg = 0x25a0,
1513 .hwcg_bit = 6,
1514 .halt_reg = 0x2fc8,
1515 .halt_bit = 20,
1516 .clkr = {
1517 .enable_reg = 0x25a0,
1518 .enable_mask = BIT(4),
1519 .hw.init = &(struct clk_init_data){
1520 .name = "pmem_clk",
1521 .ops = &clk_branch_ops,
1522 .flags = CLK_IS_ROOT,
1523 },
1524 },
1525};
1526
1527static struct clk_rcg prng_src = {
1528 .ns_reg = 0x2e80,
1529 .p = {
1530 .pre_div_shift = 3,
1531 .pre_div_width = 4,
1532 },
1533 .s = {
1534 .src_sel_shift = 0,
1535 .parent_map = gcc_pxo_pll8_map,
1536 },
1537 .clkr = {
1538 .hw.init = &(struct clk_init_data){
1539 .name = "prng_src",
1540 .parent_names = gcc_pxo_pll8,
1541 .num_parents = 2,
1542 .ops = &clk_rcg_ops,
1543 },
1544 },
1545};
1546
1547static struct clk_branch prng_clk = {
1548 .halt_reg = 0x2fd8,
1549 .halt_check = BRANCH_HALT_VOTED,
1550 .halt_bit = 10,
1551 .clkr = {
1552 .enable_reg = 0x3080,
1553 .enable_mask = BIT(10),
1554 .hw.init = &(struct clk_init_data){
1555 .name = "prng_clk",
1556 .parent_names = (const char *[]){ "prng_src" },
1557 .num_parents = 1,
1558 .ops = &clk_branch_ops,
1559 },
1560 },
1561};
1562
1563static const struct freq_tbl clk_tbl_sdc[] = {
1564 { 144000, P_PXO, 3, 2, 125 },
1565 { 400000, P_PLL8, 4, 1, 240 },
1566 { 16000000, P_PLL8, 4, 1, 6 },
1567 { 17070000, P_PLL8, 1, 2, 45 },
1568 { 20210000, P_PLL8, 1, 1, 19 },
1569 { 24000000, P_PLL8, 4, 1, 4 },
1570 { 48000000, P_PLL8, 4, 1, 2 },
1571 { 64000000, P_PLL8, 3, 1, 2 },
1572 { 96000000, P_PLL8, 4, 0, 0 },
1573 { 192000000, P_PLL8, 2, 0, 0 },
1574 { }
1575};
1576
1577static struct clk_rcg sdc1_src = {
1578 .ns_reg = 0x282c,
1579 .md_reg = 0x2828,
1580 .mn = {
1581 .mnctr_en_bit = 8,
1582 .mnctr_reset_bit = 7,
1583 .mnctr_mode_shift = 5,
1584 .n_val_shift = 16,
1585 .m_val_shift = 16,
1586 .width = 8,
1587 },
1588 .p = {
1589 .pre_div_shift = 3,
1590 .pre_div_width = 2,
1591 },
1592 .s = {
1593 .src_sel_shift = 0,
1594 .parent_map = gcc_pxo_pll8_map,
1595 },
1596 .freq_tbl = clk_tbl_sdc,
1597 .clkr = {
1598 .enable_reg = 0x282c,
1599 .enable_mask = BIT(11),
1600 .hw.init = &(struct clk_init_data){
1601 .name = "sdc1_src",
1602 .parent_names = gcc_pxo_pll8,
1603 .num_parents = 2,
1604 .ops = &clk_rcg_ops,
1605 .flags = CLK_SET_RATE_GATE,
1606 },
1607 }
1608};
1609
1610static struct clk_branch sdc1_clk = {
1611 .halt_reg = 0x2fc8,
1612 .halt_bit = 6,
1613 .clkr = {
1614 .enable_reg = 0x282c,
1615 .enable_mask = BIT(9),
1616 .hw.init = &(struct clk_init_data){
1617 .name = "sdc1_clk",
1618 .parent_names = (const char *[]){ "sdc1_src" },
1619 .num_parents = 1,
1620 .ops = &clk_branch_ops,
1621 .flags = CLK_SET_RATE_PARENT,
1622 },
1623 },
1624};
1625
1626static struct clk_rcg sdc2_src = {
1627 .ns_reg = 0x284c,
1628 .md_reg = 0x2848,
1629 .mn = {
1630 .mnctr_en_bit = 8,
1631 .mnctr_reset_bit = 7,
1632 .mnctr_mode_shift = 5,
1633 .n_val_shift = 16,
1634 .m_val_shift = 16,
1635 .width = 8,
1636 },
1637 .p = {
1638 .pre_div_shift = 3,
1639 .pre_div_width = 2,
1640 },
1641 .s = {
1642 .src_sel_shift = 0,
1643 .parent_map = gcc_pxo_pll8_map,
1644 },
1645 .freq_tbl = clk_tbl_sdc,
1646 .clkr = {
1647 .enable_reg = 0x284c,
1648 .enable_mask = BIT(11),
1649 .hw.init = &(struct clk_init_data){
1650 .name = "sdc2_src",
1651 .parent_names = gcc_pxo_pll8,
1652 .num_parents = 2,
1653 .ops = &clk_rcg_ops,
1654 .flags = CLK_SET_RATE_GATE,
1655 },
1656 }
1657};
1658
1659static struct clk_branch sdc2_clk = {
1660 .halt_reg = 0x2fc8,
1661 .halt_bit = 5,
1662 .clkr = {
1663 .enable_reg = 0x284c,
1664 .enable_mask = BIT(9),
1665 .hw.init = &(struct clk_init_data){
1666 .name = "sdc2_clk",
1667 .parent_names = (const char *[]){ "sdc2_src" },
1668 .num_parents = 1,
1669 .ops = &clk_branch_ops,
1670 .flags = CLK_SET_RATE_PARENT,
1671 },
1672 },
1673};
1674
1675static struct clk_rcg sdc3_src = {
1676 .ns_reg = 0x286c,
1677 .md_reg = 0x2868,
1678 .mn = {
1679 .mnctr_en_bit = 8,
1680 .mnctr_reset_bit = 7,
1681 .mnctr_mode_shift = 5,
1682 .n_val_shift = 16,
1683 .m_val_shift = 16,
1684 .width = 8,
1685 },
1686 .p = {
1687 .pre_div_shift = 3,
1688 .pre_div_width = 2,
1689 },
1690 .s = {
1691 .src_sel_shift = 0,
1692 .parent_map = gcc_pxo_pll8_map,
1693 },
1694 .freq_tbl = clk_tbl_sdc,
1695 .clkr = {
1696 .enable_reg = 0x286c,
1697 .enable_mask = BIT(11),
1698 .hw.init = &(struct clk_init_data){
1699 .name = "sdc3_src",
1700 .parent_names = gcc_pxo_pll8,
1701 .num_parents = 2,
1702 .ops = &clk_rcg_ops,
1703 .flags = CLK_SET_RATE_GATE,
1704 },
1705 }
1706};
1707
1708static struct clk_branch sdc3_clk = {
1709 .halt_reg = 0x2fc8,
1710 .halt_bit = 4,
1711 .clkr = {
1712 .enable_reg = 0x286c,
1713 .enable_mask = BIT(9),
1714 .hw.init = &(struct clk_init_data){
1715 .name = "sdc3_clk",
1716 .parent_names = (const char *[]){ "sdc3_src" },
1717 .num_parents = 1,
1718 .ops = &clk_branch_ops,
1719 .flags = CLK_SET_RATE_PARENT,
1720 },
1721 },
1722};
1723
1724static struct clk_rcg sdc4_src = {
1725 .ns_reg = 0x288c,
1726 .md_reg = 0x2888,
1727 .mn = {
1728 .mnctr_en_bit = 8,
1729 .mnctr_reset_bit = 7,
1730 .mnctr_mode_shift = 5,
1731 .n_val_shift = 16,
1732 .m_val_shift = 16,
1733 .width = 8,
1734 },
1735 .p = {
1736 .pre_div_shift = 3,
1737 .pre_div_width = 2,
1738 },
1739 .s = {
1740 .src_sel_shift = 0,
1741 .parent_map = gcc_pxo_pll8_map,
1742 },
1743 .freq_tbl = clk_tbl_sdc,
1744 .clkr = {
1745 .enable_reg = 0x288c,
1746 .enable_mask = BIT(11),
1747 .hw.init = &(struct clk_init_data){
1748 .name = "sdc4_src",
1749 .parent_names = gcc_pxo_pll8,
1750 .num_parents = 2,
1751 .ops = &clk_rcg_ops,
1752 .flags = CLK_SET_RATE_GATE,
1753 },
1754 }
1755};
1756
1757static struct clk_branch sdc4_clk = {
1758 .halt_reg = 0x2fc8,
1759 .halt_bit = 3,
1760 .clkr = {
1761 .enable_reg = 0x288c,
1762 .enable_mask = BIT(9),
1763 .hw.init = &(struct clk_init_data){
1764 .name = "sdc4_clk",
1765 .parent_names = (const char *[]){ "sdc4_src" },
1766 .num_parents = 1,
1767 .ops = &clk_branch_ops,
1768 .flags = CLK_SET_RATE_PARENT,
1769 },
1770 },
1771};
1772
1773static struct clk_rcg sdc5_src = {
1774 .ns_reg = 0x28ac,
1775 .md_reg = 0x28a8,
1776 .mn = {
1777 .mnctr_en_bit = 8,
1778 .mnctr_reset_bit = 7,
1779 .mnctr_mode_shift = 5,
1780 .n_val_shift = 16,
1781 .m_val_shift = 16,
1782 .width = 8,
1783 },
1784 .p = {
1785 .pre_div_shift = 3,
1786 .pre_div_width = 2,
1787 },
1788 .s = {
1789 .src_sel_shift = 0,
1790 .parent_map = gcc_pxo_pll8_map,
1791 },
1792 .freq_tbl = clk_tbl_sdc,
1793 .clkr = {
1794 .enable_reg = 0x28ac,
1795 .enable_mask = BIT(11),
1796 .hw.init = &(struct clk_init_data){
1797 .name = "sdc5_src",
1798 .parent_names = gcc_pxo_pll8,
1799 .num_parents = 2,
1800 .ops = &clk_rcg_ops,
1801 .flags = CLK_SET_RATE_GATE,
1802 },
1803 }
1804};
1805
1806static struct clk_branch sdc5_clk = {
1807 .halt_reg = 0x2fc8,
1808 .halt_bit = 2,
1809 .clkr = {
1810 .enable_reg = 0x28ac,
1811 .enable_mask = BIT(9),
1812 .hw.init = &(struct clk_init_data){
1813 .name = "sdc5_clk",
1814 .parent_names = (const char *[]){ "sdc5_src" },
1815 .num_parents = 1,
1816 .ops = &clk_branch_ops,
1817 .flags = CLK_SET_RATE_PARENT,
1818 },
1819 },
1820};
1821
1822static const struct freq_tbl clk_tbl_tsif_ref[] = {
1823 { 105000, P_PXO, 1, 1, 256 },
1824 { }
1825};
1826
1827static struct clk_rcg tsif_ref_src = {
1828 .ns_reg = 0x2710,
1829 .md_reg = 0x270c,
1830 .mn = {
1831 .mnctr_en_bit = 8,
1832 .mnctr_reset_bit = 7,
1833 .mnctr_mode_shift = 5,
1834 .n_val_shift = 16,
1835 .m_val_shift = 16,
1836 .width = 16,
1837 },
1838 .p = {
1839 .pre_div_shift = 3,
1840 .pre_div_width = 2,
1841 },
1842 .s = {
1843 .src_sel_shift = 0,
1844 .parent_map = gcc_pxo_pll8_map,
1845 },
1846 .freq_tbl = clk_tbl_tsif_ref,
1847 .clkr = {
1848 .enable_reg = 0x2710,
1849 .enable_mask = BIT(11),
1850 .hw.init = &(struct clk_init_data){
1851 .name = "tsif_ref_src",
1852 .parent_names = gcc_pxo_pll8,
1853 .num_parents = 2,
1854 .ops = &clk_rcg_ops,
1855 .flags = CLK_SET_RATE_GATE,
1856 },
1857 }
1858};
1859
1860static struct clk_branch tsif_ref_clk = {
1861 .halt_reg = 0x2fd4,
1862 .halt_bit = 5,
1863 .clkr = {
1864 .enable_reg = 0x2710,
1865 .enable_mask = BIT(9),
1866 .hw.init = &(struct clk_init_data){
1867 .name = "tsif_ref_clk",
1868 .parent_names = (const char *[]){ "tsif_ref_src" },
1869 .num_parents = 1,
1870 .ops = &clk_branch_ops,
1871 .flags = CLK_SET_RATE_PARENT,
1872 },
1873 },
1874};
1875
1876static const struct freq_tbl clk_tbl_usb[] = {
1877 { 60000000, P_PLL8, 1, 5, 32 },
1878 { }
1879};
1880
1881static struct clk_rcg usb_hs1_xcvr_src = {
1882 .ns_reg = 0x290c,
1883 .md_reg = 0x2908,
1884 .mn = {
1885 .mnctr_en_bit = 8,
1886 .mnctr_reset_bit = 7,
1887 .mnctr_mode_shift = 5,
1888 .n_val_shift = 16,
1889 .m_val_shift = 16,
1890 .width = 8,
1891 },
1892 .p = {
1893 .pre_div_shift = 3,
1894 .pre_div_width = 2,
1895 },
1896 .s = {
1897 .src_sel_shift = 0,
1898 .parent_map = gcc_pxo_pll8_map,
1899 },
1900 .freq_tbl = clk_tbl_usb,
1901 .clkr = {
1902 .enable_reg = 0x290c,
1903 .enable_mask = BIT(11),
1904 .hw.init = &(struct clk_init_data){
1905 .name = "usb_hs1_xcvr_src",
1906 .parent_names = gcc_pxo_pll8,
1907 .num_parents = 2,
1908 .ops = &clk_rcg_ops,
1909 .flags = CLK_SET_RATE_GATE,
1910 },
1911 }
1912};
1913
1914static struct clk_branch usb_hs1_xcvr_clk = {
1915 .halt_reg = 0x2fc8,
1916 .halt_bit = 0,
1917 .clkr = {
1918 .enable_reg = 0x290c,
1919 .enable_mask = BIT(9),
1920 .hw.init = &(struct clk_init_data){
1921 .name = "usb_hs1_xcvr_clk",
1922 .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
1923 .num_parents = 1,
1924 .ops = &clk_branch_ops,
1925 .flags = CLK_SET_RATE_PARENT,
1926 },
1927 },
1928};
1929
1930static struct clk_rcg usb_hsic_xcvr_fs_src = {
1931 .ns_reg = 0x2928,
1932 .md_reg = 0x2924,
1933 .mn = {
1934 .mnctr_en_bit = 8,
1935 .mnctr_reset_bit = 7,
1936 .mnctr_mode_shift = 5,
1937 .n_val_shift = 16,
1938 .m_val_shift = 16,
1939 .width = 8,
1940 },
1941 .p = {
1942 .pre_div_shift = 3,
1943 .pre_div_width = 2,
1944 },
1945 .s = {
1946 .src_sel_shift = 0,
1947 .parent_map = gcc_pxo_pll8_map,
1948 },
1949 .freq_tbl = clk_tbl_usb,
1950 .clkr = {
1951 .enable_reg = 0x2928,
1952 .enable_mask = BIT(11),
1953 .hw.init = &(struct clk_init_data){
1954 .name = "usb_hsic_xcvr_fs_src",
1955 .parent_names = gcc_pxo_pll8,
1956 .num_parents = 2,
1957 .ops = &clk_rcg_ops,
1958 .flags = CLK_SET_RATE_GATE,
1959 },
1960 }
1961};
1962
1963static const char *usb_hsic_xcvr_fs_src_p[] = { "usb_hsic_xcvr_fs_src" };
1964
1965static struct clk_branch usb_hsic_xcvr_fs_clk = {
1966 .halt_reg = 0x2fc8,
1967 .halt_bit = 2,
1968 .clkr = {
1969 .enable_reg = 0x2928,
1970 .enable_mask = BIT(9),
1971 .hw.init = &(struct clk_init_data){
1972 .name = "usb_hsic_xcvr_fs_clk",
1973 .parent_names = usb_hsic_xcvr_fs_src_p,
1974 .num_parents = 1,
1975 .ops = &clk_branch_ops,
1976 .flags = CLK_SET_RATE_PARENT,
1977 },
1978 },
1979};
1980
1981static struct clk_branch usb_hsic_system_clk = {
1982 .halt_reg = 0x2fcc,
1983 .halt_bit = 24,
1984 .clkr = {
1985 .enable_reg = 0x292c,
1986 .enable_mask = BIT(4),
1987 .hw.init = &(struct clk_init_data){
1988 .parent_names = usb_hsic_xcvr_fs_src_p,
1989 .num_parents = 1,
1990 .name = "usb_hsic_system_clk",
1991 .ops = &clk_branch_ops,
1992 .flags = CLK_SET_RATE_PARENT,
1993 },
1994 },
1995};
1996
1997static struct clk_branch usb_hsic_hsic_clk = {
1998 .halt_reg = 0x2fcc,
1999 .halt_bit = 19,
2000 .clkr = {
2001 .enable_reg = 0x2b44,
2002 .enable_mask = BIT(0),
2003 .hw.init = &(struct clk_init_data){
2004 .parent_names = (const char *[]){ "pll14_vote" },
2005 .num_parents = 1,
2006 .name = "usb_hsic_hsic_clk",
2007 .ops = &clk_branch_ops,
2008 },
2009 },
2010};
2011
2012static struct clk_branch usb_hsic_hsio_cal_clk = {
2013 .halt_reg = 0x2fcc,
2014 .halt_bit = 23,
2015 .clkr = {
2016 .enable_reg = 0x2b48,
2017 .enable_mask = BIT(0),
2018 .hw.init = &(struct clk_init_data){
2019 .name = "usb_hsic_hsio_cal_clk",
2020 .ops = &clk_branch_ops,
2021 .flags = CLK_IS_ROOT,
2022 },
2023 },
2024};
2025
2026static struct clk_rcg usb_fs1_xcvr_fs_src = {
2027 .ns_reg = 0x2968,
2028 .md_reg = 0x2964,
2029 .mn = {
2030 .mnctr_en_bit = 8,
2031 .mnctr_reset_bit = 7,
2032 .mnctr_mode_shift = 5,
2033 .n_val_shift = 16,
2034 .m_val_shift = 16,
2035 .width = 8,
2036 },
2037 .p = {
2038 .pre_div_shift = 3,
2039 .pre_div_width = 2,
2040 },
2041 .s = {
2042 .src_sel_shift = 0,
2043 .parent_map = gcc_pxo_pll8_map,
2044 },
2045 .freq_tbl = clk_tbl_usb,
2046 .clkr = {
2047 .enable_reg = 0x2968,
2048 .enable_mask = BIT(11),
2049 .hw.init = &(struct clk_init_data){
2050 .name = "usb_fs1_xcvr_fs_src",
2051 .parent_names = gcc_pxo_pll8,
2052 .num_parents = 2,
2053 .ops = &clk_rcg_ops,
2054 .flags = CLK_SET_RATE_GATE,
2055 },
2056 }
2057};
2058
2059static const char *usb_fs1_xcvr_fs_src_p[] = { "usb_fs1_xcvr_fs_src" };
2060
2061static struct clk_branch usb_fs1_xcvr_fs_clk = {
2062 .halt_reg = 0x2fcc,
2063 .halt_bit = 15,
2064 .clkr = {
2065 .enable_reg = 0x2968,
2066 .enable_mask = BIT(9),
2067 .hw.init = &(struct clk_init_data){
2068 .name = "usb_fs1_xcvr_fs_clk",
2069 .parent_names = usb_fs1_xcvr_fs_src_p,
2070 .num_parents = 1,
2071 .ops = &clk_branch_ops,
2072 .flags = CLK_SET_RATE_PARENT,
2073 },
2074 },
2075};
2076
2077static struct clk_branch usb_fs1_system_clk = {
2078 .halt_reg = 0x2fcc,
2079 .halt_bit = 16,
2080 .clkr = {
2081 .enable_reg = 0x296c,
2082 .enable_mask = BIT(4),
2083 .hw.init = &(struct clk_init_data){
2084 .parent_names = usb_fs1_xcvr_fs_src_p,
2085 .num_parents = 1,
2086 .name = "usb_fs1_system_clk",
2087 .ops = &clk_branch_ops,
2088 .flags = CLK_SET_RATE_PARENT,
2089 },
2090 },
2091};
2092
2093static struct clk_rcg usb_fs2_xcvr_fs_src = {
2094 .ns_reg = 0x2988,
2095 .md_reg = 0x2984,
2096 .mn = {
2097 .mnctr_en_bit = 8,
2098 .mnctr_reset_bit = 7,
2099 .mnctr_mode_shift = 5,
2100 .n_val_shift = 16,
2101 .m_val_shift = 16,
2102 .width = 8,
2103 },
2104 .p = {
2105 .pre_div_shift = 3,
2106 .pre_div_width = 2,
2107 },
2108 .s = {
2109 .src_sel_shift = 0,
2110 .parent_map = gcc_pxo_pll8_map,
2111 },
2112 .freq_tbl = clk_tbl_usb,
2113 .clkr = {
2114 .enable_reg = 0x2988,
2115 .enable_mask = BIT(11),
2116 .hw.init = &(struct clk_init_data){
2117 .name = "usb_fs2_xcvr_fs_src",
2118 .parent_names = gcc_pxo_pll8,
2119 .num_parents = 2,
2120 .ops = &clk_rcg_ops,
2121 .flags = CLK_SET_RATE_GATE,
2122 },
2123 }
2124};
2125
2126static const char *usb_fs2_xcvr_fs_src_p[] = { "usb_fs2_xcvr_fs_src" };
2127
2128static struct clk_branch usb_fs2_xcvr_fs_clk = {
2129 .halt_reg = 0x2fcc,
2130 .halt_bit = 12,
2131 .clkr = {
2132 .enable_reg = 0x2988,
2133 .enable_mask = BIT(9),
2134 .hw.init = &(struct clk_init_data){
2135 .name = "usb_fs2_xcvr_fs_clk",
2136 .parent_names = usb_fs2_xcvr_fs_src_p,
2137 .num_parents = 1,
2138 .ops = &clk_branch_ops,
2139 .flags = CLK_SET_RATE_PARENT,
2140 },
2141 },
2142};
2143
2144static struct clk_branch usb_fs2_system_clk = {
2145 .halt_reg = 0x2fcc,
2146 .halt_bit = 13,
2147 .clkr = {
2148 .enable_reg = 0x298c,
2149 .enable_mask = BIT(4),
2150 .hw.init = &(struct clk_init_data){
2151 .name = "usb_fs2_system_clk",
2152 .parent_names = usb_fs2_xcvr_fs_src_p,
2153 .num_parents = 1,
2154 .ops = &clk_branch_ops,
2155 .flags = CLK_SET_RATE_PARENT,
2156 },
2157 },
2158};
2159
2160static struct clk_branch ce1_core_clk = {
2161 .hwcg_reg = 0x2724,
2162 .hwcg_bit = 6,
2163 .halt_reg = 0x2fd4,
2164 .halt_bit = 27,
2165 .clkr = {
2166 .enable_reg = 0x2724,
2167 .enable_mask = BIT(4),
2168 .hw.init = &(struct clk_init_data){
2169 .name = "ce1_core_clk",
2170 .ops = &clk_branch_ops,
2171 .flags = CLK_IS_ROOT,
2172 },
2173 },
2174};
2175
2176static struct clk_branch ce1_h_clk = {
2177 .halt_reg = 0x2fd4,
2178 .halt_bit = 1,
2179 .clkr = {
2180 .enable_reg = 0x2720,
2181 .enable_mask = BIT(4),
2182 .hw.init = &(struct clk_init_data){
2183 .name = "ce1_h_clk",
2184 .ops = &clk_branch_ops,
2185 .flags = CLK_IS_ROOT,
2186 },
2187 },
2188};
2189
2190static struct clk_branch dma_bam_h_clk = {
2191 .hwcg_reg = 0x25c0,
2192 .hwcg_bit = 6,
2193 .halt_reg = 0x2fc8,
2194 .halt_bit = 12,
2195 .clkr = {
2196 .enable_reg = 0x25c0,
2197 .enable_mask = BIT(4),
2198 .hw.init = &(struct clk_init_data){
2199 .name = "dma_bam_h_clk",
2200 .ops = &clk_branch_ops,
2201 .flags = CLK_IS_ROOT,
2202 },
2203 },
2204};
2205
2206static struct clk_branch gsbi1_h_clk = {
2207 .hwcg_reg = 0x29c0,
2208 .hwcg_bit = 6,
2209 .halt_reg = 0x2fcc,
2210 .halt_bit = 11,
2211 .clkr = {
2212 .enable_reg = 0x29c0,
2213 .enable_mask = BIT(4),
2214 .hw.init = &(struct clk_init_data){
2215 .name = "gsbi1_h_clk",
2216 .ops = &clk_branch_ops,
2217 .flags = CLK_IS_ROOT,
2218 },
2219 },
2220};
2221
2222static struct clk_branch gsbi2_h_clk = {
2223 .hwcg_reg = 0x29e0,
2224 .hwcg_bit = 6,
2225 .halt_reg = 0x2fcc,
2226 .halt_bit = 7,
2227 .clkr = {
2228 .enable_reg = 0x29e0,
2229 .enable_mask = BIT(4),
2230 .hw.init = &(struct clk_init_data){
2231 .name = "gsbi2_h_clk",
2232 .ops = &clk_branch_ops,
2233 .flags = CLK_IS_ROOT,
2234 },
2235 },
2236};
2237
2238static struct clk_branch gsbi3_h_clk = {
2239 .hwcg_reg = 0x2a00,
2240 .hwcg_bit = 6,
2241 .halt_reg = 0x2fcc,
2242 .halt_bit = 3,
2243 .clkr = {
2244 .enable_reg = 0x2a00,
2245 .enable_mask = BIT(4),
2246 .hw.init = &(struct clk_init_data){
2247 .name = "gsbi3_h_clk",
2248 .ops = &clk_branch_ops,
2249 .flags = CLK_IS_ROOT,
2250 },
2251 },
2252};
2253
2254static struct clk_branch gsbi4_h_clk = {
2255 .hwcg_reg = 0x2a20,
2256 .hwcg_bit = 6,
2257 .halt_reg = 0x2fd0,
2258 .halt_bit = 27,
2259 .clkr = {
2260 .enable_reg = 0x2a20,
2261 .enable_mask = BIT(4),
2262 .hw.init = &(struct clk_init_data){
2263 .name = "gsbi4_h_clk",
2264 .ops = &clk_branch_ops,
2265 .flags = CLK_IS_ROOT,
2266 },
2267 },
2268};
2269
2270static struct clk_branch gsbi5_h_clk = {
2271 .hwcg_reg = 0x2a40,
2272 .hwcg_bit = 6,
2273 .halt_reg = 0x2fd0,
2274 .halt_bit = 23,
2275 .clkr = {
2276 .enable_reg = 0x2a40,
2277 .enable_mask = BIT(4),
2278 .hw.init = &(struct clk_init_data){
2279 .name = "gsbi5_h_clk",
2280 .ops = &clk_branch_ops,
2281 .flags = CLK_IS_ROOT,
2282 },
2283 },
2284};
2285
2286static struct clk_branch gsbi6_h_clk = {
2287 .hwcg_reg = 0x2a60,
2288 .hwcg_bit = 6,
2289 .halt_reg = 0x2fd0,
2290 .halt_bit = 19,
2291 .clkr = {
2292 .enable_reg = 0x2a60,
2293 .enable_mask = BIT(4),
2294 .hw.init = &(struct clk_init_data){
2295 .name = "gsbi6_h_clk",
2296 .ops = &clk_branch_ops,
2297 .flags = CLK_IS_ROOT,
2298 },
2299 },
2300};
2301
2302static struct clk_branch gsbi7_h_clk = {
2303 .hwcg_reg = 0x2a80,
2304 .hwcg_bit = 6,
2305 .halt_reg = 0x2fd0,
2306 .halt_bit = 15,
2307 .clkr = {
2308 .enable_reg = 0x2a80,
2309 .enable_mask = BIT(4),
2310 .hw.init = &(struct clk_init_data){
2311 .name = "gsbi7_h_clk",
2312 .ops = &clk_branch_ops,
2313 .flags = CLK_IS_ROOT,
2314 },
2315 },
2316};
2317
2318static struct clk_branch gsbi8_h_clk = {
2319 .hwcg_reg = 0x2aa0,
2320 .hwcg_bit = 6,
2321 .halt_reg = 0x2fd0,
2322 .halt_bit = 11,
2323 .clkr = {
2324 .enable_reg = 0x2aa0,
2325 .enable_mask = BIT(4),
2326 .hw.init = &(struct clk_init_data){
2327 .name = "gsbi8_h_clk",
2328 .ops = &clk_branch_ops,
2329 .flags = CLK_IS_ROOT,
2330 },
2331 },
2332};
2333
2334static struct clk_branch gsbi9_h_clk = {
2335 .hwcg_reg = 0x2ac0,
2336 .hwcg_bit = 6,
2337 .halt_reg = 0x2fd0,
2338 .halt_bit = 7,
2339 .clkr = {
2340 .enable_reg = 0x2ac0,
2341 .enable_mask = BIT(4),
2342 .hw.init = &(struct clk_init_data){
2343 .name = "gsbi9_h_clk",
2344 .ops = &clk_branch_ops,
2345 .flags = CLK_IS_ROOT,
2346 },
2347 },
2348};
2349
2350static struct clk_branch gsbi10_h_clk = {
2351 .hwcg_reg = 0x2ae0,
2352 .hwcg_bit = 6,
2353 .halt_reg = 0x2fd0,
2354 .halt_bit = 3,
2355 .clkr = {
2356 .enable_reg = 0x2ae0,
2357 .enable_mask = BIT(4),
2358 .hw.init = &(struct clk_init_data){
2359 .name = "gsbi10_h_clk",
2360 .ops = &clk_branch_ops,
2361 .flags = CLK_IS_ROOT,
2362 },
2363 },
2364};
2365
2366static struct clk_branch gsbi11_h_clk = {
2367 .hwcg_reg = 0x2b00,
2368 .hwcg_bit = 6,
2369 .halt_reg = 0x2fd4,
2370 .halt_bit = 18,
2371 .clkr = {
2372 .enable_reg = 0x2b00,
2373 .enable_mask = BIT(4),
2374 .hw.init = &(struct clk_init_data){
2375 .name = "gsbi11_h_clk",
2376 .ops = &clk_branch_ops,
2377 .flags = CLK_IS_ROOT,
2378 },
2379 },
2380};
2381
2382static struct clk_branch gsbi12_h_clk = {
2383 .hwcg_reg = 0x2b20,
2384 .hwcg_bit = 6,
2385 .halt_reg = 0x2fd4,
2386 .halt_bit = 14,
2387 .clkr = {
2388 .enable_reg = 0x2b20,
2389 .enable_mask = BIT(4),
2390 .hw.init = &(struct clk_init_data){
2391 .name = "gsbi12_h_clk",
2392 .ops = &clk_branch_ops,
2393 .flags = CLK_IS_ROOT,
2394 },
2395 },
2396};
2397
2398static struct clk_branch tsif_h_clk = {
2399 .hwcg_reg = 0x2700,
2400 .hwcg_bit = 6,
2401 .halt_reg = 0x2fd4,
2402 .halt_bit = 7,
2403 .clkr = {
2404 .enable_reg = 0x2700,
2405 .enable_mask = BIT(4),
2406 .hw.init = &(struct clk_init_data){
2407 .name = "tsif_h_clk",
2408 .ops = &clk_branch_ops,
2409 .flags = CLK_IS_ROOT,
2410 },
2411 },
2412};
2413
2414static struct clk_branch usb_fs1_h_clk = {
2415 .halt_reg = 0x2fcc,
2416 .halt_bit = 17,
2417 .clkr = {
2418 .enable_reg = 0x2960,
2419 .enable_mask = BIT(4),
2420 .hw.init = &(struct clk_init_data){
2421 .name = "usb_fs1_h_clk",
2422 .ops = &clk_branch_ops,
2423 .flags = CLK_IS_ROOT,
2424 },
2425 },
2426};
2427
2428static struct clk_branch usb_fs2_h_clk = {
2429 .halt_reg = 0x2fcc,
2430 .halt_bit = 14,
2431 .clkr = {
2432 .enable_reg = 0x2980,
2433 .enable_mask = BIT(4),
2434 .hw.init = &(struct clk_init_data){
2435 .name = "usb_fs2_h_clk",
2436 .ops = &clk_branch_ops,
2437 .flags = CLK_IS_ROOT,
2438 },
2439 },
2440};
2441
2442static struct clk_branch usb_hs1_h_clk = {
2443 .hwcg_reg = 0x2900,
2444 .hwcg_bit = 6,
2445 .halt_reg = 0x2fc8,
2446 .halt_bit = 1,
2447 .clkr = {
2448 .enable_reg = 0x2900,
2449 .enable_mask = BIT(4),
2450 .hw.init = &(struct clk_init_data){
2451 .name = "usb_hs1_h_clk",
2452 .ops = &clk_branch_ops,
2453 .flags = CLK_IS_ROOT,
2454 },
2455 },
2456};
2457
2458static struct clk_branch usb_hsic_h_clk = {
2459 .halt_reg = 0x2fcc,
2460 .halt_bit = 28,
2461 .clkr = {
2462 .enable_reg = 0x2920,
2463 .enable_mask = BIT(4),
2464 .hw.init = &(struct clk_init_data){
2465 .name = "usb_hsic_h_clk",
2466 .ops = &clk_branch_ops,
2467 .flags = CLK_IS_ROOT,
2468 },
2469 },
2470};
2471
2472static struct clk_branch sdc1_h_clk = {
2473 .hwcg_reg = 0x2820,
2474 .hwcg_bit = 6,
2475 .halt_reg = 0x2fc8,
2476 .halt_bit = 11,
2477 .clkr = {
2478 .enable_reg = 0x2820,
2479 .enable_mask = BIT(4),
2480 .hw.init = &(struct clk_init_data){
2481 .name = "sdc1_h_clk",
2482 .ops = &clk_branch_ops,
2483 .flags = CLK_IS_ROOT,
2484 },
2485 },
2486};
2487
2488static struct clk_branch sdc2_h_clk = {
2489 .hwcg_reg = 0x2840,
2490 .hwcg_bit = 6,
2491 .halt_reg = 0x2fc8,
2492 .halt_bit = 10,
2493 .clkr = {
2494 .enable_reg = 0x2840,
2495 .enable_mask = BIT(4),
2496 .hw.init = &(struct clk_init_data){
2497 .name = "sdc2_h_clk",
2498 .ops = &clk_branch_ops,
2499 .flags = CLK_IS_ROOT,
2500 },
2501 },
2502};
2503
2504static struct clk_branch sdc3_h_clk = {
2505 .hwcg_reg = 0x2860,
2506 .hwcg_bit = 6,
2507 .halt_reg = 0x2fc8,
2508 .halt_bit = 9,
2509 .clkr = {
2510 .enable_reg = 0x2860,
2511 .enable_mask = BIT(4),
2512 .hw.init = &(struct clk_init_data){
2513 .name = "sdc3_h_clk",
2514 .ops = &clk_branch_ops,
2515 .flags = CLK_IS_ROOT,
2516 },
2517 },
2518};
2519
2520static struct clk_branch sdc4_h_clk = {
2521 .hwcg_reg = 0x2880,
2522 .hwcg_bit = 6,
2523 .halt_reg = 0x2fc8,
2524 .halt_bit = 8,
2525 .clkr = {
2526 .enable_reg = 0x2880,
2527 .enable_mask = BIT(4),
2528 .hw.init = &(struct clk_init_data){
2529 .name = "sdc4_h_clk",
2530 .ops = &clk_branch_ops,
2531 .flags = CLK_IS_ROOT,
2532 },
2533 },
2534};
2535
2536static struct clk_branch sdc5_h_clk = {
2537 .hwcg_reg = 0x28a0,
2538 .hwcg_bit = 6,
2539 .halt_reg = 0x2fc8,
2540 .halt_bit = 7,
2541 .clkr = {
2542 .enable_reg = 0x28a0,
2543 .enable_mask = BIT(4),
2544 .hw.init = &(struct clk_init_data){
2545 .name = "sdc5_h_clk",
2546 .ops = &clk_branch_ops,
2547 .flags = CLK_IS_ROOT,
2548 },
2549 },
2550};
2551
2552static struct clk_branch adm0_clk = {
2553 .halt_reg = 0x2fdc,
2554 .halt_check = BRANCH_HALT_VOTED,
2555 .halt_bit = 14,
2556 .clkr = {
2557 .enable_reg = 0x3080,
2558 .enable_mask = BIT(2),
2559 .hw.init = &(struct clk_init_data){
2560 .name = "adm0_clk",
2561 .ops = &clk_branch_ops,
2562 .flags = CLK_IS_ROOT,
2563 },
2564 },
2565};
2566
2567static struct clk_branch adm0_pbus_clk = {
2568 .hwcg_reg = 0x2208,
2569 .hwcg_bit = 6,
2570 .halt_reg = 0x2fdc,
2571 .halt_check = BRANCH_HALT_VOTED,
2572 .halt_bit = 13,
2573 .clkr = {
2574 .enable_reg = 0x3080,
2575 .enable_mask = BIT(3),
2576 .hw.init = &(struct clk_init_data){
2577 .name = "adm0_pbus_clk",
2578 .ops = &clk_branch_ops,
2579 .flags = CLK_IS_ROOT,
2580 },
2581 },
2582};
2583
2584static struct clk_branch pmic_arb0_h_clk = {
2585 .halt_reg = 0x2fd8,
2586 .halt_check = BRANCH_HALT_VOTED,
2587 .halt_bit = 22,
2588 .clkr = {
2589 .enable_reg = 0x3080,
2590 .enable_mask = BIT(8),
2591 .hw.init = &(struct clk_init_data){
2592 .name = "pmic_arb0_h_clk",
2593 .ops = &clk_branch_ops,
2594 .flags = CLK_IS_ROOT,
2595 },
2596 },
2597};
2598
2599static struct clk_branch pmic_arb1_h_clk = {
2600 .halt_reg = 0x2fd8,
2601 .halt_check = BRANCH_HALT_VOTED,
2602 .halt_bit = 21,
2603 .clkr = {
2604 .enable_reg = 0x3080,
2605 .enable_mask = BIT(9),
2606 .hw.init = &(struct clk_init_data){
2607 .name = "pmic_arb1_h_clk",
2608 .ops = &clk_branch_ops,
2609 .flags = CLK_IS_ROOT,
2610 },
2611 },
2612};
2613
2614static struct clk_branch pmic_ssbi2_clk = {
2615 .halt_reg = 0x2fd8,
2616 .halt_check = BRANCH_HALT_VOTED,
2617 .halt_bit = 23,
2618 .clkr = {
2619 .enable_reg = 0x3080,
2620 .enable_mask = BIT(7),
2621 .hw.init = &(struct clk_init_data){
2622 .name = "pmic_ssbi2_clk",
2623 .ops = &clk_branch_ops,
2624 .flags = CLK_IS_ROOT,
2625 },
2626 },
2627};
2628
2629static struct clk_branch rpm_msg_ram_h_clk = {
2630 .hwcg_reg = 0x27e0,
2631 .hwcg_bit = 6,
2632 .halt_reg = 0x2fd8,
2633 .halt_check = BRANCH_HALT_VOTED,
2634 .halt_bit = 12,
2635 .clkr = {
2636 .enable_reg = 0x3080,
2637 .enable_mask = BIT(6),
2638 .hw.init = &(struct clk_init_data){
2639 .name = "rpm_msg_ram_h_clk",
2640 .ops = &clk_branch_ops,
2641 .flags = CLK_IS_ROOT,
2642 },
2643 },
2644};
2645
2646static struct clk_regmap *gcc_msm8960_clks[] = {
2647 [PLL3] = &pll3.clkr,
2648 [PLL8] = &pll8.clkr,
2649 [PLL8_VOTE] = &pll8_vote,
2650 [PLL14] = &pll14.clkr,
2651 [PLL14_VOTE] = &pll14_vote,
2652 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
2653 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
2654 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
2655 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
2656 [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
2657 [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
2658 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
2659 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
2660 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
2661 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
2662 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
2663 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
2664 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
2665 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
2666 [GSBI8_UART_SRC] = &gsbi8_uart_src.clkr,
2667 [GSBI8_UART_CLK] = &gsbi8_uart_clk.clkr,
2668 [GSBI9_UART_SRC] = &gsbi9_uart_src.clkr,
2669 [GSBI9_UART_CLK] = &gsbi9_uart_clk.clkr,
2670 [GSBI10_UART_SRC] = &gsbi10_uart_src.clkr,
2671 [GSBI10_UART_CLK] = &gsbi10_uart_clk.clkr,
2672 [GSBI11_UART_SRC] = &gsbi11_uart_src.clkr,
2673 [GSBI11_UART_CLK] = &gsbi11_uart_clk.clkr,
2674 [GSBI12_UART_SRC] = &gsbi12_uart_src.clkr,
2675 [GSBI12_UART_CLK] = &gsbi12_uart_clk.clkr,
2676 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
2677 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
2678 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
2679 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
2680 [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
2681 [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
2682 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
2683 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
2684 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
2685 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
2686 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
2687 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
2688 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
2689 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
2690 [GSBI8_QUP_SRC] = &gsbi8_qup_src.clkr,
2691 [GSBI8_QUP_CLK] = &gsbi8_qup_clk.clkr,
2692 [GSBI9_QUP_SRC] = &gsbi9_qup_src.clkr,
2693 [GSBI9_QUP_CLK] = &gsbi9_qup_clk.clkr,
2694 [GSBI10_QUP_SRC] = &gsbi10_qup_src.clkr,
2695 [GSBI10_QUP_CLK] = &gsbi10_qup_clk.clkr,
2696 [GSBI11_QUP_SRC] = &gsbi11_qup_src.clkr,
2697 [GSBI11_QUP_CLK] = &gsbi11_qup_clk.clkr,
2698 [GSBI12_QUP_SRC] = &gsbi12_qup_src.clkr,
2699 [GSBI12_QUP_CLK] = &gsbi12_qup_clk.clkr,
2700 [GP0_SRC] = &gp0_src.clkr,
2701 [GP0_CLK] = &gp0_clk.clkr,
2702 [GP1_SRC] = &gp1_src.clkr,
2703 [GP1_CLK] = &gp1_clk.clkr,
2704 [GP2_SRC] = &gp2_src.clkr,
2705 [GP2_CLK] = &gp2_clk.clkr,
2706 [PMEM_A_CLK] = &pmem_clk.clkr,
2707 [PRNG_SRC] = &prng_src.clkr,
2708 [PRNG_CLK] = &prng_clk.clkr,
2709 [SDC1_SRC] = &sdc1_src.clkr,
2710 [SDC1_CLK] = &sdc1_clk.clkr,
2711 [SDC2_SRC] = &sdc2_src.clkr,
2712 [SDC2_CLK] = &sdc2_clk.clkr,
2713 [SDC3_SRC] = &sdc3_src.clkr,
2714 [SDC3_CLK] = &sdc3_clk.clkr,
2715 [SDC4_SRC] = &sdc4_src.clkr,
2716 [SDC4_CLK] = &sdc4_clk.clkr,
2717 [SDC5_SRC] = &sdc5_src.clkr,
2718 [SDC5_CLK] = &sdc5_clk.clkr,
2719 [TSIF_REF_SRC] = &tsif_ref_src.clkr,
2720 [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
2721 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
2722 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
2723 [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
2724 [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
2725 [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
2726 [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
2727 [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
2728 [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
2729 [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
2730 [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
2731 [USB_FS2_XCVR_FS_SRC] = &usb_fs2_xcvr_fs_src.clkr,
2732 [USB_FS2_XCVR_FS_CLK] = &usb_fs2_xcvr_fs_clk.clkr,
2733 [USB_FS2_SYSTEM_CLK] = &usb_fs2_system_clk.clkr,
2734 [CE1_CORE_CLK] = &ce1_core_clk.clkr,
2735 [CE1_H_CLK] = &ce1_h_clk.clkr,
2736 [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
2737 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
2738 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
2739 [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
2740 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
2741 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
2742 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
2743 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
2744 [GSBI8_H_CLK] = &gsbi8_h_clk.clkr,
2745 [GSBI9_H_CLK] = &gsbi9_h_clk.clkr,
2746 [GSBI10_H_CLK] = &gsbi10_h_clk.clkr,
2747 [GSBI11_H_CLK] = &gsbi11_h_clk.clkr,
2748 [GSBI12_H_CLK] = &gsbi12_h_clk.clkr,
2749 [TSIF_H_CLK] = &tsif_h_clk.clkr,
2750 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
2751 [USB_FS2_H_CLK] = &usb_fs2_h_clk.clkr,
2752 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
2753 [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
2754 [SDC1_H_CLK] = &sdc1_h_clk.clkr,
2755 [SDC2_H_CLK] = &sdc2_h_clk.clkr,
2756 [SDC3_H_CLK] = &sdc3_h_clk.clkr,
2757 [SDC4_H_CLK] = &sdc4_h_clk.clkr,
2758 [SDC5_H_CLK] = &sdc5_h_clk.clkr,
2759 [ADM0_CLK] = &adm0_clk.clkr,
2760 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
2761 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
2762 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
2763 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
2764 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
2765};
2766
2767static const struct qcom_reset_map gcc_msm8960_resets[] = {
2768 [SFAB_MSS_Q6_SW_RESET] = { 0x2040, 7 },
2769 [SFAB_MSS_Q6_FW_RESET] = { 0x2044, 7 },
2770 [QDSS_STM_RESET] = { 0x2060, 6 },
2771 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
2772 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
2773 [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
2774 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
2775 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
2776 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
2777 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
2778 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
2779 [ADM0_C2_RESET] = { 0x220c, 4},
2780 [ADM0_C1_RESET] = { 0x220c, 3},
2781 [ADM0_C0_RESET] = { 0x220c, 2},
2782 [ADM0_PBUS_RESET] = { 0x220c, 1 },
2783 [ADM0_RESET] = { 0x220c },
2784 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
2785 [QDSS_POR_RESET] = { 0x2260, 4 },
2786 [QDSS_TSCTR_RESET] = { 0x2260, 3 },
2787 [QDSS_HRESET_RESET] = { 0x2260, 2 },
2788 [QDSS_AXI_RESET] = { 0x2260, 1 },
2789 [QDSS_DBG_RESET] = { 0x2260 },
2790 [PCIE_A_RESET] = { 0x22c0, 7 },
2791 [PCIE_AUX_RESET] = { 0x22c8, 7 },
2792 [PCIE_H_RESET] = { 0x22d0, 7 },
2793 [SFAB_PCIE_M_RESET] = { 0x22d4, 1 },
2794 [SFAB_PCIE_S_RESET] = { 0x22d4 },
2795 [SFAB_MSS_M_RESET] = { 0x2340, 7 },
2796 [SFAB_USB3_M_RESET] = { 0x2360, 7 },
2797 [SFAB_RIVA_M_RESET] = { 0x2380, 7 },
2798 [SFAB_LPASS_RESET] = { 0x23a0, 7 },
2799 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
2800 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
2801 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
2802 [SFAB_SATA_S_RESET] = { 0x2480, 7 },
2803 [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
2804 [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
2805 [DFAB_SWAY0_RESET] = { 0x2540, 7 },
2806 [DFAB_SWAY1_RESET] = { 0x2544, 7 },
2807 [DFAB_ARB0_RESET] = { 0x2560, 7 },
2808 [DFAB_ARB1_RESET] = { 0x2564, 7 },
2809 [PPSS_PROC_RESET] = { 0x2594, 1 },
2810 [PPSS_RESET] = { 0x2594},
2811 [DMA_BAM_RESET] = { 0x25c0, 7 },
2812 [SIC_TIC_RESET] = { 0x2600, 7 },
2813 [SLIMBUS_H_RESET] = { 0x2620, 7 },
2814 [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
2815 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
2816 [TSIF_H_RESET] = { 0x2700, 7 },
2817 [CE1_H_RESET] = { 0x2720, 7 },
2818 [CE1_CORE_RESET] = { 0x2724, 7 },
2819 [CE1_SLEEP_RESET] = { 0x2728, 7 },
2820 [CE2_H_RESET] = { 0x2740, 7 },
2821 [CE2_CORE_RESET] = { 0x2744, 7 },
2822 [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
2823 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
2824 [RPM_PROC_RESET] = { 0x27c0, 7 },
2825 [PMIC_SSBI2_RESET] = { 0x270c, 12 },
2826 [SDC1_RESET] = { 0x2830 },
2827 [SDC2_RESET] = { 0x2850 },
2828 [SDC3_RESET] = { 0x2870 },
2829 [SDC4_RESET] = { 0x2890 },
2830 [SDC5_RESET] = { 0x28b0 },
2831 [DFAB_A2_RESET] = { 0x28c0, 7 },
2832 [USB_HS1_RESET] = { 0x2910 },
2833 [USB_HSIC_RESET] = { 0x2934 },
2834 [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
2835 [USB_FS1_RESET] = { 0x2974 },
2836 [USB_FS2_XCVR_RESET] = { 0x2994, 1 },
2837 [USB_FS2_RESET] = { 0x2994 },
2838 [GSBI1_RESET] = { 0x29dc },
2839 [GSBI2_RESET] = { 0x29fc },
2840 [GSBI3_RESET] = { 0x2a1c },
2841 [GSBI4_RESET] = { 0x2a3c },
2842 [GSBI5_RESET] = { 0x2a5c },
2843 [GSBI6_RESET] = { 0x2a7c },
2844 [GSBI7_RESET] = { 0x2a9c },
2845 [GSBI8_RESET] = { 0x2abc },
2846 [GSBI9_RESET] = { 0x2adc },
2847 [GSBI10_RESET] = { 0x2afc },
2848 [GSBI11_RESET] = { 0x2b1c },
2849 [GSBI12_RESET] = { 0x2b3c },
2850 [SPDM_RESET] = { 0x2b6c },
2851 [TLMM_H_RESET] = { 0x2ba0, 7 },
2852 [SFAB_MSS_S_RESET] = { 0x2c00, 7 },
2853 [MSS_SLP_RESET] = { 0x2c60, 7 },
2854 [MSS_Q6SW_JTAG_RESET] = { 0x2c68, 7 },
2855 [MSS_Q6FW_JTAG_RESET] = { 0x2c6c, 7 },
2856 [MSS_RESET] = { 0x2c64 },
2857 [SATA_H_RESET] = { 0x2c80, 7 },
2858 [SATA_RXOOB_RESE] = { 0x2c8c, 7 },
2859 [SATA_PMALIVE_RESET] = { 0x2c90, 7 },
2860 [SATA_SFAB_M_RESET] = { 0x2c98, 7 },
2861 [TSSC_RESET] = { 0x2ca0, 7 },
2862 [PDM_RESET] = { 0x2cc0, 12 },
2863 [MPM_H_RESET] = { 0x2da0, 7 },
2864 [MPM_RESET] = { 0x2da4 },
2865 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
2866 [PRNG_RESET] = { 0x2e80, 12 },
2867 [RIVA_RESET] = { 0x35e0 },
2868};
2869
2870static const struct regmap_config gcc_msm8960_regmap_config = {
2871 .reg_bits = 32,
2872 .reg_stride = 4,
2873 .val_bits = 32,
2874 .max_register = 0x3660,
2875 .fast_io = true,
2876};
2877
2878static const struct of_device_id gcc_msm8960_match_table[] = {
2879 { .compatible = "qcom,gcc-msm8960" },
2880 { }
2881};
2882MODULE_DEVICE_TABLE(of, gcc_msm8960_match_table);
2883
2884struct qcom_cc {
2885 struct qcom_reset_controller reset;
2886 struct clk_onecell_data data;
2887 struct clk *clks[];
2888};
2889
2890static int gcc_msm8960_probe(struct platform_device *pdev)
2891{
2892 void __iomem *base;
2893 struct resource *res;
2894 int i, ret;
2895 struct device *dev = &pdev->dev;
2896 struct clk *clk;
2897 struct clk_onecell_data *data;
2898 struct clk **clks;
2899 struct regmap *regmap;
2900 size_t num_clks;
2901 struct qcom_reset_controller *reset;
2902 struct qcom_cc *cc;
2903
2904 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2905 base = devm_ioremap_resource(dev, res);
2906 if (IS_ERR(base))
2907 return PTR_ERR(base);
2908
2909 regmap = devm_regmap_init_mmio(dev, base, &gcc_msm8960_regmap_config);
2910 if (IS_ERR(regmap))
2911 return PTR_ERR(regmap);
2912
2913 num_clks = ARRAY_SIZE(gcc_msm8960_clks);
2914 cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*clks) * num_clks,
2915 GFP_KERNEL);
2916 if (!cc)
2917 return -ENOMEM;
2918
2919 clks = cc->clks;
2920 data = &cc->data;
2921 data->clks = clks;
2922 data->clk_num = num_clks;
2923
2924 /* Temporary until RPM clocks supported */
2925 clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 19200000);
2926 if (IS_ERR(clk))
2927 return PTR_ERR(clk);
2928
2929 clk = clk_register_fixed_rate(dev, "pxo", NULL, CLK_IS_ROOT, 27000000);
2930 if (IS_ERR(clk))
2931 return PTR_ERR(clk);
2932
2933 for (i = 0; i < num_clks; i++) {
2934 if (!gcc_msm8960_clks[i])
2935 continue;
2936 clk = devm_clk_register_regmap(dev, gcc_msm8960_clks[i]);
2937 if (IS_ERR(clk))
2938 return PTR_ERR(clk);
2939 clks[i] = clk;
2940 }
2941
2942 ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, data);
2943 if (ret)
2944 return ret;
2945
2946 reset = &cc->reset;
2947 reset->rcdev.of_node = dev->of_node;
2948 reset->rcdev.ops = &qcom_reset_ops,
2949 reset->rcdev.owner = THIS_MODULE,
2950 reset->rcdev.nr_resets = ARRAY_SIZE(gcc_msm8960_resets),
2951 reset->regmap = regmap;
2952 reset->reset_map = gcc_msm8960_resets,
2953 platform_set_drvdata(pdev, &reset->rcdev);
2954
2955 ret = reset_controller_register(&reset->rcdev);
2956 if (ret)
2957 of_clk_del_provider(dev->of_node);
2958
2959 return ret;
2960}
2961
2962static int gcc_msm8960_remove(struct platform_device *pdev)
2963{
2964 of_clk_del_provider(pdev->dev.of_node);
2965 reset_controller_unregister(platform_get_drvdata(pdev));
2966 return 0;
2967}
2968
2969static struct platform_driver gcc_msm8960_driver = {
2970 .probe = gcc_msm8960_probe,
2971 .remove = gcc_msm8960_remove,
2972 .driver = {
2973 .name = "gcc-msm8960",
2974 .owner = THIS_MODULE,
2975 .of_match_table = gcc_msm8960_match_table,
2976 },
2977};
2978
2979static int __init gcc_msm8960_init(void)
2980{
2981 return platform_driver_register(&gcc_msm8960_driver);
2982}
2983core_initcall(gcc_msm8960_init);
2984
2985static void __exit gcc_msm8960_exit(void)
2986{
2987 platform_driver_unregister(&gcc_msm8960_driver);
2988}
2989module_exit(gcc_msm8960_exit);
2990
2991MODULE_DESCRIPTION("QCOM GCC MSM8960 Driver");
2992MODULE_LICENSE("GPL v2");
2993MODULE_ALIAS("platform:gcc-msm8960");
diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c
new file mode 100644
index 000000000000..51d457e2b959
--- /dev/null
+++ b/drivers/clk/qcom/gcc-msm8974.c
@@ -0,0 +1,2694 @@
1/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/bitops.h>
16#include <linux/err.h>
17#include <linux/platform_device.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/clk-provider.h>
22#include <linux/regmap.h>
23#include <linux/reset-controller.h>
24
25#include <dt-bindings/clock/qcom,gcc-msm8974.h>
26#include <dt-bindings/reset/qcom,gcc-msm8974.h>
27
28#include "clk-regmap.h"
29#include "clk-pll.h"
30#include "clk-rcg.h"
31#include "clk-branch.h"
32#include "reset.h"
33
34#define P_XO 0
35#define P_GPLL0 1
36#define P_GPLL1 1
37
38static const u8 gcc_xo_gpll0_map[] = {
39 [P_XO] = 0,
40 [P_GPLL0] = 1,
41};
42
43static const char *gcc_xo_gpll0[] = {
44 "xo",
45 "gpll0_vote",
46};
47
48#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
49
50static struct clk_pll gpll0 = {
51 .l_reg = 0x0004,
52 .m_reg = 0x0008,
53 .n_reg = 0x000c,
54 .config_reg = 0x0014,
55 .mode_reg = 0x0000,
56 .status_reg = 0x001c,
57 .status_bit = 17,
58 .clkr.hw.init = &(struct clk_init_data){
59 .name = "gpll0",
60 .parent_names = (const char *[]){ "xo" },
61 .num_parents = 1,
62 .ops = &clk_pll_ops,
63 },
64};
65
66static struct clk_regmap gpll0_vote = {
67 .enable_reg = 0x1480,
68 .enable_mask = BIT(0),
69 .hw.init = &(struct clk_init_data){
70 .name = "gpll0_vote",
71 .parent_names = (const char *[]){ "gpll0" },
72 .num_parents = 1,
73 .ops = &clk_pll_vote_ops,
74 },
75};
76
77static struct clk_rcg2 config_noc_clk_src = {
78 .cmd_rcgr = 0x0150,
79 .hid_width = 5,
80 .parent_map = gcc_xo_gpll0_map,
81 .clkr.hw.init = &(struct clk_init_data){
82 .name = "config_noc_clk_src",
83 .parent_names = gcc_xo_gpll0,
84 .num_parents = 2,
85 .ops = &clk_rcg2_ops,
86 },
87};
88
89static struct clk_rcg2 periph_noc_clk_src = {
90 .cmd_rcgr = 0x0190,
91 .hid_width = 5,
92 .parent_map = gcc_xo_gpll0_map,
93 .clkr.hw.init = &(struct clk_init_data){
94 .name = "periph_noc_clk_src",
95 .parent_names = gcc_xo_gpll0,
96 .num_parents = 2,
97 .ops = &clk_rcg2_ops,
98 },
99};
100
101static struct clk_rcg2 system_noc_clk_src = {
102 .cmd_rcgr = 0x0120,
103 .hid_width = 5,
104 .parent_map = gcc_xo_gpll0_map,
105 .clkr.hw.init = &(struct clk_init_data){
106 .name = "system_noc_clk_src",
107 .parent_names = gcc_xo_gpll0,
108 .num_parents = 2,
109 .ops = &clk_rcg2_ops,
110 },
111};
112
113static struct clk_pll gpll1 = {
114 .l_reg = 0x0044,
115 .m_reg = 0x0048,
116 .n_reg = 0x004c,
117 .config_reg = 0x0054,
118 .mode_reg = 0x0040,
119 .status_reg = 0x005c,
120 .status_bit = 17,
121 .clkr.hw.init = &(struct clk_init_data){
122 .name = "gpll1",
123 .parent_names = (const char *[]){ "xo" },
124 .num_parents = 1,
125 .ops = &clk_pll_ops,
126 },
127};
128
129static struct clk_regmap gpll1_vote = {
130 .enable_reg = 0x1480,
131 .enable_mask = BIT(1),
132 .hw.init = &(struct clk_init_data){
133 .name = "gpll1_vote",
134 .parent_names = (const char *[]){ "gpll1" },
135 .num_parents = 1,
136 .ops = &clk_pll_vote_ops,
137 },
138};
139
140static const struct freq_tbl ftbl_gcc_usb30_master_clk[] = {
141 F(125000000, P_GPLL0, 1, 5, 24),
142 { }
143};
144
145static struct clk_rcg2 usb30_master_clk_src = {
146 .cmd_rcgr = 0x03d4,
147 .mnd_width = 8,
148 .hid_width = 5,
149 .parent_map = gcc_xo_gpll0_map,
150 .freq_tbl = ftbl_gcc_usb30_master_clk,
151 .clkr.hw.init = &(struct clk_init_data){
152 .name = "usb30_master_clk_src",
153 .parent_names = gcc_xo_gpll0,
154 .num_parents = 2,
155 .ops = &clk_rcg2_ops,
156 },
157};
158
159static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk[] = {
160 F(19200000, P_XO, 1, 0, 0),
161 F(37500000, P_GPLL0, 16, 0, 0),
162 F(50000000, P_GPLL0, 12, 0, 0),
163 { }
164};
165
166static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
167 .cmd_rcgr = 0x0660,
168 .hid_width = 5,
169 .parent_map = gcc_xo_gpll0_map,
170 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
171 .clkr.hw.init = &(struct clk_init_data){
172 .name = "blsp1_qup1_i2c_apps_clk_src",
173 .parent_names = gcc_xo_gpll0,
174 .num_parents = 2,
175 .ops = &clk_rcg2_ops,
176 },
177};
178
179static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk[] = {
180 F(960000, P_XO, 10, 1, 2),
181 F(4800000, P_XO, 4, 0, 0),
182 F(9600000, P_XO, 2, 0, 0),
183 F(15000000, P_GPLL0, 10, 1, 4),
184 F(19200000, P_XO, 1, 0, 0),
185 F(25000000, P_GPLL0, 12, 1, 2),
186 F(50000000, P_GPLL0, 12, 0, 0),
187 { }
188};
189
190static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
191 .cmd_rcgr = 0x064c,
192 .mnd_width = 8,
193 .hid_width = 5,
194 .parent_map = gcc_xo_gpll0_map,
195 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
196 .clkr.hw.init = &(struct clk_init_data){
197 .name = "blsp1_qup1_spi_apps_clk_src",
198 .parent_names = gcc_xo_gpll0,
199 .num_parents = 2,
200 .ops = &clk_rcg2_ops,
201 },
202};
203
204static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
205 .cmd_rcgr = 0x06e0,
206 .hid_width = 5,
207 .parent_map = gcc_xo_gpll0_map,
208 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
209 .clkr.hw.init = &(struct clk_init_data){
210 .name = "blsp1_qup2_i2c_apps_clk_src",
211 .parent_names = gcc_xo_gpll0,
212 .num_parents = 2,
213 .ops = &clk_rcg2_ops,
214 },
215};
216
217static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
218 .cmd_rcgr = 0x06cc,
219 .mnd_width = 8,
220 .hid_width = 5,
221 .parent_map = gcc_xo_gpll0_map,
222 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
223 .clkr.hw.init = &(struct clk_init_data){
224 .name = "blsp1_qup2_spi_apps_clk_src",
225 .parent_names = gcc_xo_gpll0,
226 .num_parents = 2,
227 .ops = &clk_rcg2_ops,
228 },
229};
230
231static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
232 .cmd_rcgr = 0x0760,
233 .hid_width = 5,
234 .parent_map = gcc_xo_gpll0_map,
235 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
236 .clkr.hw.init = &(struct clk_init_data){
237 .name = "blsp1_qup3_i2c_apps_clk_src",
238 .parent_names = gcc_xo_gpll0,
239 .num_parents = 2,
240 .ops = &clk_rcg2_ops,
241 },
242};
243
244static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
245 .cmd_rcgr = 0x074c,
246 .mnd_width = 8,
247 .hid_width = 5,
248 .parent_map = gcc_xo_gpll0_map,
249 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
250 .clkr.hw.init = &(struct clk_init_data){
251 .name = "blsp1_qup3_spi_apps_clk_src",
252 .parent_names = gcc_xo_gpll0,
253 .num_parents = 2,
254 .ops = &clk_rcg2_ops,
255 },
256};
257
258static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
259 .cmd_rcgr = 0x07e0,
260 .hid_width = 5,
261 .parent_map = gcc_xo_gpll0_map,
262 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
263 .clkr.hw.init = &(struct clk_init_data){
264 .name = "blsp1_qup4_i2c_apps_clk_src",
265 .parent_names = gcc_xo_gpll0,
266 .num_parents = 2,
267 .ops = &clk_rcg2_ops,
268 },
269};
270
271static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
272 .cmd_rcgr = 0x07cc,
273 .mnd_width = 8,
274 .hid_width = 5,
275 .parent_map = gcc_xo_gpll0_map,
276 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
277 .clkr.hw.init = &(struct clk_init_data){
278 .name = "blsp1_qup4_spi_apps_clk_src",
279 .parent_names = gcc_xo_gpll0,
280 .num_parents = 2,
281 .ops = &clk_rcg2_ops,
282 },
283};
284
285static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
286 .cmd_rcgr = 0x0860,
287 .hid_width = 5,
288 .parent_map = gcc_xo_gpll0_map,
289 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
290 .clkr.hw.init = &(struct clk_init_data){
291 .name = "blsp1_qup5_i2c_apps_clk_src",
292 .parent_names = gcc_xo_gpll0,
293 .num_parents = 2,
294 .ops = &clk_rcg2_ops,
295 },
296};
297
298static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
299 .cmd_rcgr = 0x084c,
300 .mnd_width = 8,
301 .hid_width = 5,
302 .parent_map = gcc_xo_gpll0_map,
303 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
304 .clkr.hw.init = &(struct clk_init_data){
305 .name = "blsp1_qup5_spi_apps_clk_src",
306 .parent_names = gcc_xo_gpll0,
307 .num_parents = 2,
308 .ops = &clk_rcg2_ops,
309 },
310};
311
312static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
313 .cmd_rcgr = 0x08e0,
314 .hid_width = 5,
315 .parent_map = gcc_xo_gpll0_map,
316 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
317 .clkr.hw.init = &(struct clk_init_data){
318 .name = "blsp1_qup6_i2c_apps_clk_src",
319 .parent_names = gcc_xo_gpll0,
320 .num_parents = 2,
321 .ops = &clk_rcg2_ops,
322 },
323};
324
325static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
326 .cmd_rcgr = 0x08cc,
327 .mnd_width = 8,
328 .hid_width = 5,
329 .parent_map = gcc_xo_gpll0_map,
330 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
331 .clkr.hw.init = &(struct clk_init_data){
332 .name = "blsp1_qup6_spi_apps_clk_src",
333 .parent_names = gcc_xo_gpll0,
334 .num_parents = 2,
335 .ops = &clk_rcg2_ops,
336 },
337};
338
339static const struct freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = {
340 F(3686400, P_GPLL0, 1, 96, 15625),
341 F(7372800, P_GPLL0, 1, 192, 15625),
342 F(14745600, P_GPLL0, 1, 384, 15625),
343 F(16000000, P_GPLL0, 5, 2, 15),
344 F(19200000, P_XO, 1, 0, 0),
345 F(24000000, P_GPLL0, 5, 1, 5),
346 F(32000000, P_GPLL0, 1, 4, 75),
347 F(40000000, P_GPLL0, 15, 0, 0),
348 F(46400000, P_GPLL0, 1, 29, 375),
349 F(48000000, P_GPLL0, 12.5, 0, 0),
350 F(51200000, P_GPLL0, 1, 32, 375),
351 F(56000000, P_GPLL0, 1, 7, 75),
352 F(58982400, P_GPLL0, 1, 1536, 15625),
353 F(60000000, P_GPLL0, 10, 0, 0),
354 F(63160000, P_GPLL0, 9.5, 0, 0),
355 { }
356};
357
358static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
359 .cmd_rcgr = 0x068c,
360 .mnd_width = 16,
361 .hid_width = 5,
362 .parent_map = gcc_xo_gpll0_map,
363 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
364 .clkr.hw.init = &(struct clk_init_data){
365 .name = "blsp1_uart1_apps_clk_src",
366 .parent_names = gcc_xo_gpll0,
367 .num_parents = 2,
368 .ops = &clk_rcg2_ops,
369 },
370};
371
372static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
373 .cmd_rcgr = 0x070c,
374 .mnd_width = 16,
375 .hid_width = 5,
376 .parent_map = gcc_xo_gpll0_map,
377 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
378 .clkr.hw.init = &(struct clk_init_data){
379 .name = "blsp1_uart2_apps_clk_src",
380 .parent_names = gcc_xo_gpll0,
381 .num_parents = 2,
382 .ops = &clk_rcg2_ops,
383 },
384};
385
386static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
387 .cmd_rcgr = 0x078c,
388 .mnd_width = 16,
389 .hid_width = 5,
390 .parent_map = gcc_xo_gpll0_map,
391 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
392 .clkr.hw.init = &(struct clk_init_data){
393 .name = "blsp1_uart3_apps_clk_src",
394 .parent_names = gcc_xo_gpll0,
395 .num_parents = 2,
396 .ops = &clk_rcg2_ops,
397 },
398};
399
400static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
401 .cmd_rcgr = 0x080c,
402 .mnd_width = 16,
403 .hid_width = 5,
404 .parent_map = gcc_xo_gpll0_map,
405 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
406 .clkr.hw.init = &(struct clk_init_data){
407 .name = "blsp1_uart4_apps_clk_src",
408 .parent_names = gcc_xo_gpll0,
409 .num_parents = 2,
410 .ops = &clk_rcg2_ops,
411 },
412};
413
414static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
415 .cmd_rcgr = 0x088c,
416 .mnd_width = 16,
417 .hid_width = 5,
418 .parent_map = gcc_xo_gpll0_map,
419 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
420 .clkr.hw.init = &(struct clk_init_data){
421 .name = "blsp1_uart5_apps_clk_src",
422 .parent_names = gcc_xo_gpll0,
423 .num_parents = 2,
424 .ops = &clk_rcg2_ops,
425 },
426};
427
428static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
429 .cmd_rcgr = 0x090c,
430 .mnd_width = 16,
431 .hid_width = 5,
432 .parent_map = gcc_xo_gpll0_map,
433 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
434 .clkr.hw.init = &(struct clk_init_data){
435 .name = "blsp1_uart6_apps_clk_src",
436 .parent_names = gcc_xo_gpll0,
437 .num_parents = 2,
438 .ops = &clk_rcg2_ops,
439 },
440};
441
442static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
443 .cmd_rcgr = 0x09a0,
444 .hid_width = 5,
445 .parent_map = gcc_xo_gpll0_map,
446 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
447 .clkr.hw.init = &(struct clk_init_data){
448 .name = "blsp2_qup1_i2c_apps_clk_src",
449 .parent_names = gcc_xo_gpll0,
450 .num_parents = 2,
451 .ops = &clk_rcg2_ops,
452 },
453};
454
455static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
456 .cmd_rcgr = 0x098c,
457 .mnd_width = 8,
458 .hid_width = 5,
459 .parent_map = gcc_xo_gpll0_map,
460 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
461 .clkr.hw.init = &(struct clk_init_data){
462 .name = "blsp2_qup1_spi_apps_clk_src",
463 .parent_names = gcc_xo_gpll0,
464 .num_parents = 2,
465 .ops = &clk_rcg2_ops,
466 },
467};
468
469static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
470 .cmd_rcgr = 0x0a20,
471 .hid_width = 5,
472 .parent_map = gcc_xo_gpll0_map,
473 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
474 .clkr.hw.init = &(struct clk_init_data){
475 .name = "blsp2_qup2_i2c_apps_clk_src",
476 .parent_names = gcc_xo_gpll0,
477 .num_parents = 2,
478 .ops = &clk_rcg2_ops,
479 },
480};
481
482static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
483 .cmd_rcgr = 0x0a0c,
484 .mnd_width = 8,
485 .hid_width = 5,
486 .parent_map = gcc_xo_gpll0_map,
487 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
488 .clkr.hw.init = &(struct clk_init_data){
489 .name = "blsp2_qup2_spi_apps_clk_src",
490 .parent_names = gcc_xo_gpll0,
491 .num_parents = 2,
492 .ops = &clk_rcg2_ops,
493 },
494};
495
496static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
497 .cmd_rcgr = 0x0aa0,
498 .hid_width = 5,
499 .parent_map = gcc_xo_gpll0_map,
500 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
501 .clkr.hw.init = &(struct clk_init_data){
502 .name = "blsp2_qup3_i2c_apps_clk_src",
503 .parent_names = gcc_xo_gpll0,
504 .num_parents = 2,
505 .ops = &clk_rcg2_ops,
506 },
507};
508
509static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
510 .cmd_rcgr = 0x0a8c,
511 .mnd_width = 8,
512 .hid_width = 5,
513 .parent_map = gcc_xo_gpll0_map,
514 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
515 .clkr.hw.init = &(struct clk_init_data){
516 .name = "blsp2_qup3_spi_apps_clk_src",
517 .parent_names = gcc_xo_gpll0,
518 .num_parents = 2,
519 .ops = &clk_rcg2_ops,
520 },
521};
522
523static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
524 .cmd_rcgr = 0x0b20,
525 .hid_width = 5,
526 .parent_map = gcc_xo_gpll0_map,
527 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
528 .clkr.hw.init = &(struct clk_init_data){
529 .name = "blsp2_qup4_i2c_apps_clk_src",
530 .parent_names = gcc_xo_gpll0,
531 .num_parents = 2,
532 .ops = &clk_rcg2_ops,
533 },
534};
535
536static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
537 .cmd_rcgr = 0x0b0c,
538 .mnd_width = 8,
539 .hid_width = 5,
540 .parent_map = gcc_xo_gpll0_map,
541 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
542 .clkr.hw.init = &(struct clk_init_data){
543 .name = "blsp2_qup4_spi_apps_clk_src",
544 .parent_names = gcc_xo_gpll0,
545 .num_parents = 2,
546 .ops = &clk_rcg2_ops,
547 },
548};
549
550static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
551 .cmd_rcgr = 0x0ba0,
552 .hid_width = 5,
553 .parent_map = gcc_xo_gpll0_map,
554 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
555 .clkr.hw.init = &(struct clk_init_data){
556 .name = "blsp2_qup5_i2c_apps_clk_src",
557 .parent_names = gcc_xo_gpll0,
558 .num_parents = 2,
559 .ops = &clk_rcg2_ops,
560 },
561};
562
563static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
564 .cmd_rcgr = 0x0b8c,
565 .mnd_width = 8,
566 .hid_width = 5,
567 .parent_map = gcc_xo_gpll0_map,
568 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
569 .clkr.hw.init = &(struct clk_init_data){
570 .name = "blsp2_qup5_spi_apps_clk_src",
571 .parent_names = gcc_xo_gpll0,
572 .num_parents = 2,
573 .ops = &clk_rcg2_ops,
574 },
575};
576
577static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
578 .cmd_rcgr = 0x0c20,
579 .hid_width = 5,
580 .parent_map = gcc_xo_gpll0_map,
581 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
582 .clkr.hw.init = &(struct clk_init_data){
583 .name = "blsp2_qup6_i2c_apps_clk_src",
584 .parent_names = gcc_xo_gpll0,
585 .num_parents = 2,
586 .ops = &clk_rcg2_ops,
587 },
588};
589
590static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
591 .cmd_rcgr = 0x0c0c,
592 .mnd_width = 8,
593 .hid_width = 5,
594 .parent_map = gcc_xo_gpll0_map,
595 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
596 .clkr.hw.init = &(struct clk_init_data){
597 .name = "blsp2_qup6_spi_apps_clk_src",
598 .parent_names = gcc_xo_gpll0,
599 .num_parents = 2,
600 .ops = &clk_rcg2_ops,
601 },
602};
603
604static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
605 .cmd_rcgr = 0x09cc,
606 .mnd_width = 16,
607 .hid_width = 5,
608 .parent_map = gcc_xo_gpll0_map,
609 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
610 .clkr.hw.init = &(struct clk_init_data){
611 .name = "blsp2_uart1_apps_clk_src",
612 .parent_names = gcc_xo_gpll0,
613 .num_parents = 2,
614 .ops = &clk_rcg2_ops,
615 },
616};
617
618static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
619 .cmd_rcgr = 0x0a4c,
620 .mnd_width = 16,
621 .hid_width = 5,
622 .parent_map = gcc_xo_gpll0_map,
623 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
624 .clkr.hw.init = &(struct clk_init_data){
625 .name = "blsp2_uart2_apps_clk_src",
626 .parent_names = gcc_xo_gpll0,
627 .num_parents = 2,
628 .ops = &clk_rcg2_ops,
629 },
630};
631
632static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
633 .cmd_rcgr = 0x0acc,
634 .mnd_width = 16,
635 .hid_width = 5,
636 .parent_map = gcc_xo_gpll0_map,
637 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
638 .clkr.hw.init = &(struct clk_init_data){
639 .name = "blsp2_uart3_apps_clk_src",
640 .parent_names = gcc_xo_gpll0,
641 .num_parents = 2,
642 .ops = &clk_rcg2_ops,
643 },
644};
645
646static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
647 .cmd_rcgr = 0x0b4c,
648 .mnd_width = 16,
649 .hid_width = 5,
650 .parent_map = gcc_xo_gpll0_map,
651 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
652 .clkr.hw.init = &(struct clk_init_data){
653 .name = "blsp2_uart4_apps_clk_src",
654 .parent_names = gcc_xo_gpll0,
655 .num_parents = 2,
656 .ops = &clk_rcg2_ops,
657 },
658};
659
660static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
661 .cmd_rcgr = 0x0bcc,
662 .mnd_width = 16,
663 .hid_width = 5,
664 .parent_map = gcc_xo_gpll0_map,
665 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
666 .clkr.hw.init = &(struct clk_init_data){
667 .name = "blsp2_uart5_apps_clk_src",
668 .parent_names = gcc_xo_gpll0,
669 .num_parents = 2,
670 .ops = &clk_rcg2_ops,
671 },
672};
673
674static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
675 .cmd_rcgr = 0x0c4c,
676 .mnd_width = 16,
677 .hid_width = 5,
678 .parent_map = gcc_xo_gpll0_map,
679 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
680 .clkr.hw.init = &(struct clk_init_data){
681 .name = "blsp2_uart6_apps_clk_src",
682 .parent_names = gcc_xo_gpll0,
683 .num_parents = 2,
684 .ops = &clk_rcg2_ops,
685 },
686};
687
688static const struct freq_tbl ftbl_gcc_ce1_clk[] = {
689 F(50000000, P_GPLL0, 12, 0, 0),
690 F(75000000, P_GPLL0, 8, 0, 0),
691 F(100000000, P_GPLL0, 6, 0, 0),
692 F(150000000, P_GPLL0, 4, 0, 0),
693 { }
694};
695
696static struct clk_rcg2 ce1_clk_src = {
697 .cmd_rcgr = 0x1050,
698 .hid_width = 5,
699 .parent_map = gcc_xo_gpll0_map,
700 .freq_tbl = ftbl_gcc_ce1_clk,
701 .clkr.hw.init = &(struct clk_init_data){
702 .name = "ce1_clk_src",
703 .parent_names = gcc_xo_gpll0,
704 .num_parents = 2,
705 .ops = &clk_rcg2_ops,
706 },
707};
708
709static const struct freq_tbl ftbl_gcc_ce2_clk[] = {
710 F(50000000, P_GPLL0, 12, 0, 0),
711 F(75000000, P_GPLL0, 8, 0, 0),
712 F(100000000, P_GPLL0, 6, 0, 0),
713 F(150000000, P_GPLL0, 4, 0, 0),
714 { }
715};
716
717static struct clk_rcg2 ce2_clk_src = {
718 .cmd_rcgr = 0x1090,
719 .hid_width = 5,
720 .parent_map = gcc_xo_gpll0_map,
721 .freq_tbl = ftbl_gcc_ce2_clk,
722 .clkr.hw.init = &(struct clk_init_data){
723 .name = "ce2_clk_src",
724 .parent_names = gcc_xo_gpll0,
725 .num_parents = 2,
726 .ops = &clk_rcg2_ops,
727 },
728};
729
730static const struct freq_tbl ftbl_gcc_gp_clk[] = {
731 F(4800000, P_XO, 4, 0, 0),
732 F(6000000, P_GPLL0, 10, 1, 10),
733 F(6750000, P_GPLL0, 1, 1, 89),
734 F(8000000, P_GPLL0, 15, 1, 5),
735 F(9600000, P_XO, 2, 0, 0),
736 F(16000000, P_GPLL0, 1, 2, 75),
737 F(19200000, P_XO, 1, 0, 0),
738 F(24000000, P_GPLL0, 5, 1, 5),
739 { }
740};
741
742
743static struct clk_rcg2 gp1_clk_src = {
744 .cmd_rcgr = 0x1904,
745 .mnd_width = 8,
746 .hid_width = 5,
747 .parent_map = gcc_xo_gpll0_map,
748 .freq_tbl = ftbl_gcc_gp_clk,
749 .clkr.hw.init = &(struct clk_init_data){
750 .name = "gp1_clk_src",
751 .parent_names = gcc_xo_gpll0,
752 .num_parents = 2,
753 .ops = &clk_rcg2_ops,
754 },
755};
756
757static struct clk_rcg2 gp2_clk_src = {
758 .cmd_rcgr = 0x1944,
759 .mnd_width = 8,
760 .hid_width = 5,
761 .parent_map = gcc_xo_gpll0_map,
762 .freq_tbl = ftbl_gcc_gp_clk,
763 .clkr.hw.init = &(struct clk_init_data){
764 .name = "gp2_clk_src",
765 .parent_names = gcc_xo_gpll0,
766 .num_parents = 2,
767 .ops = &clk_rcg2_ops,
768 },
769};
770
771static struct clk_rcg2 gp3_clk_src = {
772 .cmd_rcgr = 0x1984,
773 .mnd_width = 8,
774 .hid_width = 5,
775 .parent_map = gcc_xo_gpll0_map,
776 .freq_tbl = ftbl_gcc_gp_clk,
777 .clkr.hw.init = &(struct clk_init_data){
778 .name = "gp3_clk_src",
779 .parent_names = gcc_xo_gpll0,
780 .num_parents = 2,
781 .ops = &clk_rcg2_ops,
782 },
783};
784
785static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
786 F(60000000, P_GPLL0, 10, 0, 0),
787 { }
788};
789
790static struct clk_rcg2 pdm2_clk_src = {
791 .cmd_rcgr = 0x0cd0,
792 .hid_width = 5,
793 .parent_map = gcc_xo_gpll0_map,
794 .freq_tbl = ftbl_gcc_pdm2_clk,
795 .clkr.hw.init = &(struct clk_init_data){
796 .name = "pdm2_clk_src",
797 .parent_names = gcc_xo_gpll0,
798 .num_parents = 2,
799 .ops = &clk_rcg2_ops,
800 },
801};
802
803static const struct freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] = {
804 F(144000, P_XO, 16, 3, 25),
805 F(400000, P_XO, 12, 1, 4),
806 F(20000000, P_GPLL0, 15, 1, 2),
807 F(25000000, P_GPLL0, 12, 1, 2),
808 F(50000000, P_GPLL0, 12, 0, 0),
809 F(100000000, P_GPLL0, 6, 0, 0),
810 F(200000000, P_GPLL0, 3, 0, 0),
811 { }
812};
813
814static struct clk_rcg2 sdcc1_apps_clk_src = {
815 .cmd_rcgr = 0x04d0,
816 .mnd_width = 8,
817 .hid_width = 5,
818 .parent_map = gcc_xo_gpll0_map,
819 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
820 .clkr.hw.init = &(struct clk_init_data){
821 .name = "sdcc1_apps_clk_src",
822 .parent_names = gcc_xo_gpll0,
823 .num_parents = 2,
824 .ops = &clk_rcg2_ops,
825 },
826};
827
828static struct clk_rcg2 sdcc2_apps_clk_src = {
829 .cmd_rcgr = 0x0510,
830 .mnd_width = 8,
831 .hid_width = 5,
832 .parent_map = gcc_xo_gpll0_map,
833 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
834 .clkr.hw.init = &(struct clk_init_data){
835 .name = "sdcc2_apps_clk_src",
836 .parent_names = gcc_xo_gpll0,
837 .num_parents = 2,
838 .ops = &clk_rcg2_ops,
839 },
840};
841
842static struct clk_rcg2 sdcc3_apps_clk_src = {
843 .cmd_rcgr = 0x0550,
844 .mnd_width = 8,
845 .hid_width = 5,
846 .parent_map = gcc_xo_gpll0_map,
847 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
848 .clkr.hw.init = &(struct clk_init_data){
849 .name = "sdcc3_apps_clk_src",
850 .parent_names = gcc_xo_gpll0,
851 .num_parents = 2,
852 .ops = &clk_rcg2_ops,
853 },
854};
855
856static struct clk_rcg2 sdcc4_apps_clk_src = {
857 .cmd_rcgr = 0x0590,
858 .mnd_width = 8,
859 .hid_width = 5,
860 .parent_map = gcc_xo_gpll0_map,
861 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
862 .clkr.hw.init = &(struct clk_init_data){
863 .name = "sdcc4_apps_clk_src",
864 .parent_names = gcc_xo_gpll0,
865 .num_parents = 2,
866 .ops = &clk_rcg2_ops,
867 },
868};
869
870static const struct freq_tbl ftbl_gcc_tsif_ref_clk[] = {
871 F(105000, P_XO, 2, 1, 91),
872 { }
873};
874
875static struct clk_rcg2 tsif_ref_clk_src = {
876 .cmd_rcgr = 0x0d90,
877 .mnd_width = 8,
878 .hid_width = 5,
879 .parent_map = gcc_xo_gpll0_map,
880 .freq_tbl = ftbl_gcc_tsif_ref_clk,
881 .clkr.hw.init = &(struct clk_init_data){
882 .name = "tsif_ref_clk_src",
883 .parent_names = gcc_xo_gpll0,
884 .num_parents = 2,
885 .ops = &clk_rcg2_ops,
886 },
887};
888
889static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = {
890 F(60000000, P_GPLL0, 10, 0, 0),
891 { }
892};
893
894static struct clk_rcg2 usb30_mock_utmi_clk_src = {
895 .cmd_rcgr = 0x03e8,
896 .hid_width = 5,
897 .parent_map = gcc_xo_gpll0_map,
898 .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk,
899 .clkr.hw.init = &(struct clk_init_data){
900 .name = "usb30_mock_utmi_clk_src",
901 .parent_names = gcc_xo_gpll0,
902 .num_parents = 2,
903 .ops = &clk_rcg2_ops,
904 },
905};
906
907static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
908 F(60000000, P_GPLL0, 10, 0, 0),
909 F(75000000, P_GPLL0, 8, 0, 0),
910 { }
911};
912
913static struct clk_rcg2 usb_hs_system_clk_src = {
914 .cmd_rcgr = 0x0490,
915 .hid_width = 5,
916 .parent_map = gcc_xo_gpll0_map,
917 .freq_tbl = ftbl_gcc_usb_hs_system_clk,
918 .clkr.hw.init = &(struct clk_init_data){
919 .name = "usb_hs_system_clk_src",
920 .parent_names = gcc_xo_gpll0,
921 .num_parents = 2,
922 .ops = &clk_rcg2_ops,
923 },
924};
925
926static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = {
927 F(480000000, P_GPLL1, 1, 0, 0),
928 { }
929};
930
931static u8 usb_hsic_clk_src_map[] = {
932 [P_XO] = 0,
933 [P_GPLL1] = 4,
934};
935
936static struct clk_rcg2 usb_hsic_clk_src = {
937 .cmd_rcgr = 0x0440,
938 .hid_width = 5,
939 .parent_map = usb_hsic_clk_src_map,
940 .freq_tbl = ftbl_gcc_usb_hsic_clk,
941 .clkr.hw.init = &(struct clk_init_data){
942 .name = "usb_hsic_clk_src",
943 .parent_names = (const char *[]){
944 "xo",
945 "gpll1_vote",
946 },
947 .num_parents = 2,
948 .ops = &clk_rcg2_ops,
949 },
950};
951
952static const struct freq_tbl ftbl_gcc_usb_hsic_io_cal_clk[] = {
953 F(9600000, P_XO, 2, 0, 0),
954 { }
955};
956
957static struct clk_rcg2 usb_hsic_io_cal_clk_src = {
958 .cmd_rcgr = 0x0458,
959 .hid_width = 5,
960 .parent_map = gcc_xo_gpll0_map,
961 .freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk,
962 .clkr.hw.init = &(struct clk_init_data){
963 .name = "usb_hsic_io_cal_clk_src",
964 .parent_names = gcc_xo_gpll0,
965 .num_parents = 1,
966 .ops = &clk_rcg2_ops,
967 },
968};
969
970static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk[] = {
971 F(60000000, P_GPLL0, 10, 0, 0),
972 F(75000000, P_GPLL0, 8, 0, 0),
973 { }
974};
975
976static struct clk_rcg2 usb_hsic_system_clk_src = {
977 .cmd_rcgr = 0x041c,
978 .hid_width = 5,
979 .parent_map = gcc_xo_gpll0_map,
980 .freq_tbl = ftbl_gcc_usb_hsic_system_clk,
981 .clkr.hw.init = &(struct clk_init_data){
982 .name = "usb_hsic_system_clk_src",
983 .parent_names = gcc_xo_gpll0,
984 .num_parents = 2,
985 .ops = &clk_rcg2_ops,
986 },
987};
988
989static struct clk_regmap gcc_mmss_gpll0_clk_src = {
990 .enable_reg = 0x1484,
991 .enable_mask = BIT(26),
992 .hw.init = &(struct clk_init_data){
993 .name = "mmss_gpll0_vote",
994 .parent_names = (const char *[]){
995 "gpll0_vote",
996 },
997 .num_parents = 1,
998 .ops = &clk_branch_simple_ops,
999 },
1000};
1001
1002static struct clk_branch gcc_bam_dma_ahb_clk = {
1003 .halt_reg = 0x0d44,
1004 .halt_check = BRANCH_HALT_VOTED,
1005 .clkr = {
1006 .enable_reg = 0x1484,
1007 .enable_mask = BIT(12),
1008 .hw.init = &(struct clk_init_data){
1009 .name = "gcc_bam_dma_ahb_clk",
1010 .parent_names = (const char *[]){
1011 "periph_noc_clk_src",
1012 },
1013 .num_parents = 1,
1014 .ops = &clk_branch2_ops,
1015 },
1016 },
1017};
1018
1019static struct clk_branch gcc_blsp1_ahb_clk = {
1020 .halt_reg = 0x05c4,
1021 .halt_check = BRANCH_HALT_VOTED,
1022 .clkr = {
1023 .enable_reg = 0x1484,
1024 .enable_mask = BIT(17),
1025 .hw.init = &(struct clk_init_data){
1026 .name = "gcc_blsp1_ahb_clk",
1027 .parent_names = (const char *[]){
1028 "periph_noc_clk_src",
1029 },
1030 .num_parents = 1,
1031 .ops = &clk_branch2_ops,
1032 },
1033 },
1034};
1035
1036static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1037 .halt_reg = 0x0648,
1038 .clkr = {
1039 .enable_reg = 0x0648,
1040 .enable_mask = BIT(0),
1041 .hw.init = &(struct clk_init_data){
1042 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1043 .parent_names = (const char *[]){
1044 "blsp1_qup1_i2c_apps_clk_src",
1045 },
1046 .num_parents = 1,
1047 .flags = CLK_SET_RATE_PARENT,
1048 .ops = &clk_branch2_ops,
1049 },
1050 },
1051};
1052
1053static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1054 .halt_reg = 0x0644,
1055 .clkr = {
1056 .enable_reg = 0x0644,
1057 .enable_mask = BIT(0),
1058 .hw.init = &(struct clk_init_data){
1059 .name = "gcc_blsp1_qup1_spi_apps_clk",
1060 .parent_names = (const char *[]){
1061 "blsp1_qup1_spi_apps_clk_src",
1062 },
1063 .num_parents = 1,
1064 .flags = CLK_SET_RATE_PARENT,
1065 .ops = &clk_branch2_ops,
1066 },
1067 },
1068};
1069
1070static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1071 .halt_reg = 0x06c8,
1072 .clkr = {
1073 .enable_reg = 0x06c8,
1074 .enable_mask = BIT(0),
1075 .hw.init = &(struct clk_init_data){
1076 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1077 .parent_names = (const char *[]){
1078 "blsp1_qup2_i2c_apps_clk_src",
1079 },
1080 .num_parents = 1,
1081 .flags = CLK_SET_RATE_PARENT,
1082 .ops = &clk_branch2_ops,
1083 },
1084 },
1085};
1086
1087static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1088 .halt_reg = 0x06c4,
1089 .clkr = {
1090 .enable_reg = 0x06c4,
1091 .enable_mask = BIT(0),
1092 .hw.init = &(struct clk_init_data){
1093 .name = "gcc_blsp1_qup2_spi_apps_clk",
1094 .parent_names = (const char *[]){
1095 "blsp1_qup2_spi_apps_clk_src",
1096 },
1097 .num_parents = 1,
1098 .flags = CLK_SET_RATE_PARENT,
1099 .ops = &clk_branch2_ops,
1100 },
1101 },
1102};
1103
1104static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1105 .halt_reg = 0x0748,
1106 .clkr = {
1107 .enable_reg = 0x0748,
1108 .enable_mask = BIT(0),
1109 .hw.init = &(struct clk_init_data){
1110 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1111 .parent_names = (const char *[]){
1112 "blsp1_qup3_i2c_apps_clk_src",
1113 },
1114 .num_parents = 1,
1115 .flags = CLK_SET_RATE_PARENT,
1116 .ops = &clk_branch2_ops,
1117 },
1118 },
1119};
1120
1121static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1122 .halt_reg = 0x0744,
1123 .clkr = {
1124 .enable_reg = 0x0744,
1125 .enable_mask = BIT(0),
1126 .hw.init = &(struct clk_init_data){
1127 .name = "gcc_blsp1_qup3_spi_apps_clk",
1128 .parent_names = (const char *[]){
1129 "blsp1_qup3_spi_apps_clk_src",
1130 },
1131 .num_parents = 1,
1132 .flags = CLK_SET_RATE_PARENT,
1133 .ops = &clk_branch2_ops,
1134 },
1135 },
1136};
1137
1138static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1139 .halt_reg = 0x07c8,
1140 .clkr = {
1141 .enable_reg = 0x07c8,
1142 .enable_mask = BIT(0),
1143 .hw.init = &(struct clk_init_data){
1144 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1145 .parent_names = (const char *[]){
1146 "blsp1_qup4_i2c_apps_clk_src",
1147 },
1148 .num_parents = 1,
1149 .flags = CLK_SET_RATE_PARENT,
1150 .ops = &clk_branch2_ops,
1151 },
1152 },
1153};
1154
1155static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1156 .halt_reg = 0x07c4,
1157 .clkr = {
1158 .enable_reg = 0x07c4,
1159 .enable_mask = BIT(0),
1160 .hw.init = &(struct clk_init_data){
1161 .name = "gcc_blsp1_qup4_spi_apps_clk",
1162 .parent_names = (const char *[]){
1163 "blsp1_qup4_spi_apps_clk_src",
1164 },
1165 .num_parents = 1,
1166 .flags = CLK_SET_RATE_PARENT,
1167 .ops = &clk_branch2_ops,
1168 },
1169 },
1170};
1171
1172static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1173 .halt_reg = 0x0848,
1174 .clkr = {
1175 .enable_reg = 0x0848,
1176 .enable_mask = BIT(0),
1177 .hw.init = &(struct clk_init_data){
1178 .name = "gcc_blsp1_qup5_i2c_apps_clk",
1179 .parent_names = (const char *[]){
1180 "blsp1_qup5_i2c_apps_clk_src",
1181 },
1182 .num_parents = 1,
1183 .flags = CLK_SET_RATE_PARENT,
1184 .ops = &clk_branch2_ops,
1185 },
1186 },
1187};
1188
1189static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1190 .halt_reg = 0x0844,
1191 .clkr = {
1192 .enable_reg = 0x0844,
1193 .enable_mask = BIT(0),
1194 .hw.init = &(struct clk_init_data){
1195 .name = "gcc_blsp1_qup5_spi_apps_clk",
1196 .parent_names = (const char *[]){
1197 "blsp1_qup5_spi_apps_clk_src",
1198 },
1199 .num_parents = 1,
1200 .flags = CLK_SET_RATE_PARENT,
1201 .ops = &clk_branch2_ops,
1202 },
1203 },
1204};
1205
1206static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1207 .halt_reg = 0x08c8,
1208 .clkr = {
1209 .enable_reg = 0x08c8,
1210 .enable_mask = BIT(0),
1211 .hw.init = &(struct clk_init_data){
1212 .name = "gcc_blsp1_qup6_i2c_apps_clk",
1213 .parent_names = (const char *[]){
1214 "blsp1_qup6_i2c_apps_clk_src",
1215 },
1216 .num_parents = 1,
1217 .flags = CLK_SET_RATE_PARENT,
1218 .ops = &clk_branch2_ops,
1219 },
1220 },
1221};
1222
1223static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1224 .halt_reg = 0x08c4,
1225 .clkr = {
1226 .enable_reg = 0x08c4,
1227 .enable_mask = BIT(0),
1228 .hw.init = &(struct clk_init_data){
1229 .name = "gcc_blsp1_qup6_spi_apps_clk",
1230 .parent_names = (const char *[]){
1231 "blsp1_qup6_spi_apps_clk_src",
1232 },
1233 .num_parents = 1,
1234 .flags = CLK_SET_RATE_PARENT,
1235 .ops = &clk_branch2_ops,
1236 },
1237 },
1238};
1239
1240static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1241 .halt_reg = 0x0684,
1242 .clkr = {
1243 .enable_reg = 0x0684,
1244 .enable_mask = BIT(0),
1245 .hw.init = &(struct clk_init_data){
1246 .name = "gcc_blsp1_uart1_apps_clk",
1247 .parent_names = (const char *[]){
1248 "blsp1_uart1_apps_clk_src",
1249 },
1250 .num_parents = 1,
1251 .flags = CLK_SET_RATE_PARENT,
1252 .ops = &clk_branch2_ops,
1253 },
1254 },
1255};
1256
1257static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1258 .halt_reg = 0x0704,
1259 .clkr = {
1260 .enable_reg = 0x0704,
1261 .enable_mask = BIT(0),
1262 .hw.init = &(struct clk_init_data){
1263 .name = "gcc_blsp1_uart2_apps_clk",
1264 .parent_names = (const char *[]){
1265 "blsp1_uart2_apps_clk_src",
1266 },
1267 .num_parents = 1,
1268 .flags = CLK_SET_RATE_PARENT,
1269 .ops = &clk_branch2_ops,
1270 },
1271 },
1272};
1273
1274static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1275 .halt_reg = 0x0784,
1276 .clkr = {
1277 .enable_reg = 0x0784,
1278 .enable_mask = BIT(0),
1279 .hw.init = &(struct clk_init_data){
1280 .name = "gcc_blsp1_uart3_apps_clk",
1281 .parent_names = (const char *[]){
1282 "blsp1_uart3_apps_clk_src",
1283 },
1284 .num_parents = 1,
1285 .flags = CLK_SET_RATE_PARENT,
1286 .ops = &clk_branch2_ops,
1287 },
1288 },
1289};
1290
1291static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1292 .halt_reg = 0x0804,
1293 .clkr = {
1294 .enable_reg = 0x0804,
1295 .enable_mask = BIT(0),
1296 .hw.init = &(struct clk_init_data){
1297 .name = "gcc_blsp1_uart4_apps_clk",
1298 .parent_names = (const char *[]){
1299 "blsp1_uart4_apps_clk_src",
1300 },
1301 .num_parents = 1,
1302 .flags = CLK_SET_RATE_PARENT,
1303 .ops = &clk_branch2_ops,
1304 },
1305 },
1306};
1307
1308static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1309 .halt_reg = 0x0884,
1310 .clkr = {
1311 .enable_reg = 0x0884,
1312 .enable_mask = BIT(0),
1313 .hw.init = &(struct clk_init_data){
1314 .name = "gcc_blsp1_uart5_apps_clk",
1315 .parent_names = (const char *[]){
1316 "blsp1_uart5_apps_clk_src",
1317 },
1318 .num_parents = 1,
1319 .flags = CLK_SET_RATE_PARENT,
1320 .ops = &clk_branch2_ops,
1321 },
1322 },
1323};
1324
1325static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1326 .halt_reg = 0x0904,
1327 .clkr = {
1328 .enable_reg = 0x0904,
1329 .enable_mask = BIT(0),
1330 .hw.init = &(struct clk_init_data){
1331 .name = "gcc_blsp1_uart6_apps_clk",
1332 .parent_names = (const char *[]){
1333 "blsp1_uart6_apps_clk_src",
1334 },
1335 .num_parents = 1,
1336 .flags = CLK_SET_RATE_PARENT,
1337 .ops = &clk_branch2_ops,
1338 },
1339 },
1340};
1341
1342static struct clk_branch gcc_blsp2_ahb_clk = {
1343 .halt_reg = 0x05c4,
1344 .halt_check = BRANCH_HALT_VOTED,
1345 .clkr = {
1346 .enable_reg = 0x1484,
1347 .enable_mask = BIT(15),
1348 .hw.init = &(struct clk_init_data){
1349 .name = "gcc_blsp2_ahb_clk",
1350 .parent_names = (const char *[]){
1351 "periph_noc_clk_src",
1352 },
1353 .num_parents = 1,
1354 .ops = &clk_branch2_ops,
1355 },
1356 },
1357};
1358
1359static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1360 .halt_reg = 0x0988,
1361 .clkr = {
1362 .enable_reg = 0x0988,
1363 .enable_mask = BIT(0),
1364 .hw.init = &(struct clk_init_data){
1365 .name = "gcc_blsp2_qup1_i2c_apps_clk",
1366 .parent_names = (const char *[]){
1367 "blsp2_qup1_i2c_apps_clk_src",
1368 },
1369 .num_parents = 1,
1370 .flags = CLK_SET_RATE_PARENT,
1371 .ops = &clk_branch2_ops,
1372 },
1373 },
1374};
1375
1376static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1377 .halt_reg = 0x0984,
1378 .clkr = {
1379 .enable_reg = 0x0984,
1380 .enable_mask = BIT(0),
1381 .hw.init = &(struct clk_init_data){
1382 .name = "gcc_blsp2_qup1_spi_apps_clk",
1383 .parent_names = (const char *[]){
1384 "blsp2_qup1_spi_apps_clk_src",
1385 },
1386 .num_parents = 1,
1387 .flags = CLK_SET_RATE_PARENT,
1388 .ops = &clk_branch2_ops,
1389 },
1390 },
1391};
1392
1393static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1394 .halt_reg = 0x0a08,
1395 .clkr = {
1396 .enable_reg = 0x0a08,
1397 .enable_mask = BIT(0),
1398 .hw.init = &(struct clk_init_data){
1399 .name = "gcc_blsp2_qup2_i2c_apps_clk",
1400 .parent_names = (const char *[]){
1401 "blsp2_qup2_i2c_apps_clk_src",
1402 },
1403 .num_parents = 1,
1404 .flags = CLK_SET_RATE_PARENT,
1405 .ops = &clk_branch2_ops,
1406 },
1407 },
1408};
1409
1410static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1411 .halt_reg = 0x0a04,
1412 .clkr = {
1413 .enable_reg = 0x0a04,
1414 .enable_mask = BIT(0),
1415 .hw.init = &(struct clk_init_data){
1416 .name = "gcc_blsp2_qup2_spi_apps_clk",
1417 .parent_names = (const char *[]){
1418 "blsp2_qup2_spi_apps_clk_src",
1419 },
1420 .num_parents = 1,
1421 .flags = CLK_SET_RATE_PARENT,
1422 .ops = &clk_branch2_ops,
1423 },
1424 },
1425};
1426
1427static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1428 .halt_reg = 0x0a88,
1429 .clkr = {
1430 .enable_reg = 0x0a88,
1431 .enable_mask = BIT(0),
1432 .hw.init = &(struct clk_init_data){
1433 .name = "gcc_blsp2_qup3_i2c_apps_clk",
1434 .parent_names = (const char *[]){
1435 "blsp2_qup3_i2c_apps_clk_src",
1436 },
1437 .num_parents = 1,
1438 .flags = CLK_SET_RATE_PARENT,
1439 .ops = &clk_branch2_ops,
1440 },
1441 },
1442};
1443
1444static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1445 .halt_reg = 0x0a84,
1446 .clkr = {
1447 .enable_reg = 0x0a84,
1448 .enable_mask = BIT(0),
1449 .hw.init = &(struct clk_init_data){
1450 .name = "gcc_blsp2_qup3_spi_apps_clk",
1451 .parent_names = (const char *[]){
1452 "blsp2_qup3_spi_apps_clk_src",
1453 },
1454 .num_parents = 1,
1455 .flags = CLK_SET_RATE_PARENT,
1456 .ops = &clk_branch2_ops,
1457 },
1458 },
1459};
1460
1461static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1462 .halt_reg = 0x0b08,
1463 .clkr = {
1464 .enable_reg = 0x0b08,
1465 .enable_mask = BIT(0),
1466 .hw.init = &(struct clk_init_data){
1467 .name = "gcc_blsp2_qup4_i2c_apps_clk",
1468 .parent_names = (const char *[]){
1469 "blsp2_qup4_i2c_apps_clk_src",
1470 },
1471 .num_parents = 1,
1472 .flags = CLK_SET_RATE_PARENT,
1473 .ops = &clk_branch2_ops,
1474 },
1475 },
1476};
1477
1478static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1479 .halt_reg = 0x0b04,
1480 .clkr = {
1481 .enable_reg = 0x0b04,
1482 .enable_mask = BIT(0),
1483 .hw.init = &(struct clk_init_data){
1484 .name = "gcc_blsp2_qup4_spi_apps_clk",
1485 .parent_names = (const char *[]){
1486 "blsp2_qup4_spi_apps_clk_src",
1487 },
1488 .num_parents = 1,
1489 .flags = CLK_SET_RATE_PARENT,
1490 .ops = &clk_branch2_ops,
1491 },
1492 },
1493};
1494
1495static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
1496 .halt_reg = 0x0b88,
1497 .clkr = {
1498 .enable_reg = 0x0b88,
1499 .enable_mask = BIT(0),
1500 .hw.init = &(struct clk_init_data){
1501 .name = "gcc_blsp2_qup5_i2c_apps_clk",
1502 .parent_names = (const char *[]){
1503 "blsp2_qup5_i2c_apps_clk_src",
1504 },
1505 .num_parents = 1,
1506 .flags = CLK_SET_RATE_PARENT,
1507 .ops = &clk_branch2_ops,
1508 },
1509 },
1510};
1511
1512static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
1513 .halt_reg = 0x0b84,
1514 .clkr = {
1515 .enable_reg = 0x0b84,
1516 .enable_mask = BIT(0),
1517 .hw.init = &(struct clk_init_data){
1518 .name = "gcc_blsp2_qup5_spi_apps_clk",
1519 .parent_names = (const char *[]){
1520 "blsp2_qup5_spi_apps_clk_src",
1521 },
1522 .num_parents = 1,
1523 .flags = CLK_SET_RATE_PARENT,
1524 .ops = &clk_branch2_ops,
1525 },
1526 },
1527};
1528
1529static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
1530 .halt_reg = 0x0c08,
1531 .clkr = {
1532 .enable_reg = 0x0c08,
1533 .enable_mask = BIT(0),
1534 .hw.init = &(struct clk_init_data){
1535 .name = "gcc_blsp2_qup6_i2c_apps_clk",
1536 .parent_names = (const char *[]){
1537 "blsp2_qup6_i2c_apps_clk_src",
1538 },
1539 .num_parents = 1,
1540 .flags = CLK_SET_RATE_PARENT,
1541 .ops = &clk_branch2_ops,
1542 },
1543 },
1544};
1545
1546static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
1547 .halt_reg = 0x0c04,
1548 .clkr = {
1549 .enable_reg = 0x0c04,
1550 .enable_mask = BIT(0),
1551 .hw.init = &(struct clk_init_data){
1552 .name = "gcc_blsp2_qup6_spi_apps_clk",
1553 .parent_names = (const char *[]){
1554 "blsp2_qup6_spi_apps_clk_src",
1555 },
1556 .num_parents = 1,
1557 .flags = CLK_SET_RATE_PARENT,
1558 .ops = &clk_branch2_ops,
1559 },
1560 },
1561};
1562
1563static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1564 .halt_reg = 0x09c4,
1565 .clkr = {
1566 .enable_reg = 0x09c4,
1567 .enable_mask = BIT(0),
1568 .hw.init = &(struct clk_init_data){
1569 .name = "gcc_blsp2_uart1_apps_clk",
1570 .parent_names = (const char *[]){
1571 "blsp2_uart1_apps_clk_src",
1572 },
1573 .num_parents = 1,
1574 .flags = CLK_SET_RATE_PARENT,
1575 .ops = &clk_branch2_ops,
1576 },
1577 },
1578};
1579
1580static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1581 .halt_reg = 0x0a44,
1582 .clkr = {
1583 .enable_reg = 0x0a44,
1584 .enable_mask = BIT(0),
1585 .hw.init = &(struct clk_init_data){
1586 .name = "gcc_blsp2_uart2_apps_clk",
1587 .parent_names = (const char *[]){
1588 "blsp2_uart2_apps_clk_src",
1589 },
1590 .num_parents = 1,
1591 .flags = CLK_SET_RATE_PARENT,
1592 .ops = &clk_branch2_ops,
1593 },
1594 },
1595};
1596
1597static struct clk_branch gcc_blsp2_uart3_apps_clk = {
1598 .halt_reg = 0x0ac4,
1599 .clkr = {
1600 .enable_reg = 0x0ac4,
1601 .enable_mask = BIT(0),
1602 .hw.init = &(struct clk_init_data){
1603 .name = "gcc_blsp2_uart3_apps_clk",
1604 .parent_names = (const char *[]){
1605 "blsp2_uart3_apps_clk_src",
1606 },
1607 .num_parents = 1,
1608 .flags = CLK_SET_RATE_PARENT,
1609 .ops = &clk_branch2_ops,
1610 },
1611 },
1612};
1613
1614static struct clk_branch gcc_blsp2_uart4_apps_clk = {
1615 .halt_reg = 0x0b44,
1616 .clkr = {
1617 .enable_reg = 0x0b44,
1618 .enable_mask = BIT(0),
1619 .hw.init = &(struct clk_init_data){
1620 .name = "gcc_blsp2_uart4_apps_clk",
1621 .parent_names = (const char *[]){
1622 "blsp2_uart4_apps_clk_src",
1623 },
1624 .num_parents = 1,
1625 .flags = CLK_SET_RATE_PARENT,
1626 .ops = &clk_branch2_ops,
1627 },
1628 },
1629};
1630
1631static struct clk_branch gcc_blsp2_uart5_apps_clk = {
1632 .halt_reg = 0x0bc4,
1633 .clkr = {
1634 .enable_reg = 0x0bc4,
1635 .enable_mask = BIT(0),
1636 .hw.init = &(struct clk_init_data){
1637 .name = "gcc_blsp2_uart5_apps_clk",
1638 .parent_names = (const char *[]){
1639 "blsp2_uart5_apps_clk_src",
1640 },
1641 .num_parents = 1,
1642 .flags = CLK_SET_RATE_PARENT,
1643 .ops = &clk_branch2_ops,
1644 },
1645 },
1646};
1647
1648static struct clk_branch gcc_blsp2_uart6_apps_clk = {
1649 .halt_reg = 0x0c44,
1650 .clkr = {
1651 .enable_reg = 0x0c44,
1652 .enable_mask = BIT(0),
1653 .hw.init = &(struct clk_init_data){
1654 .name = "gcc_blsp2_uart6_apps_clk",
1655 .parent_names = (const char *[]){
1656 "blsp2_uart6_apps_clk_src",
1657 },
1658 .num_parents = 1,
1659 .flags = CLK_SET_RATE_PARENT,
1660 .ops = &clk_branch2_ops,
1661 },
1662 },
1663};
1664
1665static struct clk_branch gcc_boot_rom_ahb_clk = {
1666 .halt_reg = 0x0e04,
1667 .halt_check = BRANCH_HALT_VOTED,
1668 .clkr = {
1669 .enable_reg = 0x1484,
1670 .enable_mask = BIT(10),
1671 .hw.init = &(struct clk_init_data){
1672 .name = "gcc_boot_rom_ahb_clk",
1673 .parent_names = (const char *[]){
1674 "config_noc_clk_src",
1675 },
1676 .num_parents = 1,
1677 .ops = &clk_branch2_ops,
1678 },
1679 },
1680};
1681
1682static struct clk_branch gcc_ce1_ahb_clk = {
1683 .halt_reg = 0x104c,
1684 .halt_check = BRANCH_HALT_VOTED,
1685 .clkr = {
1686 .enable_reg = 0x1484,
1687 .enable_mask = BIT(3),
1688 .hw.init = &(struct clk_init_data){
1689 .name = "gcc_ce1_ahb_clk",
1690 .parent_names = (const char *[]){
1691 "config_noc_clk_src",
1692 },
1693 .num_parents = 1,
1694 .ops = &clk_branch2_ops,
1695 },
1696 },
1697};
1698
1699static struct clk_branch gcc_ce1_axi_clk = {
1700 .halt_reg = 0x1048,
1701 .halt_check = BRANCH_HALT_VOTED,
1702 .clkr = {
1703 .enable_reg = 0x1484,
1704 .enable_mask = BIT(4),
1705 .hw.init = &(struct clk_init_data){
1706 .name = "gcc_ce1_axi_clk",
1707 .parent_names = (const char *[]){
1708 "system_noc_clk_src",
1709 },
1710 .num_parents = 1,
1711 .ops = &clk_branch2_ops,
1712 },
1713 },
1714};
1715
1716static struct clk_branch gcc_ce1_clk = {
1717 .halt_reg = 0x1050,
1718 .halt_check = BRANCH_HALT_VOTED,
1719 .clkr = {
1720 .enable_reg = 0x1484,
1721 .enable_mask = BIT(5),
1722 .hw.init = &(struct clk_init_data){
1723 .name = "gcc_ce1_clk",
1724 .parent_names = (const char *[]){
1725 "ce1_clk_src",
1726 },
1727 .num_parents = 1,
1728 .ops = &clk_branch2_ops,
1729 },
1730 },
1731};
1732
1733static struct clk_branch gcc_ce2_ahb_clk = {
1734 .halt_reg = 0x108c,
1735 .halt_check = BRANCH_HALT_VOTED,
1736 .clkr = {
1737 .enable_reg = 0x1484,
1738 .enable_mask = BIT(0),
1739 .hw.init = &(struct clk_init_data){
1740 .name = "gcc_ce2_ahb_clk",
1741 .parent_names = (const char *[]){
1742 "config_noc_clk_src",
1743 },
1744 .num_parents = 1,
1745 .ops = &clk_branch2_ops,
1746 },
1747 },
1748};
1749
1750static struct clk_branch gcc_ce2_axi_clk = {
1751 .halt_reg = 0x1088,
1752 .halt_check = BRANCH_HALT_VOTED,
1753 .clkr = {
1754 .enable_reg = 0x1484,
1755 .enable_mask = BIT(1),
1756 .hw.init = &(struct clk_init_data){
1757 .name = "gcc_ce2_axi_clk",
1758 .parent_names = (const char *[]){
1759 "system_noc_clk_src",
1760 },
1761 .num_parents = 1,
1762 .ops = &clk_branch2_ops,
1763 },
1764 },
1765};
1766
1767static struct clk_branch gcc_ce2_clk = {
1768 .halt_reg = 0x1090,
1769 .halt_check = BRANCH_HALT_VOTED,
1770 .clkr = {
1771 .enable_reg = 0x1484,
1772 .enable_mask = BIT(2),
1773 .hw.init = &(struct clk_init_data){
1774 .name = "gcc_ce2_clk",
1775 .parent_names = (const char *[]){
1776 "ce2_clk_src",
1777 },
1778 .num_parents = 1,
1779 .flags = CLK_SET_RATE_PARENT,
1780 .ops = &clk_branch2_ops,
1781 },
1782 },
1783};
1784
1785static struct clk_branch gcc_gp1_clk = {
1786 .halt_reg = 0x1900,
1787 .clkr = {
1788 .enable_reg = 0x1900,
1789 .enable_mask = BIT(0),
1790 .hw.init = &(struct clk_init_data){
1791 .name = "gcc_gp1_clk",
1792 .parent_names = (const char *[]){
1793 "gp1_clk_src",
1794 },
1795 .num_parents = 1,
1796 .flags = CLK_SET_RATE_PARENT,
1797 .ops = &clk_branch2_ops,
1798 },
1799 },
1800};
1801
1802static struct clk_branch gcc_gp2_clk = {
1803 .halt_reg = 0x1940,
1804 .clkr = {
1805 .enable_reg = 0x1940,
1806 .enable_mask = BIT(0),
1807 .hw.init = &(struct clk_init_data){
1808 .name = "gcc_gp2_clk",
1809 .parent_names = (const char *[]){
1810 "gp2_clk_src",
1811 },
1812 .num_parents = 1,
1813 .flags = CLK_SET_RATE_PARENT,
1814 .ops = &clk_branch2_ops,
1815 },
1816 },
1817};
1818
1819static struct clk_branch gcc_gp3_clk = {
1820 .halt_reg = 0x1980,
1821 .clkr = {
1822 .enable_reg = 0x1980,
1823 .enable_mask = BIT(0),
1824 .hw.init = &(struct clk_init_data){
1825 .name = "gcc_gp3_clk",
1826 .parent_names = (const char *[]){
1827 "gp3_clk_src",
1828 },
1829 .num_parents = 1,
1830 .flags = CLK_SET_RATE_PARENT,
1831 .ops = &clk_branch2_ops,
1832 },
1833 },
1834};
1835
1836static struct clk_branch gcc_lpass_q6_axi_clk = {
1837 .halt_reg = 0x11c0,
1838 .clkr = {
1839 .enable_reg = 0x11c0,
1840 .enable_mask = BIT(0),
1841 .hw.init = &(struct clk_init_data){
1842 .name = "gcc_lpass_q6_axi_clk",
1843 .parent_names = (const char *[]){
1844 "system_noc_clk_src",
1845 },
1846 .num_parents = 1,
1847 .ops = &clk_branch2_ops,
1848 },
1849 },
1850};
1851
1852static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
1853 .halt_reg = 0x024c,
1854 .clkr = {
1855 .enable_reg = 0x024c,
1856 .enable_mask = BIT(0),
1857 .hw.init = &(struct clk_init_data){
1858 .name = "gcc_mmss_noc_cfg_ahb_clk",
1859 .parent_names = (const char *[]){
1860 "config_noc_clk_src",
1861 },
1862 .num_parents = 1,
1863 .ops = &clk_branch2_ops,
1864 .flags = CLK_IGNORE_UNUSED,
1865 },
1866 },
1867};
1868
1869static struct clk_branch gcc_ocmem_noc_cfg_ahb_clk = {
1870 .halt_reg = 0x0248,
1871 .clkr = {
1872 .enable_reg = 0x0248,
1873 .enable_mask = BIT(0),
1874 .hw.init = &(struct clk_init_data){
1875 .name = "gcc_ocmem_noc_cfg_ahb_clk",
1876 .parent_names = (const char *[]){
1877 "config_noc_clk_src",
1878 },
1879 .num_parents = 1,
1880 .ops = &clk_branch2_ops,
1881 },
1882 },
1883};
1884
1885static struct clk_branch gcc_mss_cfg_ahb_clk = {
1886 .halt_reg = 0x0280,
1887 .clkr = {
1888 .enable_reg = 0x0280,
1889 .enable_mask = BIT(0),
1890 .hw.init = &(struct clk_init_data){
1891 .name = "gcc_mss_cfg_ahb_clk",
1892 .parent_names = (const char *[]){
1893 "config_noc_clk_src",
1894 },
1895 .num_parents = 1,
1896 .ops = &clk_branch2_ops,
1897 },
1898 },
1899};
1900
1901static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
1902 .halt_reg = 0x0284,
1903 .clkr = {
1904 .enable_reg = 0x0284,
1905 .enable_mask = BIT(0),
1906 .hw.init = &(struct clk_init_data){
1907 .name = "gcc_mss_q6_bimc_axi_clk",
1908 .flags = CLK_IS_ROOT,
1909 .ops = &clk_branch2_ops,
1910 },
1911 },
1912};
1913
1914static struct clk_branch gcc_pdm2_clk = {
1915 .halt_reg = 0x0ccc,
1916 .clkr = {
1917 .enable_reg = 0x0ccc,
1918 .enable_mask = BIT(0),
1919 .hw.init = &(struct clk_init_data){
1920 .name = "gcc_pdm2_clk",
1921 .parent_names = (const char *[]){
1922 "pdm2_clk_src",
1923 },
1924 .num_parents = 1,
1925 .flags = CLK_SET_RATE_PARENT,
1926 .ops = &clk_branch2_ops,
1927 },
1928 },
1929};
1930
1931static struct clk_branch gcc_pdm_ahb_clk = {
1932 .halt_reg = 0x0cc4,
1933 .clkr = {
1934 .enable_reg = 0x0cc4,
1935 .enable_mask = BIT(0),
1936 .hw.init = &(struct clk_init_data){
1937 .name = "gcc_pdm_ahb_clk",
1938 .parent_names = (const char *[]){
1939 "periph_noc_clk_src",
1940 },
1941 .num_parents = 1,
1942 .ops = &clk_branch2_ops,
1943 },
1944 },
1945};
1946
1947static struct clk_branch gcc_prng_ahb_clk = {
1948 .halt_reg = 0x0d04,
1949 .halt_check = BRANCH_HALT_VOTED,
1950 .clkr = {
1951 .enable_reg = 0x1484,
1952 .enable_mask = BIT(13),
1953 .hw.init = &(struct clk_init_data){
1954 .name = "gcc_prng_ahb_clk",
1955 .parent_names = (const char *[]){
1956 "periph_noc_clk_src",
1957 },
1958 .num_parents = 1,
1959 .ops = &clk_branch2_ops,
1960 },
1961 },
1962};
1963
1964static struct clk_branch gcc_sdcc1_ahb_clk = {
1965 .halt_reg = 0x04c8,
1966 .clkr = {
1967 .enable_reg = 0x04c8,
1968 .enable_mask = BIT(0),
1969 .hw.init = &(struct clk_init_data){
1970 .name = "gcc_sdcc1_ahb_clk",
1971 .parent_names = (const char *[]){
1972 "periph_noc_clk_src",
1973 },
1974 .num_parents = 1,
1975 .ops = &clk_branch2_ops,
1976 },
1977 },
1978};
1979
1980static struct clk_branch gcc_sdcc1_apps_clk = {
1981 .halt_reg = 0x04c4,
1982 .clkr = {
1983 .enable_reg = 0x04c4,
1984 .enable_mask = BIT(0),
1985 .hw.init = &(struct clk_init_data){
1986 .name = "gcc_sdcc1_apps_clk",
1987 .parent_names = (const char *[]){
1988 "sdcc1_apps_clk_src",
1989 },
1990 .num_parents = 1,
1991 .flags = CLK_SET_RATE_PARENT,
1992 .ops = &clk_branch2_ops,
1993 },
1994 },
1995};
1996
1997static struct clk_branch gcc_sdcc2_ahb_clk = {
1998 .halt_reg = 0x0508,
1999 .clkr = {
2000 .enable_reg = 0x0508,
2001 .enable_mask = BIT(0),
2002 .hw.init = &(struct clk_init_data){
2003 .name = "gcc_sdcc2_ahb_clk",
2004 .parent_names = (const char *[]){
2005 "periph_noc_clk_src",
2006 },
2007 .num_parents = 1,
2008 .ops = &clk_branch2_ops,
2009 },
2010 },
2011};
2012
2013static struct clk_branch gcc_sdcc2_apps_clk = {
2014 .halt_reg = 0x0504,
2015 .clkr = {
2016 .enable_reg = 0x0504,
2017 .enable_mask = BIT(0),
2018 .hw.init = &(struct clk_init_data){
2019 .name = "gcc_sdcc2_apps_clk",
2020 .parent_names = (const char *[]){
2021 "sdcc2_apps_clk_src",
2022 },
2023 .num_parents = 1,
2024 .flags = CLK_SET_RATE_PARENT,
2025 .ops = &clk_branch2_ops,
2026 },
2027 },
2028};
2029
2030static struct clk_branch gcc_sdcc3_ahb_clk = {
2031 .halt_reg = 0x0548,
2032 .clkr = {
2033 .enable_reg = 0x0548,
2034 .enable_mask = BIT(0),
2035 .hw.init = &(struct clk_init_data){
2036 .name = "gcc_sdcc3_ahb_clk",
2037 .parent_names = (const char *[]){
2038 "periph_noc_clk_src",
2039 },
2040 .num_parents = 1,
2041 .ops = &clk_branch2_ops,
2042 },
2043 },
2044};
2045
2046static struct clk_branch gcc_sdcc3_apps_clk = {
2047 .halt_reg = 0x0544,
2048 .clkr = {
2049 .enable_reg = 0x0544,
2050 .enable_mask = BIT(0),
2051 .hw.init = &(struct clk_init_data){
2052 .name = "gcc_sdcc3_apps_clk",
2053 .parent_names = (const char *[]){
2054 "sdcc3_apps_clk_src",
2055 },
2056 .num_parents = 1,
2057 .flags = CLK_SET_RATE_PARENT,
2058 .ops = &clk_branch2_ops,
2059 },
2060 },
2061};
2062
2063static struct clk_branch gcc_sdcc4_ahb_clk = {
2064 .halt_reg = 0x0588,
2065 .clkr = {
2066 .enable_reg = 0x0588,
2067 .enable_mask = BIT(0),
2068 .hw.init = &(struct clk_init_data){
2069 .name = "gcc_sdcc4_ahb_clk",
2070 .parent_names = (const char *[]){
2071 "periph_noc_clk_src",
2072 },
2073 .num_parents = 1,
2074 .ops = &clk_branch2_ops,
2075 },
2076 },
2077};
2078
2079static struct clk_branch gcc_sdcc4_apps_clk = {
2080 .halt_reg = 0x0584,
2081 .clkr = {
2082 .enable_reg = 0x0584,
2083 .enable_mask = BIT(0),
2084 .hw.init = &(struct clk_init_data){
2085 .name = "gcc_sdcc4_apps_clk",
2086 .parent_names = (const char *[]){
2087 "sdcc4_apps_clk_src",
2088 },
2089 .num_parents = 1,
2090 .flags = CLK_SET_RATE_PARENT,
2091 .ops = &clk_branch2_ops,
2092 },
2093 },
2094};
2095
2096static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
2097 .halt_reg = 0x0108,
2098 .clkr = {
2099 .enable_reg = 0x0108,
2100 .enable_mask = BIT(0),
2101 .hw.init = &(struct clk_init_data){
2102 .name = "gcc_sys_noc_usb3_axi_clk",
2103 .parent_names = (const char *[]){
2104 "usb30_master_clk_src",
2105 },
2106 .num_parents = 1,
2107 .flags = CLK_SET_RATE_PARENT,
2108 .ops = &clk_branch2_ops,
2109 },
2110 },
2111};
2112
2113static struct clk_branch gcc_tsif_ahb_clk = {
2114 .halt_reg = 0x0d84,
2115 .clkr = {
2116 .enable_reg = 0x0d84,
2117 .enable_mask = BIT(0),
2118 .hw.init = &(struct clk_init_data){
2119 .name = "gcc_tsif_ahb_clk",
2120 .parent_names = (const char *[]){
2121 "periph_noc_clk_src",
2122 },
2123 .num_parents = 1,
2124 .ops = &clk_branch2_ops,
2125 },
2126 },
2127};
2128
2129static struct clk_branch gcc_tsif_ref_clk = {
2130 .halt_reg = 0x0d88,
2131 .clkr = {
2132 .enable_reg = 0x0d88,
2133 .enable_mask = BIT(0),
2134 .hw.init = &(struct clk_init_data){
2135 .name = "gcc_tsif_ref_clk",
2136 .parent_names = (const char *[]){
2137 "tsif_ref_clk_src",
2138 },
2139 .num_parents = 1,
2140 .flags = CLK_SET_RATE_PARENT,
2141 .ops = &clk_branch2_ops,
2142 },
2143 },
2144};
2145
2146static struct clk_branch gcc_usb2a_phy_sleep_clk = {
2147 .halt_reg = 0x04ac,
2148 .clkr = {
2149 .enable_reg = 0x04ac,
2150 .enable_mask = BIT(0),
2151 .hw.init = &(struct clk_init_data){
2152 .name = "gcc_usb2a_phy_sleep_clk",
2153 .parent_names = (const char *[]){
2154 "sleep_clk_src",
2155 },
2156 .num_parents = 1,
2157 .ops = &clk_branch2_ops,
2158 },
2159 },
2160};
2161
2162static struct clk_branch gcc_usb2b_phy_sleep_clk = {
2163 .halt_reg = 0x04b4,
2164 .clkr = {
2165 .enable_reg = 0x04b4,
2166 .enable_mask = BIT(0),
2167 .hw.init = &(struct clk_init_data){
2168 .name = "gcc_usb2b_phy_sleep_clk",
2169 .parent_names = (const char *[]){
2170 "sleep_clk_src",
2171 },
2172 .num_parents = 1,
2173 .ops = &clk_branch2_ops,
2174 },
2175 },
2176};
2177
2178static struct clk_branch gcc_usb30_master_clk = {
2179 .halt_reg = 0x03c8,
2180 .clkr = {
2181 .enable_reg = 0x03c8,
2182 .enable_mask = BIT(0),
2183 .hw.init = &(struct clk_init_data){
2184 .name = "gcc_usb30_master_clk",
2185 .parent_names = (const char *[]){
2186 "usb30_master_clk_src",
2187 },
2188 .num_parents = 1,
2189 .flags = CLK_SET_RATE_PARENT,
2190 .ops = &clk_branch2_ops,
2191 },
2192 },
2193};
2194
2195static struct clk_branch gcc_usb30_mock_utmi_clk = {
2196 .halt_reg = 0x03d0,
2197 .clkr = {
2198 .enable_reg = 0x03d0,
2199 .enable_mask = BIT(0),
2200 .hw.init = &(struct clk_init_data){
2201 .name = "gcc_usb30_mock_utmi_clk",
2202 .parent_names = (const char *[]){
2203 "usb30_mock_utmi_clk_src",
2204 },
2205 .num_parents = 1,
2206 .flags = CLK_SET_RATE_PARENT,
2207 .ops = &clk_branch2_ops,
2208 },
2209 },
2210};
2211
2212static struct clk_branch gcc_usb30_sleep_clk = {
2213 .halt_reg = 0x03cc,
2214 .clkr = {
2215 .enable_reg = 0x03cc,
2216 .enable_mask = BIT(0),
2217 .hw.init = &(struct clk_init_data){
2218 .name = "gcc_usb30_sleep_clk",
2219 .parent_names = (const char *[]){
2220 "sleep_clk_src",
2221 },
2222 .num_parents = 1,
2223 .ops = &clk_branch2_ops,
2224 },
2225 },
2226};
2227
2228static struct clk_branch gcc_usb_hs_ahb_clk = {
2229 .halt_reg = 0x0488,
2230 .clkr = {
2231 .enable_reg = 0x0488,
2232 .enable_mask = BIT(0),
2233 .hw.init = &(struct clk_init_data){
2234 .name = "gcc_usb_hs_ahb_clk",
2235 .parent_names = (const char *[]){
2236 "periph_noc_clk_src",
2237 },
2238 .num_parents = 1,
2239 .ops = &clk_branch2_ops,
2240 },
2241 },
2242};
2243
2244static struct clk_branch gcc_usb_hs_system_clk = {
2245 .halt_reg = 0x0484,
2246 .clkr = {
2247 .enable_reg = 0x0484,
2248 .enable_mask = BIT(0),
2249 .hw.init = &(struct clk_init_data){
2250 .name = "gcc_usb_hs_system_clk",
2251 .parent_names = (const char *[]){
2252 "usb_hs_system_clk_src",
2253 },
2254 .num_parents = 1,
2255 .flags = CLK_SET_RATE_PARENT,
2256 .ops = &clk_branch2_ops,
2257 },
2258 },
2259};
2260
2261static struct clk_branch gcc_usb_hsic_ahb_clk = {
2262 .halt_reg = 0x0408,
2263 .clkr = {
2264 .enable_reg = 0x0408,
2265 .enable_mask = BIT(0),
2266 .hw.init = &(struct clk_init_data){
2267 .name = "gcc_usb_hsic_ahb_clk",
2268 .parent_names = (const char *[]){
2269 "periph_noc_clk_src",
2270 },
2271 .num_parents = 1,
2272 .ops = &clk_branch2_ops,
2273 },
2274 },
2275};
2276
2277static struct clk_branch gcc_usb_hsic_clk = {
2278 .halt_reg = 0x0410,
2279 .clkr = {
2280 .enable_reg = 0x0410,
2281 .enable_mask = BIT(0),
2282 .hw.init = &(struct clk_init_data){
2283 .name = "gcc_usb_hsic_clk",
2284 .parent_names = (const char *[]){
2285 "usb_hsic_clk_src",
2286 },
2287 .num_parents = 1,
2288 .flags = CLK_SET_RATE_PARENT,
2289 .ops = &clk_branch2_ops,
2290 },
2291 },
2292};
2293
2294static struct clk_branch gcc_usb_hsic_io_cal_clk = {
2295 .halt_reg = 0x0414,
2296 .clkr = {
2297 .enable_reg = 0x0414,
2298 .enable_mask = BIT(0),
2299 .hw.init = &(struct clk_init_data){
2300 .name = "gcc_usb_hsic_io_cal_clk",
2301 .parent_names = (const char *[]){
2302 "usb_hsic_io_cal_clk_src",
2303 },
2304 .num_parents = 1,
2305 .flags = CLK_SET_RATE_PARENT,
2306 .ops = &clk_branch2_ops,
2307 },
2308 },
2309};
2310
2311static struct clk_branch gcc_usb_hsic_io_cal_sleep_clk = {
2312 .halt_reg = 0x0418,
2313 .clkr = {
2314 .enable_reg = 0x0418,
2315 .enable_mask = BIT(0),
2316 .hw.init = &(struct clk_init_data){
2317 .name = "gcc_usb_hsic_io_cal_sleep_clk",
2318 .parent_names = (const char *[]){
2319 "sleep_clk_src",
2320 },
2321 .num_parents = 1,
2322 .ops = &clk_branch2_ops,
2323 },
2324 },
2325};
2326
2327static struct clk_branch gcc_usb_hsic_system_clk = {
2328 .halt_reg = 0x040c,
2329 .clkr = {
2330 .enable_reg = 0x040c,
2331 .enable_mask = BIT(0),
2332 .hw.init = &(struct clk_init_data){
2333 .name = "gcc_usb_hsic_system_clk",
2334 .parent_names = (const char *[]){
2335 "usb_hsic_system_clk_src",
2336 },
2337 .num_parents = 1,
2338 .flags = CLK_SET_RATE_PARENT,
2339 .ops = &clk_branch2_ops,
2340 },
2341 },
2342};
2343
2344static struct clk_regmap *gcc_msm8974_clocks[] = {
2345 [GPLL0] = &gpll0.clkr,
2346 [GPLL0_VOTE] = &gpll0_vote,
2347 [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
2348 [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
2349 [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
2350 [GPLL1] = &gpll1.clkr,
2351 [GPLL1_VOTE] = &gpll1_vote,
2352 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2353 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2354 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2355 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2356 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2357 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2358 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2359 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2360 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2361 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
2362 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
2363 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
2364 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
2365 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2366 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2367 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2368 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
2369 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
2370 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
2371 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
2372 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
2373 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
2374 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
2375 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
2376 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
2377 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
2378 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
2379 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
2380 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
2381 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
2382 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
2383 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
2384 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
2385 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
2386 [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
2387 [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
2388 [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
2389 [CE1_CLK_SRC] = &ce1_clk_src.clkr,
2390 [CE2_CLK_SRC] = &ce2_clk_src.clkr,
2391 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
2392 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
2393 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
2394 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2395 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2396 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2397 [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
2398 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
2399 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
2400 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2401 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
2402 [USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr,
2403 [USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr,
2404 [USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr,
2405 [GCC_BAM_DMA_AHB_CLK] = &gcc_bam_dma_ahb_clk.clkr,
2406 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2407 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2408 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2409 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2410 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2411 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2412 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2413 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2414 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2415 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
2416 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
2417 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
2418 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
2419 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2420 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2421 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2422 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
2423 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
2424 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
2425 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2426 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
2427 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
2428 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
2429 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
2430 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
2431 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
2432 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
2433 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
2434 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
2435 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
2436 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
2437 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
2438 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
2439 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
2440 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
2441 [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
2442 [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
2443 [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
2444 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2445 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
2446 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
2447 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
2448 [GCC_CE2_AHB_CLK] = &gcc_ce2_ahb_clk.clkr,
2449 [GCC_CE2_AXI_CLK] = &gcc_ce2_axi_clk.clkr,
2450 [GCC_CE2_CLK] = &gcc_ce2_clk.clkr,
2451 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2452 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2453 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2454 [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr,
2455 [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
2456 [GCC_OCMEM_NOC_CFG_AHB_CLK] = &gcc_ocmem_noc_cfg_ahb_clk.clkr,
2457 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
2458 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
2459 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2460 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2461 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2462 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2463 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2464 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2465 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2466 [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
2467 [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
2468 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
2469 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
2470 [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
2471 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
2472 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
2473 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
2474 [GCC_USB2B_PHY_SLEEP_CLK] = &gcc_usb2b_phy_sleep_clk.clkr,
2475 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2476 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2477 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
2478 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
2479 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
2480 [GCC_USB_HSIC_AHB_CLK] = &gcc_usb_hsic_ahb_clk.clkr,
2481 [GCC_USB_HSIC_CLK] = &gcc_usb_hsic_clk.clkr,
2482 [GCC_USB_HSIC_IO_CAL_CLK] = &gcc_usb_hsic_io_cal_clk.clkr,
2483 [GCC_USB_HSIC_IO_CAL_SLEEP_CLK] = &gcc_usb_hsic_io_cal_sleep_clk.clkr,
2484 [GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr,
2485 [GCC_MMSS_GPLL0_CLK_SRC] = &gcc_mmss_gpll0_clk_src,
2486};
2487
2488static const struct qcom_reset_map gcc_msm8974_resets[] = {
2489 [GCC_SYSTEM_NOC_BCR] = { 0x0100 },
2490 [GCC_CONFIG_NOC_BCR] = { 0x0140 },
2491 [GCC_PERIPH_NOC_BCR] = { 0x0180 },
2492 [GCC_IMEM_BCR] = { 0x0200 },
2493 [GCC_MMSS_BCR] = { 0x0240 },
2494 [GCC_QDSS_BCR] = { 0x0300 },
2495 [GCC_USB_30_BCR] = { 0x03c0 },
2496 [GCC_USB3_PHY_BCR] = { 0x03fc },
2497 [GCC_USB_HS_HSIC_BCR] = { 0x0400 },
2498 [GCC_USB_HS_BCR] = { 0x0480 },
2499 [GCC_USB2A_PHY_BCR] = { 0x04a8 },
2500 [GCC_USB2B_PHY_BCR] = { 0x04b0 },
2501 [GCC_SDCC1_BCR] = { 0x04c0 },
2502 [GCC_SDCC2_BCR] = { 0x0500 },
2503 [GCC_SDCC3_BCR] = { 0x0540 },
2504 [GCC_SDCC4_BCR] = { 0x0580 },
2505 [GCC_BLSP1_BCR] = { 0x05c0 },
2506 [GCC_BLSP1_QUP1_BCR] = { 0x0640 },
2507 [GCC_BLSP1_UART1_BCR] = { 0x0680 },
2508 [GCC_BLSP1_QUP2_BCR] = { 0x06c0 },
2509 [GCC_BLSP1_UART2_BCR] = { 0x0700 },
2510 [GCC_BLSP1_QUP3_BCR] = { 0x0740 },
2511 [GCC_BLSP1_UART3_BCR] = { 0x0780 },
2512 [GCC_BLSP1_QUP4_BCR] = { 0x07c0 },
2513 [GCC_BLSP1_UART4_BCR] = { 0x0800 },
2514 [GCC_BLSP1_QUP5_BCR] = { 0x0840 },
2515 [GCC_BLSP1_UART5_BCR] = { 0x0880 },
2516 [GCC_BLSP1_QUP6_BCR] = { 0x08c0 },
2517 [GCC_BLSP1_UART6_BCR] = { 0x0900 },
2518 [GCC_BLSP2_BCR] = { 0x0940 },
2519 [GCC_BLSP2_QUP1_BCR] = { 0x0980 },
2520 [GCC_BLSP2_UART1_BCR] = { 0x09c0 },
2521 [GCC_BLSP2_QUP2_BCR] = { 0x0a00 },
2522 [GCC_BLSP2_UART2_BCR] = { 0x0a40 },
2523 [GCC_BLSP2_QUP3_BCR] = { 0x0a80 },
2524 [GCC_BLSP2_UART3_BCR] = { 0x0ac0 },
2525 [GCC_BLSP2_QUP4_BCR] = { 0x0b00 },
2526 [GCC_BLSP2_UART4_BCR] = { 0x0b40 },
2527 [GCC_BLSP2_QUP5_BCR] = { 0x0b80 },
2528 [GCC_BLSP2_UART5_BCR] = { 0x0bc0 },
2529 [GCC_BLSP2_QUP6_BCR] = { 0x0c00 },
2530 [GCC_BLSP2_UART6_BCR] = { 0x0c40 },
2531 [GCC_PDM_BCR] = { 0x0cc0 },
2532 [GCC_BAM_DMA_BCR] = { 0x0d40 },
2533 [GCC_TSIF_BCR] = { 0x0d80 },
2534 [GCC_TCSR_BCR] = { 0x0dc0 },
2535 [GCC_BOOT_ROM_BCR] = { 0x0e00 },
2536 [GCC_MSG_RAM_BCR] = { 0x0e40 },
2537 [GCC_TLMM_BCR] = { 0x0e80 },
2538 [GCC_MPM_BCR] = { 0x0ec0 },
2539 [GCC_SEC_CTRL_BCR] = { 0x0f40 },
2540 [GCC_SPMI_BCR] = { 0x0fc0 },
2541 [GCC_SPDM_BCR] = { 0x1000 },
2542 [GCC_CE1_BCR] = { 0x1040 },
2543 [GCC_CE2_BCR] = { 0x1080 },
2544 [GCC_BIMC_BCR] = { 0x1100 },
2545 [GCC_MPM_NON_AHB_RESET] = { 0x0ec4, 2 },
2546 [GCC_MPM_AHB_RESET] = { 0x0ec4, 1 },
2547 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x1240 },
2548 [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x1248 },
2549 [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x1280 },
2550 [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x1288 },
2551 [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x1290 },
2552 [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x1298 },
2553 [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x12a0 },
2554 [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x12c0 },
2555 [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x12c8 },
2556 [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x12d0 },
2557 [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x12d8 },
2558 [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x12e0 },
2559 [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x12e8 },
2560 [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x12f0 },
2561 [GCC_DEHR_BCR] = { 0x1300 },
2562 [GCC_RBCPR_BCR] = { 0x1380 },
2563 [GCC_MSS_RESTART] = { 0x1680 },
2564 [GCC_LPASS_RESTART] = { 0x16c0 },
2565 [GCC_WCSS_RESTART] = { 0x1700 },
2566 [GCC_VENUS_RESTART] = { 0x1740 },
2567};
2568
2569static const struct regmap_config gcc_msm8974_regmap_config = {
2570 .reg_bits = 32,
2571 .reg_stride = 4,
2572 .val_bits = 32,
2573 .max_register = 0x1fc0,
2574 .fast_io = true,
2575};
2576
2577static const struct of_device_id gcc_msm8974_match_table[] = {
2578 { .compatible = "qcom,gcc-msm8974" },
2579 { }
2580};
2581MODULE_DEVICE_TABLE(of, gcc_msm8974_match_table);
2582
2583struct qcom_cc {
2584 struct qcom_reset_controller reset;
2585 struct clk_onecell_data data;
2586 struct clk *clks[];
2587};
2588
2589static int gcc_msm8974_probe(struct platform_device *pdev)
2590{
2591 void __iomem *base;
2592 struct resource *res;
2593 int i, ret;
2594 struct device *dev = &pdev->dev;
2595 struct clk *clk;
2596 struct clk_onecell_data *data;
2597 struct clk **clks;
2598 struct regmap *regmap;
2599 size_t num_clks;
2600 struct qcom_reset_controller *reset;
2601 struct qcom_cc *cc;
2602
2603 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2604 base = devm_ioremap_resource(dev, res);
2605 if (IS_ERR(base))
2606 return PTR_ERR(base);
2607
2608 regmap = devm_regmap_init_mmio(dev, base, &gcc_msm8974_regmap_config);
2609 if (IS_ERR(regmap))
2610 return PTR_ERR(regmap);
2611
2612 num_clks = ARRAY_SIZE(gcc_msm8974_clocks);
2613 cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*clks) * num_clks,
2614 GFP_KERNEL);
2615 if (!cc)
2616 return -ENOMEM;
2617
2618 clks = cc->clks;
2619 data = &cc->data;
2620 data->clks = clks;
2621 data->clk_num = num_clks;
2622
2623 /* Temporary until RPM clocks supported */
2624 clk = clk_register_fixed_rate(dev, "xo", NULL, CLK_IS_ROOT, 19200000);
2625 if (IS_ERR(clk))
2626 return PTR_ERR(clk);
2627
2628 /* Should move to DT node? */
2629 clk = clk_register_fixed_rate(dev, "sleep_clk_src", NULL,
2630 CLK_IS_ROOT, 32768);
2631 if (IS_ERR(clk))
2632 return PTR_ERR(clk);
2633
2634 for (i = 0; i < num_clks; i++) {
2635 if (!gcc_msm8974_clocks[i])
2636 continue;
2637 clk = devm_clk_register_regmap(dev, gcc_msm8974_clocks[i]);
2638 if (IS_ERR(clk))
2639 return PTR_ERR(clk);
2640 clks[i] = clk;
2641 }
2642
2643 ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, data);
2644 if (ret)
2645 return ret;
2646
2647 reset = &cc->reset;
2648 reset->rcdev.of_node = dev->of_node;
2649 reset->rcdev.ops = &qcom_reset_ops,
2650 reset->rcdev.owner = THIS_MODULE,
2651 reset->rcdev.nr_resets = ARRAY_SIZE(gcc_msm8974_resets),
2652 reset->regmap = regmap;
2653 reset->reset_map = gcc_msm8974_resets,
2654 platform_set_drvdata(pdev, &reset->rcdev);
2655
2656 ret = reset_controller_register(&reset->rcdev);
2657 if (ret)
2658 of_clk_del_provider(dev->of_node);
2659
2660 return ret;
2661}
2662
2663static int gcc_msm8974_remove(struct platform_device *pdev)
2664{
2665 of_clk_del_provider(pdev->dev.of_node);
2666 reset_controller_unregister(platform_get_drvdata(pdev));
2667 return 0;
2668}
2669
2670static struct platform_driver gcc_msm8974_driver = {
2671 .probe = gcc_msm8974_probe,
2672 .remove = gcc_msm8974_remove,
2673 .driver = {
2674 .name = "gcc-msm8974",
2675 .owner = THIS_MODULE,
2676 .of_match_table = gcc_msm8974_match_table,
2677 },
2678};
2679
2680static int __init gcc_msm8974_init(void)
2681{
2682 return platform_driver_register(&gcc_msm8974_driver);
2683}
2684core_initcall(gcc_msm8974_init);
2685
2686static void __exit gcc_msm8974_exit(void)
2687{
2688 platform_driver_unregister(&gcc_msm8974_driver);
2689}
2690module_exit(gcc_msm8974_exit);
2691
2692MODULE_DESCRIPTION("QCOM GCC MSM8974 Driver");
2693MODULE_LICENSE("GPL v2");
2694MODULE_ALIAS("platform:gcc-msm8974");
diff --git a/drivers/clk/qcom/mmcc-msm8960.c b/drivers/clk/qcom/mmcc-msm8960.c
new file mode 100644
index 000000000000..f9b59c7e48e9
--- /dev/null
+++ b/drivers/clk/qcom/mmcc-msm8960.c
@@ -0,0 +1,2321 @@
1/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/bitops.h>
16#include <linux/err.h>
17#include <linux/delay.h>
18#include <linux/platform_device.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/of_device.h>
22#include <linux/clk-provider.h>
23#include <linux/regmap.h>
24#include <linux/reset-controller.h>
25
26#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
27#include <dt-bindings/reset/qcom,mmcc-msm8960.h>
28
29#include "clk-regmap.h"
30#include "clk-pll.h"
31#include "clk-rcg.h"
32#include "clk-branch.h"
33#include "reset.h"
34
35#define P_PXO 0
36#define P_PLL8 1
37#define P_PLL2 2
38#define P_PLL3 3
39
40static u8 mmcc_pxo_pll8_pll2_map[] = {
41 [P_PXO] = 0,
42 [P_PLL8] = 2,
43 [P_PLL2] = 1,
44};
45
46static const char *mmcc_pxo_pll8_pll2[] = {
47 "pxo",
48 "pll8_vote",
49 "pll2",
50};
51
52static u8 mmcc_pxo_pll8_pll2_pll3_map[] = {
53 [P_PXO] = 0,
54 [P_PLL8] = 2,
55 [P_PLL2] = 1,
56 [P_PLL3] = 3,
57};
58
59static const char *mmcc_pxo_pll8_pll2_pll3[] = {
60 "pxo",
61 "pll2",
62 "pll8_vote",
63 "pll3",
64};
65
66static struct clk_pll pll2 = {
67 .l_reg = 0x320,
68 .m_reg = 0x324,
69 .n_reg = 0x328,
70 .config_reg = 0x32c,
71 .mode_reg = 0x31c,
72 .status_reg = 0x334,
73 .status_bit = 16,
74 .clkr.hw.init = &(struct clk_init_data){
75 .name = "pll2",
76 .parent_names = (const char *[]){ "pxo" },
77 .num_parents = 1,
78 .ops = &clk_pll_ops,
79 },
80};
81
82static struct freq_tbl clk_tbl_cam[] = {
83 { 6000000, P_PLL8, 4, 1, 16 },
84 { 8000000, P_PLL8, 4, 1, 12 },
85 { 12000000, P_PLL8, 4, 1, 8 },
86 { 16000000, P_PLL8, 4, 1, 6 },
87 { 19200000, P_PLL8, 4, 1, 5 },
88 { 24000000, P_PLL8, 4, 1, 4 },
89 { 32000000, P_PLL8, 4, 1, 3 },
90 { 48000000, P_PLL8, 4, 1, 2 },
91 { 64000000, P_PLL8, 3, 1, 2 },
92 { 96000000, P_PLL8, 4, 0, 0 },
93 { 128000000, P_PLL8, 3, 0, 0 },
94 { }
95};
96
97static struct clk_rcg camclk0_src = {
98 .ns_reg = 0x0148,
99 .md_reg = 0x0144,
100 .mn = {
101 .mnctr_en_bit = 5,
102 .mnctr_reset_bit = 8,
103 .reset_in_cc = true,
104 .mnctr_mode_shift = 6,
105 .n_val_shift = 24,
106 .m_val_shift = 8,
107 .width = 8,
108 },
109 .p = {
110 .pre_div_shift = 14,
111 .pre_div_width = 2,
112 },
113 .s = {
114 .src_sel_shift = 0,
115 .parent_map = mmcc_pxo_pll8_pll2_map,
116 },
117 .freq_tbl = clk_tbl_cam,
118 .clkr = {
119 .enable_reg = 0x0140,
120 .enable_mask = BIT(2),
121 .hw.init = &(struct clk_init_data){
122 .name = "camclk0_src",
123 .parent_names = mmcc_pxo_pll8_pll2,
124 .num_parents = 3,
125 .ops = &clk_rcg_ops,
126 },
127 },
128};
129
130static struct clk_branch camclk0_clk = {
131 .halt_reg = 0x01e8,
132 .halt_bit = 15,
133 .clkr = {
134 .enable_reg = 0x0140,
135 .enable_mask = BIT(0),
136 .hw.init = &(struct clk_init_data){
137 .name = "camclk0_clk",
138 .parent_names = (const char *[]){ "camclk0_src" },
139 .num_parents = 1,
140 .ops = &clk_branch_ops,
141 },
142 },
143
144};
145
146static struct clk_rcg camclk1_src = {
147 .ns_reg = 0x015c,
148 .md_reg = 0x0158,
149 .mn = {
150 .mnctr_en_bit = 5,
151 .mnctr_reset_bit = 8,
152 .reset_in_cc = true,
153 .mnctr_mode_shift = 6,
154 .n_val_shift = 24,
155 .m_val_shift = 8,
156 .width = 8,
157 },
158 .p = {
159 .pre_div_shift = 14,
160 .pre_div_width = 2,
161 },
162 .s = {
163 .src_sel_shift = 0,
164 .parent_map = mmcc_pxo_pll8_pll2_map,
165 },
166 .freq_tbl = clk_tbl_cam,
167 .clkr = {
168 .enable_reg = 0x0154,
169 .enable_mask = BIT(2),
170 .hw.init = &(struct clk_init_data){
171 .name = "camclk1_src",
172 .parent_names = mmcc_pxo_pll8_pll2,
173 .num_parents = 3,
174 .ops = &clk_rcg_ops,
175 },
176 },
177};
178
179static struct clk_branch camclk1_clk = {
180 .halt_reg = 0x01e8,
181 .halt_bit = 16,
182 .clkr = {
183 .enable_reg = 0x0154,
184 .enable_mask = BIT(0),
185 .hw.init = &(struct clk_init_data){
186 .name = "camclk1_clk",
187 .parent_names = (const char *[]){ "camclk1_src" },
188 .num_parents = 1,
189 .ops = &clk_branch_ops,
190 },
191 },
192
193};
194
195static struct clk_rcg camclk2_src = {
196 .ns_reg = 0x0228,
197 .md_reg = 0x0224,
198 .mn = {
199 .mnctr_en_bit = 5,
200 .mnctr_reset_bit = 8,
201 .reset_in_cc = true,
202 .mnctr_mode_shift = 6,
203 .n_val_shift = 24,
204 .m_val_shift = 8,
205 .width = 8,
206 },
207 .p = {
208 .pre_div_shift = 14,
209 .pre_div_width = 2,
210 },
211 .s = {
212 .src_sel_shift = 0,
213 .parent_map = mmcc_pxo_pll8_pll2_map,
214 },
215 .freq_tbl = clk_tbl_cam,
216 .clkr = {
217 .enable_reg = 0x0220,
218 .enable_mask = BIT(2),
219 .hw.init = &(struct clk_init_data){
220 .name = "camclk2_src",
221 .parent_names = mmcc_pxo_pll8_pll2,
222 .num_parents = 3,
223 .ops = &clk_rcg_ops,
224 },
225 },
226};
227
228static struct clk_branch camclk2_clk = {
229 .halt_reg = 0x01e8,
230 .halt_bit = 16,
231 .clkr = {
232 .enable_reg = 0x0220,
233 .enable_mask = BIT(0),
234 .hw.init = &(struct clk_init_data){
235 .name = "camclk2_clk",
236 .parent_names = (const char *[]){ "camclk2_src" },
237 .num_parents = 1,
238 .ops = &clk_branch_ops,
239 },
240 },
241
242};
243
244static struct freq_tbl clk_tbl_csi[] = {
245 { 27000000, P_PXO, 1, 0, 0 },
246 { 85330000, P_PLL8, 1, 2, 9 },
247 { 177780000, P_PLL2, 1, 2, 9 },
248 { }
249};
250
251static struct clk_rcg csi0_src = {
252 .ns_reg = 0x0048,
253 .md_reg = 0x0044,
254 .mn = {
255 .mnctr_en_bit = 5,
256 .mnctr_reset_bit = 7,
257 .mnctr_mode_shift = 6,
258 .n_val_shift = 24,
259 .m_val_shift = 8,
260 .width = 8,
261 },
262 .p = {
263 .pre_div_shift = 14,
264 .pre_div_width = 2,
265 },
266 .s = {
267 .src_sel_shift = 0,
268 .parent_map = mmcc_pxo_pll8_pll2_map,
269 },
270 .freq_tbl = clk_tbl_csi,
271 .clkr = {
272 .enable_reg = 0x0040,
273 .enable_mask = BIT(2),
274 .hw.init = &(struct clk_init_data){
275 .name = "csi0_src",
276 .parent_names = mmcc_pxo_pll8_pll2,
277 .num_parents = 3,
278 .ops = &clk_rcg_ops,
279 },
280 },
281};
282
283static struct clk_branch csi0_clk = {
284 .halt_reg = 0x01cc,
285 .halt_bit = 13,
286 .clkr = {
287 .enable_reg = 0x0040,
288 .enable_mask = BIT(0),
289 .hw.init = &(struct clk_init_data){
290 .parent_names = (const char *[]){ "csi0_src" },
291 .num_parents = 1,
292 .name = "csi0_clk",
293 .ops = &clk_branch_ops,
294 .flags = CLK_SET_RATE_PARENT,
295 },
296 },
297};
298
299static struct clk_branch csi0_phy_clk = {
300 .halt_reg = 0x01e8,
301 .halt_bit = 9,
302 .clkr = {
303 .enable_reg = 0x0040,
304 .enable_mask = BIT(8),
305 .hw.init = &(struct clk_init_data){
306 .parent_names = (const char *[]){ "csi0_src" },
307 .num_parents = 1,
308 .name = "csi0_phy_clk",
309 .ops = &clk_branch_ops,
310 .flags = CLK_SET_RATE_PARENT,
311 },
312 },
313};
314
315static struct clk_rcg csi1_src = {
316 .ns_reg = 0x0010,
317 .md_reg = 0x0028,
318 .mn = {
319 .mnctr_en_bit = 5,
320 .mnctr_reset_bit = 7,
321 .mnctr_mode_shift = 6,
322 .n_val_shift = 24,
323 .m_val_shift = 8,
324 .width = 8,
325 },
326 .p = {
327 .pre_div_shift = 14,
328 .pre_div_width = 2,
329 },
330 .s = {
331 .src_sel_shift = 0,
332 .parent_map = mmcc_pxo_pll8_pll2_map,
333 },
334 .freq_tbl = clk_tbl_csi,
335 .clkr = {
336 .enable_reg = 0x0024,
337 .enable_mask = BIT(2),
338 .hw.init = &(struct clk_init_data){
339 .name = "csi1_src",
340 .parent_names = mmcc_pxo_pll8_pll2,
341 .num_parents = 3,
342 .ops = &clk_rcg_ops,
343 },
344 },
345};
346
347static struct clk_branch csi1_clk = {
348 .halt_reg = 0x01cc,
349 .halt_bit = 14,
350 .clkr = {
351 .enable_reg = 0x0024,
352 .enable_mask = BIT(0),
353 .hw.init = &(struct clk_init_data){
354 .parent_names = (const char *[]){ "csi1_src" },
355 .num_parents = 1,
356 .name = "csi1_clk",
357 .ops = &clk_branch_ops,
358 .flags = CLK_SET_RATE_PARENT,
359 },
360 },
361};
362
363static struct clk_branch csi1_phy_clk = {
364 .halt_reg = 0x01e8,
365 .halt_bit = 10,
366 .clkr = {
367 .enable_reg = 0x0024,
368 .enable_mask = BIT(8),
369 .hw.init = &(struct clk_init_data){
370 .parent_names = (const char *[]){ "csi1_src" },
371 .num_parents = 1,
372 .name = "csi1_phy_clk",
373 .ops = &clk_branch_ops,
374 .flags = CLK_SET_RATE_PARENT,
375 },
376 },
377};
378
379static struct clk_rcg csi2_src = {
380 .ns_reg = 0x0234,
381 .md_reg = 0x022c,
382 .mn = {
383 .mnctr_en_bit = 5,
384 .mnctr_reset_bit = 7,
385 .mnctr_mode_shift = 6,
386 .n_val_shift = 24,
387 .m_val_shift = 8,
388 .width = 8,
389 },
390 .p = {
391 .pre_div_shift = 14,
392 .pre_div_width = 2,
393 },
394 .s = {
395 .src_sel_shift = 0,
396 .parent_map = mmcc_pxo_pll8_pll2_map,
397 },
398 .freq_tbl = clk_tbl_csi,
399 .clkr = {
400 .enable_reg = 0x022c,
401 .enable_mask = BIT(2),
402 .hw.init = &(struct clk_init_data){
403 .name = "csi2_src",
404 .parent_names = mmcc_pxo_pll8_pll2,
405 .num_parents = 3,
406 .ops = &clk_rcg_ops,
407 },
408 },
409};
410
411static struct clk_branch csi2_clk = {
412 .halt_reg = 0x01cc,
413 .halt_bit = 29,
414 .clkr = {
415 .enable_reg = 0x022c,
416 .enable_mask = BIT(0),
417 .hw.init = &(struct clk_init_data){
418 .parent_names = (const char *[]){ "csi2_src" },
419 .num_parents = 1,
420 .name = "csi2_clk",
421 .ops = &clk_branch_ops,
422 .flags = CLK_SET_RATE_PARENT,
423 },
424 },
425};
426
427static struct clk_branch csi2_phy_clk = {
428 .halt_reg = 0x01e8,
429 .halt_bit = 29,
430 .clkr = {
431 .enable_reg = 0x022c,
432 .enable_mask = BIT(8),
433 .hw.init = &(struct clk_init_data){
434 .parent_names = (const char *[]){ "csi2_src" },
435 .num_parents = 1,
436 .name = "csi2_phy_clk",
437 .ops = &clk_branch_ops,
438 .flags = CLK_SET_RATE_PARENT,
439 },
440 },
441};
442
443struct clk_pix_rdi {
444 u32 s_reg;
445 u32 s_mask;
446 u32 s2_reg;
447 u32 s2_mask;
448 struct clk_regmap clkr;
449};
450
451#define to_clk_pix_rdi(_hw) \
452 container_of(to_clk_regmap(_hw), struct clk_pix_rdi, clkr)
453
454static int pix_rdi_set_parent(struct clk_hw *hw, u8 index)
455{
456 int i;
457 int ret = 0;
458 u32 val;
459 struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
460 struct clk *clk = hw->clk;
461 int num_parents = __clk_get_num_parents(hw->clk);
462
463 /*
464 * These clocks select three inputs via two muxes. One mux selects
465 * between csi0 and csi1 and the second mux selects between that mux's
466 * output and csi2. The source and destination selections for each
467 * mux must be clocking for the switch to succeed so just turn on
468 * all three sources because it's easier than figuring out what source
469 * needs to be on at what time.
470 */
471 for (i = 0; i < num_parents; i++) {
472 ret = clk_prepare_enable(clk_get_parent_by_index(clk, i));
473 if (ret)
474 goto err;
475 }
476
477 if (index == 2)
478 val = rdi->s2_mask;
479 else
480 val = 0;
481 regmap_update_bits(rdi->clkr.regmap, rdi->s2_reg, rdi->s2_mask, val);
482 /*
483 * Wait at least 6 cycles of slowest clock
484 * for the glitch-free MUX to fully switch sources.
485 */
486 udelay(1);
487
488 if (index == 1)
489 val = rdi->s_mask;
490 else
491 val = 0;
492 regmap_update_bits(rdi->clkr.regmap, rdi->s_reg, rdi->s_mask, val);
493 /*
494 * Wait at least 6 cycles of slowest clock
495 * for the glitch-free MUX to fully switch sources.
496 */
497 udelay(1);
498
499err:
500 for (i--; i >= 0; i--)
501 clk_disable_unprepare(clk_get_parent_by_index(clk, i));
502
503 return ret;
504}
505
506static u8 pix_rdi_get_parent(struct clk_hw *hw)
507{
508 u32 val;
509 struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
510
511
512 regmap_read(rdi->clkr.regmap, rdi->s2_reg, &val);
513 if (val & rdi->s2_mask)
514 return 2;
515
516 regmap_read(rdi->clkr.regmap, rdi->s_reg, &val);
517 if (val & rdi->s_mask)
518 return 1;
519
520 return 0;
521}
522
523static const struct clk_ops clk_ops_pix_rdi = {
524 .enable = clk_enable_regmap,
525 .disable = clk_disable_regmap,
526 .set_parent = pix_rdi_set_parent,
527 .get_parent = pix_rdi_get_parent,
528 .determine_rate = __clk_mux_determine_rate,
529};
530
531static const char *pix_rdi_parents[] = {
532 "csi0_clk",
533 "csi1_clk",
534 "csi2_clk",
535};
536
537static struct clk_pix_rdi csi_pix_clk = {
538 .s_reg = 0x0058,
539 .s_mask = BIT(25),
540 .s2_reg = 0x0238,
541 .s2_mask = BIT(13),
542 .clkr = {
543 .enable_reg = 0x0058,
544 .enable_mask = BIT(26),
545 .hw.init = &(struct clk_init_data){
546 .name = "csi_pix_clk",
547 .parent_names = pix_rdi_parents,
548 .num_parents = 3,
549 .ops = &clk_ops_pix_rdi,
550 },
551 },
552};
553
554static struct clk_pix_rdi csi_pix1_clk = {
555 .s_reg = 0x0238,
556 .s_mask = BIT(8),
557 .s2_reg = 0x0238,
558 .s2_mask = BIT(9),
559 .clkr = {
560 .enable_reg = 0x0238,
561 .enable_mask = BIT(10),
562 .hw.init = &(struct clk_init_data){
563 .name = "csi_pix1_clk",
564 .parent_names = pix_rdi_parents,
565 .num_parents = 3,
566 .ops = &clk_ops_pix_rdi,
567 },
568 },
569};
570
571static struct clk_pix_rdi csi_rdi_clk = {
572 .s_reg = 0x0058,
573 .s_mask = BIT(12),
574 .s2_reg = 0x0238,
575 .s2_mask = BIT(12),
576 .clkr = {
577 .enable_reg = 0x0058,
578 .enable_mask = BIT(13),
579 .hw.init = &(struct clk_init_data){
580 .name = "csi_rdi_clk",
581 .parent_names = pix_rdi_parents,
582 .num_parents = 3,
583 .ops = &clk_ops_pix_rdi,
584 },
585 },
586};
587
588static struct clk_pix_rdi csi_rdi1_clk = {
589 .s_reg = 0x0238,
590 .s_mask = BIT(0),
591 .s2_reg = 0x0238,
592 .s2_mask = BIT(1),
593 .clkr = {
594 .enable_reg = 0x0238,
595 .enable_mask = BIT(2),
596 .hw.init = &(struct clk_init_data){
597 .name = "csi_rdi1_clk",
598 .parent_names = pix_rdi_parents,
599 .num_parents = 3,
600 .ops = &clk_ops_pix_rdi,
601 },
602 },
603};
604
605static struct clk_pix_rdi csi_rdi2_clk = {
606 .s_reg = 0x0238,
607 .s_mask = BIT(4),
608 .s2_reg = 0x0238,
609 .s2_mask = BIT(5),
610 .clkr = {
611 .enable_reg = 0x0238,
612 .enable_mask = BIT(6),
613 .hw.init = &(struct clk_init_data){
614 .name = "csi_rdi2_clk",
615 .parent_names = pix_rdi_parents,
616 .num_parents = 3,
617 .ops = &clk_ops_pix_rdi,
618 },
619 },
620};
621
622static struct freq_tbl clk_tbl_csiphytimer[] = {
623 { 85330000, P_PLL8, 1, 2, 9 },
624 { 177780000, P_PLL2, 1, 2, 9 },
625 { }
626};
627
628static struct clk_rcg csiphytimer_src = {
629 .ns_reg = 0x0168,
630 .md_reg = 0x0164,
631 .mn = {
632 .mnctr_en_bit = 5,
633 .mnctr_reset_bit = 8,
634 .reset_in_cc = true,
635 .mnctr_mode_shift = 6,
636 .n_val_shift = 24,
637 .m_val_shift = 8,
638 .width = 8,
639 },
640 .p = {
641 .pre_div_shift = 14,
642 .pre_div_width = 2,
643 },
644 .s = {
645 .src_sel_shift = 0,
646 .parent_map = mmcc_pxo_pll8_pll2_map,
647 },
648 .freq_tbl = clk_tbl_csiphytimer,
649 .clkr = {
650 .enable_reg = 0x0160,
651 .enable_mask = BIT(2),
652 .hw.init = &(struct clk_init_data){
653 .name = "csiphytimer_src",
654 .parent_names = mmcc_pxo_pll8_pll2,
655 .num_parents = 3,
656 .ops = &clk_rcg_ops,
657 },
658 },
659};
660
661static const char *csixphy_timer_src[] = { "csiphytimer_src" };
662
663static struct clk_branch csiphy0_timer_clk = {
664 .halt_reg = 0x01e8,
665 .halt_bit = 17,
666 .clkr = {
667 .enable_reg = 0x0160,
668 .enable_mask = BIT(0),
669 .hw.init = &(struct clk_init_data){
670 .parent_names = csixphy_timer_src,
671 .num_parents = 1,
672 .name = "csiphy0_timer_clk",
673 .ops = &clk_branch_ops,
674 .flags = CLK_SET_RATE_PARENT,
675 },
676 },
677};
678
679static struct clk_branch csiphy1_timer_clk = {
680 .halt_reg = 0x01e8,
681 .halt_bit = 18,
682 .clkr = {
683 .enable_reg = 0x0160,
684 .enable_mask = BIT(9),
685 .hw.init = &(struct clk_init_data){
686 .parent_names = csixphy_timer_src,
687 .num_parents = 1,
688 .name = "csiphy1_timer_clk",
689 .ops = &clk_branch_ops,
690 .flags = CLK_SET_RATE_PARENT,
691 },
692 },
693};
694
695static struct clk_branch csiphy2_timer_clk = {
696 .halt_reg = 0x01e8,
697 .halt_bit = 30,
698 .clkr = {
699 .enable_reg = 0x0160,
700 .enable_mask = BIT(11),
701 .hw.init = &(struct clk_init_data){
702 .parent_names = csixphy_timer_src,
703 .num_parents = 1,
704 .name = "csiphy2_timer_clk",
705 .ops = &clk_branch_ops,
706 .flags = CLK_SET_RATE_PARENT,
707 },
708 },
709};
710
711static struct freq_tbl clk_tbl_gfx2d[] = {
712 { 27000000, P_PXO, 1, 0 },
713 { 48000000, P_PLL8, 1, 8 },
714 { 54857000, P_PLL8, 1, 7 },
715 { 64000000, P_PLL8, 1, 6 },
716 { 76800000, P_PLL8, 1, 5 },
717 { 96000000, P_PLL8, 1, 4 },
718 { 128000000, P_PLL8, 1, 3 },
719 { 145455000, P_PLL2, 2, 11 },
720 { 160000000, P_PLL2, 1, 5 },
721 { 177778000, P_PLL2, 2, 9 },
722 { 200000000, P_PLL2, 1, 4 },
723 { 228571000, P_PLL2, 2, 7 },
724 { }
725};
726
727static struct clk_dyn_rcg gfx2d0_src = {
728 .ns_reg = 0x0070,
729 .md_reg[0] = 0x0064,
730 .md_reg[1] = 0x0068,
731 .mn[0] = {
732 .mnctr_en_bit = 8,
733 .mnctr_reset_bit = 25,
734 .mnctr_mode_shift = 9,
735 .n_val_shift = 20,
736 .m_val_shift = 4,
737 .width = 4,
738 },
739 .mn[1] = {
740 .mnctr_en_bit = 5,
741 .mnctr_reset_bit = 24,
742 .mnctr_mode_shift = 6,
743 .n_val_shift = 16,
744 .m_val_shift = 4,
745 .width = 4,
746 },
747 .s[0] = {
748 .src_sel_shift = 3,
749 .parent_map = mmcc_pxo_pll8_pll2_map,
750 },
751 .s[1] = {
752 .src_sel_shift = 0,
753 .parent_map = mmcc_pxo_pll8_pll2_map,
754 },
755 .mux_sel_bit = 11,
756 .freq_tbl = clk_tbl_gfx2d,
757 .clkr = {
758 .enable_reg = 0x0060,
759 .enable_mask = BIT(2),
760 .hw.init = &(struct clk_init_data){
761 .name = "gfx2d0_src",
762 .parent_names = mmcc_pxo_pll8_pll2,
763 .num_parents = 3,
764 .ops = &clk_dyn_rcg_ops,
765 },
766 },
767};
768
769static struct clk_branch gfx2d0_clk = {
770 .halt_reg = 0x01c8,
771 .halt_bit = 9,
772 .clkr = {
773 .enable_reg = 0x0060,
774 .enable_mask = BIT(0),
775 .hw.init = &(struct clk_init_data){
776 .name = "gfx2d0_clk",
777 .parent_names = (const char *[]){ "gfx2d0_src" },
778 .num_parents = 1,
779 .ops = &clk_branch_ops,
780 .flags = CLK_SET_RATE_PARENT,
781 },
782 },
783};
784
785static struct clk_dyn_rcg gfx2d1_src = {
786 .ns_reg = 0x007c,
787 .md_reg[0] = 0x0078,
788 .md_reg[1] = 0x006c,
789 .mn[0] = {
790 .mnctr_en_bit = 8,
791 .mnctr_reset_bit = 25,
792 .mnctr_mode_shift = 9,
793 .n_val_shift = 20,
794 .m_val_shift = 4,
795 .width = 4,
796 },
797 .mn[1] = {
798 .mnctr_en_bit = 5,
799 .mnctr_reset_bit = 24,
800 .mnctr_mode_shift = 6,
801 .n_val_shift = 16,
802 .m_val_shift = 4,
803 .width = 4,
804 },
805 .s[0] = {
806 .src_sel_shift = 3,
807 .parent_map = mmcc_pxo_pll8_pll2_map,
808 },
809 .s[1] = {
810 .src_sel_shift = 0,
811 .parent_map = mmcc_pxo_pll8_pll2_map,
812 },
813 .mux_sel_bit = 11,
814 .freq_tbl = clk_tbl_gfx2d,
815 .clkr = {
816 .enable_reg = 0x0074,
817 .enable_mask = BIT(2),
818 .hw.init = &(struct clk_init_data){
819 .name = "gfx2d1_src",
820 .parent_names = mmcc_pxo_pll8_pll2,
821 .num_parents = 3,
822 .ops = &clk_dyn_rcg_ops,
823 },
824 },
825};
826
827static struct clk_branch gfx2d1_clk = {
828 .halt_reg = 0x01c8,
829 .halt_bit = 14,
830 .clkr = {
831 .enable_reg = 0x0074,
832 .enable_mask = BIT(0),
833 .hw.init = &(struct clk_init_data){
834 .name = "gfx2d1_clk",
835 .parent_names = (const char *[]){ "gfx2d1_src" },
836 .num_parents = 1,
837 .ops = &clk_branch_ops,
838 .flags = CLK_SET_RATE_PARENT,
839 },
840 },
841};
842
843static struct freq_tbl clk_tbl_gfx3d[] = {
844 { 27000000, P_PXO, 1, 0 },
845 { 48000000, P_PLL8, 1, 8 },
846 { 54857000, P_PLL8, 1, 7 },
847 { 64000000, P_PLL8, 1, 6 },
848 { 76800000, P_PLL8, 1, 5 },
849 { 96000000, P_PLL8, 1, 4 },
850 { 128000000, P_PLL8, 1, 3 },
851 { 145455000, P_PLL2, 2, 11 },
852 { 160000000, P_PLL2, 1, 5 },
853 { 177778000, P_PLL2, 2, 9 },
854 { 200000000, P_PLL2, 1, 4 },
855 { 228571000, P_PLL2, 2, 7 },
856 { 266667000, P_PLL2, 1, 3 },
857 { 300000000, P_PLL3, 1, 4 },
858 { 320000000, P_PLL2, 2, 5 },
859 { 400000000, P_PLL2, 1, 2 },
860 { }
861};
862
863static struct clk_dyn_rcg gfx3d_src = {
864 .ns_reg = 0x008c,
865 .md_reg[0] = 0x0084,
866 .md_reg[1] = 0x0088,
867 .mn[0] = {
868 .mnctr_en_bit = 8,
869 .mnctr_reset_bit = 25,
870 .mnctr_mode_shift = 9,
871 .n_val_shift = 18,
872 .m_val_shift = 4,
873 .width = 4,
874 },
875 .mn[1] = {
876 .mnctr_en_bit = 5,
877 .mnctr_reset_bit = 24,
878 .mnctr_mode_shift = 6,
879 .n_val_shift = 14,
880 .m_val_shift = 4,
881 .width = 4,
882 },
883 .s[0] = {
884 .src_sel_shift = 3,
885 .parent_map = mmcc_pxo_pll8_pll2_pll3_map,
886 },
887 .s[1] = {
888 .src_sel_shift = 0,
889 .parent_map = mmcc_pxo_pll8_pll2_pll3_map,
890 },
891 .mux_sel_bit = 11,
892 .freq_tbl = clk_tbl_gfx3d,
893 .clkr = {
894 .enable_reg = 0x0080,
895 .enable_mask = BIT(2),
896 .hw.init = &(struct clk_init_data){
897 .name = "gfx3d_src",
898 .parent_names = mmcc_pxo_pll8_pll2_pll3,
899 .num_parents = 3,
900 .ops = &clk_dyn_rcg_ops,
901 },
902 },
903};
904
905static struct clk_branch gfx3d_clk = {
906 .halt_reg = 0x01c8,
907 .halt_bit = 4,
908 .clkr = {
909 .enable_reg = 0x0080,
910 .enable_mask = BIT(0),
911 .hw.init = &(struct clk_init_data){
912 .name = "gfx3d_clk",
913 .parent_names = (const char *[]){ "gfx3d_src" },
914 .num_parents = 1,
915 .ops = &clk_branch_ops,
916 .flags = CLK_SET_RATE_PARENT,
917 },
918 },
919};
920
921static struct freq_tbl clk_tbl_ijpeg[] = {
922 { 27000000, P_PXO, 1, 0, 0 },
923 { 36570000, P_PLL8, 1, 2, 21 },
924 { 54860000, P_PLL8, 7, 0, 0 },
925 { 96000000, P_PLL8, 4, 0, 0 },
926 { 109710000, P_PLL8, 1, 2, 7 },
927 { 128000000, P_PLL8, 3, 0, 0 },
928 { 153600000, P_PLL8, 1, 2, 5 },
929 { 200000000, P_PLL2, 4, 0, 0 },
930 { 228571000, P_PLL2, 1, 2, 7 },
931 { 266667000, P_PLL2, 1, 1, 3 },
932 { 320000000, P_PLL2, 1, 2, 5 },
933 { }
934};
935
936static struct clk_rcg ijpeg_src = {
937 .ns_reg = 0x00a0,
938 .md_reg = 0x009c,
939 .mn = {
940 .mnctr_en_bit = 5,
941 .mnctr_reset_bit = 7,
942 .mnctr_mode_shift = 6,
943 .n_val_shift = 16,
944 .m_val_shift = 8,
945 .width = 8,
946 },
947 .p = {
948 .pre_div_shift = 12,
949 .pre_div_width = 2,
950 },
951 .s = {
952 .src_sel_shift = 0,
953 .parent_map = mmcc_pxo_pll8_pll2_map,
954 },
955 .freq_tbl = clk_tbl_ijpeg,
956 .clkr = {
957 .enable_reg = 0x0098,
958 .enable_mask = BIT(2),
959 .hw.init = &(struct clk_init_data){
960 .name = "ijpeg_src",
961 .parent_names = mmcc_pxo_pll8_pll2,
962 .num_parents = 3,
963 .ops = &clk_rcg_ops,
964 },
965 },
966};
967
968static struct clk_branch ijpeg_clk = {
969 .halt_reg = 0x01c8,
970 .halt_bit = 24,
971 .clkr = {
972 .enable_reg = 0x0098,
973 .enable_mask = BIT(0),
974 .hw.init = &(struct clk_init_data){
975 .name = "ijpeg_clk",
976 .parent_names = (const char *[]){ "ijpeg_src" },
977 .num_parents = 1,
978 .ops = &clk_branch_ops,
979 .flags = CLK_SET_RATE_PARENT,
980 },
981 },
982};
983
984static struct freq_tbl clk_tbl_jpegd[] = {
985 { 64000000, P_PLL8, 6 },
986 { 76800000, P_PLL8, 5 },
987 { 96000000, P_PLL8, 4 },
988 { 160000000, P_PLL2, 5 },
989 { 200000000, P_PLL2, 4 },
990 { }
991};
992
993static struct clk_rcg jpegd_src = {
994 .ns_reg = 0x00ac,
995 .p = {
996 .pre_div_shift = 12,
997 .pre_div_width = 2,
998 },
999 .s = {
1000 .src_sel_shift = 0,
1001 .parent_map = mmcc_pxo_pll8_pll2_map,
1002 },
1003 .freq_tbl = clk_tbl_jpegd,
1004 .clkr = {
1005 .enable_reg = 0x00a4,
1006 .enable_mask = BIT(2),
1007 .hw.init = &(struct clk_init_data){
1008 .name = "jpegd_src",
1009 .parent_names = mmcc_pxo_pll8_pll2,
1010 .num_parents = 3,
1011 .ops = &clk_rcg_ops,
1012 },
1013 },
1014};
1015
1016static struct clk_branch jpegd_clk = {
1017 .halt_reg = 0x01c8,
1018 .halt_bit = 19,
1019 .clkr = {
1020 .enable_reg = 0x00a4,
1021 .enable_mask = BIT(0),
1022 .hw.init = &(struct clk_init_data){
1023 .name = "jpegd_clk",
1024 .parent_names = (const char *[]){ "jpegd_src" },
1025 .num_parents = 1,
1026 .ops = &clk_branch_ops,
1027 .flags = CLK_SET_RATE_PARENT,
1028 },
1029 },
1030};
1031
1032static struct freq_tbl clk_tbl_mdp[] = {
1033 { 9600000, P_PLL8, 1, 1, 40 },
1034 { 13710000, P_PLL8, 1, 1, 28 },
1035 { 27000000, P_PXO, 1, 0, 0 },
1036 { 29540000, P_PLL8, 1, 1, 13 },
1037 { 34910000, P_PLL8, 1, 1, 11 },
1038 { 38400000, P_PLL8, 1, 1, 10 },
1039 { 59080000, P_PLL8, 1, 2, 13 },
1040 { 76800000, P_PLL8, 1, 1, 5 },
1041 { 85330000, P_PLL8, 1, 2, 9 },
1042 { 96000000, P_PLL8, 1, 1, 4 },
1043 { 128000000, P_PLL8, 1, 1, 3 },
1044 { 160000000, P_PLL2, 1, 1, 5 },
1045 { 177780000, P_PLL2, 1, 2, 9 },
1046 { 200000000, P_PLL2, 1, 1, 4 },
1047 { 228571000, P_PLL2, 1, 2, 7 },
1048 { 266667000, P_PLL2, 1, 1, 3 },
1049 { }
1050};
1051
1052static struct clk_dyn_rcg mdp_src = {
1053 .ns_reg = 0x00d0,
1054 .md_reg[0] = 0x00c4,
1055 .md_reg[1] = 0x00c8,
1056 .mn[0] = {
1057 .mnctr_en_bit = 8,
1058 .mnctr_reset_bit = 31,
1059 .mnctr_mode_shift = 9,
1060 .n_val_shift = 22,
1061 .m_val_shift = 8,
1062 .width = 8,
1063 },
1064 .mn[1] = {
1065 .mnctr_en_bit = 5,
1066 .mnctr_reset_bit = 30,
1067 .mnctr_mode_shift = 6,
1068 .n_val_shift = 14,
1069 .m_val_shift = 8,
1070 .width = 8,
1071 },
1072 .s[0] = {
1073 .src_sel_shift = 3,
1074 .parent_map = mmcc_pxo_pll8_pll2_map,
1075 },
1076 .s[1] = {
1077 .src_sel_shift = 0,
1078 .parent_map = mmcc_pxo_pll8_pll2_map,
1079 },
1080 .mux_sel_bit = 11,
1081 .freq_tbl = clk_tbl_mdp,
1082 .clkr = {
1083 .enable_reg = 0x00c0,
1084 .enable_mask = BIT(2),
1085 .hw.init = &(struct clk_init_data){
1086 .name = "mdp_src",
1087 .parent_names = mmcc_pxo_pll8_pll2,
1088 .num_parents = 3,
1089 .ops = &clk_dyn_rcg_ops,
1090 },
1091 },
1092};
1093
1094static struct clk_branch mdp_clk = {
1095 .halt_reg = 0x01d0,
1096 .halt_bit = 10,
1097 .clkr = {
1098 .enable_reg = 0x00c0,
1099 .enable_mask = BIT(0),
1100 .hw.init = &(struct clk_init_data){
1101 .name = "mdp_clk",
1102 .parent_names = (const char *[]){ "mdp_src" },
1103 .num_parents = 1,
1104 .ops = &clk_branch_ops,
1105 .flags = CLK_SET_RATE_PARENT,
1106 },
1107 },
1108};
1109
1110static struct clk_branch mdp_lut_clk = {
1111 .halt_reg = 0x01e8,
1112 .halt_bit = 13,
1113 .clkr = {
1114 .enable_reg = 0x016c,
1115 .enable_mask = BIT(0),
1116 .hw.init = &(struct clk_init_data){
1117 .parent_names = (const char *[]){ "mdp_clk" },
1118 .num_parents = 1,
1119 .name = "mdp_lut_clk",
1120 .ops = &clk_branch_ops,
1121 .flags = CLK_SET_RATE_PARENT,
1122 },
1123 },
1124};
1125
1126static struct clk_branch mdp_vsync_clk = {
1127 .halt_reg = 0x01cc,
1128 .halt_bit = 22,
1129 .clkr = {
1130 .enable_reg = 0x0058,
1131 .enable_mask = BIT(6),
1132 .hw.init = &(struct clk_init_data){
1133 .name = "mdp_vsync_clk",
1134 .parent_names = (const char *[]){ "pxo" },
1135 .num_parents = 1,
1136 .ops = &clk_branch_ops
1137 },
1138 },
1139};
1140
1141static struct freq_tbl clk_tbl_rot[] = {
1142 { 27000000, P_PXO, 1 },
1143 { 29540000, P_PLL8, 13 },
1144 { 32000000, P_PLL8, 12 },
1145 { 38400000, P_PLL8, 10 },
1146 { 48000000, P_PLL8, 8 },
1147 { 54860000, P_PLL8, 7 },
1148 { 64000000, P_PLL8, 6 },
1149 { 76800000, P_PLL8, 5 },
1150 { 96000000, P_PLL8, 4 },
1151 { 100000000, P_PLL2, 8 },
1152 { 114290000, P_PLL2, 7 },
1153 { 133330000, P_PLL2, 6 },
1154 { 160000000, P_PLL2, 5 },
1155 { 200000000, P_PLL2, 4 },
1156 { }
1157};
1158
1159static struct clk_dyn_rcg rot_src = {
1160 .ns_reg = 0x00e8,
1161 .p[0] = {
1162 .pre_div_shift = 22,
1163 .pre_div_width = 4,
1164 },
1165 .p[1] = {
1166 .pre_div_shift = 26,
1167 .pre_div_width = 4,
1168 },
1169 .s[0] = {
1170 .src_sel_shift = 16,
1171 .parent_map = mmcc_pxo_pll8_pll2_map,
1172 },
1173 .s[1] = {
1174 .src_sel_shift = 19,
1175 .parent_map = mmcc_pxo_pll8_pll2_map,
1176 },
1177 .mux_sel_bit = 30,
1178 .freq_tbl = clk_tbl_rot,
1179 .clkr = {
1180 .enable_reg = 0x00e0,
1181 .enable_mask = BIT(2),
1182 .hw.init = &(struct clk_init_data){
1183 .name = "rot_src",
1184 .parent_names = mmcc_pxo_pll8_pll2,
1185 .num_parents = 3,
1186 .ops = &clk_dyn_rcg_ops,
1187 },
1188 },
1189};
1190
1191static struct clk_branch rot_clk = {
1192 .halt_reg = 0x01d0,
1193 .halt_bit = 15,
1194 .clkr = {
1195 .enable_reg = 0x00e0,
1196 .enable_mask = BIT(0),
1197 .hw.init = &(struct clk_init_data){
1198 .name = "rot_clk",
1199 .parent_names = (const char *[]){ "rot_src" },
1200 .num_parents = 1,
1201 .ops = &clk_branch_ops,
1202 .flags = CLK_SET_RATE_PARENT,
1203 },
1204 },
1205};
1206
1207#define P_HDMI_PLL 1
1208
1209static u8 mmcc_pxo_hdmi_map[] = {
1210 [P_PXO] = 0,
1211 [P_HDMI_PLL] = 2,
1212};
1213
1214static const char *mmcc_pxo_hdmi[] = {
1215 "pxo",
1216 "hdmi_pll",
1217};
1218
1219static struct freq_tbl clk_tbl_tv[] = {
1220 { 25200000, P_HDMI_PLL, 1, 0, 0 },
1221 { 27000000, P_HDMI_PLL, 1, 0, 0 },
1222 { 27030000, P_HDMI_PLL, 1, 0, 0 },
1223 { 74250000, P_HDMI_PLL, 1, 0, 0 },
1224 { 108000000, P_HDMI_PLL, 1, 0, 0 },
1225 { 148500000, P_HDMI_PLL, 1, 0, 0 },
1226 { }
1227};
1228
1229static struct clk_rcg tv_src = {
1230 .ns_reg = 0x00f4,
1231 .md_reg = 0x00f0,
1232 .mn = {
1233 .mnctr_en_bit = 5,
1234 .mnctr_reset_bit = 7,
1235 .mnctr_mode_shift = 6,
1236 .n_val_shift = 16,
1237 .m_val_shift = 8,
1238 .width = 8,
1239 },
1240 .p = {
1241 .pre_div_shift = 14,
1242 .pre_div_width = 2,
1243 },
1244 .s = {
1245 .src_sel_shift = 0,
1246 .parent_map = mmcc_pxo_hdmi_map,
1247 },
1248 .freq_tbl = clk_tbl_tv,
1249 .clkr = {
1250 .enable_reg = 0x00ec,
1251 .enable_mask = BIT(2),
1252 .hw.init = &(struct clk_init_data){
1253 .name = "tv_src",
1254 .parent_names = mmcc_pxo_hdmi,
1255 .num_parents = 2,
1256 .ops = &clk_rcg_ops,
1257 .flags = CLK_SET_RATE_PARENT,
1258 },
1259 },
1260};
1261
1262static const char *tv_src_name[] = { "tv_src" };
1263
1264static struct clk_branch tv_enc_clk = {
1265 .halt_reg = 0x01d4,
1266 .halt_bit = 9,
1267 .clkr = {
1268 .enable_reg = 0x00ec,
1269 .enable_mask = BIT(8),
1270 .hw.init = &(struct clk_init_data){
1271 .parent_names = tv_src_name,
1272 .num_parents = 1,
1273 .name = "tv_enc_clk",
1274 .ops = &clk_branch_ops,
1275 .flags = CLK_SET_RATE_PARENT,
1276 },
1277 },
1278};
1279
1280static struct clk_branch tv_dac_clk = {
1281 .halt_reg = 0x01d4,
1282 .halt_bit = 10,
1283 .clkr = {
1284 .enable_reg = 0x00ec,
1285 .enable_mask = BIT(10),
1286 .hw.init = &(struct clk_init_data){
1287 .parent_names = tv_src_name,
1288 .num_parents = 1,
1289 .name = "tv_dac_clk",
1290 .ops = &clk_branch_ops,
1291 .flags = CLK_SET_RATE_PARENT,
1292 },
1293 },
1294};
1295
1296static struct clk_branch mdp_tv_clk = {
1297 .halt_reg = 0x01d4,
1298 .halt_bit = 12,
1299 .clkr = {
1300 .enable_reg = 0x00ec,
1301 .enable_mask = BIT(0),
1302 .hw.init = &(struct clk_init_data){
1303 .parent_names = tv_src_name,
1304 .num_parents = 1,
1305 .name = "mdp_tv_clk",
1306 .ops = &clk_branch_ops,
1307 .flags = CLK_SET_RATE_PARENT,
1308 },
1309 },
1310};
1311
1312static struct clk_branch hdmi_tv_clk = {
1313 .halt_reg = 0x01d4,
1314 .halt_bit = 11,
1315 .clkr = {
1316 .enable_reg = 0x00ec,
1317 .enable_mask = BIT(12),
1318 .hw.init = &(struct clk_init_data){
1319 .parent_names = tv_src_name,
1320 .num_parents = 1,
1321 .name = "hdmi_tv_clk",
1322 .ops = &clk_branch_ops,
1323 .flags = CLK_SET_RATE_PARENT,
1324 },
1325 },
1326};
1327
1328static struct clk_branch hdmi_app_clk = {
1329 .halt_reg = 0x01cc,
1330 .halt_bit = 25,
1331 .clkr = {
1332 .enable_reg = 0x005c,
1333 .enable_mask = BIT(11),
1334 .hw.init = &(struct clk_init_data){
1335 .parent_names = (const char *[]){ "pxo" },
1336 .num_parents = 1,
1337 .name = "hdmi_app_clk",
1338 .ops = &clk_branch_ops,
1339 },
1340 },
1341};
1342
1343static struct freq_tbl clk_tbl_vcodec[] = {
1344 { 27000000, P_PXO, 1, 0 },
1345 { 32000000, P_PLL8, 1, 12 },
1346 { 48000000, P_PLL8, 1, 8 },
1347 { 54860000, P_PLL8, 1, 7 },
1348 { 96000000, P_PLL8, 1, 4 },
1349 { 133330000, P_PLL2, 1, 6 },
1350 { 200000000, P_PLL2, 1, 4 },
1351 { 228570000, P_PLL2, 2, 7 },
1352 { 266670000, P_PLL2, 1, 3 },
1353 { }
1354};
1355
1356static struct clk_dyn_rcg vcodec_src = {
1357 .ns_reg = 0x0100,
1358 .md_reg[0] = 0x00fc,
1359 .md_reg[1] = 0x0128,
1360 .mn[0] = {
1361 .mnctr_en_bit = 5,
1362 .mnctr_reset_bit = 31,
1363 .mnctr_mode_shift = 6,
1364 .n_val_shift = 11,
1365 .m_val_shift = 8,
1366 .width = 8,
1367 },
1368 .mn[1] = {
1369 .mnctr_en_bit = 10,
1370 .mnctr_reset_bit = 30,
1371 .mnctr_mode_shift = 11,
1372 .n_val_shift = 19,
1373 .m_val_shift = 8,
1374 .width = 8,
1375 },
1376 .s[0] = {
1377 .src_sel_shift = 27,
1378 .parent_map = mmcc_pxo_pll8_pll2_map,
1379 },
1380 .s[1] = {
1381 .src_sel_shift = 0,
1382 .parent_map = mmcc_pxo_pll8_pll2_map,
1383 },
1384 .mux_sel_bit = 13,
1385 .freq_tbl = clk_tbl_vcodec,
1386 .clkr = {
1387 .enable_reg = 0x00f8,
1388 .enable_mask = BIT(2),
1389 .hw.init = &(struct clk_init_data){
1390 .name = "vcodec_src",
1391 .parent_names = mmcc_pxo_pll8_pll2,
1392 .num_parents = 3,
1393 .ops = &clk_dyn_rcg_ops,
1394 },
1395 },
1396};
1397
1398static struct clk_branch vcodec_clk = {
1399 .halt_reg = 0x01d0,
1400 .halt_bit = 29,
1401 .clkr = {
1402 .enable_reg = 0x00f8,
1403 .enable_mask = BIT(0),
1404 .hw.init = &(struct clk_init_data){
1405 .name = "vcodec_clk",
1406 .parent_names = (const char *[]){ "vcodec_src" },
1407 .num_parents = 1,
1408 .ops = &clk_branch_ops,
1409 .flags = CLK_SET_RATE_PARENT,
1410 },
1411 },
1412};
1413
1414static struct freq_tbl clk_tbl_vpe[] = {
1415 { 27000000, P_PXO, 1 },
1416 { 34909000, P_PLL8, 11 },
1417 { 38400000, P_PLL8, 10 },
1418 { 64000000, P_PLL8, 6 },
1419 { 76800000, P_PLL8, 5 },
1420 { 96000000, P_PLL8, 4 },
1421 { 100000000, P_PLL2, 8 },
1422 { 160000000, P_PLL2, 5 },
1423 { }
1424};
1425
1426static struct clk_rcg vpe_src = {
1427 .ns_reg = 0x0118,
1428 .p = {
1429 .pre_div_shift = 12,
1430 .pre_div_width = 4,
1431 },
1432 .s = {
1433 .src_sel_shift = 0,
1434 .parent_map = mmcc_pxo_pll8_pll2_map,
1435 },
1436 .freq_tbl = clk_tbl_vpe,
1437 .clkr = {
1438 .enable_reg = 0x0110,
1439 .enable_mask = BIT(2),
1440 .hw.init = &(struct clk_init_data){
1441 .name = "vpe_src",
1442 .parent_names = mmcc_pxo_pll8_pll2,
1443 .num_parents = 3,
1444 .ops = &clk_rcg_ops,
1445 },
1446 },
1447};
1448
1449static struct clk_branch vpe_clk = {
1450 .halt_reg = 0x01c8,
1451 .halt_bit = 28,
1452 .clkr = {
1453 .enable_reg = 0x0110,
1454 .enable_mask = BIT(0),
1455 .hw.init = &(struct clk_init_data){
1456 .name = "vpe_clk",
1457 .parent_names = (const char *[]){ "vpe_src" },
1458 .num_parents = 1,
1459 .ops = &clk_branch_ops,
1460 .flags = CLK_SET_RATE_PARENT,
1461 },
1462 },
1463};
1464
1465static struct freq_tbl clk_tbl_vfe[] = {
1466 { 13960000, P_PLL8, 1, 2, 55 },
1467 { 27000000, P_PXO, 1, 0, 0 },
1468 { 36570000, P_PLL8, 1, 2, 21 },
1469 { 38400000, P_PLL8, 2, 1, 5 },
1470 { 45180000, P_PLL8, 1, 2, 17 },
1471 { 48000000, P_PLL8, 2, 1, 4 },
1472 { 54860000, P_PLL8, 1, 1, 7 },
1473 { 64000000, P_PLL8, 2, 1, 3 },
1474 { 76800000, P_PLL8, 1, 1, 5 },
1475 { 96000000, P_PLL8, 2, 1, 2 },
1476 { 109710000, P_PLL8, 1, 2, 7 },
1477 { 128000000, P_PLL8, 1, 1, 3 },
1478 { 153600000, P_PLL8, 1, 2, 5 },
1479 { 200000000, P_PLL2, 2, 1, 2 },
1480 { 228570000, P_PLL2, 1, 2, 7 },
1481 { 266667000, P_PLL2, 1, 1, 3 },
1482 { 320000000, P_PLL2, 1, 2, 5 },
1483 { }
1484};
1485
1486static struct clk_rcg vfe_src = {
1487 .ns_reg = 0x0108,
1488 .mn = {
1489 .mnctr_en_bit = 5,
1490 .mnctr_reset_bit = 7,
1491 .mnctr_mode_shift = 6,
1492 .n_val_shift = 16,
1493 .m_val_shift = 8,
1494 .width = 8,
1495 },
1496 .p = {
1497 .pre_div_shift = 10,
1498 .pre_div_width = 1,
1499 },
1500 .s = {
1501 .src_sel_shift = 0,
1502 .parent_map = mmcc_pxo_pll8_pll2_map,
1503 },
1504 .freq_tbl = clk_tbl_vfe,
1505 .clkr = {
1506 .enable_reg = 0x0104,
1507 .enable_mask = BIT(2),
1508 .hw.init = &(struct clk_init_data){
1509 .name = "vfe_src",
1510 .parent_names = mmcc_pxo_pll8_pll2,
1511 .num_parents = 3,
1512 .ops = &clk_rcg_ops,
1513 },
1514 },
1515};
1516
1517static struct clk_branch vfe_clk = {
1518 .halt_reg = 0x01cc,
1519 .halt_bit = 6,
1520 .clkr = {
1521 .enable_reg = 0x0104,
1522 .enable_mask = BIT(0),
1523 .hw.init = &(struct clk_init_data){
1524 .name = "vfe_clk",
1525 .parent_names = (const char *[]){ "vfe_src" },
1526 .num_parents = 1,
1527 .ops = &clk_branch_ops,
1528 .flags = CLK_SET_RATE_PARENT,
1529 },
1530 },
1531};
1532
1533static struct clk_branch vfe_csi_clk = {
1534 .halt_reg = 0x01cc,
1535 .halt_bit = 8,
1536 .clkr = {
1537 .enable_reg = 0x0104,
1538 .enable_mask = BIT(12),
1539 .hw.init = &(struct clk_init_data){
1540 .parent_names = (const char *[]){ "vfe_src" },
1541 .num_parents = 1,
1542 .name = "vfe_csi_clk",
1543 .ops = &clk_branch_ops,
1544 .flags = CLK_SET_RATE_PARENT,
1545 },
1546 },
1547};
1548
1549static struct clk_branch gmem_axi_clk = {
1550 .halt_reg = 0x01d8,
1551 .halt_bit = 6,
1552 .clkr = {
1553 .enable_reg = 0x0018,
1554 .enable_mask = BIT(24),
1555 .hw.init = &(struct clk_init_data){
1556 .name = "gmem_axi_clk",
1557 .ops = &clk_branch_ops,
1558 .flags = CLK_IS_ROOT,
1559 },
1560 },
1561};
1562
1563static struct clk_branch ijpeg_axi_clk = {
1564 .hwcg_reg = 0x0018,
1565 .hwcg_bit = 11,
1566 .halt_reg = 0x01d8,
1567 .halt_bit = 4,
1568 .clkr = {
1569 .enable_reg = 0x0018,
1570 .enable_mask = BIT(21),
1571 .hw.init = &(struct clk_init_data){
1572 .name = "ijpeg_axi_clk",
1573 .ops = &clk_branch_ops,
1574 .flags = CLK_IS_ROOT,
1575 },
1576 },
1577};
1578
1579static struct clk_branch mmss_imem_axi_clk = {
1580 .hwcg_reg = 0x0018,
1581 .hwcg_bit = 15,
1582 .halt_reg = 0x01d8,
1583 .halt_bit = 7,
1584 .clkr = {
1585 .enable_reg = 0x0018,
1586 .enable_mask = BIT(22),
1587 .hw.init = &(struct clk_init_data){
1588 .name = "mmss_imem_axi_clk",
1589 .ops = &clk_branch_ops,
1590 .flags = CLK_IS_ROOT,
1591 },
1592 },
1593};
1594
1595static struct clk_branch jpegd_axi_clk = {
1596 .halt_reg = 0x01d8,
1597 .halt_bit = 5,
1598 .clkr = {
1599 .enable_reg = 0x0018,
1600 .enable_mask = BIT(25),
1601 .hw.init = &(struct clk_init_data){
1602 .name = "jpegd_axi_clk",
1603 .ops = &clk_branch_ops,
1604 .flags = CLK_IS_ROOT,
1605 },
1606 },
1607};
1608
1609static struct clk_branch vcodec_axi_b_clk = {
1610 .hwcg_reg = 0x0114,
1611 .hwcg_bit = 22,
1612 .halt_reg = 0x01e8,
1613 .halt_bit = 25,
1614 .clkr = {
1615 .enable_reg = 0x0114,
1616 .enable_mask = BIT(23),
1617 .hw.init = &(struct clk_init_data){
1618 .name = "vcodec_axi_b_clk",
1619 .ops = &clk_branch_ops,
1620 .flags = CLK_IS_ROOT,
1621 },
1622 },
1623};
1624
1625static struct clk_branch vcodec_axi_a_clk = {
1626 .hwcg_reg = 0x0114,
1627 .hwcg_bit = 24,
1628 .halt_reg = 0x01e8,
1629 .halt_bit = 26,
1630 .clkr = {
1631 .enable_reg = 0x0114,
1632 .enable_mask = BIT(25),
1633 .hw.init = &(struct clk_init_data){
1634 .name = "vcodec_axi_a_clk",
1635 .ops = &clk_branch_ops,
1636 .flags = CLK_IS_ROOT,
1637 },
1638 },
1639};
1640
1641static struct clk_branch vcodec_axi_clk = {
1642 .hwcg_reg = 0x0018,
1643 .hwcg_bit = 13,
1644 .halt_reg = 0x01d8,
1645 .halt_bit = 3,
1646 .clkr = {
1647 .enable_reg = 0x0018,
1648 .enable_mask = BIT(19),
1649 .hw.init = &(struct clk_init_data){
1650 .name = "vcodec_axi_clk",
1651 .ops = &clk_branch_ops,
1652 .flags = CLK_IS_ROOT,
1653 },
1654 },
1655};
1656
1657static struct clk_branch vfe_axi_clk = {
1658 .halt_reg = 0x01d8,
1659 .halt_bit = 0,
1660 .clkr = {
1661 .enable_reg = 0x0018,
1662 .enable_mask = BIT(18),
1663 .hw.init = &(struct clk_init_data){
1664 .name = "vfe_axi_clk",
1665 .ops = &clk_branch_ops,
1666 .flags = CLK_IS_ROOT,
1667 },
1668 },
1669};
1670
1671static struct clk_branch mdp_axi_clk = {
1672 .hwcg_reg = 0x0018,
1673 .hwcg_bit = 16,
1674 .halt_reg = 0x01d8,
1675 .halt_bit = 8,
1676 .clkr = {
1677 .enable_reg = 0x0018,
1678 .enable_mask = BIT(23),
1679 .hw.init = &(struct clk_init_data){
1680 .name = "mdp_axi_clk",
1681 .ops = &clk_branch_ops,
1682 .flags = CLK_IS_ROOT,
1683 },
1684 },
1685};
1686
1687static struct clk_branch rot_axi_clk = {
1688 .hwcg_reg = 0x0020,
1689 .hwcg_bit = 25,
1690 .halt_reg = 0x01d8,
1691 .halt_bit = 2,
1692 .clkr = {
1693 .enable_reg = 0x0020,
1694 .enable_mask = BIT(24),
1695 .hw.init = &(struct clk_init_data){
1696 .name = "rot_axi_clk",
1697 .ops = &clk_branch_ops,
1698 .flags = CLK_IS_ROOT,
1699 },
1700 },
1701};
1702
1703static struct clk_branch vpe_axi_clk = {
1704 .hwcg_reg = 0x0020,
1705 .hwcg_bit = 27,
1706 .halt_reg = 0x01d8,
1707 .halt_bit = 1,
1708 .clkr = {
1709 .enable_reg = 0x0020,
1710 .enable_mask = BIT(26),
1711 .hw.init = &(struct clk_init_data){
1712 .name = "vpe_axi_clk",
1713 .ops = &clk_branch_ops,
1714 .flags = CLK_IS_ROOT,
1715 },
1716 },
1717};
1718
1719static struct clk_branch gfx3d_axi_clk = {
1720 .hwcg_reg = 0x0244,
1721 .hwcg_bit = 24,
1722 .halt_reg = 0x0240,
1723 .halt_bit = 30,
1724 .clkr = {
1725 .enable_reg = 0x0244,
1726 .enable_mask = BIT(25),
1727 .hw.init = &(struct clk_init_data){
1728 .name = "gfx3d_axi_clk",
1729 .ops = &clk_branch_ops,
1730 .flags = CLK_IS_ROOT,
1731 },
1732 },
1733};
1734
1735static struct clk_branch amp_ahb_clk = {
1736 .halt_reg = 0x01dc,
1737 .halt_bit = 18,
1738 .clkr = {
1739 .enable_reg = 0x0008,
1740 .enable_mask = BIT(24),
1741 .hw.init = &(struct clk_init_data){
1742 .name = "amp_ahb_clk",
1743 .ops = &clk_branch_ops,
1744 .flags = CLK_IS_ROOT,
1745 },
1746 },
1747};
1748
1749static struct clk_branch csi_ahb_clk = {
1750 .halt_reg = 0x01dc,
1751 .halt_bit = 16,
1752 .clkr = {
1753 .enable_reg = 0x0008,
1754 .enable_mask = BIT(7),
1755 .hw.init = &(struct clk_init_data){
1756 .name = "csi_ahb_clk",
1757 .ops = &clk_branch_ops,
1758 .flags = CLK_IS_ROOT
1759 },
1760 },
1761};
1762
1763static struct clk_branch dsi_m_ahb_clk = {
1764 .halt_reg = 0x01dc,
1765 .halt_bit = 19,
1766 .clkr = {
1767 .enable_reg = 0x0008,
1768 .enable_mask = BIT(9),
1769 .hw.init = &(struct clk_init_data){
1770 .name = "dsi_m_ahb_clk",
1771 .ops = &clk_branch_ops,
1772 .flags = CLK_IS_ROOT,
1773 },
1774 },
1775};
1776
1777static struct clk_branch dsi_s_ahb_clk = {
1778 .hwcg_reg = 0x0038,
1779 .hwcg_bit = 20,
1780 .halt_reg = 0x01dc,
1781 .halt_bit = 21,
1782 .clkr = {
1783 .enable_reg = 0x0008,
1784 .enable_mask = BIT(18),
1785 .hw.init = &(struct clk_init_data){
1786 .name = "dsi_s_ahb_clk",
1787 .ops = &clk_branch_ops,
1788 .flags = CLK_IS_ROOT,
1789 },
1790 },
1791};
1792
1793static struct clk_branch dsi2_m_ahb_clk = {
1794 .halt_reg = 0x01d8,
1795 .halt_bit = 18,
1796 .clkr = {
1797 .enable_reg = 0x0008,
1798 .enable_mask = BIT(17),
1799 .hw.init = &(struct clk_init_data){
1800 .name = "dsi2_m_ahb_clk",
1801 .ops = &clk_branch_ops,
1802 .flags = CLK_IS_ROOT
1803 },
1804 },
1805};
1806
1807static struct clk_branch dsi2_s_ahb_clk = {
1808 .hwcg_reg = 0x0038,
1809 .hwcg_bit = 15,
1810 .halt_reg = 0x01dc,
1811 .halt_bit = 20,
1812 .clkr = {
1813 .enable_reg = 0x0008,
1814 .enable_mask = BIT(22),
1815 .hw.init = &(struct clk_init_data){
1816 .name = "dsi2_s_ahb_clk",
1817 .ops = &clk_branch_ops,
1818 .flags = CLK_IS_ROOT,
1819 },
1820 },
1821};
1822
1823static struct clk_branch gfx2d0_ahb_clk = {
1824 .hwcg_reg = 0x0038,
1825 .hwcg_bit = 28,
1826 .halt_reg = 0x01dc,
1827 .halt_bit = 2,
1828 .clkr = {
1829 .enable_reg = 0x0008,
1830 .enable_mask = BIT(19),
1831 .hw.init = &(struct clk_init_data){
1832 .name = "gfx2d0_ahb_clk",
1833 .ops = &clk_branch_ops,
1834 .flags = CLK_IS_ROOT,
1835 },
1836 },
1837};
1838
1839static struct clk_branch gfx2d1_ahb_clk = {
1840 .hwcg_reg = 0x0038,
1841 .hwcg_bit = 29,
1842 .halt_reg = 0x01dc,
1843 .halt_bit = 3,
1844 .clkr = {
1845 .enable_reg = 0x0008,
1846 .enable_mask = BIT(2),
1847 .hw.init = &(struct clk_init_data){
1848 .name = "gfx2d1_ahb_clk",
1849 .ops = &clk_branch_ops,
1850 .flags = CLK_IS_ROOT,
1851 },
1852 },
1853};
1854
1855static struct clk_branch gfx3d_ahb_clk = {
1856 .hwcg_reg = 0x0038,
1857 .hwcg_bit = 27,
1858 .halt_reg = 0x01dc,
1859 .halt_bit = 4,
1860 .clkr = {
1861 .enable_reg = 0x0008,
1862 .enable_mask = BIT(3),
1863 .hw.init = &(struct clk_init_data){
1864 .name = "gfx3d_ahb_clk",
1865 .ops = &clk_branch_ops,
1866 .flags = CLK_IS_ROOT,
1867 },
1868 },
1869};
1870
1871static struct clk_branch hdmi_m_ahb_clk = {
1872 .hwcg_reg = 0x0038,
1873 .hwcg_bit = 21,
1874 .halt_reg = 0x01dc,
1875 .halt_bit = 5,
1876 .clkr = {
1877 .enable_reg = 0x0008,
1878 .enable_mask = BIT(14),
1879 .hw.init = &(struct clk_init_data){
1880 .name = "hdmi_m_ahb_clk",
1881 .ops = &clk_branch_ops,
1882 .flags = CLK_IS_ROOT,
1883 },
1884 },
1885};
1886
1887static struct clk_branch hdmi_s_ahb_clk = {
1888 .hwcg_reg = 0x0038,
1889 .hwcg_bit = 22,
1890 .halt_reg = 0x01dc,
1891 .halt_bit = 6,
1892 .clkr = {
1893 .enable_reg = 0x0008,
1894 .enable_mask = BIT(4),
1895 .hw.init = &(struct clk_init_data){
1896 .name = "hdmi_s_ahb_clk",
1897 .ops = &clk_branch_ops,
1898 .flags = CLK_IS_ROOT,
1899 },
1900 },
1901};
1902
1903static struct clk_branch ijpeg_ahb_clk = {
1904 .halt_reg = 0x01dc,
1905 .halt_bit = 9,
1906 .clkr = {
1907 .enable_reg = 0x0008,
1908 .enable_mask = BIT(5),
1909 .hw.init = &(struct clk_init_data){
1910 .name = "ijpeg_ahb_clk",
1911 .ops = &clk_branch_ops,
1912 .flags = CLK_IS_ROOT
1913 },
1914 },
1915};
1916
1917static struct clk_branch mmss_imem_ahb_clk = {
1918 .hwcg_reg = 0x0038,
1919 .hwcg_bit = 12,
1920 .halt_reg = 0x01dc,
1921 .halt_bit = 10,
1922 .clkr = {
1923 .enable_reg = 0x0008,
1924 .enable_mask = BIT(6),
1925 .hw.init = &(struct clk_init_data){
1926 .name = "mmss_imem_ahb_clk",
1927 .ops = &clk_branch_ops,
1928 .flags = CLK_IS_ROOT
1929 },
1930 },
1931};
1932
1933static struct clk_branch jpegd_ahb_clk = {
1934 .halt_reg = 0x01dc,
1935 .halt_bit = 7,
1936 .clkr = {
1937 .enable_reg = 0x0008,
1938 .enable_mask = BIT(21),
1939 .hw.init = &(struct clk_init_data){
1940 .name = "jpegd_ahb_clk",
1941 .ops = &clk_branch_ops,
1942 .flags = CLK_IS_ROOT,
1943 },
1944 },
1945};
1946
1947static struct clk_branch mdp_ahb_clk = {
1948 .halt_reg = 0x01dc,
1949 .halt_bit = 11,
1950 .clkr = {
1951 .enable_reg = 0x0008,
1952 .enable_mask = BIT(10),
1953 .hw.init = &(struct clk_init_data){
1954 .name = "mdp_ahb_clk",
1955 .ops = &clk_branch_ops,
1956 .flags = CLK_IS_ROOT,
1957 },
1958 },
1959};
1960
1961static struct clk_branch rot_ahb_clk = {
1962 .halt_reg = 0x01dc,
1963 .halt_bit = 13,
1964 .clkr = {
1965 .enable_reg = 0x0008,
1966 .enable_mask = BIT(12),
1967 .hw.init = &(struct clk_init_data){
1968 .name = "rot_ahb_clk",
1969 .ops = &clk_branch_ops,
1970 .flags = CLK_IS_ROOT
1971 },
1972 },
1973};
1974
1975static struct clk_branch smmu_ahb_clk = {
1976 .hwcg_reg = 0x0008,
1977 .hwcg_bit = 26,
1978 .halt_reg = 0x01dc,
1979 .halt_bit = 22,
1980 .clkr = {
1981 .enable_reg = 0x0008,
1982 .enable_mask = BIT(15),
1983 .hw.init = &(struct clk_init_data){
1984 .name = "smmu_ahb_clk",
1985 .ops = &clk_branch_ops,
1986 .flags = CLK_IS_ROOT,
1987 },
1988 },
1989};
1990
1991static struct clk_branch tv_enc_ahb_clk = {
1992 .halt_reg = 0x01dc,
1993 .halt_bit = 23,
1994 .clkr = {
1995 .enable_reg = 0x0008,
1996 .enable_mask = BIT(25),
1997 .hw.init = &(struct clk_init_data){
1998 .name = "tv_enc_ahb_clk",
1999 .ops = &clk_branch_ops,
2000 .flags = CLK_IS_ROOT,
2001 },
2002 },
2003};
2004
2005static struct clk_branch vcodec_ahb_clk = {
2006 .hwcg_reg = 0x0038,
2007 .hwcg_bit = 26,
2008 .halt_reg = 0x01dc,
2009 .halt_bit = 12,
2010 .clkr = {
2011 .enable_reg = 0x0008,
2012 .enable_mask = BIT(11),
2013 .hw.init = &(struct clk_init_data){
2014 .name = "vcodec_ahb_clk",
2015 .ops = &clk_branch_ops,
2016 .flags = CLK_IS_ROOT,
2017 },
2018 },
2019};
2020
2021static struct clk_branch vfe_ahb_clk = {
2022 .halt_reg = 0x01dc,
2023 .halt_bit = 14,
2024 .clkr = {
2025 .enable_reg = 0x0008,
2026 .enable_mask = BIT(13),
2027 .hw.init = &(struct clk_init_data){
2028 .name = "vfe_ahb_clk",
2029 .ops = &clk_branch_ops,
2030 .flags = CLK_IS_ROOT,
2031 },
2032 },
2033};
2034
2035static struct clk_branch vpe_ahb_clk = {
2036 .halt_reg = 0x01dc,
2037 .halt_bit = 15,
2038 .clkr = {
2039 .enable_reg = 0x0008,
2040 .enable_mask = BIT(16),
2041 .hw.init = &(struct clk_init_data){
2042 .name = "vpe_ahb_clk",
2043 .ops = &clk_branch_ops,
2044 .flags = CLK_IS_ROOT,
2045 },
2046 },
2047};
2048
2049static struct clk_regmap *mmcc_msm8960_clks[] = {
2050 [TV_ENC_AHB_CLK] = &tv_enc_ahb_clk.clkr,
2051 [AMP_AHB_CLK] = &amp_ahb_clk.clkr,
2052 [DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr,
2053 [JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr,
2054 [GFX2D0_AHB_CLK] = &gfx2d0_ahb_clk.clkr,
2055 [DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr,
2056 [DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr,
2057 [VPE_AHB_CLK] = &vpe_ahb_clk.clkr,
2058 [SMMU_AHB_CLK] = &smmu_ahb_clk.clkr,
2059 [HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr,
2060 [VFE_AHB_CLK] = &vfe_ahb_clk.clkr,
2061 [ROT_AHB_CLK] = &rot_ahb_clk.clkr,
2062 [VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr,
2063 [MDP_AHB_CLK] = &mdp_ahb_clk.clkr,
2064 [DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr,
2065 [CSI_AHB_CLK] = &csi_ahb_clk.clkr,
2066 [MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr,
2067 [IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr,
2068 [HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr,
2069 [GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr,
2070 [GFX2D1_AHB_CLK] = &gfx2d1_ahb_clk.clkr,
2071 [JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr,
2072 [GMEM_AXI_CLK] = &gmem_axi_clk.clkr,
2073 [MDP_AXI_CLK] = &mdp_axi_clk.clkr,
2074 [MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr,
2075 [IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr,
2076 [GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr,
2077 [VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr,
2078 [VFE_AXI_CLK] = &vfe_axi_clk.clkr,
2079 [VPE_AXI_CLK] = &vpe_axi_clk.clkr,
2080 [ROT_AXI_CLK] = &rot_axi_clk.clkr,
2081 [VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr,
2082 [VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr,
2083 [CSI0_SRC] = &csi0_src.clkr,
2084 [CSI0_CLK] = &csi0_clk.clkr,
2085 [CSI0_PHY_CLK] = &csi0_phy_clk.clkr,
2086 [CSI1_SRC] = &csi1_src.clkr,
2087 [CSI1_CLK] = &csi1_clk.clkr,
2088 [CSI1_PHY_CLK] = &csi1_phy_clk.clkr,
2089 [CSI2_SRC] = &csi2_src.clkr,
2090 [CSI2_CLK] = &csi2_clk.clkr,
2091 [CSI2_PHY_CLK] = &csi2_phy_clk.clkr,
2092 [CSI_PIX_CLK] = &csi_pix_clk.clkr,
2093 [CSI_RDI_CLK] = &csi_rdi_clk.clkr,
2094 [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr,
2095 [HDMI_APP_CLK] = &hdmi_app_clk.clkr,
2096 [CSI_PIX1_CLK] = &csi_pix1_clk.clkr,
2097 [CSI_RDI2_CLK] = &csi_rdi2_clk.clkr,
2098 [CSI_RDI1_CLK] = &csi_rdi1_clk.clkr,
2099 [GFX2D0_SRC] = &gfx2d0_src.clkr,
2100 [GFX2D0_CLK] = &gfx2d0_clk.clkr,
2101 [GFX2D1_SRC] = &gfx2d1_src.clkr,
2102 [GFX2D1_CLK] = &gfx2d1_clk.clkr,
2103 [GFX3D_SRC] = &gfx3d_src.clkr,
2104 [GFX3D_CLK] = &gfx3d_clk.clkr,
2105 [IJPEG_SRC] = &ijpeg_src.clkr,
2106 [IJPEG_CLK] = &ijpeg_clk.clkr,
2107 [JPEGD_SRC] = &jpegd_src.clkr,
2108 [JPEGD_CLK] = &jpegd_clk.clkr,
2109 [MDP_SRC] = &mdp_src.clkr,
2110 [MDP_CLK] = &mdp_clk.clkr,
2111 [MDP_LUT_CLK] = &mdp_lut_clk.clkr,
2112 [ROT_SRC] = &rot_src.clkr,
2113 [ROT_CLK] = &rot_clk.clkr,
2114 [TV_ENC_CLK] = &tv_enc_clk.clkr,
2115 [TV_DAC_CLK] = &tv_dac_clk.clkr,
2116 [HDMI_TV_CLK] = &hdmi_tv_clk.clkr,
2117 [MDP_TV_CLK] = &mdp_tv_clk.clkr,
2118 [TV_SRC] = &tv_src.clkr,
2119 [VCODEC_SRC] = &vcodec_src.clkr,
2120 [VCODEC_CLK] = &vcodec_clk.clkr,
2121 [VFE_SRC] = &vfe_src.clkr,
2122 [VFE_CLK] = &vfe_clk.clkr,
2123 [VFE_CSI_CLK] = &vfe_csi_clk.clkr,
2124 [VPE_SRC] = &vpe_src.clkr,
2125 [VPE_CLK] = &vpe_clk.clkr,
2126 [CAMCLK0_SRC] = &camclk0_src.clkr,
2127 [CAMCLK0_CLK] = &camclk0_clk.clkr,
2128 [CAMCLK1_SRC] = &camclk1_src.clkr,
2129 [CAMCLK1_CLK] = &camclk1_clk.clkr,
2130 [CAMCLK2_SRC] = &camclk2_src.clkr,
2131 [CAMCLK2_CLK] = &camclk2_clk.clkr,
2132 [CSIPHYTIMER_SRC] = &csiphytimer_src.clkr,
2133 [CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr,
2134 [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr,
2135 [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr,
2136 [PLL2] = &pll2.clkr,
2137};
2138
2139static const struct qcom_reset_map mmcc_msm8960_resets[] = {
2140 [VPE_AXI_RESET] = { 0x0208, 15 },
2141 [IJPEG_AXI_RESET] = { 0x0208, 14 },
2142 [MPD_AXI_RESET] = { 0x0208, 13 },
2143 [VFE_AXI_RESET] = { 0x0208, 9 },
2144 [SP_AXI_RESET] = { 0x0208, 8 },
2145 [VCODEC_AXI_RESET] = { 0x0208, 7 },
2146 [ROT_AXI_RESET] = { 0x0208, 6 },
2147 [VCODEC_AXI_A_RESET] = { 0x0208, 5 },
2148 [VCODEC_AXI_B_RESET] = { 0x0208, 4 },
2149 [FAB_S3_AXI_RESET] = { 0x0208, 3 },
2150 [FAB_S2_AXI_RESET] = { 0x0208, 2 },
2151 [FAB_S1_AXI_RESET] = { 0x0208, 1 },
2152 [FAB_S0_AXI_RESET] = { 0x0208 },
2153 [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
2154 [SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
2155 [SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
2156 [SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
2157 [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
2158 [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
2159 [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
2160 [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
2161 [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
2162 [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
2163 [SMMU_GFX2D0_AHB_RESET] = { 0x020c, 21 },
2164 [SMMU_GFX2D1_AHB_RESET] = { 0x020c, 20 },
2165 [APU_AHB_RESET] = { 0x020c, 18 },
2166 [CSI_AHB_RESET] = { 0x020c, 17 },
2167 [TV_ENC_AHB_RESET] = { 0x020c, 15 },
2168 [VPE_AHB_RESET] = { 0x020c, 14 },
2169 [FABRIC_AHB_RESET] = { 0x020c, 13 },
2170 [GFX2D0_AHB_RESET] = { 0x020c, 12 },
2171 [GFX2D1_AHB_RESET] = { 0x020c, 11 },
2172 [GFX3D_AHB_RESET] = { 0x020c, 10 },
2173 [HDMI_AHB_RESET] = { 0x020c, 9 },
2174 [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
2175 [IJPEG_AHB_RESET] = { 0x020c, 7 },
2176 [DSI_M_AHB_RESET] = { 0x020c, 6 },
2177 [DSI_S_AHB_RESET] = { 0x020c, 5 },
2178 [JPEGD_AHB_RESET] = { 0x020c, 4 },
2179 [MDP_AHB_RESET] = { 0x020c, 3 },
2180 [ROT_AHB_RESET] = { 0x020c, 2 },
2181 [VCODEC_AHB_RESET] = { 0x020c, 1 },
2182 [VFE_AHB_RESET] = { 0x020c, 0 },
2183 [DSI2_M_AHB_RESET] = { 0x0210, 31 },
2184 [DSI2_S_AHB_RESET] = { 0x0210, 30 },
2185 [CSIPHY2_RESET] = { 0x0210, 29 },
2186 [CSI_PIX1_RESET] = { 0x0210, 28 },
2187 [CSIPHY0_RESET] = { 0x0210, 27 },
2188 [CSIPHY1_RESET] = { 0x0210, 26 },
2189 [DSI2_RESET] = { 0x0210, 25 },
2190 [VFE_CSI_RESET] = { 0x0210, 24 },
2191 [MDP_RESET] = { 0x0210, 21 },
2192 [AMP_RESET] = { 0x0210, 20 },
2193 [JPEGD_RESET] = { 0x0210, 19 },
2194 [CSI1_RESET] = { 0x0210, 18 },
2195 [VPE_RESET] = { 0x0210, 17 },
2196 [MMSS_FABRIC_RESET] = { 0x0210, 16 },
2197 [VFE_RESET] = { 0x0210, 15 },
2198 [GFX2D0_RESET] = { 0x0210, 14 },
2199 [GFX2D1_RESET] = { 0x0210, 13 },
2200 [GFX3D_RESET] = { 0x0210, 12 },
2201 [HDMI_RESET] = { 0x0210, 11 },
2202 [MMSS_IMEM_RESET] = { 0x0210, 10 },
2203 [IJPEG_RESET] = { 0x0210, 9 },
2204 [CSI0_RESET] = { 0x0210, 8 },
2205 [DSI_RESET] = { 0x0210, 7 },
2206 [VCODEC_RESET] = { 0x0210, 6 },
2207 [MDP_TV_RESET] = { 0x0210, 4 },
2208 [MDP_VSYNC_RESET] = { 0x0210, 3 },
2209 [ROT_RESET] = { 0x0210, 2 },
2210 [TV_HDMI_RESET] = { 0x0210, 1 },
2211 [TV_ENC_RESET] = { 0x0210 },
2212 [CSI2_RESET] = { 0x0214, 2 },
2213 [CSI_RDI1_RESET] = { 0x0214, 1 },
2214 [CSI_RDI2_RESET] = { 0x0214 },
2215};
2216
2217static const struct regmap_config mmcc_msm8960_regmap_config = {
2218 .reg_bits = 32,
2219 .reg_stride = 4,
2220 .val_bits = 32,
2221 .max_register = 0x334,
2222 .fast_io = true,
2223};
2224
2225static const struct of_device_id mmcc_msm8960_match_table[] = {
2226 { .compatible = "qcom,mmcc-msm8960" },
2227 { }
2228};
2229MODULE_DEVICE_TABLE(of, mmcc_msm8960_match_table);
2230
2231struct qcom_cc {
2232 struct qcom_reset_controller reset;
2233 struct clk_onecell_data data;
2234 struct clk *clks[];
2235};
2236
2237static int mmcc_msm8960_probe(struct platform_device *pdev)
2238{
2239 void __iomem *base;
2240 struct resource *res;
2241 int i, ret;
2242 struct device *dev = &pdev->dev;
2243 struct clk *clk;
2244 struct clk_onecell_data *data;
2245 struct clk **clks;
2246 struct regmap *regmap;
2247 size_t num_clks;
2248 struct qcom_reset_controller *reset;
2249 struct qcom_cc *cc;
2250
2251 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2252 base = devm_ioremap_resource(dev, res);
2253 if (IS_ERR(base))
2254 return PTR_ERR(base);
2255
2256 regmap = devm_regmap_init_mmio(dev, base, &mmcc_msm8960_regmap_config);
2257 if (IS_ERR(regmap))
2258 return PTR_ERR(regmap);
2259
2260 num_clks = ARRAY_SIZE(mmcc_msm8960_clks);
2261 cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*clks) * num_clks,
2262 GFP_KERNEL);
2263 if (!cc)
2264 return -ENOMEM;
2265
2266 clks = cc->clks;
2267 data = &cc->data;
2268 data->clks = clks;
2269 data->clk_num = num_clks;
2270
2271 for (i = 0; i < num_clks; i++) {
2272 if (!mmcc_msm8960_clks[i])
2273 continue;
2274 clk = devm_clk_register_regmap(dev, mmcc_msm8960_clks[i]);
2275 if (IS_ERR(clk))
2276 return PTR_ERR(clk);
2277 clks[i] = clk;
2278 }
2279
2280 ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, data);
2281 if (ret)
2282 return ret;
2283
2284 reset = &cc->reset;
2285 reset->rcdev.of_node = dev->of_node;
2286 reset->rcdev.ops = &qcom_reset_ops,
2287 reset->rcdev.owner = THIS_MODULE,
2288 reset->rcdev.nr_resets = ARRAY_SIZE(mmcc_msm8960_resets),
2289 reset->regmap = regmap;
2290 reset->reset_map = mmcc_msm8960_resets,
2291 platform_set_drvdata(pdev, &reset->rcdev);
2292
2293 ret = reset_controller_register(&reset->rcdev);
2294 if (ret)
2295 of_clk_del_provider(dev->of_node);
2296
2297 return ret;
2298}
2299
2300static int mmcc_msm8960_remove(struct platform_device *pdev)
2301{
2302 of_clk_del_provider(pdev->dev.of_node);
2303 reset_controller_unregister(platform_get_drvdata(pdev));
2304 return 0;
2305}
2306
2307static struct platform_driver mmcc_msm8960_driver = {
2308 .probe = mmcc_msm8960_probe,
2309 .remove = mmcc_msm8960_remove,
2310 .driver = {
2311 .name = "mmcc-msm8960",
2312 .owner = THIS_MODULE,
2313 .of_match_table = mmcc_msm8960_match_table,
2314 },
2315};
2316
2317module_platform_driver(mmcc_msm8960_driver);
2318
2319MODULE_DESCRIPTION("QCOM MMCC MSM8960 Driver");
2320MODULE_LICENSE("GPL v2");
2321MODULE_ALIAS("platform:mmcc-msm8960");
diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
new file mode 100644
index 000000000000..c95774514b81
--- /dev/null
+++ b/drivers/clk/qcom/mmcc-msm8974.c
@@ -0,0 +1,2625 @@
1/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/bitops.h>
16#include <linux/err.h>
17#include <linux/platform_device.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/clk-provider.h>
22#include <linux/regmap.h>
23#include <linux/reset-controller.h>
24
25#include <dt-bindings/clock/qcom,mmcc-msm8974.h>
26#include <dt-bindings/reset/qcom,mmcc-msm8974.h>
27
28#include "clk-regmap.h"
29#include "clk-pll.h"
30#include "clk-rcg.h"
31#include "clk-branch.h"
32#include "reset.h"
33
34#define P_XO 0
35#define P_MMPLL0 1
36#define P_EDPLINK 1
37#define P_MMPLL1 2
38#define P_HDMIPLL 2
39#define P_GPLL0 3
40#define P_EDPVCO 3
41#define P_GPLL1 4
42#define P_DSI0PLL 4
43#define P_MMPLL2 4
44#define P_MMPLL3 4
45#define P_DSI1PLL 5
46
47static const u8 mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
48 [P_XO] = 0,
49 [P_MMPLL0] = 1,
50 [P_MMPLL1] = 2,
51 [P_GPLL0] = 5,
52};
53
54static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = {
55 "xo",
56 "mmpll0_vote",
57 "mmpll1_vote",
58 "mmss_gpll0_vote",
59};
60
61static const u8 mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
62 [P_XO] = 0,
63 [P_MMPLL0] = 1,
64 [P_HDMIPLL] = 4,
65 [P_GPLL0] = 5,
66 [P_DSI0PLL] = 2,
67 [P_DSI1PLL] = 3,
68};
69
70static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
71 "xo",
72 "mmpll0_vote",
73 "hdmipll",
74 "mmss_gpll0_vote",
75 "dsi0pll",
76 "dsi1pll",
77};
78
79static const u8 mmcc_xo_mmpll0_1_2_gpll0_map[] = {
80 [P_XO] = 0,
81 [P_MMPLL0] = 1,
82 [P_MMPLL1] = 2,
83 [P_GPLL0] = 5,
84 [P_MMPLL2] = 3,
85};
86
87static const char *mmcc_xo_mmpll0_1_2_gpll0[] = {
88 "xo",
89 "mmpll0_vote",
90 "mmpll1_vote",
91 "mmss_gpll0_vote",
92 "mmpll2",
93};
94
95static const u8 mmcc_xo_mmpll0_1_3_gpll0_map[] = {
96 [P_XO] = 0,
97 [P_MMPLL0] = 1,
98 [P_MMPLL1] = 2,
99 [P_GPLL0] = 5,
100 [P_MMPLL3] = 3,
101};
102
103static const char *mmcc_xo_mmpll0_1_3_gpll0[] = {
104 "xo",
105 "mmpll0_vote",
106 "mmpll1_vote",
107 "mmss_gpll0_vote",
108 "mmpll3",
109};
110
111static const u8 mmcc_xo_mmpll0_1_gpll1_0_map[] = {
112 [P_XO] = 0,
113 [P_MMPLL0] = 1,
114 [P_MMPLL1] = 2,
115 [P_GPLL0] = 5,
116 [P_GPLL1] = 4,
117};
118
119static const char *mmcc_xo_mmpll0_1_gpll1_0[] = {
120 "xo",
121 "mmpll0_vote",
122 "mmpll1_vote",
123 "mmss_gpll0_vote",
124 "gpll1_vote",
125};
126
127static const u8 mmcc_xo_dsi_hdmi_edp_map[] = {
128 [P_XO] = 0,
129 [P_EDPLINK] = 4,
130 [P_HDMIPLL] = 3,
131 [P_EDPVCO] = 5,
132 [P_DSI0PLL] = 1,
133 [P_DSI1PLL] = 2,
134};
135
136static const char *mmcc_xo_dsi_hdmi_edp[] = {
137 "xo",
138 "edp_link_clk",
139 "hdmipll",
140 "edp_vco_div",
141 "dsi0pll",
142 "dsi1pll",
143};
144
145static const u8 mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
146 [P_XO] = 0,
147 [P_EDPLINK] = 4,
148 [P_HDMIPLL] = 3,
149 [P_GPLL0] = 5,
150 [P_DSI0PLL] = 1,
151 [P_DSI1PLL] = 2,
152};
153
154static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = {
155 "xo",
156 "edp_link_clk",
157 "hdmipll",
158 "gpll0_vote",
159 "dsi0pll",
160 "dsi1pll",
161};
162
163#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
164
165static struct clk_pll mmpll0 = {
166 .l_reg = 0x0004,
167 .m_reg = 0x0008,
168 .n_reg = 0x000c,
169 .config_reg = 0x0014,
170 .mode_reg = 0x0000,
171 .status_reg = 0x001c,
172 .clkr.hw.init = &(struct clk_init_data){
173 .name = "mmpll0",
174 .parent_names = (const char *[]){ "xo" },
175 .num_parents = 1,
176 .ops = &clk_pll_ops,
177 },
178};
179
180static struct clk_regmap mmpll0_vote = {
181 .enable_reg = 0x0100,
182 .enable_mask = BIT(0),
183 .hw.init = &(struct clk_init_data){
184 .name = "mmpll0_vote",
185 .parent_names = (const char *[]){ "mmpll0" },
186 .num_parents = 1,
187 .ops = &clk_pll_vote_ops,
188 },
189};
190
191static struct clk_pll mmpll1 = {
192 .l_reg = 0x0044,
193 .m_reg = 0x0048,
194 .n_reg = 0x004c,
195 .config_reg = 0x0054,
196 .mode_reg = 0x0040,
197 .status_reg = 0x005c,
198 .clkr.hw.init = &(struct clk_init_data){
199 .name = "mmpll1",
200 .parent_names = (const char *[]){ "xo" },
201 .num_parents = 1,
202 .ops = &clk_pll_ops,
203 },
204};
205
206static struct clk_regmap mmpll1_vote = {
207 .enable_reg = 0x0100,
208 .enable_mask = BIT(1),
209 .hw.init = &(struct clk_init_data){
210 .name = "mmpll1_vote",
211 .parent_names = (const char *[]){ "mmpll1" },
212 .num_parents = 1,
213 .ops = &clk_pll_vote_ops,
214 },
215};
216
217static struct clk_pll mmpll2 = {
218 .l_reg = 0x4104,
219 .m_reg = 0x4108,
220 .n_reg = 0x410c,
221 .config_reg = 0x4114,
222 .mode_reg = 0x4100,
223 .status_reg = 0x411c,
224 .clkr.hw.init = &(struct clk_init_data){
225 .name = "mmpll2",
226 .parent_names = (const char *[]){ "xo" },
227 .num_parents = 1,
228 .ops = &clk_pll_ops,
229 },
230};
231
232static struct clk_pll mmpll3 = {
233 .l_reg = 0x0084,
234 .m_reg = 0x0088,
235 .n_reg = 0x008c,
236 .config_reg = 0x0094,
237 .mode_reg = 0x0080,
238 .status_reg = 0x009c,
239 .clkr.hw.init = &(struct clk_init_data){
240 .name = "mmpll3",
241 .parent_names = (const char *[]){ "xo" },
242 .num_parents = 1,
243 .ops = &clk_pll_ops,
244 },
245};
246
247static struct clk_rcg2 mmss_ahb_clk_src = {
248 .cmd_rcgr = 0x5000,
249 .hid_width = 5,
250 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
251 .clkr.hw.init = &(struct clk_init_data){
252 .name = "mmss_ahb_clk_src",
253 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
254 .num_parents = 4,
255 .ops = &clk_rcg2_ops,
256 },
257};
258
259static struct freq_tbl ftbl_mmss_axi_clk[] = {
260 F( 19200000, P_XO, 1, 0, 0),
261 F( 37500000, P_GPLL0, 16, 0, 0),
262 F( 50000000, P_GPLL0, 12, 0, 0),
263 F( 75000000, P_GPLL0, 8, 0, 0),
264 F(100000000, P_GPLL0, 6, 0, 0),
265 F(150000000, P_GPLL0, 4, 0, 0),
266 F(291750000, P_MMPLL1, 4, 0, 0),
267 F(400000000, P_MMPLL0, 2, 0, 0),
268 F(466800000, P_MMPLL1, 2.5, 0, 0),
269};
270
271static struct clk_rcg2 mmss_axi_clk_src = {
272 .cmd_rcgr = 0x5040,
273 .hid_width = 5,
274 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
275 .freq_tbl = ftbl_mmss_axi_clk,
276 .clkr.hw.init = &(struct clk_init_data){
277 .name = "mmss_axi_clk_src",
278 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
279 .num_parents = 4,
280 .ops = &clk_rcg2_ops,
281 },
282};
283
284static struct freq_tbl ftbl_ocmemnoc_clk[] = {
285 F( 19200000, P_XO, 1, 0, 0),
286 F( 37500000, P_GPLL0, 16, 0, 0),
287 F( 50000000, P_GPLL0, 12, 0, 0),
288 F( 75000000, P_GPLL0, 8, 0, 0),
289 F(100000000, P_GPLL0, 6, 0, 0),
290 F(150000000, P_GPLL0, 4, 0, 0),
291 F(291750000, P_MMPLL1, 4, 0, 0),
292 F(400000000, P_MMPLL0, 2, 0, 0),
293};
294
295static struct clk_rcg2 ocmemnoc_clk_src = {
296 .cmd_rcgr = 0x5090,
297 .hid_width = 5,
298 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
299 .freq_tbl = ftbl_ocmemnoc_clk,
300 .clkr.hw.init = &(struct clk_init_data){
301 .name = "ocmemnoc_clk_src",
302 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
303 .num_parents = 4,
304 .ops = &clk_rcg2_ops,
305 },
306};
307
308static struct freq_tbl ftbl_camss_csi0_3_clk[] = {
309 F(100000000, P_GPLL0, 6, 0, 0),
310 F(200000000, P_MMPLL0, 4, 0, 0),
311 { }
312};
313
314static struct clk_rcg2 csi0_clk_src = {
315 .cmd_rcgr = 0x3090,
316 .hid_width = 5,
317 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
318 .freq_tbl = ftbl_camss_csi0_3_clk,
319 .clkr.hw.init = &(struct clk_init_data){
320 .name = "csi0_clk_src",
321 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
322 .num_parents = 4,
323 .ops = &clk_rcg2_ops,
324 },
325};
326
327static struct clk_rcg2 csi1_clk_src = {
328 .cmd_rcgr = 0x3100,
329 .hid_width = 5,
330 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
331 .freq_tbl = ftbl_camss_csi0_3_clk,
332 .clkr.hw.init = &(struct clk_init_data){
333 .name = "csi1_clk_src",
334 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
335 .num_parents = 4,
336 .ops = &clk_rcg2_ops,
337 },
338};
339
340static struct clk_rcg2 csi2_clk_src = {
341 .cmd_rcgr = 0x3160,
342 .hid_width = 5,
343 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
344 .freq_tbl = ftbl_camss_csi0_3_clk,
345 .clkr.hw.init = &(struct clk_init_data){
346 .name = "csi2_clk_src",
347 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
348 .num_parents = 4,
349 .ops = &clk_rcg2_ops,
350 },
351};
352
353static struct clk_rcg2 csi3_clk_src = {
354 .cmd_rcgr = 0x31c0,
355 .hid_width = 5,
356 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
357 .freq_tbl = ftbl_camss_csi0_3_clk,
358 .clkr.hw.init = &(struct clk_init_data){
359 .name = "csi3_clk_src",
360 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
361 .num_parents = 4,
362 .ops = &clk_rcg2_ops,
363 },
364};
365
366static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
367 F(37500000, P_GPLL0, 16, 0, 0),
368 F(50000000, P_GPLL0, 12, 0, 0),
369 F(60000000, P_GPLL0, 10, 0, 0),
370 F(80000000, P_GPLL0, 7.5, 0, 0),
371 F(100000000, P_GPLL0, 6, 0, 0),
372 F(109090000, P_GPLL0, 5.5, 0, 0),
373 F(133330000, P_GPLL0, 4.5, 0, 0),
374 F(200000000, P_GPLL0, 3, 0, 0),
375 F(228570000, P_MMPLL0, 3.5, 0, 0),
376 F(266670000, P_MMPLL0, 3, 0, 0),
377 F(320000000, P_MMPLL0, 2.5, 0, 0),
378 F(400000000, P_MMPLL0, 2, 0, 0),
379 F(465000000, P_MMPLL3, 2, 0, 0),
380 { }
381};
382
383static struct clk_rcg2 vfe0_clk_src = {
384 .cmd_rcgr = 0x3600,
385 .hid_width = 5,
386 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
387 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
388 .clkr.hw.init = &(struct clk_init_data){
389 .name = "vfe0_clk_src",
390 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
391 .num_parents = 4,
392 .ops = &clk_rcg2_ops,
393 },
394};
395
396static struct clk_rcg2 vfe1_clk_src = {
397 .cmd_rcgr = 0x3620,
398 .hid_width = 5,
399 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
400 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
401 .clkr.hw.init = &(struct clk_init_data){
402 .name = "vfe1_clk_src",
403 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
404 .num_parents = 4,
405 .ops = &clk_rcg2_ops,
406 },
407};
408
409static struct freq_tbl ftbl_mdss_mdp_clk[] = {
410 F(37500000, P_GPLL0, 16, 0, 0),
411 F(60000000, P_GPLL0, 10, 0, 0),
412 F(75000000, P_GPLL0, 8, 0, 0),
413 F(85710000, P_GPLL0, 7, 0, 0),
414 F(100000000, P_GPLL0, 6, 0, 0),
415 F(133330000, P_MMPLL0, 6, 0, 0),
416 F(160000000, P_MMPLL0, 5, 0, 0),
417 F(200000000, P_MMPLL0, 4, 0, 0),
418 F(228570000, P_MMPLL0, 3.5, 0, 0),
419 F(240000000, P_GPLL0, 2.5, 0, 0),
420 F(266670000, P_MMPLL0, 3, 0, 0),
421 F(320000000, P_MMPLL0, 2.5, 0, 0),
422 { }
423};
424
425static struct clk_rcg2 mdp_clk_src = {
426 .cmd_rcgr = 0x2040,
427 .hid_width = 5,
428 .parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map,
429 .freq_tbl = ftbl_mdss_mdp_clk,
430 .clkr.hw.init = &(struct clk_init_data){
431 .name = "mdp_clk_src",
432 .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
433 .num_parents = 6,
434 .ops = &clk_rcg2_ops,
435 },
436};
437
438static struct clk_rcg2 gfx3d_clk_src = {
439 .cmd_rcgr = 0x4000,
440 .hid_width = 5,
441 .parent_map = mmcc_xo_mmpll0_1_2_gpll0_map,
442 .clkr.hw.init = &(struct clk_init_data){
443 .name = "gfx3d_clk_src",
444 .parent_names = mmcc_xo_mmpll0_1_2_gpll0,
445 .num_parents = 5,
446 .ops = &clk_rcg2_ops,
447 },
448};
449
450static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
451 F(75000000, P_GPLL0, 8, 0, 0),
452 F(133330000, P_GPLL0, 4.5, 0, 0),
453 F(200000000, P_GPLL0, 3, 0, 0),
454 F(228570000, P_MMPLL0, 3.5, 0, 0),
455 F(266670000, P_MMPLL0, 3, 0, 0),
456 F(320000000, P_MMPLL0, 2.5, 0, 0),
457 { }
458};
459
460static struct clk_rcg2 jpeg0_clk_src = {
461 .cmd_rcgr = 0x3500,
462 .hid_width = 5,
463 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
464 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
465 .clkr.hw.init = &(struct clk_init_data){
466 .name = "jpeg0_clk_src",
467 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
468 .num_parents = 4,
469 .ops = &clk_rcg2_ops,
470 },
471};
472
473static struct clk_rcg2 jpeg1_clk_src = {
474 .cmd_rcgr = 0x3520,
475 .hid_width = 5,
476 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
477 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
478 .clkr.hw.init = &(struct clk_init_data){
479 .name = "jpeg1_clk_src",
480 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
481 .num_parents = 4,
482 .ops = &clk_rcg2_ops,
483 },
484};
485
486static struct clk_rcg2 jpeg2_clk_src = {
487 .cmd_rcgr = 0x3540,
488 .hid_width = 5,
489 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
490 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
491 .clkr.hw.init = &(struct clk_init_data){
492 .name = "jpeg2_clk_src",
493 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
494 .num_parents = 4,
495 .ops = &clk_rcg2_ops,
496 },
497};
498
499static struct freq_tbl ftbl_mdss_pclk0_clk[] = {
500 F(125000000, P_DSI0PLL, 2, 0, 0),
501 F(250000000, P_DSI0PLL, 1, 0, 0),
502 { }
503};
504
505static struct freq_tbl ftbl_mdss_pclk1_clk[] = {
506 F(125000000, P_DSI1PLL, 2, 0, 0),
507 F(250000000, P_DSI1PLL, 1, 0, 0),
508 { }
509};
510
511static struct clk_rcg2 pclk0_clk_src = {
512 .cmd_rcgr = 0x2000,
513 .mnd_width = 8,
514 .hid_width = 5,
515 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
516 .freq_tbl = ftbl_mdss_pclk0_clk,
517 .clkr.hw.init = &(struct clk_init_data){
518 .name = "pclk0_clk_src",
519 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
520 .num_parents = 6,
521 .ops = &clk_rcg2_ops,
522 },
523};
524
525static struct clk_rcg2 pclk1_clk_src = {
526 .cmd_rcgr = 0x2020,
527 .mnd_width = 8,
528 .hid_width = 5,
529 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
530 .freq_tbl = ftbl_mdss_pclk1_clk,
531 .clkr.hw.init = &(struct clk_init_data){
532 .name = "pclk1_clk_src",
533 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
534 .num_parents = 6,
535 .ops = &clk_rcg2_ops,
536 },
537};
538
539static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
540 F(50000000, P_GPLL0, 12, 0, 0),
541 F(100000000, P_GPLL0, 6, 0, 0),
542 F(133330000, P_MMPLL0, 6, 0, 0),
543 F(200000000, P_MMPLL0, 4, 0, 0),
544 F(266670000, P_MMPLL0, 3, 0, 0),
545 F(465000000, P_MMPLL3, 2, 0, 0),
546 { }
547};
548
549static struct clk_rcg2 vcodec0_clk_src = {
550 .cmd_rcgr = 0x1000,
551 .mnd_width = 8,
552 .hid_width = 5,
553 .parent_map = mmcc_xo_mmpll0_1_3_gpll0_map,
554 .freq_tbl = ftbl_venus0_vcodec0_clk,
555 .clkr.hw.init = &(struct clk_init_data){
556 .name = "vcodec0_clk_src",
557 .parent_names = mmcc_xo_mmpll0_1_3_gpll0,
558 .num_parents = 5,
559 .ops = &clk_rcg2_ops,
560 },
561};
562
563static struct freq_tbl ftbl_camss_cci_cci_clk[] = {
564 F(19200000, P_XO, 1, 0, 0),
565 { }
566};
567
568static struct clk_rcg2 cci_clk_src = {
569 .cmd_rcgr = 0x3300,
570 .hid_width = 5,
571 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
572 .freq_tbl = ftbl_camss_cci_cci_clk,
573 .clkr.hw.init = &(struct clk_init_data){
574 .name = "cci_clk_src",
575 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
576 .num_parents = 4,
577 .ops = &clk_rcg2_ops,
578 },
579};
580
581static struct freq_tbl ftbl_camss_gp0_1_clk[] = {
582 F(10000, P_XO, 16, 1, 120),
583 F(24000, P_XO, 16, 1, 50),
584 F(6000000, P_GPLL0, 10, 1, 10),
585 F(12000000, P_GPLL0, 10, 1, 5),
586 F(13000000, P_GPLL0, 4, 13, 150),
587 F(24000000, P_GPLL0, 5, 1, 5),
588 { }
589};
590
591static struct clk_rcg2 camss_gp0_clk_src = {
592 .cmd_rcgr = 0x3420,
593 .mnd_width = 8,
594 .hid_width = 5,
595 .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map,
596 .freq_tbl = ftbl_camss_gp0_1_clk,
597 .clkr.hw.init = &(struct clk_init_data){
598 .name = "camss_gp0_clk_src",
599 .parent_names = mmcc_xo_mmpll0_1_gpll1_0,
600 .num_parents = 5,
601 .ops = &clk_rcg2_ops,
602 },
603};
604
605static struct clk_rcg2 camss_gp1_clk_src = {
606 .cmd_rcgr = 0x3450,
607 .mnd_width = 8,
608 .hid_width = 5,
609 .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map,
610 .freq_tbl = ftbl_camss_gp0_1_clk,
611 .clkr.hw.init = &(struct clk_init_data){
612 .name = "camss_gp1_clk_src",
613 .parent_names = mmcc_xo_mmpll0_1_gpll1_0,
614 .num_parents = 5,
615 .ops = &clk_rcg2_ops,
616 },
617};
618
619static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
620 F(4800000, P_XO, 4, 0, 0),
621 F(6000000, P_GPLL0, 10, 1, 10),
622 F(8000000, P_GPLL0, 15, 1, 5),
623 F(9600000, P_XO, 2, 0, 0),
624 F(16000000, P_GPLL0, 12.5, 1, 3),
625 F(19200000, P_XO, 1, 0, 0),
626 F(24000000, P_GPLL0, 5, 1, 5),
627 F(32000000, P_MMPLL0, 5, 1, 5),
628 F(48000000, P_GPLL0, 12.5, 0, 0),
629 F(64000000, P_MMPLL0, 12.5, 0, 0),
630 F(66670000, P_GPLL0, 9, 0, 0),
631 { }
632};
633
634static struct clk_rcg2 mclk0_clk_src = {
635 .cmd_rcgr = 0x3360,
636 .hid_width = 5,
637 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
638 .freq_tbl = ftbl_camss_mclk0_3_clk,
639 .clkr.hw.init = &(struct clk_init_data){
640 .name = "mclk0_clk_src",
641 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
642 .num_parents = 4,
643 .ops = &clk_rcg2_ops,
644 },
645};
646
647static struct clk_rcg2 mclk1_clk_src = {
648 .cmd_rcgr = 0x3390,
649 .hid_width = 5,
650 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
651 .freq_tbl = ftbl_camss_mclk0_3_clk,
652 .clkr.hw.init = &(struct clk_init_data){
653 .name = "mclk1_clk_src",
654 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
655 .num_parents = 4,
656 .ops = &clk_rcg2_ops,
657 },
658};
659
660static struct clk_rcg2 mclk2_clk_src = {
661 .cmd_rcgr = 0x33c0,
662 .hid_width = 5,
663 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
664 .freq_tbl = ftbl_camss_mclk0_3_clk,
665 .clkr.hw.init = &(struct clk_init_data){
666 .name = "mclk2_clk_src",
667 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
668 .num_parents = 4,
669 .ops = &clk_rcg2_ops,
670 },
671};
672
673static struct clk_rcg2 mclk3_clk_src = {
674 .cmd_rcgr = 0x33f0,
675 .hid_width = 5,
676 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
677 .freq_tbl = ftbl_camss_mclk0_3_clk,
678 .clkr.hw.init = &(struct clk_init_data){
679 .name = "mclk3_clk_src",
680 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
681 .num_parents = 4,
682 .ops = &clk_rcg2_ops,
683 },
684};
685
686static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
687 F(100000000, P_GPLL0, 6, 0, 0),
688 F(200000000, P_MMPLL0, 4, 0, 0),
689 { }
690};
691
692static struct clk_rcg2 csi0phytimer_clk_src = {
693 .cmd_rcgr = 0x3000,
694 .hid_width = 5,
695 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
696 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
697 .clkr.hw.init = &(struct clk_init_data){
698 .name = "csi0phytimer_clk_src",
699 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
700 .num_parents = 4,
701 .ops = &clk_rcg2_ops,
702 },
703};
704
705static struct clk_rcg2 csi1phytimer_clk_src = {
706 .cmd_rcgr = 0x3030,
707 .hid_width = 5,
708 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
709 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
710 .clkr.hw.init = &(struct clk_init_data){
711 .name = "csi1phytimer_clk_src",
712 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
713 .num_parents = 4,
714 .ops = &clk_rcg2_ops,
715 },
716};
717
718static struct clk_rcg2 csi2phytimer_clk_src = {
719 .cmd_rcgr = 0x3060,
720 .hid_width = 5,
721 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
722 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
723 .clkr.hw.init = &(struct clk_init_data){
724 .name = "csi2phytimer_clk_src",
725 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
726 .num_parents = 4,
727 .ops = &clk_rcg2_ops,
728 },
729};
730
731static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
732 F(133330000, P_GPLL0, 4.5, 0, 0),
733 F(266670000, P_MMPLL0, 3, 0, 0),
734 F(320000000, P_MMPLL0, 2.5, 0, 0),
735 F(400000000, P_MMPLL0, 2, 0, 0),
736 F(465000000, P_MMPLL3, 2, 0, 0),
737 { }
738};
739
740static struct clk_rcg2 cpp_clk_src = {
741 .cmd_rcgr = 0x3640,
742 .hid_width = 5,
743 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
744 .freq_tbl = ftbl_camss_vfe_cpp_clk,
745 .clkr.hw.init = &(struct clk_init_data){
746 .name = "cpp_clk_src",
747 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
748 .num_parents = 4,
749 .ops = &clk_rcg2_ops,
750 },
751};
752
753static struct freq_tbl ftbl_mdss_byte0_clk[] = {
754 F(93750000, P_DSI0PLL, 8, 0, 0),
755 F(187500000, P_DSI0PLL, 4, 0, 0),
756 { }
757};
758
759static struct freq_tbl ftbl_mdss_byte1_clk[] = {
760 F(93750000, P_DSI1PLL, 8, 0, 0),
761 F(187500000, P_DSI1PLL, 4, 0, 0),
762 { }
763};
764
765static struct clk_rcg2 byte0_clk_src = {
766 .cmd_rcgr = 0x2120,
767 .hid_width = 5,
768 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
769 .freq_tbl = ftbl_mdss_byte0_clk,
770 .clkr.hw.init = &(struct clk_init_data){
771 .name = "byte0_clk_src",
772 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
773 .num_parents = 6,
774 .ops = &clk_rcg2_ops,
775 },
776};
777
778static struct clk_rcg2 byte1_clk_src = {
779 .cmd_rcgr = 0x2140,
780 .hid_width = 5,
781 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
782 .freq_tbl = ftbl_mdss_byte1_clk,
783 .clkr.hw.init = &(struct clk_init_data){
784 .name = "byte1_clk_src",
785 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
786 .num_parents = 6,
787 .ops = &clk_rcg2_ops,
788 },
789};
790
791static struct freq_tbl ftbl_mdss_edpaux_clk[] = {
792 F(19200000, P_XO, 1, 0, 0),
793 { }
794};
795
796static struct clk_rcg2 edpaux_clk_src = {
797 .cmd_rcgr = 0x20e0,
798 .hid_width = 5,
799 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
800 .freq_tbl = ftbl_mdss_edpaux_clk,
801 .clkr.hw.init = &(struct clk_init_data){
802 .name = "edpaux_clk_src",
803 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
804 .num_parents = 4,
805 .ops = &clk_rcg2_ops,
806 },
807};
808
809static struct freq_tbl ftbl_mdss_edplink_clk[] = {
810 F(135000000, P_EDPLINK, 2, 0, 0),
811 F(270000000, P_EDPLINK, 11, 0, 0),
812 { }
813};
814
815static struct clk_rcg2 edplink_clk_src = {
816 .cmd_rcgr = 0x20c0,
817 .hid_width = 5,
818 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
819 .freq_tbl = ftbl_mdss_edplink_clk,
820 .clkr.hw.init = &(struct clk_init_data){
821 .name = "edplink_clk_src",
822 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
823 .num_parents = 6,
824 .ops = &clk_rcg2_ops,
825 },
826};
827
828static struct freq_tbl ftbl_mdss_edppixel_clk[] = {
829 F(175000000, P_EDPVCO, 2, 0, 0),
830 F(350000000, P_EDPVCO, 11, 0, 0),
831 { }
832};
833
834static struct clk_rcg2 edppixel_clk_src = {
835 .cmd_rcgr = 0x20a0,
836 .mnd_width = 8,
837 .hid_width = 5,
838 .parent_map = mmcc_xo_dsi_hdmi_edp_map,
839 .freq_tbl = ftbl_mdss_edppixel_clk,
840 .clkr.hw.init = &(struct clk_init_data){
841 .name = "edppixel_clk_src",
842 .parent_names = mmcc_xo_dsi_hdmi_edp,
843 .num_parents = 6,
844 .ops = &clk_rcg2_ops,
845 },
846};
847
848static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
849 F(19200000, P_XO, 1, 0, 0),
850 { }
851};
852
853static struct clk_rcg2 esc0_clk_src = {
854 .cmd_rcgr = 0x2160,
855 .hid_width = 5,
856 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
857 .freq_tbl = ftbl_mdss_esc0_1_clk,
858 .clkr.hw.init = &(struct clk_init_data){
859 .name = "esc0_clk_src",
860 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
861 .num_parents = 6,
862 .ops = &clk_rcg2_ops,
863 },
864};
865
866static struct clk_rcg2 esc1_clk_src = {
867 .cmd_rcgr = 0x2180,
868 .hid_width = 5,
869 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
870 .freq_tbl = ftbl_mdss_esc0_1_clk,
871 .clkr.hw.init = &(struct clk_init_data){
872 .name = "esc1_clk_src",
873 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
874 .num_parents = 6,
875 .ops = &clk_rcg2_ops,
876 },
877};
878
879static struct freq_tbl ftbl_mdss_extpclk_clk[] = {
880 F(25200000, P_HDMIPLL, 1, 0, 0),
881 F(27000000, P_HDMIPLL, 1, 0, 0),
882 F(27030000, P_HDMIPLL, 1, 0, 0),
883 F(65000000, P_HDMIPLL, 1, 0, 0),
884 F(74250000, P_HDMIPLL, 1, 0, 0),
885 F(108000000, P_HDMIPLL, 1, 0, 0),
886 F(148500000, P_HDMIPLL, 1, 0, 0),
887 F(268500000, P_HDMIPLL, 1, 0, 0),
888 F(297000000, P_HDMIPLL, 1, 0, 0),
889 { }
890};
891
892static struct clk_rcg2 extpclk_clk_src = {
893 .cmd_rcgr = 0x2060,
894 .hid_width = 5,
895 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
896 .freq_tbl = ftbl_mdss_extpclk_clk,
897 .clkr.hw.init = &(struct clk_init_data){
898 .name = "extpclk_clk_src",
899 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
900 .num_parents = 6,
901 .ops = &clk_rcg2_ops,
902 },
903};
904
905static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
906 F(19200000, P_XO, 1, 0, 0),
907 { }
908};
909
910static struct clk_rcg2 hdmi_clk_src = {
911 .cmd_rcgr = 0x2100,
912 .hid_width = 5,
913 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
914 .freq_tbl = ftbl_mdss_hdmi_clk,
915 .clkr.hw.init = &(struct clk_init_data){
916 .name = "hdmi_clk_src",
917 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
918 .num_parents = 4,
919 .ops = &clk_rcg2_ops,
920 },
921};
922
923static struct freq_tbl ftbl_mdss_vsync_clk[] = {
924 F(19200000, P_XO, 1, 0, 0),
925 { }
926};
927
928static struct clk_rcg2 vsync_clk_src = {
929 .cmd_rcgr = 0x2080,
930 .hid_width = 5,
931 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
932 .freq_tbl = ftbl_mdss_vsync_clk,
933 .clkr.hw.init = &(struct clk_init_data){
934 .name = "vsync_clk_src",
935 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
936 .num_parents = 4,
937 .ops = &clk_rcg2_ops,
938 },
939};
940
941static struct clk_branch camss_cci_cci_ahb_clk = {
942 .halt_reg = 0x3348,
943 .clkr = {
944 .enable_reg = 0x3348,
945 .enable_mask = BIT(0),
946 .hw.init = &(struct clk_init_data){
947 .name = "camss_cci_cci_ahb_clk",
948 .parent_names = (const char *[]){
949 "mmss_ahb_clk_src",
950 },
951 .num_parents = 1,
952 .ops = &clk_branch2_ops,
953 },
954 },
955};
956
957static struct clk_branch camss_cci_cci_clk = {
958 .halt_reg = 0x3344,
959 .clkr = {
960 .enable_reg = 0x3344,
961 .enable_mask = BIT(0),
962 .hw.init = &(struct clk_init_data){
963 .name = "camss_cci_cci_clk",
964 .parent_names = (const char *[]){
965 "cci_clk_src",
966 },
967 .num_parents = 1,
968 .flags = CLK_SET_RATE_PARENT,
969 .ops = &clk_branch2_ops,
970 },
971 },
972};
973
974static struct clk_branch camss_csi0_ahb_clk = {
975 .halt_reg = 0x30bc,
976 .clkr = {
977 .enable_reg = 0x30bc,
978 .enable_mask = BIT(0),
979 .hw.init = &(struct clk_init_data){
980 .name = "camss_csi0_ahb_clk",
981 .parent_names = (const char *[]){
982 "mmss_ahb_clk_src",
983 },
984 .num_parents = 1,
985 .ops = &clk_branch2_ops,
986 },
987 },
988};
989
990static struct clk_branch camss_csi0_clk = {
991 .halt_reg = 0x30b4,
992 .clkr = {
993 .enable_reg = 0x30b4,
994 .enable_mask = BIT(0),
995 .hw.init = &(struct clk_init_data){
996 .name = "camss_csi0_clk",
997 .parent_names = (const char *[]){
998 "csi0_clk_src",
999 },
1000 .num_parents = 1,
1001 .flags = CLK_SET_RATE_PARENT,
1002 .ops = &clk_branch2_ops,
1003 },
1004 },
1005};
1006
1007static struct clk_branch camss_csi0phy_clk = {
1008 .halt_reg = 0x30c4,
1009 .clkr = {
1010 .enable_reg = 0x30c4,
1011 .enable_mask = BIT(0),
1012 .hw.init = &(struct clk_init_data){
1013 .name = "camss_csi0phy_clk",
1014 .parent_names = (const char *[]){
1015 "csi0_clk_src",
1016 },
1017 .num_parents = 1,
1018 .flags = CLK_SET_RATE_PARENT,
1019 .ops = &clk_branch2_ops,
1020 },
1021 },
1022};
1023
1024static struct clk_branch camss_csi0pix_clk = {
1025 .halt_reg = 0x30e4,
1026 .clkr = {
1027 .enable_reg = 0x30e4,
1028 .enable_mask = BIT(0),
1029 .hw.init = &(struct clk_init_data){
1030 .name = "camss_csi0pix_clk",
1031 .parent_names = (const char *[]){
1032 "csi0_clk_src",
1033 },
1034 .num_parents = 1,
1035 .flags = CLK_SET_RATE_PARENT,
1036 .ops = &clk_branch2_ops,
1037 },
1038 },
1039};
1040
1041static struct clk_branch camss_csi0rdi_clk = {
1042 .halt_reg = 0x30d4,
1043 .clkr = {
1044 .enable_reg = 0x30d4,
1045 .enable_mask = BIT(0),
1046 .hw.init = &(struct clk_init_data){
1047 .name = "camss_csi0rdi_clk",
1048 .parent_names = (const char *[]){
1049 "csi0_clk_src",
1050 },
1051 .num_parents = 1,
1052 .flags = CLK_SET_RATE_PARENT,
1053 .ops = &clk_branch2_ops,
1054 },
1055 },
1056};
1057
1058static struct clk_branch camss_csi1_ahb_clk = {
1059 .halt_reg = 0x3128,
1060 .clkr = {
1061 .enable_reg = 0x3128,
1062 .enable_mask = BIT(0),
1063 .hw.init = &(struct clk_init_data){
1064 .name = "camss_csi1_ahb_clk",
1065 .parent_names = (const char *[]){
1066 "mmss_ahb_clk_src",
1067 },
1068 .num_parents = 1,
1069 .ops = &clk_branch2_ops,
1070 },
1071 },
1072};
1073
1074static struct clk_branch camss_csi1_clk = {
1075 .halt_reg = 0x3124,
1076 .clkr = {
1077 .enable_reg = 0x3124,
1078 .enable_mask = BIT(0),
1079 .hw.init = &(struct clk_init_data){
1080 .name = "camss_csi1_clk",
1081 .parent_names = (const char *[]){
1082 "csi1_clk_src",
1083 },
1084 .num_parents = 1,
1085 .flags = CLK_SET_RATE_PARENT,
1086 .ops = &clk_branch2_ops,
1087 },
1088 },
1089};
1090
1091static struct clk_branch camss_csi1phy_clk = {
1092 .halt_reg = 0x3134,
1093 .clkr = {
1094 .enable_reg = 0x3134,
1095 .enable_mask = BIT(0),
1096 .hw.init = &(struct clk_init_data){
1097 .name = "camss_csi1phy_clk",
1098 .parent_names = (const char *[]){
1099 "csi1_clk_src",
1100 },
1101 .num_parents = 1,
1102 .flags = CLK_SET_RATE_PARENT,
1103 .ops = &clk_branch2_ops,
1104 },
1105 },
1106};
1107
1108static struct clk_branch camss_csi1pix_clk = {
1109 .halt_reg = 0x3154,
1110 .clkr = {
1111 .enable_reg = 0x3154,
1112 .enable_mask = BIT(0),
1113 .hw.init = &(struct clk_init_data){
1114 .name = "camss_csi1pix_clk",
1115 .parent_names = (const char *[]){
1116 "csi1_clk_src",
1117 },
1118 .num_parents = 1,
1119 .flags = CLK_SET_RATE_PARENT,
1120 .ops = &clk_branch2_ops,
1121 },
1122 },
1123};
1124
1125static struct clk_branch camss_csi1rdi_clk = {
1126 .halt_reg = 0x3144,
1127 .clkr = {
1128 .enable_reg = 0x3144,
1129 .enable_mask = BIT(0),
1130 .hw.init = &(struct clk_init_data){
1131 .name = "camss_csi1rdi_clk",
1132 .parent_names = (const char *[]){
1133 "csi1_clk_src",
1134 },
1135 .num_parents = 1,
1136 .flags = CLK_SET_RATE_PARENT,
1137 .ops = &clk_branch2_ops,
1138 },
1139 },
1140};
1141
1142static struct clk_branch camss_csi2_ahb_clk = {
1143 .halt_reg = 0x3188,
1144 .clkr = {
1145 .enable_reg = 0x3188,
1146 .enable_mask = BIT(0),
1147 .hw.init = &(struct clk_init_data){
1148 .name = "camss_csi2_ahb_clk",
1149 .parent_names = (const char *[]){
1150 "mmss_ahb_clk_src",
1151 },
1152 .num_parents = 1,
1153 .ops = &clk_branch2_ops,
1154 },
1155 },
1156};
1157
1158static struct clk_branch camss_csi2_clk = {
1159 .halt_reg = 0x3184,
1160 .clkr = {
1161 .enable_reg = 0x3184,
1162 .enable_mask = BIT(0),
1163 .hw.init = &(struct clk_init_data){
1164 .name = "camss_csi2_clk",
1165 .parent_names = (const char *[]){
1166 "csi2_clk_src",
1167 },
1168 .num_parents = 1,
1169 .flags = CLK_SET_RATE_PARENT,
1170 .ops = &clk_branch2_ops,
1171 },
1172 },
1173};
1174
1175static struct clk_branch camss_csi2phy_clk = {
1176 .halt_reg = 0x3194,
1177 .clkr = {
1178 .enable_reg = 0x3194,
1179 .enable_mask = BIT(0),
1180 .hw.init = &(struct clk_init_data){
1181 .name = "camss_csi2phy_clk",
1182 .parent_names = (const char *[]){
1183 "csi2_clk_src",
1184 },
1185 .num_parents = 1,
1186 .flags = CLK_SET_RATE_PARENT,
1187 .ops = &clk_branch2_ops,
1188 },
1189 },
1190};
1191
1192static struct clk_branch camss_csi2pix_clk = {
1193 .halt_reg = 0x31b4,
1194 .clkr = {
1195 .enable_reg = 0x31b4,
1196 .enable_mask = BIT(0),
1197 .hw.init = &(struct clk_init_data){
1198 .name = "camss_csi2pix_clk",
1199 .parent_names = (const char *[]){
1200 "csi2_clk_src",
1201 },
1202 .num_parents = 1,
1203 .flags = CLK_SET_RATE_PARENT,
1204 .ops = &clk_branch2_ops,
1205 },
1206 },
1207};
1208
1209static struct clk_branch camss_csi2rdi_clk = {
1210 .halt_reg = 0x31a4,
1211 .clkr = {
1212 .enable_reg = 0x31a4,
1213 .enable_mask = BIT(0),
1214 .hw.init = &(struct clk_init_data){
1215 .name = "camss_csi2rdi_clk",
1216 .parent_names = (const char *[]){
1217 "csi2_clk_src",
1218 },
1219 .num_parents = 1,
1220 .flags = CLK_SET_RATE_PARENT,
1221 .ops = &clk_branch2_ops,
1222 },
1223 },
1224};
1225
1226static struct clk_branch camss_csi3_ahb_clk = {
1227 .halt_reg = 0x31e8,
1228 .clkr = {
1229 .enable_reg = 0x31e8,
1230 .enable_mask = BIT(0),
1231 .hw.init = &(struct clk_init_data){
1232 .name = "camss_csi3_ahb_clk",
1233 .parent_names = (const char *[]){
1234 "mmss_ahb_clk_src",
1235 },
1236 .num_parents = 1,
1237 .ops = &clk_branch2_ops,
1238 },
1239 },
1240};
1241
1242static struct clk_branch camss_csi3_clk = {
1243 .halt_reg = 0x31e4,
1244 .clkr = {
1245 .enable_reg = 0x31e4,
1246 .enable_mask = BIT(0),
1247 .hw.init = &(struct clk_init_data){
1248 .name = "camss_csi3_clk",
1249 .parent_names = (const char *[]){
1250 "csi3_clk_src",
1251 },
1252 .num_parents = 1,
1253 .flags = CLK_SET_RATE_PARENT,
1254 .ops = &clk_branch2_ops,
1255 },
1256 },
1257};
1258
1259static struct clk_branch camss_csi3phy_clk = {
1260 .halt_reg = 0x31f4,
1261 .clkr = {
1262 .enable_reg = 0x31f4,
1263 .enable_mask = BIT(0),
1264 .hw.init = &(struct clk_init_data){
1265 .name = "camss_csi3phy_clk",
1266 .parent_names = (const char *[]){
1267 "csi3_clk_src",
1268 },
1269 .num_parents = 1,
1270 .flags = CLK_SET_RATE_PARENT,
1271 .ops = &clk_branch2_ops,
1272 },
1273 },
1274};
1275
1276static struct clk_branch camss_csi3pix_clk = {
1277 .halt_reg = 0x3214,
1278 .clkr = {
1279 .enable_reg = 0x3214,
1280 .enable_mask = BIT(0),
1281 .hw.init = &(struct clk_init_data){
1282 .name = "camss_csi3pix_clk",
1283 .parent_names = (const char *[]){
1284 "csi3_clk_src",
1285 },
1286 .num_parents = 1,
1287 .flags = CLK_SET_RATE_PARENT,
1288 .ops = &clk_branch2_ops,
1289 },
1290 },
1291};
1292
1293static struct clk_branch camss_csi3rdi_clk = {
1294 .halt_reg = 0x3204,
1295 .clkr = {
1296 .enable_reg = 0x3204,
1297 .enable_mask = BIT(0),
1298 .hw.init = &(struct clk_init_data){
1299 .name = "camss_csi3rdi_clk",
1300 .parent_names = (const char *[]){
1301 "csi3_clk_src",
1302 },
1303 .num_parents = 1,
1304 .flags = CLK_SET_RATE_PARENT,
1305 .ops = &clk_branch2_ops,
1306 },
1307 },
1308};
1309
1310static struct clk_branch camss_csi_vfe0_clk = {
1311 .halt_reg = 0x3704,
1312 .clkr = {
1313 .enable_reg = 0x3704,
1314 .enable_mask = BIT(0),
1315 .hw.init = &(struct clk_init_data){
1316 .name = "camss_csi_vfe0_clk",
1317 .parent_names = (const char *[]){
1318 "vfe0_clk_src",
1319 },
1320 .num_parents = 1,
1321 .flags = CLK_SET_RATE_PARENT,
1322 .ops = &clk_branch2_ops,
1323 },
1324 },
1325};
1326
1327static struct clk_branch camss_csi_vfe1_clk = {
1328 .halt_reg = 0x3714,
1329 .clkr = {
1330 .enable_reg = 0x3714,
1331 .enable_mask = BIT(0),
1332 .hw.init = &(struct clk_init_data){
1333 .name = "camss_csi_vfe1_clk",
1334 .parent_names = (const char *[]){
1335 "vfe1_clk_src",
1336 },
1337 .num_parents = 1,
1338 .flags = CLK_SET_RATE_PARENT,
1339 .ops = &clk_branch2_ops,
1340 },
1341 },
1342};
1343
1344static struct clk_branch camss_gp0_clk = {
1345 .halt_reg = 0x3444,
1346 .clkr = {
1347 .enable_reg = 0x3444,
1348 .enable_mask = BIT(0),
1349 .hw.init = &(struct clk_init_data){
1350 .name = "camss_gp0_clk",
1351 .parent_names = (const char *[]){
1352 "camss_gp0_clk_src",
1353 },
1354 .num_parents = 1,
1355 .flags = CLK_SET_RATE_PARENT,
1356 .ops = &clk_branch2_ops,
1357 },
1358 },
1359};
1360
1361static struct clk_branch camss_gp1_clk = {
1362 .halt_reg = 0x3474,
1363 .clkr = {
1364 .enable_reg = 0x3474,
1365 .enable_mask = BIT(0),
1366 .hw.init = &(struct clk_init_data){
1367 .name = "camss_gp1_clk",
1368 .parent_names = (const char *[]){
1369 "camss_gp1_clk_src",
1370 },
1371 .num_parents = 1,
1372 .flags = CLK_SET_RATE_PARENT,
1373 .ops = &clk_branch2_ops,
1374 },
1375 },
1376};
1377
1378static struct clk_branch camss_ispif_ahb_clk = {
1379 .halt_reg = 0x3224,
1380 .clkr = {
1381 .enable_reg = 0x3224,
1382 .enable_mask = BIT(0),
1383 .hw.init = &(struct clk_init_data){
1384 .name = "camss_ispif_ahb_clk",
1385 .parent_names = (const char *[]){
1386 "mmss_ahb_clk_src",
1387 },
1388 .num_parents = 1,
1389 .ops = &clk_branch2_ops,
1390 },
1391 },
1392};
1393
1394static struct clk_branch camss_jpeg_jpeg0_clk = {
1395 .halt_reg = 0x35a8,
1396 .clkr = {
1397 .enable_reg = 0x35a8,
1398 .enable_mask = BIT(0),
1399 .hw.init = &(struct clk_init_data){
1400 .name = "camss_jpeg_jpeg0_clk",
1401 .parent_names = (const char *[]){
1402 "jpeg0_clk_src",
1403 },
1404 .num_parents = 1,
1405 .flags = CLK_SET_RATE_PARENT,
1406 .ops = &clk_branch2_ops,
1407 },
1408 },
1409};
1410
1411static struct clk_branch camss_jpeg_jpeg1_clk = {
1412 .halt_reg = 0x35ac,
1413 .clkr = {
1414 .enable_reg = 0x35ac,
1415 .enable_mask = BIT(0),
1416 .hw.init = &(struct clk_init_data){
1417 .name = "camss_jpeg_jpeg1_clk",
1418 .parent_names = (const char *[]){
1419 "jpeg1_clk_src",
1420 },
1421 .num_parents = 1,
1422 .flags = CLK_SET_RATE_PARENT,
1423 .ops = &clk_branch2_ops,
1424 },
1425 },
1426};
1427
1428static struct clk_branch camss_jpeg_jpeg2_clk = {
1429 .halt_reg = 0x35b0,
1430 .clkr = {
1431 .enable_reg = 0x35b0,
1432 .enable_mask = BIT(0),
1433 .hw.init = &(struct clk_init_data){
1434 .name = "camss_jpeg_jpeg2_clk",
1435 .parent_names = (const char *[]){
1436 "jpeg2_clk_src",
1437 },
1438 .num_parents = 1,
1439 .flags = CLK_SET_RATE_PARENT,
1440 .ops = &clk_branch2_ops,
1441 },
1442 },
1443};
1444
1445static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
1446 .halt_reg = 0x35b4,
1447 .clkr = {
1448 .enable_reg = 0x35b4,
1449 .enable_mask = BIT(0),
1450 .hw.init = &(struct clk_init_data){
1451 .name = "camss_jpeg_jpeg_ahb_clk",
1452 .parent_names = (const char *[]){
1453 "mmss_ahb_clk_src",
1454 },
1455 .num_parents = 1,
1456 .ops = &clk_branch2_ops,
1457 },
1458 },
1459};
1460
1461static struct clk_branch camss_jpeg_jpeg_axi_clk = {
1462 .halt_reg = 0x35b8,
1463 .clkr = {
1464 .enable_reg = 0x35b8,
1465 .enable_mask = BIT(0),
1466 .hw.init = &(struct clk_init_data){
1467 .name = "camss_jpeg_jpeg_axi_clk",
1468 .parent_names = (const char *[]){
1469 "mmss_axi_clk_src",
1470 },
1471 .num_parents = 1,
1472 .ops = &clk_branch2_ops,
1473 },
1474 },
1475};
1476
1477static struct clk_branch camss_jpeg_jpeg_ocmemnoc_clk = {
1478 .halt_reg = 0x35bc,
1479 .clkr = {
1480 .enable_reg = 0x35bc,
1481 .enable_mask = BIT(0),
1482 .hw.init = &(struct clk_init_data){
1483 .name = "camss_jpeg_jpeg_ocmemnoc_clk",
1484 .parent_names = (const char *[]){
1485 "ocmemnoc_clk_src",
1486 },
1487 .num_parents = 1,
1488 .flags = CLK_SET_RATE_PARENT,
1489 .ops = &clk_branch2_ops,
1490 },
1491 },
1492};
1493
1494static struct clk_branch camss_mclk0_clk = {
1495 .halt_reg = 0x3384,
1496 .clkr = {
1497 .enable_reg = 0x3384,
1498 .enable_mask = BIT(0),
1499 .hw.init = &(struct clk_init_data){
1500 .name = "camss_mclk0_clk",
1501 .parent_names = (const char *[]){
1502 "mclk0_clk_src",
1503 },
1504 .num_parents = 1,
1505 .flags = CLK_SET_RATE_PARENT,
1506 .ops = &clk_branch2_ops,
1507 },
1508 },
1509};
1510
1511static struct clk_branch camss_mclk1_clk = {
1512 .halt_reg = 0x33b4,
1513 .clkr = {
1514 .enable_reg = 0x33b4,
1515 .enable_mask = BIT(0),
1516 .hw.init = &(struct clk_init_data){
1517 .name = "camss_mclk1_clk",
1518 .parent_names = (const char *[]){
1519 "mclk1_clk_src",
1520 },
1521 .num_parents = 1,
1522 .flags = CLK_SET_RATE_PARENT,
1523 .ops = &clk_branch2_ops,
1524 },
1525 },
1526};
1527
1528static struct clk_branch camss_mclk2_clk = {
1529 .halt_reg = 0x33e4,
1530 .clkr = {
1531 .enable_reg = 0x33e4,
1532 .enable_mask = BIT(0),
1533 .hw.init = &(struct clk_init_data){
1534 .name = "camss_mclk2_clk",
1535 .parent_names = (const char *[]){
1536 "mclk2_clk_src",
1537 },
1538 .num_parents = 1,
1539 .flags = CLK_SET_RATE_PARENT,
1540 .ops = &clk_branch2_ops,
1541 },
1542 },
1543};
1544
1545static struct clk_branch camss_mclk3_clk = {
1546 .halt_reg = 0x3414,
1547 .clkr = {
1548 .enable_reg = 0x3414,
1549 .enable_mask = BIT(0),
1550 .hw.init = &(struct clk_init_data){
1551 .name = "camss_mclk3_clk",
1552 .parent_names = (const char *[]){
1553 "mclk3_clk_src",
1554 },
1555 .num_parents = 1,
1556 .flags = CLK_SET_RATE_PARENT,
1557 .ops = &clk_branch2_ops,
1558 },
1559 },
1560};
1561
1562static struct clk_branch camss_micro_ahb_clk = {
1563 .halt_reg = 0x3494,
1564 .clkr = {
1565 .enable_reg = 0x3494,
1566 .enable_mask = BIT(0),
1567 .hw.init = &(struct clk_init_data){
1568 .name = "camss_micro_ahb_clk",
1569 .parent_names = (const char *[]){
1570 "mmss_ahb_clk_src",
1571 },
1572 .num_parents = 1,
1573 .ops = &clk_branch2_ops,
1574 },
1575 },
1576};
1577
1578static struct clk_branch camss_phy0_csi0phytimer_clk = {
1579 .halt_reg = 0x3024,
1580 .clkr = {
1581 .enable_reg = 0x3024,
1582 .enable_mask = BIT(0),
1583 .hw.init = &(struct clk_init_data){
1584 .name = "camss_phy0_csi0phytimer_clk",
1585 .parent_names = (const char *[]){
1586 "csi0phytimer_clk_src",
1587 },
1588 .num_parents = 1,
1589 .flags = CLK_SET_RATE_PARENT,
1590 .ops = &clk_branch2_ops,
1591 },
1592 },
1593};
1594
1595static struct clk_branch camss_phy1_csi1phytimer_clk = {
1596 .halt_reg = 0x3054,
1597 .clkr = {
1598 .enable_reg = 0x3054,
1599 .enable_mask = BIT(0),
1600 .hw.init = &(struct clk_init_data){
1601 .name = "camss_phy1_csi1phytimer_clk",
1602 .parent_names = (const char *[]){
1603 "csi1phytimer_clk_src",
1604 },
1605 .num_parents = 1,
1606 .flags = CLK_SET_RATE_PARENT,
1607 .ops = &clk_branch2_ops,
1608 },
1609 },
1610};
1611
1612static struct clk_branch camss_phy2_csi2phytimer_clk = {
1613 .halt_reg = 0x3084,
1614 .clkr = {
1615 .enable_reg = 0x3084,
1616 .enable_mask = BIT(0),
1617 .hw.init = &(struct clk_init_data){
1618 .name = "camss_phy2_csi2phytimer_clk",
1619 .parent_names = (const char *[]){
1620 "csi2phytimer_clk_src",
1621 },
1622 .num_parents = 1,
1623 .flags = CLK_SET_RATE_PARENT,
1624 .ops = &clk_branch2_ops,
1625 },
1626 },
1627};
1628
1629static struct clk_branch camss_top_ahb_clk = {
1630 .halt_reg = 0x3484,
1631 .clkr = {
1632 .enable_reg = 0x3484,
1633 .enable_mask = BIT(0),
1634 .hw.init = &(struct clk_init_data){
1635 .name = "camss_top_ahb_clk",
1636 .parent_names = (const char *[]){
1637 "mmss_ahb_clk_src",
1638 },
1639 .num_parents = 1,
1640 .ops = &clk_branch2_ops,
1641 },
1642 },
1643};
1644
1645static struct clk_branch camss_vfe_cpp_ahb_clk = {
1646 .halt_reg = 0x36b4,
1647 .clkr = {
1648 .enable_reg = 0x36b4,
1649 .enable_mask = BIT(0),
1650 .hw.init = &(struct clk_init_data){
1651 .name = "camss_vfe_cpp_ahb_clk",
1652 .parent_names = (const char *[]){
1653 "mmss_ahb_clk_src",
1654 },
1655 .num_parents = 1,
1656 .ops = &clk_branch2_ops,
1657 },
1658 },
1659};
1660
1661static struct clk_branch camss_vfe_cpp_clk = {
1662 .halt_reg = 0x36b0,
1663 .clkr = {
1664 .enable_reg = 0x36b0,
1665 .enable_mask = BIT(0),
1666 .hw.init = &(struct clk_init_data){
1667 .name = "camss_vfe_cpp_clk",
1668 .parent_names = (const char *[]){
1669 "cpp_clk_src",
1670 },
1671 .num_parents = 1,
1672 .flags = CLK_SET_RATE_PARENT,
1673 .ops = &clk_branch2_ops,
1674 },
1675 },
1676};
1677
1678static struct clk_branch camss_vfe_vfe0_clk = {
1679 .halt_reg = 0x36a8,
1680 .clkr = {
1681 .enable_reg = 0x36a8,
1682 .enable_mask = BIT(0),
1683 .hw.init = &(struct clk_init_data){
1684 .name = "camss_vfe_vfe0_clk",
1685 .parent_names = (const char *[]){
1686 "vfe0_clk_src",
1687 },
1688 .num_parents = 1,
1689 .flags = CLK_SET_RATE_PARENT,
1690 .ops = &clk_branch2_ops,
1691 },
1692 },
1693};
1694
1695static struct clk_branch camss_vfe_vfe1_clk = {
1696 .halt_reg = 0x36ac,
1697 .clkr = {
1698 .enable_reg = 0x36ac,
1699 .enable_mask = BIT(0),
1700 .hw.init = &(struct clk_init_data){
1701 .name = "camss_vfe_vfe1_clk",
1702 .parent_names = (const char *[]){
1703 "vfe1_clk_src",
1704 },
1705 .num_parents = 1,
1706 .flags = CLK_SET_RATE_PARENT,
1707 .ops = &clk_branch2_ops,
1708 },
1709 },
1710};
1711
1712static struct clk_branch camss_vfe_vfe_ahb_clk = {
1713 .halt_reg = 0x36b8,
1714 .clkr = {
1715 .enable_reg = 0x36b8,
1716 .enable_mask = BIT(0),
1717 .hw.init = &(struct clk_init_data){
1718 .name = "camss_vfe_vfe_ahb_clk",
1719 .parent_names = (const char *[]){
1720 "mmss_ahb_clk_src",
1721 },
1722 .num_parents = 1,
1723 .ops = &clk_branch2_ops,
1724 },
1725 },
1726};
1727
1728static struct clk_branch camss_vfe_vfe_axi_clk = {
1729 .halt_reg = 0x36bc,
1730 .clkr = {
1731 .enable_reg = 0x36bc,
1732 .enable_mask = BIT(0),
1733 .hw.init = &(struct clk_init_data){
1734 .name = "camss_vfe_vfe_axi_clk",
1735 .parent_names = (const char *[]){
1736 "mmss_axi_clk_src",
1737 },
1738 .num_parents = 1,
1739 .ops = &clk_branch2_ops,
1740 },
1741 },
1742};
1743
1744static struct clk_branch camss_vfe_vfe_ocmemnoc_clk = {
1745 .halt_reg = 0x36c0,
1746 .clkr = {
1747 .enable_reg = 0x36c0,
1748 .enable_mask = BIT(0),
1749 .hw.init = &(struct clk_init_data){
1750 .name = "camss_vfe_vfe_ocmemnoc_clk",
1751 .parent_names = (const char *[]){
1752 "ocmemnoc_clk_src",
1753 },
1754 .num_parents = 1,
1755 .flags = CLK_SET_RATE_PARENT,
1756 .ops = &clk_branch2_ops,
1757 },
1758 },
1759};
1760
1761static struct clk_branch mdss_ahb_clk = {
1762 .halt_reg = 0x2308,
1763 .clkr = {
1764 .enable_reg = 0x2308,
1765 .enable_mask = BIT(0),
1766 .hw.init = &(struct clk_init_data){
1767 .name = "mdss_ahb_clk",
1768 .parent_names = (const char *[]){
1769 "mmss_ahb_clk_src",
1770 },
1771 .num_parents = 1,
1772 .ops = &clk_branch2_ops,
1773 },
1774 },
1775};
1776
1777static struct clk_branch mdss_axi_clk = {
1778 .halt_reg = 0x2310,
1779 .clkr = {
1780 .enable_reg = 0x2310,
1781 .enable_mask = BIT(0),
1782 .hw.init = &(struct clk_init_data){
1783 .name = "mdss_axi_clk",
1784 .parent_names = (const char *[]){
1785 "mmss_axi_clk_src",
1786 },
1787 .num_parents = 1,
1788 .flags = CLK_SET_RATE_PARENT,
1789 .ops = &clk_branch2_ops,
1790 },
1791 },
1792};
1793
1794static struct clk_branch mdss_byte0_clk = {
1795 .halt_reg = 0x233c,
1796 .clkr = {
1797 .enable_reg = 0x233c,
1798 .enable_mask = BIT(0),
1799 .hw.init = &(struct clk_init_data){
1800 .name = "mdss_byte0_clk",
1801 .parent_names = (const char *[]){
1802 "byte0_clk_src",
1803 },
1804 .num_parents = 1,
1805 .flags = CLK_SET_RATE_PARENT,
1806 .ops = &clk_branch2_ops,
1807 },
1808 },
1809};
1810
1811static struct clk_branch mdss_byte1_clk = {
1812 .halt_reg = 0x2340,
1813 .clkr = {
1814 .enable_reg = 0x2340,
1815 .enable_mask = BIT(0),
1816 .hw.init = &(struct clk_init_data){
1817 .name = "mdss_byte1_clk",
1818 .parent_names = (const char *[]){
1819 "byte1_clk_src",
1820 },
1821 .num_parents = 1,
1822 .flags = CLK_SET_RATE_PARENT,
1823 .ops = &clk_branch2_ops,
1824 },
1825 },
1826};
1827
1828static struct clk_branch mdss_edpaux_clk = {
1829 .halt_reg = 0x2334,
1830 .clkr = {
1831 .enable_reg = 0x2334,
1832 .enable_mask = BIT(0),
1833 .hw.init = &(struct clk_init_data){
1834 .name = "mdss_edpaux_clk",
1835 .parent_names = (const char *[]){
1836 "edpaux_clk_src",
1837 },
1838 .num_parents = 1,
1839 .flags = CLK_SET_RATE_PARENT,
1840 .ops = &clk_branch2_ops,
1841 },
1842 },
1843};
1844
1845static struct clk_branch mdss_edplink_clk = {
1846 .halt_reg = 0x2330,
1847 .clkr = {
1848 .enable_reg = 0x2330,
1849 .enable_mask = BIT(0),
1850 .hw.init = &(struct clk_init_data){
1851 .name = "mdss_edplink_clk",
1852 .parent_names = (const char *[]){
1853 "edplink_clk_src",
1854 },
1855 .num_parents = 1,
1856 .flags = CLK_SET_RATE_PARENT,
1857 .ops = &clk_branch2_ops,
1858 },
1859 },
1860};
1861
1862static struct clk_branch mdss_edppixel_clk = {
1863 .halt_reg = 0x232c,
1864 .clkr = {
1865 .enable_reg = 0x232c,
1866 .enable_mask = BIT(0),
1867 .hw.init = &(struct clk_init_data){
1868 .name = "mdss_edppixel_clk",
1869 .parent_names = (const char *[]){
1870 "edppixel_clk_src",
1871 },
1872 .num_parents = 1,
1873 .flags = CLK_SET_RATE_PARENT,
1874 .ops = &clk_branch2_ops,
1875 },
1876 },
1877};
1878
1879static struct clk_branch mdss_esc0_clk = {
1880 .halt_reg = 0x2344,
1881 .clkr = {
1882 .enable_reg = 0x2344,
1883 .enable_mask = BIT(0),
1884 .hw.init = &(struct clk_init_data){
1885 .name = "mdss_esc0_clk",
1886 .parent_names = (const char *[]){
1887 "esc0_clk_src",
1888 },
1889 .num_parents = 1,
1890 .flags = CLK_SET_RATE_PARENT,
1891 .ops = &clk_branch2_ops,
1892 },
1893 },
1894};
1895
1896static struct clk_branch mdss_esc1_clk = {
1897 .halt_reg = 0x2348,
1898 .clkr = {
1899 .enable_reg = 0x2348,
1900 .enable_mask = BIT(0),
1901 .hw.init = &(struct clk_init_data){
1902 .name = "mdss_esc1_clk",
1903 .parent_names = (const char *[]){
1904 "esc1_clk_src",
1905 },
1906 .num_parents = 1,
1907 .flags = CLK_SET_RATE_PARENT,
1908 .ops = &clk_branch2_ops,
1909 },
1910 },
1911};
1912
1913static struct clk_branch mdss_extpclk_clk = {
1914 .halt_reg = 0x2324,
1915 .clkr = {
1916 .enable_reg = 0x2324,
1917 .enable_mask = BIT(0),
1918 .hw.init = &(struct clk_init_data){
1919 .name = "mdss_extpclk_clk",
1920 .parent_names = (const char *[]){
1921 "extpclk_clk_src",
1922 },
1923 .num_parents = 1,
1924 .flags = CLK_SET_RATE_PARENT,
1925 .ops = &clk_branch2_ops,
1926 },
1927 },
1928};
1929
1930static struct clk_branch mdss_hdmi_ahb_clk = {
1931 .halt_reg = 0x230c,
1932 .clkr = {
1933 .enable_reg = 0x230c,
1934 .enable_mask = BIT(0),
1935 .hw.init = &(struct clk_init_data){
1936 .name = "mdss_hdmi_ahb_clk",
1937 .parent_names = (const char *[]){
1938 "mmss_ahb_clk_src",
1939 },
1940 .num_parents = 1,
1941 .ops = &clk_branch2_ops,
1942 },
1943 },
1944};
1945
1946static struct clk_branch mdss_hdmi_clk = {
1947 .halt_reg = 0x2338,
1948 .clkr = {
1949 .enable_reg = 0x2338,
1950 .enable_mask = BIT(0),
1951 .hw.init = &(struct clk_init_data){
1952 .name = "mdss_hdmi_clk",
1953 .parent_names = (const char *[]){
1954 "hdmi_clk_src",
1955 },
1956 .num_parents = 1,
1957 .flags = CLK_SET_RATE_PARENT,
1958 .ops = &clk_branch2_ops,
1959 },
1960 },
1961};
1962
1963static struct clk_branch mdss_mdp_clk = {
1964 .halt_reg = 0x231c,
1965 .clkr = {
1966 .enable_reg = 0x231c,
1967 .enable_mask = BIT(0),
1968 .hw.init = &(struct clk_init_data){
1969 .name = "mdss_mdp_clk",
1970 .parent_names = (const char *[]){
1971 "mdp_clk_src",
1972 },
1973 .num_parents = 1,
1974 .flags = CLK_SET_RATE_PARENT,
1975 .ops = &clk_branch2_ops,
1976 },
1977 },
1978};
1979
1980static struct clk_branch mdss_mdp_lut_clk = {
1981 .halt_reg = 0x2320,
1982 .clkr = {
1983 .enable_reg = 0x2320,
1984 .enable_mask = BIT(0),
1985 .hw.init = &(struct clk_init_data){
1986 .name = "mdss_mdp_lut_clk",
1987 .parent_names = (const char *[]){
1988 "mdp_clk_src",
1989 },
1990 .num_parents = 1,
1991 .flags = CLK_SET_RATE_PARENT,
1992 .ops = &clk_branch2_ops,
1993 },
1994 },
1995};
1996
1997static struct clk_branch mdss_pclk0_clk = {
1998 .halt_reg = 0x2314,
1999 .clkr = {
2000 .enable_reg = 0x2314,
2001 .enable_mask = BIT(0),
2002 .hw.init = &(struct clk_init_data){
2003 .name = "mdss_pclk0_clk",
2004 .parent_names = (const char *[]){
2005 "pclk0_clk_src",
2006 },
2007 .num_parents = 1,
2008 .flags = CLK_SET_RATE_PARENT,
2009 .ops = &clk_branch2_ops,
2010 },
2011 },
2012};
2013
2014static struct clk_branch mdss_pclk1_clk = {
2015 .halt_reg = 0x2318,
2016 .clkr = {
2017 .enable_reg = 0x2318,
2018 .enable_mask = BIT(0),
2019 .hw.init = &(struct clk_init_data){
2020 .name = "mdss_pclk1_clk",
2021 .parent_names = (const char *[]){
2022 "pclk1_clk_src",
2023 },
2024 .num_parents = 1,
2025 .flags = CLK_SET_RATE_PARENT,
2026 .ops = &clk_branch2_ops,
2027 },
2028 },
2029};
2030
2031static struct clk_branch mdss_vsync_clk = {
2032 .halt_reg = 0x2328,
2033 .clkr = {
2034 .enable_reg = 0x2328,
2035 .enable_mask = BIT(0),
2036 .hw.init = &(struct clk_init_data){
2037 .name = "mdss_vsync_clk",
2038 .parent_names = (const char *[]){
2039 "vsync_clk_src",
2040 },
2041 .num_parents = 1,
2042 .flags = CLK_SET_RATE_PARENT,
2043 .ops = &clk_branch2_ops,
2044 },
2045 },
2046};
2047
2048static struct clk_branch mmss_misc_ahb_clk = {
2049 .halt_reg = 0x502c,
2050 .clkr = {
2051 .enable_reg = 0x502c,
2052 .enable_mask = BIT(0),
2053 .hw.init = &(struct clk_init_data){
2054 .name = "mmss_misc_ahb_clk",
2055 .parent_names = (const char *[]){
2056 "mmss_ahb_clk_src",
2057 },
2058 .num_parents = 1,
2059 .ops = &clk_branch2_ops,
2060 },
2061 },
2062};
2063
2064static struct clk_branch mmss_mmssnoc_ahb_clk = {
2065 .halt_reg = 0x5024,
2066 .clkr = {
2067 .enable_reg = 0x5024,
2068 .enable_mask = BIT(0),
2069 .hw.init = &(struct clk_init_data){
2070 .name = "mmss_mmssnoc_ahb_clk",
2071 .parent_names = (const char *[]){
2072 "mmss_ahb_clk_src",
2073 },
2074 .num_parents = 1,
2075 .ops = &clk_branch2_ops,
2076 .flags = CLK_IGNORE_UNUSED,
2077 },
2078 },
2079};
2080
2081static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
2082 .halt_reg = 0x5028,
2083 .clkr = {
2084 .enable_reg = 0x5028,
2085 .enable_mask = BIT(0),
2086 .hw.init = &(struct clk_init_data){
2087 .name = "mmss_mmssnoc_bto_ahb_clk",
2088 .parent_names = (const char *[]){
2089 "mmss_ahb_clk_src",
2090 },
2091 .num_parents = 1,
2092 .ops = &clk_branch2_ops,
2093 .flags = CLK_IGNORE_UNUSED,
2094 },
2095 },
2096};
2097
2098static struct clk_branch mmss_mmssnoc_axi_clk = {
2099 .halt_reg = 0x506c,
2100 .clkr = {
2101 .enable_reg = 0x506c,
2102 .enable_mask = BIT(0),
2103 .hw.init = &(struct clk_init_data){
2104 .name = "mmss_mmssnoc_axi_clk",
2105 .parent_names = (const char *[]){
2106 "mmss_axi_clk_src",
2107 },
2108 .num_parents = 1,
2109 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2110 .ops = &clk_branch2_ops,
2111 },
2112 },
2113};
2114
2115static struct clk_branch mmss_s0_axi_clk = {
2116 .halt_reg = 0x5064,
2117 .clkr = {
2118 .enable_reg = 0x5064,
2119 .enable_mask = BIT(0),
2120 .hw.init = &(struct clk_init_data){
2121 .name = "mmss_s0_axi_clk",
2122 .parent_names = (const char *[]){
2123 "mmss_axi_clk_src",
2124 },
2125 .num_parents = 1,
2126 .ops = &clk_branch2_ops,
2127 .flags = CLK_IGNORE_UNUSED,
2128 },
2129 },
2130};
2131
2132static struct clk_branch ocmemcx_ahb_clk = {
2133 .halt_reg = 0x405c,
2134 .clkr = {
2135 .enable_reg = 0x405c,
2136 .enable_mask = BIT(0),
2137 .hw.init = &(struct clk_init_data){
2138 .name = "ocmemcx_ahb_clk",
2139 .parent_names = (const char *[]){
2140 "mmss_ahb_clk_src",
2141 },
2142 .num_parents = 1,
2143 .ops = &clk_branch2_ops,
2144 },
2145 },
2146};
2147
2148static struct clk_branch ocmemcx_ocmemnoc_clk = {
2149 .halt_reg = 0x4058,
2150 .clkr = {
2151 .enable_reg = 0x4058,
2152 .enable_mask = BIT(0),
2153 .hw.init = &(struct clk_init_data){
2154 .name = "ocmemcx_ocmemnoc_clk",
2155 .parent_names = (const char *[]){
2156 "ocmemnoc_clk_src",
2157 },
2158 .num_parents = 1,
2159 .flags = CLK_SET_RATE_PARENT,
2160 .ops = &clk_branch2_ops,
2161 },
2162 },
2163};
2164
2165static struct clk_branch oxili_ocmemgx_clk = {
2166 .halt_reg = 0x402c,
2167 .clkr = {
2168 .enable_reg = 0x402c,
2169 .enable_mask = BIT(0),
2170 .hw.init = &(struct clk_init_data){
2171 .name = "oxili_ocmemgx_clk",
2172 .parent_names = (const char *[]){
2173 "gfx3d_clk_src",
2174 },
2175 .num_parents = 1,
2176 .flags = CLK_SET_RATE_PARENT,
2177 .ops = &clk_branch2_ops,
2178 },
2179 },
2180};
2181
2182static struct clk_branch ocmemnoc_clk = {
2183 .halt_reg = 0x50b4,
2184 .clkr = {
2185 .enable_reg = 0x50b4,
2186 .enable_mask = BIT(0),
2187 .hw.init = &(struct clk_init_data){
2188 .name = "ocmemnoc_clk",
2189 .parent_names = (const char *[]){
2190 "ocmemnoc_clk_src",
2191 },
2192 .num_parents = 1,
2193 .flags = CLK_SET_RATE_PARENT,
2194 .ops = &clk_branch2_ops,
2195 },
2196 },
2197};
2198
2199static struct clk_branch oxili_gfx3d_clk = {
2200 .halt_reg = 0x4028,
2201 .clkr = {
2202 .enable_reg = 0x4028,
2203 .enable_mask = BIT(0),
2204 .hw.init = &(struct clk_init_data){
2205 .name = "oxili_gfx3d_clk",
2206 .parent_names = (const char *[]){
2207 "gfx3d_clk_src",
2208 },
2209 .num_parents = 1,
2210 .flags = CLK_SET_RATE_PARENT,
2211 .ops = &clk_branch2_ops,
2212 },
2213 },
2214};
2215
2216static struct clk_branch oxilicx_ahb_clk = {
2217 .halt_reg = 0x403c,
2218 .clkr = {
2219 .enable_reg = 0x403c,
2220 .enable_mask = BIT(0),
2221 .hw.init = &(struct clk_init_data){
2222 .name = "oxilicx_ahb_clk",
2223 .parent_names = (const char *[]){
2224 "mmss_ahb_clk_src",
2225 },
2226 .num_parents = 1,
2227 .ops = &clk_branch2_ops,
2228 },
2229 },
2230};
2231
2232static struct clk_branch oxilicx_axi_clk = {
2233 .halt_reg = 0x4038,
2234 .clkr = {
2235 .enable_reg = 0x4038,
2236 .enable_mask = BIT(0),
2237 .hw.init = &(struct clk_init_data){
2238 .name = "oxilicx_axi_clk",
2239 .parent_names = (const char *[]){
2240 "mmss_axi_clk_src",
2241 },
2242 .num_parents = 1,
2243 .ops = &clk_branch2_ops,
2244 },
2245 },
2246};
2247
2248static struct clk_branch venus0_ahb_clk = {
2249 .halt_reg = 0x1030,
2250 .clkr = {
2251 .enable_reg = 0x1030,
2252 .enable_mask = BIT(0),
2253 .hw.init = &(struct clk_init_data){
2254 .name = "venus0_ahb_clk",
2255 .parent_names = (const char *[]){
2256 "mmss_ahb_clk_src",
2257 },
2258 .num_parents = 1,
2259 .ops = &clk_branch2_ops,
2260 },
2261 },
2262};
2263
2264static struct clk_branch venus0_axi_clk = {
2265 .halt_reg = 0x1034,
2266 .clkr = {
2267 .enable_reg = 0x1034,
2268 .enable_mask = BIT(0),
2269 .hw.init = &(struct clk_init_data){
2270 .name = "venus0_axi_clk",
2271 .parent_names = (const char *[]){
2272 "mmss_axi_clk_src",
2273 },
2274 .num_parents = 1,
2275 .ops = &clk_branch2_ops,
2276 },
2277 },
2278};
2279
2280static struct clk_branch venus0_ocmemnoc_clk = {
2281 .halt_reg = 0x1038,
2282 .clkr = {
2283 .enable_reg = 0x1038,
2284 .enable_mask = BIT(0),
2285 .hw.init = &(struct clk_init_data){
2286 .name = "venus0_ocmemnoc_clk",
2287 .parent_names = (const char *[]){
2288 "ocmemnoc_clk_src",
2289 },
2290 .num_parents = 1,
2291 .flags = CLK_SET_RATE_PARENT,
2292 .ops = &clk_branch2_ops,
2293 },
2294 },
2295};
2296
2297static struct clk_branch venus0_vcodec0_clk = {
2298 .halt_reg = 0x1028,
2299 .clkr = {
2300 .enable_reg = 0x1028,
2301 .enable_mask = BIT(0),
2302 .hw.init = &(struct clk_init_data){
2303 .name = "venus0_vcodec0_clk",
2304 .parent_names = (const char *[]){
2305 "vcodec0_clk_src",
2306 },
2307 .num_parents = 1,
2308 .flags = CLK_SET_RATE_PARENT,
2309 .ops = &clk_branch2_ops,
2310 },
2311 },
2312};
2313
2314static const struct pll_config mmpll1_config = {
2315 .l = 60,
2316 .m = 25,
2317 .n = 32,
2318 .vco_val = 0x0,
2319 .vco_mask = 0x3 << 20,
2320 .pre_div_val = 0x0,
2321 .pre_div_mask = 0x3 << 12,
2322 .post_div_val = 0x0,
2323 .post_div_mask = 0x3 << 8,
2324 .mn_ena_mask = BIT(24),
2325 .main_output_mask = BIT(0),
2326};
2327
2328static struct pll_config mmpll3_config = {
2329 .l = 48,
2330 .m = 7,
2331 .n = 16,
2332 .vco_val = 0x0,
2333 .vco_mask = 0x3 << 20,
2334 .pre_div_val = 0x0,
2335 .pre_div_mask = 0x3 << 12,
2336 .post_div_val = 0x0,
2337 .post_div_mask = 0x3 << 8,
2338 .mn_ena_mask = BIT(24),
2339 .main_output_mask = BIT(0),
2340 .aux_output_mask = BIT(1),
2341};
2342
2343static struct clk_regmap *mmcc_msm8974_clocks[] = {
2344 [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
2345 [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
2346 [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
2347 [MMPLL0] = &mmpll0.clkr,
2348 [MMPLL0_VOTE] = &mmpll0_vote,
2349 [MMPLL1] = &mmpll1.clkr,
2350 [MMPLL1_VOTE] = &mmpll1_vote,
2351 [MMPLL2] = &mmpll2.clkr,
2352 [MMPLL3] = &mmpll3.clkr,
2353 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2354 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2355 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
2356 [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
2357 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2358 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
2359 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2360 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
2361 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2362 [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
2363 [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
2364 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2365 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
2366 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
2367 [CCI_CLK_SRC] = &cci_clk_src.clkr,
2368 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
2369 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
2370 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2371 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2372 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
2373 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
2374 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2375 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2376 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
2377 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2378 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2379 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
2380 [EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr,
2381 [EDPLINK_CLK_SRC] = &edplink_clk_src.clkr,
2382 [EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr,
2383 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2384 [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
2385 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
2386 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
2387 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2388 [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
2389 [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
2390 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
2391 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
2392 [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
2393 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
2394 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
2395 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
2396 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
2397 [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
2398 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
2399 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
2400 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
2401 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
2402 [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
2403 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
2404 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
2405 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
2406 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
2407 [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
2408 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
2409 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
2410 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
2411 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
2412 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
2413 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
2414 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
2415 [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
2416 [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
2417 [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
2418 [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
2419 [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
2420 [CAMSS_JPEG_JPEG_OCMEMNOC_CLK] = &camss_jpeg_jpeg_ocmemnoc_clk.clkr,
2421 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
2422 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
2423 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
2424 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
2425 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
2426 [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
2427 [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
2428 [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
2429 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
2430 [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
2431 [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
2432 [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
2433 [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
2434 [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
2435 [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
2436 [CAMSS_VFE_VFE_OCMEMNOC_CLK] = &camss_vfe_vfe_ocmemnoc_clk.clkr,
2437 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
2438 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
2439 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
2440 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
2441 [MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr,
2442 [MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr,
2443 [MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr,
2444 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
2445 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
2446 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
2447 [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
2448 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
2449 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
2450 [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
2451 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
2452 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
2453 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
2454 [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
2455 [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
2456 [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
2457 [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
2458 [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
2459 [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
2460 [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
2461 [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
2462 [OCMEMNOC_CLK] = &ocmemnoc_clk.clkr,
2463 [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
2464 [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
2465 [OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr,
2466 [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
2467 [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
2468 [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
2469 [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
2470};
2471
2472static const struct qcom_reset_map mmcc_msm8974_resets[] = {
2473 [SPDM_RESET] = { 0x0200 },
2474 [SPDM_RM_RESET] = { 0x0300 },
2475 [VENUS0_RESET] = { 0x1020 },
2476 [MDSS_RESET] = { 0x2300 },
2477 [CAMSS_PHY0_RESET] = { 0x3020 },
2478 [CAMSS_PHY1_RESET] = { 0x3050 },
2479 [CAMSS_PHY2_RESET] = { 0x3080 },
2480 [CAMSS_CSI0_RESET] = { 0x30b0 },
2481 [CAMSS_CSI0PHY_RESET] = { 0x30c0 },
2482 [CAMSS_CSI0RDI_RESET] = { 0x30d0 },
2483 [CAMSS_CSI0PIX_RESET] = { 0x30e0 },
2484 [CAMSS_CSI1_RESET] = { 0x3120 },
2485 [CAMSS_CSI1PHY_RESET] = { 0x3130 },
2486 [CAMSS_CSI1RDI_RESET] = { 0x3140 },
2487 [CAMSS_CSI1PIX_RESET] = { 0x3150 },
2488 [CAMSS_CSI2_RESET] = { 0x3180 },
2489 [CAMSS_CSI2PHY_RESET] = { 0x3190 },
2490 [CAMSS_CSI2RDI_RESET] = { 0x31a0 },
2491 [CAMSS_CSI2PIX_RESET] = { 0x31b0 },
2492 [CAMSS_CSI3_RESET] = { 0x31e0 },
2493 [CAMSS_CSI3PHY_RESET] = { 0x31f0 },
2494 [CAMSS_CSI3RDI_RESET] = { 0x3200 },
2495 [CAMSS_CSI3PIX_RESET] = { 0x3210 },
2496 [CAMSS_ISPIF_RESET] = { 0x3220 },
2497 [CAMSS_CCI_RESET] = { 0x3340 },
2498 [CAMSS_MCLK0_RESET] = { 0x3380 },
2499 [CAMSS_MCLK1_RESET] = { 0x33b0 },
2500 [CAMSS_MCLK2_RESET] = { 0x33e0 },
2501 [CAMSS_MCLK3_RESET] = { 0x3410 },
2502 [CAMSS_GP0_RESET] = { 0x3440 },
2503 [CAMSS_GP1_RESET] = { 0x3470 },
2504 [CAMSS_TOP_RESET] = { 0x3480 },
2505 [CAMSS_MICRO_RESET] = { 0x3490 },
2506 [CAMSS_JPEG_RESET] = { 0x35a0 },
2507 [CAMSS_VFE_RESET] = { 0x36a0 },
2508 [CAMSS_CSI_VFE0_RESET] = { 0x3700 },
2509 [CAMSS_CSI_VFE1_RESET] = { 0x3710 },
2510 [OXILI_RESET] = { 0x4020 },
2511 [OXILICX_RESET] = { 0x4030 },
2512 [OCMEMCX_RESET] = { 0x4050 },
2513 [MMSS_RBCRP_RESET] = { 0x4080 },
2514 [MMSSNOCAHB_RESET] = { 0x5020 },
2515 [MMSSNOCAXI_RESET] = { 0x5060 },
2516 [OCMEMNOC_RESET] = { 0x50b0 },
2517};
2518
2519static const struct regmap_config mmcc_msm8974_regmap_config = {
2520 .reg_bits = 32,
2521 .reg_stride = 4,
2522 .val_bits = 32,
2523 .max_register = 0x5104,
2524 .fast_io = true,
2525};
2526
2527static const struct of_device_id mmcc_msm8974_match_table[] = {
2528 { .compatible = "qcom,mmcc-msm8974" },
2529 { }
2530};
2531MODULE_DEVICE_TABLE(of, mmcc_msm8974_match_table);
2532
2533struct qcom_cc {
2534 struct qcom_reset_controller reset;
2535 struct clk_onecell_data data;
2536 struct clk *clks[];
2537};
2538
2539static int mmcc_msm8974_probe(struct platform_device *pdev)
2540{
2541 void __iomem *base;
2542 struct resource *res;
2543 int i, ret;
2544 struct device *dev = &pdev->dev;
2545 struct clk *clk;
2546 struct clk_onecell_data *data;
2547 struct clk **clks;
2548 struct regmap *regmap;
2549 size_t num_clks;
2550 struct qcom_reset_controller *reset;
2551 struct qcom_cc *cc;
2552
2553 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2554 base = devm_ioremap_resource(dev, res);
2555 if (IS_ERR(base))
2556 return PTR_ERR(base);
2557
2558 regmap = devm_regmap_init_mmio(dev, base, &mmcc_msm8974_regmap_config);
2559 if (IS_ERR(regmap))
2560 return PTR_ERR(regmap);
2561
2562 num_clks = ARRAY_SIZE(mmcc_msm8974_clocks);
2563 cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*clks) * num_clks,
2564 GFP_KERNEL);
2565 if (!cc)
2566 return -ENOMEM;
2567
2568 clks = cc->clks;
2569 data = &cc->data;
2570 data->clks = clks;
2571 data->clk_num = num_clks;
2572
2573 clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
2574 clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
2575
2576 for (i = 0; i < num_clks; i++) {
2577 if (!mmcc_msm8974_clocks[i])
2578 continue;
2579 clk = devm_clk_register_regmap(dev, mmcc_msm8974_clocks[i]);
2580 if (IS_ERR(clk))
2581 return PTR_ERR(clk);
2582 clks[i] = clk;
2583 }
2584
2585 ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, data);
2586 if (ret)
2587 return ret;
2588
2589 reset = &cc->reset;
2590 reset->rcdev.of_node = dev->of_node;
2591 reset->rcdev.ops = &qcom_reset_ops,
2592 reset->rcdev.owner = THIS_MODULE,
2593 reset->rcdev.nr_resets = ARRAY_SIZE(mmcc_msm8974_resets),
2594 reset->regmap = regmap;
2595 reset->reset_map = mmcc_msm8974_resets,
2596 platform_set_drvdata(pdev, &reset->rcdev);
2597
2598 ret = reset_controller_register(&reset->rcdev);
2599 if (ret)
2600 of_clk_del_provider(dev->of_node);
2601
2602 return ret;
2603}
2604
2605static int mmcc_msm8974_remove(struct platform_device *pdev)
2606{
2607 of_clk_del_provider(pdev->dev.of_node);
2608 reset_controller_unregister(platform_get_drvdata(pdev));
2609 return 0;
2610}
2611
2612static struct platform_driver mmcc_msm8974_driver = {
2613 .probe = mmcc_msm8974_probe,
2614 .remove = mmcc_msm8974_remove,
2615 .driver = {
2616 .name = "mmcc-msm8974",
2617 .owner = THIS_MODULE,
2618 .of_match_table = mmcc_msm8974_match_table,
2619 },
2620};
2621module_platform_driver(mmcc_msm8974_driver);
2622
2623MODULE_DESCRIPTION("QCOM MMCC MSM8974 Driver");
2624MODULE_LICENSE("GPL v2");
2625MODULE_ALIAS("platform:mmcc-msm8974");
diff --git a/drivers/clk/qcom/reset.c b/drivers/clk/qcom/reset.c
new file mode 100644
index 000000000000..6c977d3a8590
--- /dev/null
+++ b/drivers/clk/qcom/reset.c
@@ -0,0 +1,63 @@
1/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/bitops.h>
15#include <linux/export.h>
16#include <linux/regmap.h>
17#include <linux/reset-controller.h>
18#include <linux/delay.h>
19
20#include "reset.h"
21
22static int qcom_reset(struct reset_controller_dev *rcdev, unsigned long id)
23{
24 rcdev->ops->assert(rcdev, id);
25 udelay(1);
26 rcdev->ops->deassert(rcdev, id);
27 return 0;
28}
29
30static int
31qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
32{
33 struct qcom_reset_controller *rst;
34 const struct qcom_reset_map *map;
35 u32 mask;
36
37 rst = to_qcom_reset_controller(rcdev);
38 map = &rst->reset_map[id];
39 mask = BIT(map->bit);
40
41 return regmap_update_bits(rst->regmap, map->reg, mask, mask);
42}
43
44static int
45qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
46{
47 struct qcom_reset_controller *rst;
48 const struct qcom_reset_map *map;
49 u32 mask;
50
51 rst = to_qcom_reset_controller(rcdev);
52 map = &rst->reset_map[id];
53 mask = BIT(map->bit);
54
55 return regmap_update_bits(rst->regmap, map->reg, mask, 0);
56}
57
58struct reset_control_ops qcom_reset_ops = {
59 .reset = qcom_reset,
60 .assert = qcom_reset_assert,
61 .deassert = qcom_reset_deassert,
62};
63EXPORT_SYMBOL_GPL(qcom_reset_ops);
diff --git a/drivers/clk/qcom/reset.h b/drivers/clk/qcom/reset.h
new file mode 100644
index 000000000000..0e11e2130f97
--- /dev/null
+++ b/drivers/clk/qcom/reset.h
@@ -0,0 +1,37 @@
1/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef __QCOM_CLK_RESET_H__
15#define __QCOM_CLK_RESET_H__
16
17#include <linux/reset-controller.h>
18
19struct qcom_reset_map {
20 unsigned int reg;
21 u8 bit;
22};
23
24struct regmap;
25
26struct qcom_reset_controller {
27 const struct qcom_reset_map *reset_map;
28 struct regmap *regmap;
29 struct reset_controller_dev rcdev;
30};
31
32#define to_qcom_reset_controller(r) \
33 container_of(r, struct qcom_reset_controller, rcdev);
34
35extern struct reset_control_ops qcom_reset_ops;
36
37#endif
diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c
index 39b40aaede2b..884187fbfe00 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -14,9 +14,17 @@
14#include <linux/clk-provider.h> 14#include <linux/clk-provider.h>
15#include <linux/of_address.h> 15#include <linux/of_address.h>
16#include <linux/syscore_ops.h> 16#include <linux/syscore_ops.h>
17#include <linux/module.h>
18#include <linux/platform_device.h>
17 19
18#include <dt-bindings/clk/exynos-audss-clk.h> 20#include <dt-bindings/clk/exynos-audss-clk.h>
19 21
22enum exynos_audss_clk_type {
23 TYPE_EXYNOS4210,
24 TYPE_EXYNOS5250,
25 TYPE_EXYNOS5420,
26};
27
20static DEFINE_SPINLOCK(lock); 28static DEFINE_SPINLOCK(lock);
21static struct clk **clk_table; 29static struct clk **clk_table;
22static void __iomem *reg_base; 30static void __iomem *reg_base;
@@ -26,17 +34,13 @@ static struct clk_onecell_data clk_data;
26#define ASS_CLK_DIV 0x4 34#define ASS_CLK_DIV 0x4
27#define ASS_CLK_GATE 0x8 35#define ASS_CLK_GATE 0x8
28 36
37#ifdef CONFIG_PM_SLEEP
29static unsigned long reg_save[][2] = { 38static unsigned long reg_save[][2] = {
30 {ASS_CLK_SRC, 0}, 39 {ASS_CLK_SRC, 0},
31 {ASS_CLK_DIV, 0}, 40 {ASS_CLK_DIV, 0},
32 {ASS_CLK_GATE, 0}, 41 {ASS_CLK_GATE, 0},
33}; 42};
34 43
35/* list of all parent clock list */
36static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
37static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };
38
39#ifdef CONFIG_PM_SLEEP
40static int exynos_audss_clk_suspend(void) 44static int exynos_audss_clk_suspend(void)
41{ 45{
42 int i; 46 int i;
@@ -61,31 +65,69 @@ static struct syscore_ops exynos_audss_clk_syscore_ops = {
61}; 65};
62#endif /* CONFIG_PM_SLEEP */ 66#endif /* CONFIG_PM_SLEEP */
63 67
68static const struct of_device_id exynos_audss_clk_of_match[] = {
69 { .compatible = "samsung,exynos4210-audss-clock",
70 .data = (void *)TYPE_EXYNOS4210, },
71 { .compatible = "samsung,exynos5250-audss-clock",
72 .data = (void *)TYPE_EXYNOS5250, },
73 { .compatible = "samsung,exynos5420-audss-clock",
74 .data = (void *)TYPE_EXYNOS5420, },
75 {},
76};
77
64/* register exynos_audss clocks */ 78/* register exynos_audss clocks */
65static void __init exynos_audss_clk_init(struct device_node *np) 79static int exynos_audss_clk_probe(struct platform_device *pdev)
66{ 80{
67 reg_base = of_iomap(np, 0); 81 int i, ret = 0;
68 if (!reg_base) { 82 struct resource *res;
69 pr_err("%s: failed to map audss registers\n", __func__); 83 const char *mout_audss_p[] = {"fin_pll", "fout_epll"};
70 return; 84 const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"};
85 const char *sclk_pcm_p = "sclk_pcm0";
86 struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in;
87 const struct of_device_id *match;
88 enum exynos_audss_clk_type variant;
89
90 match = of_match_node(exynos_audss_clk_of_match, pdev->dev.of_node);
91 if (!match)
92 return -EINVAL;
93 variant = (enum exynos_audss_clk_type)match->data;
94
95 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
96 reg_base = devm_ioremap_resource(&pdev->dev, res);
97 if (IS_ERR(reg_base)) {
98 dev_err(&pdev->dev, "failed to map audss registers\n");
99 return PTR_ERR(reg_base);
71 } 100 }
72 101
73 clk_table = kzalloc(sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS, 102 clk_table = devm_kzalloc(&pdev->dev,
103 sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
74 GFP_KERNEL); 104 GFP_KERNEL);
75 if (!clk_table) { 105 if (!clk_table)
76 pr_err("%s: could not allocate clk lookup table\n", __func__); 106 return -ENOMEM;
77 return;
78 }
79 107
80 clk_data.clks = clk_table; 108 clk_data.clks = clk_table;
81 clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS; 109 if (variant == TYPE_EXYNOS5420)
82 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 110 clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
83 111 else
112 clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS - 1;
113
114 pll_ref = devm_clk_get(&pdev->dev, "pll_ref");
115 pll_in = devm_clk_get(&pdev->dev, "pll_in");
116 if (!IS_ERR(pll_ref))
117 mout_audss_p[0] = __clk_get_name(pll_ref);
118 if (!IS_ERR(pll_in))
119 mout_audss_p[1] = __clk_get_name(pll_in);
84 clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss", 120 clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
85 mout_audss_p, ARRAY_SIZE(mout_audss_p), 121 mout_audss_p, ARRAY_SIZE(mout_audss_p),
86 CLK_SET_RATE_NO_REPARENT, 122 CLK_SET_RATE_NO_REPARENT,
87 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); 123 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
88 124
125 cdclk = devm_clk_get(&pdev->dev, "cdclk");
126 sclk_audio = devm_clk_get(&pdev->dev, "sclk_audio");
127 if (!IS_ERR(cdclk))
128 mout_i2s_p[1] = __clk_get_name(cdclk);
129 if (!IS_ERR(sclk_audio))
130 mout_i2s_p[2] = __clk_get_name(sclk_audio);
89 clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s", 131 clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s",
90 mout_i2s_p, ARRAY_SIZE(mout_i2s_p), 132 mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
91 CLK_SET_RATE_NO_REPARENT, 133 CLK_SET_RATE_NO_REPARENT,
@@ -119,17 +161,88 @@ static void __init exynos_audss_clk_init(struct device_node *np)
119 "sclk_pcm", CLK_SET_RATE_PARENT, 161 "sclk_pcm", CLK_SET_RATE_PARENT,
120 reg_base + ASS_CLK_GATE, 4, 0, &lock); 162 reg_base + ASS_CLK_GATE, 4, 0, &lock);
121 163
164 sclk_pcm_in = devm_clk_get(&pdev->dev, "sclk_pcm_in");
165 if (!IS_ERR(sclk_pcm_in))
166 sclk_pcm_p = __clk_get_name(sclk_pcm_in);
122 clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm", 167 clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm",
123 "div_pcm0", CLK_SET_RATE_PARENT, 168 sclk_pcm_p, CLK_SET_RATE_PARENT,
124 reg_base + ASS_CLK_GATE, 5, 0, &lock); 169 reg_base + ASS_CLK_GATE, 5, 0, &lock);
125 170
171 if (variant == TYPE_EXYNOS5420) {
172 clk_table[EXYNOS_ADMA] = clk_register_gate(NULL, "adma",
173 "dout_srp", CLK_SET_RATE_PARENT,
174 reg_base + ASS_CLK_GATE, 9, 0, &lock);
175 }
176
177 for (i = 0; i < clk_data.clk_num; i++) {
178 if (IS_ERR(clk_table[i])) {
179 dev_err(&pdev->dev, "failed to register clock %d\n", i);
180 ret = PTR_ERR(clk_table[i]);
181 goto unregister;
182 }
183 }
184
185 ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get,
186 &clk_data);
187 if (ret) {
188 dev_err(&pdev->dev, "failed to add clock provider\n");
189 goto unregister;
190 }
191
126#ifdef CONFIG_PM_SLEEP 192#ifdef CONFIG_PM_SLEEP
127 register_syscore_ops(&exynos_audss_clk_syscore_ops); 193 register_syscore_ops(&exynos_audss_clk_syscore_ops);
128#endif 194#endif
129 195
130 pr_info("Exynos: Audss: clock setup completed\n"); 196 dev_info(&pdev->dev, "setup completed\n");
197
198 return 0;
199
200unregister:
201 for (i = 0; i < clk_data.clk_num; i++) {
202 if (!IS_ERR(clk_table[i]))
203 clk_unregister(clk_table[i]);
204 }
205
206 return ret;
207}
208
209static int exynos_audss_clk_remove(struct platform_device *pdev)
210{
211 int i;
212
213 of_clk_del_provider(pdev->dev.of_node);
214
215 for (i = 0; i < clk_data.clk_num; i++) {
216 if (!IS_ERR(clk_table[i]))
217 clk_unregister(clk_table[i]);
218 }
219
220 return 0;
131} 221}
132CLK_OF_DECLARE(exynos4210_audss_clk, "samsung,exynos4210-audss-clock", 222
133 exynos_audss_clk_init); 223static struct platform_driver exynos_audss_clk_driver = {
134CLK_OF_DECLARE(exynos5250_audss_clk, "samsung,exynos5250-audss-clock", 224 .driver = {
135 exynos_audss_clk_init); 225 .name = "exynos-audss-clk",
226 .owner = THIS_MODULE,
227 .of_match_table = exynos_audss_clk_of_match,
228 },
229 .probe = exynos_audss_clk_probe,
230 .remove = exynos_audss_clk_remove,
231};
232
233static int __init exynos_audss_clk_init(void)
234{
235 return platform_driver_register(&exynos_audss_clk_driver);
236}
237core_initcall(exynos_audss_clk_init);
238
239static void __exit exynos_audss_clk_exit(void)
240{
241 platform_driver_unregister(&exynos_audss_clk_driver);
242}
243module_exit(exynos_audss_clk_exit);
244
245MODULE_AUTHOR("Padmavathi Venna <padma.v@samsung.com>");
246MODULE_DESCRIPTION("Exynos Audio Subsystem Clock Controller");
247MODULE_LICENSE("GPL v2");
248MODULE_ALIAS("platform:exynos-audss-clk");
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index ad5ff50c5f28..2f7e440aebf8 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -10,6 +10,7 @@
10 * Common Clock Framework support for all Exynos4 SoCs. 10 * Common Clock Framework support for all Exynos4 SoCs.
11*/ 11*/
12 12
13#include <dt-bindings/clock/exynos4.h>
13#include <linux/clk.h> 14#include <linux/clk.h>
14#include <linux/clkdev.h> 15#include <linux/clkdev.h>
15#include <linux/clk-provider.h> 16#include <linux/clk-provider.h>
@@ -39,7 +40,7 @@
39#define SRC_TOP1 0xc214 40#define SRC_TOP1 0xc214
40#define SRC_CAM 0xc220 41#define SRC_CAM 0xc220
41#define SRC_TV 0xc224 42#define SRC_TV 0xc224
42#define SRC_MFC 0xcc28 43#define SRC_MFC 0xc228
43#define SRC_G3D 0xc22c 44#define SRC_G3D 0xc22c
44#define E4210_SRC_IMAGE 0xc230 45#define E4210_SRC_IMAGE 0xc230
45#define SRC_LCD0 0xc234 46#define SRC_LCD0 0xc234
@@ -130,68 +131,6 @@ enum exynos4_plls {
130}; 131};
131 132
132/* 133/*
133 * Let each supported clock get a unique id. This id is used to lookup the clock
134 * for device tree based platforms. The clocks are categorized into three
135 * sections: core, sclk gate and bus interface gate clocks.
136 *
137 * When adding a new clock to this list, it is advised to choose a clock
138 * category and add it to the end of that category. That is because the the
139 * device tree source file is referring to these ids and any change in the
140 * sequence number of existing clocks will require corresponding change in the
141 * device tree files. This limitation would go away when pre-processor support
142 * for dtc would be available.
143 */
144enum exynos4_clks {
145 none,
146
147 /* core clocks */
148 xxti, xusbxti, fin_pll, fout_apll, fout_mpll, fout_epll, fout_vpll,
149 sclk_apll, sclk_mpll, sclk_epll, sclk_vpll, arm_clk, aclk200, aclk100,
150 aclk160, aclk133, mout_mpll_user_t, mout_mpll_user_c, mout_core,
151 mout_apll, /* 20 */
152
153 /* gate for special clocks (sclk) */
154 sclk_fimc0 = 128, sclk_fimc1, sclk_fimc2, sclk_fimc3, sclk_cam0,
155 sclk_cam1, sclk_csis0, sclk_csis1, sclk_hdmi, sclk_mixer, sclk_dac,
156 sclk_pixel, sclk_fimd0, sclk_mdnie0, sclk_mdnie_pwm0, sclk_mipi0,
157 sclk_audio0, sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_mmc4,
158 sclk_sata, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_uart4,
159 sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
160 sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1,
161 sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0, sclk_g3d, sclk_pwm_isp,
162 sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp, sclk_fimg2d,
163
164 /* gate clocks */
165 fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0,
166 smmu_fimc1, smmu_fimc2, smmu_fimc3, smmu_jpeg, vp, mixer, tvenc, hdmi,
167 smmu_tv, mfc, smmu_mfcl, smmu_mfcr, g3d, g2d, rotator, mdma, smmu_g2d,
168 smmu_rotator, smmu_mdma, fimd0, mie0, mdnie0, dsim0, smmu_fimd0, fimd1,
169 mie1, dsim1, smmu_fimd1, pdma0, pdma1, pcie_phy, sata_phy, tsi, sdmmc0,
170 sdmmc1, sdmmc2, sdmmc3, sdmmc4, sata, sromc, usb_host, usb_device, pcie,
171 onenand, nfcon, smmu_pcie, gps, smmu_gps, uart0, uart1, uart2, uart3,
172 uart4, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c_hdmi, tsadc,
173 spi0, spi1, spi2, i2s1, i2s2, pcm0, i2s0, pcm1, pcm2, pwm, slimbus,
174 spdif, ac97, modemif, chipid, sysreg, hdmi_cec, mct, wdt, rtc, keyif,
175 audss, mipi_hsi, mdma2, pixelasyncm0, pixelasyncm1, fimc_lite0,
176 fimc_lite1, ppmuispx, ppmuispmx, fimc_isp, fimc_drc, fimc_fd, mcuisp,
177 gicisp, smmu_isp, smmu_drc, smmu_fd, smmu_lite0, smmu_lite1, mcuctl_isp,
178 mpwm_isp, i2c0_isp, i2c1_isp, mtcadc_isp, pwm_isp, wdt_isp, uart_isp,
179 asyncaxim, smmu_ispcx, spi0_isp, spi1_isp, pwm_isp_sclk, spi0_isp_sclk,
180 spi1_isp_sclk, uart_isp_sclk, tmu_apbif,
181
182 /* mux clocks */
183 mout_fimc0 = 384, mout_fimc1, mout_fimc2, mout_fimc3, mout_cam0,
184 mout_cam1, mout_csis0, mout_csis1, mout_g3d0, mout_g3d1, mout_g3d,
185 aclk400_mcuisp,
186
187 /* div clocks */
188 div_isp0 = 450, div_isp1, div_mcuisp0, div_mcuisp1, div_aclk200,
189 div_aclk400_mcuisp,
190
191 nr_clks,
192};
193
194/*
195 * list of controller registers to be saved and restored during a 134 * list of controller registers to be saved and restored during a
196 * suspend/resume cycle. 135 * suspend/resume cycle.
197 */ 136 */
@@ -347,255 +286,255 @@ PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
347 286
348/* fixed rate clocks generated outside the soc */ 287/* fixed rate clocks generated outside the soc */
349static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = { 288static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
350 FRATE(xxti, "xxti", NULL, CLK_IS_ROOT, 0), 289 FRATE(CLK_XXTI, "xxti", NULL, CLK_IS_ROOT, 0),
351 FRATE(xusbxti, "xusbxti", NULL, CLK_IS_ROOT, 0), 290 FRATE(CLK_XUSBXTI, "xusbxti", NULL, CLK_IS_ROOT, 0),
352}; 291};
353 292
354/* fixed rate clocks generated inside the soc */ 293/* fixed rate clocks generated inside the soc */
355static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = { 294static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
356 FRATE(none, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000), 295 FRATE(0, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000),
357 FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000), 296 FRATE(0, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
358 FRATE(none, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000), 297 FRATE(0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000),
359}; 298};
360 299
361static struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = { 300static struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = {
362 FRATE(none, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000), 301 FRATE(0, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000),
363}; 302};
364 303
365/* list of mux clocks supported in all exynos4 soc's */ 304/* list of mux clocks supported in all exynos4 soc's */
366static struct samsung_mux_clock exynos4_mux_clks[] __initdata = { 305static struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
367 MUX_FA(mout_apll, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, 306 MUX_FA(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
368 CLK_SET_RATE_PARENT, 0, "mout_apll"), 307 CLK_SET_RATE_PARENT, 0, "mout_apll"),
369 MUX(none, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1), 308 MUX(0, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
370 MUX(none, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1), 309 MUX(0, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1),
371 MUX(none, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1), 310 MUX(0, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
372 MUX_F(mout_g3d1, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1, 311 MUX_F(CLK_MOUT_G3D1, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1,
373 CLK_SET_RATE_PARENT, 0), 312 CLK_SET_RATE_PARENT, 0),
374 MUX_F(mout_g3d, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1, 313 MUX_F(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1,
375 CLK_SET_RATE_PARENT, 0), 314 CLK_SET_RATE_PARENT, 0),
376 MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2), 315 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2),
377 MUX(none, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1), 316 MUX(0, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1),
378 MUX(sclk_epll, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1), 317 MUX(CLK_SCLK_EPLL, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1),
379 MUX(none, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1), 318 MUX(0, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1),
380}; 319};
381 320
382/* list of mux clocks supported in exynos4210 soc */ 321/* list of mux clocks supported in exynos4210 soc */
383static struct samsung_mux_clock exynos4210_mux_early[] __initdata = { 322static struct samsung_mux_clock exynos4210_mux_early[] __initdata = {
384 MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1), 323 MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
385}; 324};
386 325
387static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = { 326static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
388 MUX(none, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1), 327 MUX(0, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1),
389 MUX(none, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1), 328 MUX(0, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1),
390 MUX(none, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1), 329 MUX(0, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1),
391 MUX(none, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1), 330 MUX(0, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1),
392 MUX(none, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1), 331 MUX(0, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1),
393 MUX(none, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1), 332 MUX(0, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1),
394 MUX(none, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1), 333 MUX(0, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1),
395 MUX(none, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1), 334 MUX(0, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1),
396 MUX(none, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1), 335 MUX(0, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1),
397 MUX(none, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4), 336 MUX(0, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4),
398 MUX(none, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4), 337 MUX(0, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4),
399 MUX(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1), 338 MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1),
400 MUX(mout_core, "mout_core", mout_core_p4210, SRC_CPU, 16, 1), 339 MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1),
401 MUX(sclk_vpll, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1), 340 MUX(CLK_SCLK_VPLL, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1),
402 MUX(mout_fimc0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4), 341 MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),
403 MUX(mout_fimc1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4), 342 MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4),
404 MUX(mout_fimc2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4), 343 MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4),
405 MUX(mout_fimc3, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4), 344 MUX(CLK_MOUT_FIMC3, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4),
406 MUX(mout_cam0, "mout_cam0", group1_p4210, SRC_CAM, 16, 4), 345 MUX(CLK_MOUT_CAM0, "mout_cam0", group1_p4210, SRC_CAM, 16, 4),
407 MUX(mout_cam1, "mout_cam1", group1_p4210, SRC_CAM, 20, 4), 346 MUX(CLK_MOUT_CAM1, "mout_cam1", group1_p4210, SRC_CAM, 20, 4),
408 MUX(mout_csis0, "mout_csis0", group1_p4210, SRC_CAM, 24, 4), 347 MUX(CLK_MOUT_CSIS0, "mout_csis0", group1_p4210, SRC_CAM, 24, 4),
409 MUX(mout_csis1, "mout_csis1", group1_p4210, SRC_CAM, 28, 4), 348 MUX(CLK_MOUT_CSIS1, "mout_csis1", group1_p4210, SRC_CAM, 28, 4),
410 MUX(none, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1), 349 MUX(0, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1),
411 MUX_F(mout_g3d0, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1, 350 MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1,
412 CLK_SET_RATE_PARENT, 0), 351 CLK_SET_RATE_PARENT, 0),
413 MUX(none, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4), 352 MUX(0, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4),
414 MUX(none, "mout_mipi0", group1_p4210, SRC_LCD0, 12, 4), 353 MUX(0, "mout_mipi0", group1_p4210, SRC_LCD0, 12, 4),
415 MUX(none, "mout_audio0", mout_audio0_p4210, SRC_MAUDIO, 0, 4), 354 MUX(0, "mout_audio0", mout_audio0_p4210, SRC_MAUDIO, 0, 4),
416 MUX(none, "mout_mmc0", group1_p4210, SRC_FSYS, 0, 4), 355 MUX(0, "mout_mmc0", group1_p4210, SRC_FSYS, 0, 4),
417 MUX(none, "mout_mmc1", group1_p4210, SRC_FSYS, 4, 4), 356 MUX(0, "mout_mmc1", group1_p4210, SRC_FSYS, 4, 4),
418 MUX(none, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4), 357 MUX(0, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4),
419 MUX(none, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4), 358 MUX(0, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4),
420 MUX(none, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4), 359 MUX(0, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4),
421 MUX(none, "mout_sata", sclk_ampll_p4210, SRC_FSYS, 24, 1), 360 MUX(0, "mout_sata", sclk_ampll_p4210, SRC_FSYS, 24, 1),
422 MUX(none, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4), 361 MUX(0, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4),
423 MUX(none, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4), 362 MUX(0, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4),
424 MUX(none, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4), 363 MUX(0, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4),
425 MUX(none, "mout_uart3", group1_p4210, SRC_PERIL0, 12, 4), 364 MUX(0, "mout_uart3", group1_p4210, SRC_PERIL0, 12, 4),
426 MUX(none, "mout_uart4", group1_p4210, SRC_PERIL0, 16, 4), 365 MUX(0, "mout_uart4", group1_p4210, SRC_PERIL0, 16, 4),
427 MUX(none, "mout_audio1", mout_audio1_p4210, SRC_PERIL1, 0, 4), 366 MUX(0, "mout_audio1", mout_audio1_p4210, SRC_PERIL1, 0, 4),
428 MUX(none, "mout_audio2", mout_audio2_p4210, SRC_PERIL1, 4, 4), 367 MUX(0, "mout_audio2", mout_audio2_p4210, SRC_PERIL1, 4, 4),
429 MUX(none, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4), 368 MUX(0, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4),
430 MUX(none, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4), 369 MUX(0, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4),
431 MUX(none, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4), 370 MUX(0, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4),
432}; 371};
433 372
434/* list of mux clocks supported in exynos4x12 soc */ 373/* list of mux clocks supported in exynos4x12 soc */
435static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = { 374static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
436 MUX(mout_mpll_user_c, "mout_mpll_user_c", mout_mpll_user_p4x12, 375 MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p4x12,
437 SRC_CPU, 24, 1), 376 SRC_CPU, 24, 1),
438 MUX(none, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1), 377 MUX(0, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1),
439 MUX(none, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1), 378 MUX(0, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1),
440 MUX(mout_mpll_user_t, "mout_mpll_user_t", mout_mpll_user_p4x12, 379 MUX(CLK_MOUT_MPLL_USER_T, "mout_mpll_user_t", mout_mpll_user_p4x12,
441 SRC_TOP1, 12, 1), 380 SRC_TOP1, 12, 1),
442 MUX(none, "mout_user_aclk266_gps", mout_user_aclk266_gps_p4x12, 381 MUX(0, "mout_user_aclk266_gps", mout_user_aclk266_gps_p4x12,
443 SRC_TOP1, 16, 1), 382 SRC_TOP1, 16, 1),
444 MUX(aclk200, "aclk200", mout_user_aclk200_p4x12, SRC_TOP1, 20, 1), 383 MUX(CLK_ACLK200, "aclk200", mout_user_aclk200_p4x12, SRC_TOP1, 20, 1),
445 MUX(aclk400_mcuisp, "aclk400_mcuisp", mout_user_aclk400_mcuisp_p4x12, 384 MUX(CLK_ACLK400_MCUISP, "aclk400_mcuisp",
446 SRC_TOP1, 24, 1), 385 mout_user_aclk400_mcuisp_p4x12, SRC_TOP1, 24, 1),
447 MUX(none, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1), 386 MUX(0, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1),
448 MUX(none, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1), 387 MUX(0, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1),
449 MUX(none, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1), 388 MUX(0, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1),
450 MUX(none, "mout_aclk133", aclk_p4412, SRC_TOP0, 24, 1), 389 MUX(0, "mout_aclk133", aclk_p4412, SRC_TOP0, 24, 1),
451 MUX(none, "mout_mdnie0", group1_p4x12, SRC_LCD0, 4, 4), 390 MUX(0, "mout_mdnie0", group1_p4x12, SRC_LCD0, 4, 4),
452 MUX(none, "mout_mdnie_pwm0", group1_p4x12, SRC_LCD0, 8, 4), 391 MUX(0, "mout_mdnie_pwm0", group1_p4x12, SRC_LCD0, 8, 4),
453 MUX(none, "mout_sata", sclk_ampll_p4x12, SRC_FSYS, 24, 1), 392 MUX(0, "mout_sata", sclk_ampll_p4x12, SRC_FSYS, 24, 1),
454 MUX(none, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1), 393 MUX(0, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1),
455 MUX(none, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1), 394 MUX(0, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1),
456 MUX(none, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1), 395 MUX(0, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1),
457 MUX(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_DMC, 12, 1), 396 MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_DMC, 12, 1),
458 MUX(sclk_vpll, "sclk_vpll", mout_vpll_p, SRC_TOP0, 8, 1), 397 MUX(CLK_SCLK_VPLL, "sclk_vpll", mout_vpll_p, SRC_TOP0, 8, 1),
459 MUX(mout_core, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1), 398 MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1),
460 MUX(mout_fimc0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4), 399 MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4),
461 MUX(mout_fimc1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4), 400 MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4),
462 MUX(mout_fimc2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4), 401 MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4),
463 MUX(mout_fimc3, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4), 402 MUX(CLK_MOUT_FIMC3, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4),
464 MUX(mout_cam0, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4), 403 MUX(CLK_MOUT_CAM0, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4),
465 MUX(mout_cam1, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4), 404 MUX(CLK_MOUT_CAM1, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4),
466 MUX(mout_csis0, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4), 405 MUX(CLK_MOUT_CSIS0, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4),
467 MUX(mout_csis1, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4), 406 MUX(CLK_MOUT_CSIS1, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4),
468 MUX(none, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1), 407 MUX(0, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1),
469 MUX_F(mout_g3d0, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1, 408 MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1,
470 CLK_SET_RATE_PARENT, 0), 409 CLK_SET_RATE_PARENT, 0),
471 MUX(none, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4), 410 MUX(0, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4),
472 MUX(none, "mout_mipi0", group1_p4x12, SRC_LCD0, 12, 4), 411 MUX(0, "mout_mipi0", group1_p4x12, SRC_LCD0, 12, 4),
473 MUX(none, "mout_audio0", mout_audio0_p4x12, SRC_MAUDIO, 0, 4), 412 MUX(0, "mout_audio0", mout_audio0_p4x12, SRC_MAUDIO, 0, 4),
474 MUX(none, "mout_mmc0", group1_p4x12, SRC_FSYS, 0, 4), 413 MUX(0, "mout_mmc0", group1_p4x12, SRC_FSYS, 0, 4),
475 MUX(none, "mout_mmc1", group1_p4x12, SRC_FSYS, 4, 4), 414 MUX(0, "mout_mmc1", group1_p4x12, SRC_FSYS, 4, 4),
476 MUX(none, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4), 415 MUX(0, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4),
477 MUX(none, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4), 416 MUX(0, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4),
478 MUX(none, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4), 417 MUX(0, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4),
479 MUX(none, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1), 418 MUX(0, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1),
480 MUX(none, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4), 419 MUX(0, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4),
481 MUX(none, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4), 420 MUX(0, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4),
482 MUX(none, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4), 421 MUX(0, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4),
483 MUX(none, "mout_uart3", group1_p4x12, SRC_PERIL0, 12, 4), 422 MUX(0, "mout_uart3", group1_p4x12, SRC_PERIL0, 12, 4),
484 MUX(none, "mout_uart4", group1_p4x12, SRC_PERIL0, 16, 4), 423 MUX(0, "mout_uart4", group1_p4x12, SRC_PERIL0, 16, 4),
485 MUX(none, "mout_audio1", mout_audio1_p4x12, SRC_PERIL1, 0, 4), 424 MUX(0, "mout_audio1", mout_audio1_p4x12, SRC_PERIL1, 0, 4),
486 MUX(none, "mout_audio2", mout_audio2_p4x12, SRC_PERIL1, 4, 4), 425 MUX(0, "mout_audio2", mout_audio2_p4x12, SRC_PERIL1, 4, 4),
487 MUX(none, "mout_spi0", group1_p4x12, SRC_PERIL1, 16, 4), 426 MUX(0, "mout_spi0", group1_p4x12, SRC_PERIL1, 16, 4),
488 MUX(none, "mout_spi1", group1_p4x12, SRC_PERIL1, 20, 4), 427 MUX(0, "mout_spi1", group1_p4x12, SRC_PERIL1, 20, 4),
489 MUX(none, "mout_spi2", group1_p4x12, SRC_PERIL1, 24, 4), 428 MUX(0, "mout_spi2", group1_p4x12, SRC_PERIL1, 24, 4),
490 MUX(none, "mout_pwm_isp", group1_p4x12, E4X12_SRC_ISP, 0, 4), 429 MUX(0, "mout_pwm_isp", group1_p4x12, E4X12_SRC_ISP, 0, 4),
491 MUX(none, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4), 430 MUX(0, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4),
492 MUX(none, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4), 431 MUX(0, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4),
493 MUX(none, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4), 432 MUX(0, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4),
494 MUX(none, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1), 433 MUX(0, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1),
495 MUX(none, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1), 434 MUX(0, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1),
496 MUX(none, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1), 435 MUX(0, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1),
497}; 436};
498 437
499/* list of divider clocks supported in all exynos4 soc's */ 438/* list of divider clocks supported in all exynos4 soc's */
500static struct samsung_div_clock exynos4_div_clks[] __initdata = { 439static struct samsung_div_clock exynos4_div_clks[] __initdata = {
501 DIV(none, "div_core", "mout_core", DIV_CPU0, 0, 3), 440 DIV(0, "div_core", "mout_core", DIV_CPU0, 0, 3),
502 DIV(none, "div_core2", "div_core", DIV_CPU0, 28, 3), 441 DIV(0, "div_core2", "div_core", DIV_CPU0, 28, 3),
503 DIV(none, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4), 442 DIV(0, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),
504 DIV(none, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4), 443 DIV(0, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4),
505 DIV(none, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4), 444 DIV(0, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4),
506 DIV(none, "div_fimc3", "mout_fimc3", DIV_CAM, 12, 4), 445 DIV(0, "div_fimc3", "mout_fimc3", DIV_CAM, 12, 4),
507 DIV(none, "div_cam0", "mout_cam0", DIV_CAM, 16, 4), 446 DIV(0, "div_cam0", "mout_cam0", DIV_CAM, 16, 4),
508 DIV(none, "div_cam1", "mout_cam1", DIV_CAM, 20, 4), 447 DIV(0, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
509 DIV(none, "div_csis0", "mout_csis0", DIV_CAM, 24, 4), 448 DIV(0, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
510 DIV(none, "div_csis1", "mout_csis1", DIV_CAM, 28, 4), 449 DIV(0, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
511 DIV(sclk_mfc, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4), 450 DIV(CLK_SCLK_MFC, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4),
512 DIV_F(none, "div_g3d", "mout_g3d", DIV_G3D, 0, 4, 451 DIV_F(0, "div_g3d", "mout_g3d", DIV_G3D, 0, 4,
513 CLK_SET_RATE_PARENT, 0), 452 CLK_SET_RATE_PARENT, 0),
514 DIV(none, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4), 453 DIV(0, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4),
515 DIV(none, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4), 454 DIV(0, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4),
516 DIV(none, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4), 455 DIV(0, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
517 DIV(sclk_pcm0, "sclk_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8), 456 DIV(CLK_SCLK_PCM0, "sclk_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8),
518 DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), 457 DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
519 DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4), 458 DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
520 DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4), 459 DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
521 DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4), 460 DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
522 DIV(sclk_pixel, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4), 461 DIV(CLK_SCLK_PIXEL, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4),
523 DIV(aclk100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4), 462 DIV(CLK_ACLK100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4),
524 DIV(aclk160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3), 463 DIV(CLK_ACLK160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3),
525 DIV(aclk133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3), 464 DIV(CLK_ACLK133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3),
526 DIV(none, "div_onenand", "mout_onenand1", DIV_TOP, 16, 3), 465 DIV(0, "div_onenand", "mout_onenand1", DIV_TOP, 16, 3),
527 DIV(sclk_slimbus, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4), 466 DIV(CLK_SCLK_SLIMBUS, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4),
528 DIV(sclk_pcm1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8), 467 DIV(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8),
529 DIV(sclk_pcm2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8), 468 DIV(CLK_SCLK_PCM2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8),
530 DIV(sclk_i2s1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6), 469 DIV(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6),
531 DIV(sclk_i2s2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6), 470 DIV(CLK_SCLK_I2S2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6),
532 DIV(none, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4), 471 DIV(0, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4),
533 DIV(none, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8), 472 DIV(0, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8),
534 DIV(none, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4), 473 DIV(0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
535 DIV(none, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4), 474 DIV(0, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
536 DIV(none, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4), 475 DIV(0, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
537 DIV(none, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4), 476 DIV(0, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
538 DIV(none, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4), 477 DIV(0, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4),
539 DIV(none, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4), 478 DIV(0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
540 DIV(none, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8), 479 DIV(0, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8),
541 DIV(none, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4), 480 DIV(0, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
542 DIV(none, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8), 481 DIV(0, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8),
543 DIV(none, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4), 482 DIV(0, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4),
544 DIV(none, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8), 483 DIV(0, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8),
545 DIV(none, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4), 484 DIV(0, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
546 DIV(none, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4), 485 DIV(0, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
547 DIV(arm_clk, "arm_clk", "div_core2", DIV_CPU0, 28, 3), 486 DIV(CLK_ARM_CLK, "arm_clk", "div_core2", DIV_CPU0, 28, 3),
548 DIV(sclk_apll, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 487 DIV(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
549 DIV_F(none, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4, 488 DIV_F(0, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4,
550 CLK_SET_RATE_PARENT, 0), 489 CLK_SET_RATE_PARENT, 0),
551 DIV_F(none, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8, 490 DIV_F(0, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8,
552 CLK_SET_RATE_PARENT, 0), 491 CLK_SET_RATE_PARENT, 0),
553 DIV_F(none, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8, 492 DIV_F(0, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8,
554 CLK_SET_RATE_PARENT, 0), 493 CLK_SET_RATE_PARENT, 0),
555 DIV_F(none, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8, 494 DIV_F(0, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8,
556 CLK_SET_RATE_PARENT, 0), 495 CLK_SET_RATE_PARENT, 0),
557 DIV_F(none, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8, 496 DIV_F(0, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8,
558 CLK_SET_RATE_PARENT, 0), 497 CLK_SET_RATE_PARENT, 0),
559}; 498};
560 499
561/* list of divider clocks supported in exynos4210 soc */ 500/* list of divider clocks supported in exynos4210 soc */
562static struct samsung_div_clock exynos4210_div_clks[] __initdata = { 501static struct samsung_div_clock exynos4210_div_clks[] __initdata = {
563 DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3), 502 DIV(CLK_ACLK200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
564 DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4), 503 DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4),
565 DIV(none, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4), 504 DIV(0, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
566 DIV(none, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4), 505 DIV(0, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4),
567 DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4), 506 DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
568 DIV_F(none, "div_mipi_pre1", "div_mipi1", E4210_DIV_LCD1, 20, 4, 507 DIV_F(0, "div_mipi_pre1", "div_mipi1", E4210_DIV_LCD1, 20, 4,
569 CLK_SET_RATE_PARENT, 0), 508 CLK_SET_RATE_PARENT, 0),
570}; 509};
571 510
572/* list of divider clocks supported in exynos4x12 soc */ 511/* list of divider clocks supported in exynos4x12 soc */
573static struct samsung_div_clock exynos4x12_div_clks[] __initdata = { 512static struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
574 DIV(none, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4), 513 DIV(0, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4),
575 DIV(none, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4), 514 DIV(0, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4),
576 DIV(none, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4), 515 DIV(0, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4),
577 DIV(none, "div_mipihsi", "mout_mipihsi", DIV_FSYS0, 20, 4), 516 DIV(0, "div_mipihsi", "mout_mipihsi", DIV_FSYS0, 20, 4),
578 DIV(none, "div_jpeg", "mout_jpeg", E4X12_DIV_CAM1, 0, 4), 517 DIV(0, "div_jpeg", "mout_jpeg", E4X12_DIV_CAM1, 0, 4),
579 DIV(div_aclk200, "div_aclk200", "mout_aclk200", DIV_TOP, 0, 3), 518 DIV(CLK_DIV_ACLK200, "div_aclk200", "mout_aclk200", DIV_TOP, 0, 3),
580 DIV(none, "div_aclk266_gps", "mout_aclk266_gps", DIV_TOP, 20, 3), 519 DIV(0, "div_aclk266_gps", "mout_aclk266_gps", DIV_TOP, 20, 3),
581 DIV(div_aclk400_mcuisp, "div_aclk400_mcuisp", "mout_aclk400_mcuisp", 520 DIV(CLK_DIV_ACLK400_MCUISP, "div_aclk400_mcuisp", "mout_aclk400_mcuisp",
582 DIV_TOP, 24, 3), 521 DIV_TOP, 24, 3),
583 DIV(none, "div_pwm_isp", "mout_pwm_isp", E4X12_DIV_ISP, 0, 4), 522 DIV(0, "div_pwm_isp", "mout_pwm_isp", E4X12_DIV_ISP, 0, 4),
584 DIV(none, "div_spi0_isp", "mout_spi0_isp", E4X12_DIV_ISP, 4, 4), 523 DIV(0, "div_spi0_isp", "mout_spi0_isp", E4X12_DIV_ISP, 4, 4),
585 DIV(none, "div_spi0_isp_pre", "div_spi0_isp", E4X12_DIV_ISP, 8, 8), 524 DIV(0, "div_spi0_isp_pre", "div_spi0_isp", E4X12_DIV_ISP, 8, 8),
586 DIV(none, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4), 525 DIV(0, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4),
587 DIV(none, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8), 526 DIV(0, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8),
588 DIV(none, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4), 527 DIV(0, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4),
589 DIV_F(div_isp0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3, 528 DIV_F(CLK_DIV_ISP0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3,
590 CLK_GET_RATE_NOCACHE, 0), 529 CLK_GET_RATE_NOCACHE, 0),
591 DIV_F(div_isp1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3, 530 DIV_F(CLK_DIV_ISP1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3,
592 CLK_GET_RATE_NOCACHE, 0), 531 CLK_GET_RATE_NOCACHE, 0),
593 DIV(none, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3), 532 DIV(0, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3),
594 DIV_F(div_mcuisp0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, 533 DIV_F(CLK_DIV_MCUISP0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1,
595 4, 3, CLK_GET_RATE_NOCACHE, 0), 534 4, 3, CLK_GET_RATE_NOCACHE, 0),
596 DIV_F(div_mcuisp1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 535 DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1,
597 8, 3, CLK_GET_RATE_NOCACHE, 0), 536 8, 3, CLK_GET_RATE_NOCACHE, 0),
598 DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4), 537 DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
599}; 538};
600 539
601/* list of gate clocks supported in all exynos4 soc's */ 540/* list of gate clocks supported in all exynos4 soc's */
@@ -605,333 +544,341 @@ static struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
605 * the device name and clock alias names specified below for some 544 * the device name and clock alias names specified below for some
606 * of the clocks can be removed. 545 * of the clocks can be removed.
607 */ 546 */
608 GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0), 547 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0),
609 GATE(sclk_spdif, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0, 0), 548 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0,
610 GATE(jpeg, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0), 549 0),
611 GATE(mie0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0), 550 GATE(CLK_JPEG, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0),
612 GATE(dsim0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0), 551 GATE(CLK_MIE0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0),
613 GATE(fimd1, "fimd1", "aclk160", E4210_GATE_IP_LCD1, 0, 0, 0), 552 GATE(CLK_DSIM0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0),
614 GATE(mie1, "mie1", "aclk160", E4210_GATE_IP_LCD1, 1, 0, 0), 553 GATE(CLK_FIMD1, "fimd1", "aclk160", E4210_GATE_IP_LCD1, 0, 0, 0),
615 GATE(dsim1, "dsim1", "aclk160", E4210_GATE_IP_LCD1, 3, 0, 0), 554 GATE(CLK_MIE1, "mie1", "aclk160", E4210_GATE_IP_LCD1, 1, 0, 0),
616 GATE(smmu_fimd1, "smmu_fimd1", "aclk160", E4210_GATE_IP_LCD1, 4, 0, 0), 555 GATE(CLK_DSIM1, "dsim1", "aclk160", E4210_GATE_IP_LCD1, 3, 0, 0),
617 GATE(tsi, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0), 556 GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk160", E4210_GATE_IP_LCD1, 4, 0,
618 GATE(sromc, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0), 557 0),
619 GATE(sclk_g3d, "sclk_g3d", "div_g3d", GATE_IP_G3D, 0, 558 GATE(CLK_TSI, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0),
559 GATE(CLK_SROMC, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0),
560 GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d", GATE_IP_G3D, 0,
620 CLK_SET_RATE_PARENT, 0), 561 CLK_SET_RATE_PARENT, 0),
621 GATE(usb_device, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0), 562 GATE(CLK_USB_DEVICE, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0),
622 GATE(onenand, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0), 563 GATE(CLK_ONENAND, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0),
623 GATE(nfcon, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0), 564 GATE(CLK_NFCON, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0),
624 GATE(gps, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0), 565 GATE(CLK_GPS, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0),
625 GATE(smmu_gps, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0), 566 GATE(CLK_SMMU_GPS, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0),
626 GATE(slimbus, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0), 567 GATE(CLK_SLIMBUS, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0),
627 GATE(sclk_cam0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4, 568 GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4,
628 CLK_SET_RATE_PARENT, 0), 569 CLK_SET_RATE_PARENT, 0),
629 GATE(sclk_cam1, "sclk_cam1", "div_cam1", GATE_SCLK_CAM, 5, 570 GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1", GATE_SCLK_CAM, 5,
630 CLK_SET_RATE_PARENT, 0), 571 CLK_SET_RATE_PARENT, 0),
631 GATE(sclk_mipi0, "sclk_mipi0", "div_mipi_pre0", 572 GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi_pre0",
632 SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0), 573 SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0),
633 GATE(sclk_audio0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0, 574 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0,
634 CLK_SET_RATE_PARENT, 0), 575 CLK_SET_RATE_PARENT, 0),
635 GATE(sclk_audio1, "sclk_audio1", "div_audio1", SRC_MASK_PERIL1, 0, 576 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1", SRC_MASK_PERIL1, 0,
636 CLK_SET_RATE_PARENT, 0), 577 CLK_SET_RATE_PARENT, 0),
637 GATE(vp, "vp", "aclk160", GATE_IP_TV, 0, 0, 0), 578 GATE(CLK_VP, "vp", "aclk160", GATE_IP_TV, 0, 0, 0),
638 GATE(mixer, "mixer", "aclk160", GATE_IP_TV, 1, 0, 0), 579 GATE(CLK_MIXER, "mixer", "aclk160", GATE_IP_TV, 1, 0, 0),
639 GATE(hdmi, "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0), 580 GATE(CLK_HDMI, "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0),
640 GATE(pwm, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0), 581 GATE(CLK_PWM, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0),
641 GATE(sdmmc4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0), 582 GATE(CLK_SDMMC4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0),
642 GATE(usb_host, "usb_host", "aclk133", GATE_IP_FSYS, 12, 0, 0), 583 GATE(CLK_USB_HOST, "usb_host", "aclk133", GATE_IP_FSYS, 12, 0, 0),
643 GATE(sclk_fimc0, "sclk_fimc0", "div_fimc0", SRC_MASK_CAM, 0, 584 GATE(CLK_SCLK_FIMC0, "sclk_fimc0", "div_fimc0", SRC_MASK_CAM, 0,
644 CLK_SET_RATE_PARENT, 0), 585 CLK_SET_RATE_PARENT, 0),
645 GATE(sclk_fimc1, "sclk_fimc1", "div_fimc1", SRC_MASK_CAM, 4, 586 GATE(CLK_SCLK_FIMC1, "sclk_fimc1", "div_fimc1", SRC_MASK_CAM, 4,
646 CLK_SET_RATE_PARENT, 0), 587 CLK_SET_RATE_PARENT, 0),
647 GATE(sclk_fimc2, "sclk_fimc2", "div_fimc2", SRC_MASK_CAM, 8, 588 GATE(CLK_SCLK_FIMC2, "sclk_fimc2", "div_fimc2", SRC_MASK_CAM, 8,
648 CLK_SET_RATE_PARENT, 0), 589 CLK_SET_RATE_PARENT, 0),
649 GATE(sclk_fimc3, "sclk_fimc3", "div_fimc3", SRC_MASK_CAM, 12, 590 GATE(CLK_SCLK_FIMC3, "sclk_fimc3", "div_fimc3", SRC_MASK_CAM, 12,
650 CLK_SET_RATE_PARENT, 0), 591 CLK_SET_RATE_PARENT, 0),
651 GATE(sclk_csis0, "sclk_csis0", "div_csis0", SRC_MASK_CAM, 24, 592 GATE(CLK_SCLK_CSIS0, "sclk_csis0", "div_csis0", SRC_MASK_CAM, 24,
652 CLK_SET_RATE_PARENT, 0), 593 CLK_SET_RATE_PARENT, 0),
653 GATE(sclk_csis1, "sclk_csis1", "div_csis1", SRC_MASK_CAM, 28, 594 GATE(CLK_SCLK_CSIS1, "sclk_csis1", "div_csis1", SRC_MASK_CAM, 28,
654 CLK_SET_RATE_PARENT, 0), 595 CLK_SET_RATE_PARENT, 0),
655 GATE(sclk_fimd0, "sclk_fimd0", "div_fimd0", SRC_MASK_LCD0, 0, 596 GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0", SRC_MASK_LCD0, 0,
656 CLK_SET_RATE_PARENT, 0), 597 CLK_SET_RATE_PARENT, 0),
657 GATE(sclk_mmc0, "sclk_mmc0", "div_mmc_pre0", SRC_MASK_FSYS, 0, 598 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0", SRC_MASK_FSYS, 0,
658 CLK_SET_RATE_PARENT, 0), 599 CLK_SET_RATE_PARENT, 0),
659 GATE(sclk_mmc1, "sclk_mmc1", "div_mmc_pre1", SRC_MASK_FSYS, 4, 600 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1", SRC_MASK_FSYS, 4,
660 CLK_SET_RATE_PARENT, 0), 601 CLK_SET_RATE_PARENT, 0),
661 GATE(sclk_mmc2, "sclk_mmc2", "div_mmc_pre2", SRC_MASK_FSYS, 8, 602 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2", SRC_MASK_FSYS, 8,
662 CLK_SET_RATE_PARENT, 0), 603 CLK_SET_RATE_PARENT, 0),
663 GATE(sclk_mmc3, "sclk_mmc3", "div_mmc_pre3", SRC_MASK_FSYS, 12, 604 GATE(CLK_SCLK_MMC3, "sclk_mmc3", "div_mmc_pre3", SRC_MASK_FSYS, 12,
664 CLK_SET_RATE_PARENT, 0), 605 CLK_SET_RATE_PARENT, 0),
665 GATE(sclk_mmc4, "sclk_mmc4", "div_mmc_pre4", SRC_MASK_FSYS, 16, 606 GATE(CLK_SCLK_MMC4, "sclk_mmc4", "div_mmc_pre4", SRC_MASK_FSYS, 16,
666 CLK_SET_RATE_PARENT, 0), 607 CLK_SET_RATE_PARENT, 0),
667 GATE(sclk_uart0, "uclk0", "div_uart0", SRC_MASK_PERIL0, 0, 608 GATE(CLK_SCLK_UART0, "uclk0", "div_uart0", SRC_MASK_PERIL0, 0,
668 CLK_SET_RATE_PARENT, 0), 609 CLK_SET_RATE_PARENT, 0),
669 GATE(sclk_uart1, "uclk1", "div_uart1", SRC_MASK_PERIL0, 4, 610 GATE(CLK_SCLK_UART1, "uclk1", "div_uart1", SRC_MASK_PERIL0, 4,
670 CLK_SET_RATE_PARENT, 0), 611 CLK_SET_RATE_PARENT, 0),
671 GATE(sclk_uart2, "uclk2", "div_uart2", SRC_MASK_PERIL0, 8, 612 GATE(CLK_SCLK_UART2, "uclk2", "div_uart2", SRC_MASK_PERIL0, 8,
672 CLK_SET_RATE_PARENT, 0), 613 CLK_SET_RATE_PARENT, 0),
673 GATE(sclk_uart3, "uclk3", "div_uart3", SRC_MASK_PERIL0, 12, 614 GATE(CLK_SCLK_UART3, "uclk3", "div_uart3", SRC_MASK_PERIL0, 12,
674 CLK_SET_RATE_PARENT, 0), 615 CLK_SET_RATE_PARENT, 0),
675 GATE(sclk_uart4, "uclk4", "div_uart4", SRC_MASK_PERIL0, 16, 616 GATE(CLK_SCLK_UART4, "uclk4", "div_uart4", SRC_MASK_PERIL0, 16,
676 CLK_SET_RATE_PARENT, 0), 617 CLK_SET_RATE_PARENT, 0),
677 GATE(sclk_audio2, "sclk_audio2", "div_audio2", SRC_MASK_PERIL1, 4, 618 GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2", SRC_MASK_PERIL1, 4,
678 CLK_SET_RATE_PARENT, 0), 619 CLK_SET_RATE_PARENT, 0),
679 GATE(sclk_spi0, "sclk_spi0", "div_spi_pre0", SRC_MASK_PERIL1, 16, 620 GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0", SRC_MASK_PERIL1, 16,
680 CLK_SET_RATE_PARENT, 0), 621 CLK_SET_RATE_PARENT, 0),
681 GATE(sclk_spi1, "sclk_spi1", "div_spi_pre1", SRC_MASK_PERIL1, 20, 622 GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi_pre1", SRC_MASK_PERIL1, 20,
682 CLK_SET_RATE_PARENT, 0), 623 CLK_SET_RATE_PARENT, 0),
683 GATE(sclk_spi2, "sclk_spi2", "div_spi_pre2", SRC_MASK_PERIL1, 24, 624 GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi_pre2", SRC_MASK_PERIL1, 24,
684 CLK_SET_RATE_PARENT, 0), 625 CLK_SET_RATE_PARENT, 0),
685 GATE(fimc0, "fimc0", "aclk160", GATE_IP_CAM, 0, 626 GATE(CLK_FIMC0, "fimc0", "aclk160", GATE_IP_CAM, 0,
686 0, 0), 627 0, 0),
687 GATE(fimc1, "fimc1", "aclk160", GATE_IP_CAM, 1, 628 GATE(CLK_FIMC1, "fimc1", "aclk160", GATE_IP_CAM, 1,
688 0, 0), 629 0, 0),
689 GATE(fimc2, "fimc2", "aclk160", GATE_IP_CAM, 2, 630 GATE(CLK_FIMC2, "fimc2", "aclk160", GATE_IP_CAM, 2,
690 0, 0), 631 0, 0),
691 GATE(fimc3, "fimc3", "aclk160", GATE_IP_CAM, 3, 632 GATE(CLK_FIMC3, "fimc3", "aclk160", GATE_IP_CAM, 3,
692 0, 0), 633 0, 0),
693 GATE(csis0, "csis0", "aclk160", GATE_IP_CAM, 4, 634 GATE(CLK_CSIS0, "csis0", "aclk160", GATE_IP_CAM, 4,
694 0, 0), 635 0, 0),
695 GATE(csis1, "csis1", "aclk160", GATE_IP_CAM, 5, 636 GATE(CLK_CSIS1, "csis1", "aclk160", GATE_IP_CAM, 5,
696 0, 0), 637 0, 0),
697 GATE(smmu_fimc0, "smmu_fimc0", "aclk160", GATE_IP_CAM, 7, 638 GATE(CLK_SMMU_FIMC0, "smmu_fimc0", "aclk160", GATE_IP_CAM, 7,
698 0, 0), 639 0, 0),
699 GATE(smmu_fimc1, "smmu_fimc1", "aclk160", GATE_IP_CAM, 8, 640 GATE(CLK_SMMU_FIMC1, "smmu_fimc1", "aclk160", GATE_IP_CAM, 8,
700 0, 0), 641 0, 0),
701 GATE(smmu_fimc2, "smmu_fimc2", "aclk160", GATE_IP_CAM, 9, 642 GATE(CLK_SMMU_FIMC2, "smmu_fimc2", "aclk160", GATE_IP_CAM, 9,
702 0, 0), 643 0, 0),
703 GATE(smmu_fimc3, "smmu_fimc3", "aclk160", GATE_IP_CAM, 10, 644 GATE(CLK_SMMU_FIMC3, "smmu_fimc3", "aclk160", GATE_IP_CAM, 10,
704 0, 0), 645 0, 0),
705 GATE(smmu_jpeg, "smmu_jpeg", "aclk160", GATE_IP_CAM, 11, 646 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk160", GATE_IP_CAM, 11,
706 0, 0), 647 0, 0),
707 GATE(pixelasyncm0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0), 648 GATE(CLK_PIXELASYNCM0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0),
708 GATE(pixelasyncm1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0), 649 GATE(CLK_PIXELASYNCM1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0),
709 GATE(smmu_tv, "smmu_tv", "aclk160", GATE_IP_TV, 4, 650 GATE(CLK_SMMU_TV, "smmu_tv", "aclk160", GATE_IP_TV, 4,
710 0, 0), 651 0, 0),
711 GATE(mfc, "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0), 652 GATE(CLK_MFC, "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0),
712 GATE(smmu_mfcl, "smmu_mfcl", "aclk100", GATE_IP_MFC, 1, 653 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk100", GATE_IP_MFC, 1,
713 0, 0), 654 0, 0),
714 GATE(smmu_mfcr, "smmu_mfcr", "aclk100", GATE_IP_MFC, 2, 655 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk100", GATE_IP_MFC, 2,
715 0, 0), 656 0, 0),
716 GATE(fimd0, "fimd0", "aclk160", GATE_IP_LCD0, 0, 657 GATE(CLK_FIMD0, "fimd0", "aclk160", GATE_IP_LCD0, 0,
717 0, 0), 658 0, 0),
718 GATE(smmu_fimd0, "smmu_fimd0", "aclk160", GATE_IP_LCD0, 4, 659 GATE(CLK_SMMU_FIMD0, "smmu_fimd0", "aclk160", GATE_IP_LCD0, 4,
719 0, 0), 660 0, 0),
720 GATE(pdma0, "pdma0", "aclk133", GATE_IP_FSYS, 0, 661 GATE(CLK_PDMA0, "pdma0", "aclk133", GATE_IP_FSYS, 0,
721 0, 0), 662 0, 0),
722 GATE(pdma1, "pdma1", "aclk133", GATE_IP_FSYS, 1, 663 GATE(CLK_PDMA1, "pdma1", "aclk133", GATE_IP_FSYS, 1,
723 0, 0), 664 0, 0),
724 GATE(sdmmc0, "sdmmc0", "aclk133", GATE_IP_FSYS, 5, 665 GATE(CLK_SDMMC0, "sdmmc0", "aclk133", GATE_IP_FSYS, 5,
725 0, 0), 666 0, 0),
726 GATE(sdmmc1, "sdmmc1", "aclk133", GATE_IP_FSYS, 6, 667 GATE(CLK_SDMMC1, "sdmmc1", "aclk133", GATE_IP_FSYS, 6,
727 0, 0), 668 0, 0),
728 GATE(sdmmc2, "sdmmc2", "aclk133", GATE_IP_FSYS, 7, 669 GATE(CLK_SDMMC2, "sdmmc2", "aclk133", GATE_IP_FSYS, 7,
729 0, 0), 670 0, 0),
730 GATE(sdmmc3, "sdmmc3", "aclk133", GATE_IP_FSYS, 8, 671 GATE(CLK_SDMMC3, "sdmmc3", "aclk133", GATE_IP_FSYS, 8,
731 0, 0), 672 0, 0),
732 GATE(uart0, "uart0", "aclk100", GATE_IP_PERIL, 0, 673 GATE(CLK_UART0, "uart0", "aclk100", GATE_IP_PERIL, 0,
733 0, 0), 674 0, 0),
734 GATE(uart1, "uart1", "aclk100", GATE_IP_PERIL, 1, 675 GATE(CLK_UART1, "uart1", "aclk100", GATE_IP_PERIL, 1,
735 0, 0), 676 0, 0),
736 GATE(uart2, "uart2", "aclk100", GATE_IP_PERIL, 2, 677 GATE(CLK_UART2, "uart2", "aclk100", GATE_IP_PERIL, 2,
737 0, 0), 678 0, 0),
738 GATE(uart3, "uart3", "aclk100", GATE_IP_PERIL, 3, 679 GATE(CLK_UART3, "uart3", "aclk100", GATE_IP_PERIL, 3,
739 0, 0), 680 0, 0),
740 GATE(uart4, "uart4", "aclk100", GATE_IP_PERIL, 4, 681 GATE(CLK_UART4, "uart4", "aclk100", GATE_IP_PERIL, 4,
741 0, 0), 682 0, 0),
742 GATE(i2c0, "i2c0", "aclk100", GATE_IP_PERIL, 6, 683 GATE(CLK_I2C0, "i2c0", "aclk100", GATE_IP_PERIL, 6,
743 0, 0), 684 0, 0),
744 GATE(i2c1, "i2c1", "aclk100", GATE_IP_PERIL, 7, 685 GATE(CLK_I2C1, "i2c1", "aclk100", GATE_IP_PERIL, 7,
745 0, 0), 686 0, 0),
746 GATE(i2c2, "i2c2", "aclk100", GATE_IP_PERIL, 8, 687 GATE(CLK_I2C2, "i2c2", "aclk100", GATE_IP_PERIL, 8,
747 0, 0), 688 0, 0),
748 GATE(i2c3, "i2c3", "aclk100", GATE_IP_PERIL, 9, 689 GATE(CLK_I2C3, "i2c3", "aclk100", GATE_IP_PERIL, 9,
749 0, 0), 690 0, 0),
750 GATE(i2c4, "i2c4", "aclk100", GATE_IP_PERIL, 10, 691 GATE(CLK_I2C4, "i2c4", "aclk100", GATE_IP_PERIL, 10,
751 0, 0), 692 0, 0),
752 GATE(i2c5, "i2c5", "aclk100", GATE_IP_PERIL, 11, 693 GATE(CLK_I2C5, "i2c5", "aclk100", GATE_IP_PERIL, 11,
753 0, 0), 694 0, 0),
754 GATE(i2c6, "i2c6", "aclk100", GATE_IP_PERIL, 12, 695 GATE(CLK_I2C6, "i2c6", "aclk100", GATE_IP_PERIL, 12,
755 0, 0), 696 0, 0),
756 GATE(i2c7, "i2c7", "aclk100", GATE_IP_PERIL, 13, 697 GATE(CLK_I2C7, "i2c7", "aclk100", GATE_IP_PERIL, 13,
757 0, 0), 698 0, 0),
758 GATE(i2c_hdmi, "i2c-hdmi", "aclk100", GATE_IP_PERIL, 14, 699 GATE(CLK_I2C_HDMI, "i2c-hdmi", "aclk100", GATE_IP_PERIL, 14,
759 0, 0), 700 0, 0),
760 GATE(spi0, "spi0", "aclk100", GATE_IP_PERIL, 16, 701 GATE(CLK_SPI0, "spi0", "aclk100", GATE_IP_PERIL, 16,
761 0, 0), 702 0, 0),
762 GATE(spi1, "spi1", "aclk100", GATE_IP_PERIL, 17, 703 GATE(CLK_SPI1, "spi1", "aclk100", GATE_IP_PERIL, 17,
763 0, 0), 704 0, 0),
764 GATE(spi2, "spi2", "aclk100", GATE_IP_PERIL, 18, 705 GATE(CLK_SPI2, "spi2", "aclk100", GATE_IP_PERIL, 18,
765 0, 0), 706 0, 0),
766 GATE(i2s1, "i2s1", "aclk100", GATE_IP_PERIL, 20, 707 GATE(CLK_I2S1, "i2s1", "aclk100", GATE_IP_PERIL, 20,
767 0, 0), 708 0, 0),
768 GATE(i2s2, "i2s2", "aclk100", GATE_IP_PERIL, 21, 709 GATE(CLK_I2S2, "i2s2", "aclk100", GATE_IP_PERIL, 21,
769 0, 0), 710 0, 0),
770 GATE(pcm1, "pcm1", "aclk100", GATE_IP_PERIL, 22, 711 GATE(CLK_PCM1, "pcm1", "aclk100", GATE_IP_PERIL, 22,
771 0, 0), 712 0, 0),
772 GATE(pcm2, "pcm2", "aclk100", GATE_IP_PERIL, 23, 713 GATE(CLK_PCM2, "pcm2", "aclk100", GATE_IP_PERIL, 23,
773 0, 0), 714 0, 0),
774 GATE(spdif, "spdif", "aclk100", GATE_IP_PERIL, 26, 715 GATE(CLK_SPDIF, "spdif", "aclk100", GATE_IP_PERIL, 26,
775 0, 0), 716 0, 0),
776 GATE(ac97, "ac97", "aclk100", GATE_IP_PERIL, 27, 717 GATE(CLK_AC97, "ac97", "aclk100", GATE_IP_PERIL, 27,
777 0, 0), 718 0, 0),
778}; 719};
779 720
780/* list of gate clocks supported in exynos4210 soc */ 721/* list of gate clocks supported in exynos4210 soc */
781static struct samsung_gate_clock exynos4210_gate_clks[] __initdata = { 722static struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
782 GATE(tvenc, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0), 723 GATE(CLK_TVENC, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0),
783 GATE(g2d, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0), 724 GATE(CLK_G2D, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0),
784 GATE(rotator, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0), 725 GATE(CLK_ROTATOR, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0),
785 GATE(mdma, "mdma", "aclk200", E4210_GATE_IP_IMAGE, 2, 0, 0), 726 GATE(CLK_MDMA, "mdma", "aclk200", E4210_GATE_IP_IMAGE, 2, 0, 0),
786 GATE(smmu_g2d, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0), 727 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0),
787 GATE(smmu_mdma, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0, 0), 728 GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0,
788 GATE(pcie_phy, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0), 729 0),
789 GATE(sata_phy, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0), 730 GATE(CLK_PCIE_PHY, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0),
790 GATE(sata, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0), 731 GATE(CLK_SATA_PHY, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0),
791 GATE(pcie, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0), 732 GATE(CLK_SATA, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0),
792 GATE(smmu_pcie, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0), 733 GATE(CLK_PCIE, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0),
793 GATE(modemif, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0), 734 GATE(CLK_SMMU_PCIE, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0),
794 GATE(chipid, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0), 735 GATE(CLK_MODEMIF, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0),
795 GATE(sysreg, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0, 736 GATE(CLK_CHIPID, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0),
737 GATE(CLK_SYSREG, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0,
796 CLK_IGNORE_UNUSED, 0), 738 CLK_IGNORE_UNUSED, 0),
797 GATE(hdmi_cec, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0, 0), 739 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0,
798 GATE(smmu_rotator, "smmu_rotator", "aclk200", 740 0),
741 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200",
799 E4210_GATE_IP_IMAGE, 4, 0, 0), 742 E4210_GATE_IP_IMAGE, 4, 0, 0),
800 GATE(sclk_mipi1, "sclk_mipi1", "div_mipi_pre1", 743 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "div_mipi_pre1",
801 E4210_SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0), 744 E4210_SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0),
802 GATE(sclk_sata, "sclk_sata", "div_sata", 745 GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata",
803 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 746 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
804 GATE(sclk_mixer, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0), 747 GATE(CLK_SCLK_MIXER, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0),
805 GATE(sclk_dac, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0), 748 GATE(CLK_SCLK_DAC, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0),
806 GATE(tsadc, "tsadc", "aclk100", GATE_IP_PERIL, 15, 749 GATE(CLK_TSADC, "tsadc", "aclk100", GATE_IP_PERIL, 15,
807 0, 0), 750 0, 0),
808 GATE(mct, "mct", "aclk100", E4210_GATE_IP_PERIR, 13, 751 GATE(CLK_MCT, "mct", "aclk100", E4210_GATE_IP_PERIR, 13,
809 0, 0), 752 0, 0),
810 GATE(wdt, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14, 753 GATE(CLK_WDT, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14,
811 0, 0), 754 0, 0),
812 GATE(rtc, "rtc", "aclk100", E4210_GATE_IP_PERIR, 15, 755 GATE(CLK_RTC, "rtc", "aclk100", E4210_GATE_IP_PERIR, 15,
813 0, 0), 756 0, 0),
814 GATE(keyif, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16, 757 GATE(CLK_KEYIF, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16,
815 0, 0), 758 0, 0),
816 GATE(sclk_fimd1, "sclk_fimd1", "div_fimd1", E4210_SRC_MASK_LCD1, 0, 759 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1", E4210_SRC_MASK_LCD1, 0,
817 CLK_SET_RATE_PARENT, 0), 760 CLK_SET_RATE_PARENT, 0),
818 GATE(tmu_apbif, "tmu_apbif", "aclk100", E4210_GATE_IP_PERIR, 17, 0, 0), 761 GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4210_GATE_IP_PERIR, 17, 0,
762 0),
819}; 763};
820 764
821/* list of gate clocks supported in exynos4x12 soc */ 765/* list of gate clocks supported in exynos4x12 soc */
822static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { 766static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
823 GATE(audss, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0), 767 GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0),
824 GATE(mdnie0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0), 768 GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0),
825 GATE(rotator, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0), 769 GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),
826 GATE(mdma2, "mdma2", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0), 770 GATE(CLK_MDMA2, "mdma2", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
827 GATE(smmu_mdma, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0, 0), 771 GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0,
828 GATE(mipi_hsi, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0), 772 0),
829 GATE(chipid, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0), 773 GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
830 GATE(sysreg, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1, 774 GATE(CLK_CHIPID, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0),
775 GATE(CLK_SYSREG, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1,
831 CLK_IGNORE_UNUSED, 0), 776 CLK_IGNORE_UNUSED, 0),
832 GATE(hdmi_cec, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0, 0), 777 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0,
833 GATE(sclk_mdnie0, "sclk_mdnie0", "div_mdnie0", 778 0),
779 GATE(CLK_SCLK_MDNIE0, "sclk_mdnie0", "div_mdnie0",
834 SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0), 780 SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0),
835 GATE(sclk_mdnie_pwm0, "sclk_mdnie_pwm0", "div_mdnie_pwm_pre0", 781 GATE(CLK_SCLK_MDNIE_PWM0, "sclk_mdnie_pwm0", "div_mdnie_pwm_pre0",
836 SRC_MASK_LCD0, 8, CLK_SET_RATE_PARENT, 0), 782 SRC_MASK_LCD0, 8, CLK_SET_RATE_PARENT, 0),
837 GATE(sclk_mipihsi, "sclk_mipihsi", "div_mipihsi", 783 GATE(CLK_SCLK_MIPIHSI, "sclk_mipihsi", "div_mipihsi",
838 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 784 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
839 GATE(smmu_rotator, "smmu_rotator", "aclk200", 785 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200",
840 E4X12_GATE_IP_IMAGE, 4, 0, 0), 786 E4X12_GATE_IP_IMAGE, 4, 0, 0),
841 GATE(mct, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13, 787 GATE(CLK_MCT, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13,
842 0, 0), 788 0, 0),
843 GATE(rtc, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15, 789 GATE(CLK_RTC, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15,
844 0, 0), 790 0, 0),
845 GATE(keyif, "keyif", "aclk100", E4X12_GATE_IP_PERIR, 16, 0, 0), 791 GATE(CLK_KEYIF, "keyif", "aclk100", E4X12_GATE_IP_PERIR, 16, 0, 0),
846 GATE(sclk_pwm_isp, "sclk_pwm_isp", "div_pwm_isp", 792 GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "div_pwm_isp",
847 E4X12_SRC_MASK_ISP, 0, CLK_SET_RATE_PARENT, 0), 793 E4X12_SRC_MASK_ISP, 0, CLK_SET_RATE_PARENT, 0),
848 GATE(sclk_spi0_isp, "sclk_spi0_isp", "div_spi0_isp_pre", 794 GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "div_spi0_isp_pre",
849 E4X12_SRC_MASK_ISP, 4, CLK_SET_RATE_PARENT, 0), 795 E4X12_SRC_MASK_ISP, 4, CLK_SET_RATE_PARENT, 0),
850 GATE(sclk_spi1_isp, "sclk_spi1_isp", "div_spi1_isp_pre", 796 GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "div_spi1_isp_pre",
851 E4X12_SRC_MASK_ISP, 8, CLK_SET_RATE_PARENT, 0), 797 E4X12_SRC_MASK_ISP, 8, CLK_SET_RATE_PARENT, 0),
852 GATE(sclk_uart_isp, "sclk_uart_isp", "div_uart_isp", 798 GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "div_uart_isp",
853 E4X12_SRC_MASK_ISP, 12, CLK_SET_RATE_PARENT, 0), 799 E4X12_SRC_MASK_ISP, 12, CLK_SET_RATE_PARENT, 0),
854 GATE(pwm_isp_sclk, "pwm_isp_sclk", "sclk_pwm_isp", 800 GATE(CLK_PWM_ISP_SCLK, "pwm_isp_sclk", "sclk_pwm_isp",
855 E4X12_GATE_IP_ISP, 0, 0, 0), 801 E4X12_GATE_IP_ISP, 0, 0, 0),
856 GATE(spi0_isp_sclk, "spi0_isp_sclk", "sclk_spi0_isp", 802 GATE(CLK_SPI0_ISP_SCLK, "spi0_isp_sclk", "sclk_spi0_isp",
857 E4X12_GATE_IP_ISP, 1, 0, 0), 803 E4X12_GATE_IP_ISP, 1, 0, 0),
858 GATE(spi1_isp_sclk, "spi1_isp_sclk", "sclk_spi1_isp", 804 GATE(CLK_SPI1_ISP_SCLK, "spi1_isp_sclk", "sclk_spi1_isp",
859 E4X12_GATE_IP_ISP, 2, 0, 0), 805 E4X12_GATE_IP_ISP, 2, 0, 0),
860 GATE(uart_isp_sclk, "uart_isp_sclk", "sclk_uart_isp", 806 GATE(CLK_UART_ISP_SCLK, "uart_isp_sclk", "sclk_uart_isp",
861 E4X12_GATE_IP_ISP, 3, 0, 0), 807 E4X12_GATE_IP_ISP, 3, 0, 0),
862 GATE(wdt, "watchdog", "aclk100", E4X12_GATE_IP_PERIR, 14, 0, 0), 808 GATE(CLK_WDT, "watchdog", "aclk100", E4X12_GATE_IP_PERIR, 14, 0, 0),
863 GATE(pcm0, "pcm0", "aclk100", E4X12_GATE_IP_MAUDIO, 2, 809 GATE(CLK_PCM0, "pcm0", "aclk100", E4X12_GATE_IP_MAUDIO, 2,
864 0, 0), 810 0, 0),
865 GATE(i2s0, "i2s0", "aclk100", E4X12_GATE_IP_MAUDIO, 3, 811 GATE(CLK_I2S0, "i2s0", "aclk100", E4X12_GATE_IP_MAUDIO, 3,
866 0, 0), 812 0, 0),
867 GATE(fimc_isp, "isp", "aclk200", E4X12_GATE_ISP0, 0, 813 GATE(CLK_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0,
868 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 814 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
869 GATE(fimc_drc, "drc", "aclk200", E4X12_GATE_ISP0, 1, 815 GATE(CLK_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1,
870 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 816 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
871 GATE(fimc_fd, "fd", "aclk200", E4X12_GATE_ISP0, 2, 817 GATE(CLK_FIMC_FD, "fd", "aclk200", E4X12_GATE_ISP0, 2,
872 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 818 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
873 GATE(fimc_lite0, "lite0", "aclk200", E4X12_GATE_ISP0, 3, 819 GATE(CLK_FIMC_LITE0, "lite0", "aclk200", E4X12_GATE_ISP0, 3,
874 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 820 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
875 GATE(fimc_lite1, "lite1", "aclk200", E4X12_GATE_ISP0, 4, 821 GATE(CLK_FIMC_LITE1, "lite1", "aclk200", E4X12_GATE_ISP0, 4,
876 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 822 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
877 GATE(mcuisp, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5, 823 GATE(CLK_MCUISP, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5,
878 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 824 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
879 GATE(gicisp, "gicisp", "aclk200", E4X12_GATE_ISP0, 7, 825 GATE(CLK_GICISP, "gicisp", "aclk200", E4X12_GATE_ISP0, 7,
880 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 826 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
881 GATE(smmu_isp, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8, 827 GATE(CLK_SMMU_ISP, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8,
882 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 828 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
883 GATE(smmu_drc, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9, 829 GATE(CLK_SMMU_DRC, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9,
884 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 830 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
885 GATE(smmu_fd, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10, 831 GATE(CLK_SMMU_FD, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10,
886 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 832 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
887 GATE(smmu_lite0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11, 833 GATE(CLK_SMMU_LITE0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11,
888 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 834 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
889 GATE(smmu_lite1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12, 835 GATE(CLK_SMMU_LITE1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12,
890 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 836 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
891 GATE(ppmuispmx, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20, 837 GATE(CLK_PPMUISPMX, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20,
892 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 838 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
893 GATE(ppmuispx, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21, 839 GATE(CLK_PPMUISPX, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21,
894 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 840 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
895 GATE(mcuctl_isp, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23, 841 GATE(CLK_MCUCTL_ISP, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23,
896 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 842 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
897 GATE(mpwm_isp, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24, 843 GATE(CLK_MPWM_ISP, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24,
898 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 844 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
899 GATE(i2c0_isp, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25, 845 GATE(CLK_I2C0_ISP, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25,
900 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 846 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
901 GATE(i2c1_isp, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26, 847 GATE(CLK_I2C1_ISP, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26,
902 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 848 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
903 GATE(mtcadc_isp, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27, 849 GATE(CLK_MTCADC_ISP, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27,
904 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 850 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
905 GATE(pwm_isp, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28, 851 GATE(CLK_PWM_ISP, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28,
906 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 852 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
907 GATE(wdt_isp, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30, 853 GATE(CLK_WDT_ISP, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30,
908 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 854 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
909 GATE(uart_isp, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31, 855 GATE(CLK_UART_ISP, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31,
910 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 856 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
911 GATE(asyncaxim, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0, 857 GATE(CLK_ASYNCAXIM, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0,
912 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 858 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
913 GATE(smmu_ispcx, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4, 859 GATE(CLK_SMMU_ISPCX, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4,
914 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 860 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
915 GATE(spi0_isp, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12, 861 GATE(CLK_SPI0_ISP, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12,
916 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 862 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
917 GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13, 863 GATE(CLK_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
918 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 864 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
919 GATE(g2d, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0), 865 GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0),
920 GATE(tmu_apbif, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0, 0), 866 GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0,
867 0),
921}; 868};
922 869
923static struct samsung_clock_alias exynos4_aliases[] __initdata = { 870static struct samsung_clock_alias exynos4_aliases[] __initdata = {
924 ALIAS(mout_core, NULL, "moutcore"), 871 ALIAS(CLK_MOUT_CORE, NULL, "moutcore"),
925 ALIAS(arm_clk, NULL, "armclk"), 872 ALIAS(CLK_ARM_CLK, NULL, "armclk"),
926 ALIAS(sclk_apll, NULL, "mout_apll"), 873 ALIAS(CLK_SCLK_APLL, NULL, "mout_apll"),
927}; 874};
928 875
929static struct samsung_clock_alias exynos4210_aliases[] __initdata = { 876static struct samsung_clock_alias exynos4210_aliases[] __initdata = {
930 ALIAS(sclk_mpll, NULL, "mout_mpll"), 877 ALIAS(CLK_SCLK_MPLL, NULL, "mout_mpll"),
931}; 878};
932 879
933static struct samsung_clock_alias exynos4x12_aliases[] __initdata = { 880static struct samsung_clock_alias exynos4x12_aliases[] __initdata = {
934 ALIAS(mout_mpll_user_c, NULL, "mout_mpll"), 881 ALIAS(CLK_MOUT_MPLL_USER_C, NULL, "mout_mpll"),
935}; 882};
936 883
937/* 884/*
@@ -977,7 +924,7 @@ static void __init exynos4_clk_register_finpll(unsigned long xom)
977 finpll_f = clk_get_rate(clk); 924 finpll_f = clk_get_rate(clk);
978 } 925 }
979 926
980 fclk.id = fin_pll; 927 fclk.id = CLK_FIN_PLL;
981 fclk.name = "fin_pll"; 928 fclk.name = "fin_pll";
982 fclk.parent_name = NULL; 929 fclk.parent_name = NULL;
983 fclk.flags = CLK_IS_ROOT; 930 fclk.flags = CLK_IS_ROOT;
@@ -1067,24 +1014,24 @@ static struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initdata = {
1067}; 1014};
1068 1015
1069static struct samsung_pll_clock exynos4210_plls[nr_plls] __initdata = { 1016static struct samsung_pll_clock exynos4210_plls[nr_plls] __initdata = {
1070 [apll] = PLL_A(pll_4508, fout_apll, "fout_apll", "fin_pll", APLL_LOCK, 1017 [apll] = PLL_A(pll_4508, CLK_FOUT_APLL, "fout_apll", "fin_pll",
1071 APLL_CON0, "fout_apll", NULL), 1018 APLL_LOCK, APLL_CON0, "fout_apll", NULL),
1072 [mpll] = PLL_A(pll_4508, fout_mpll, "fout_mpll", "fin_pll", 1019 [mpll] = PLL_A(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
1073 E4210_MPLL_LOCK, E4210_MPLL_CON0, "fout_mpll", NULL), 1020 E4210_MPLL_LOCK, E4210_MPLL_CON0, "fout_mpll", NULL),
1074 [epll] = PLL_A(pll_4600, fout_epll, "fout_epll", "fin_pll", EPLL_LOCK, 1021 [epll] = PLL_A(pll_4600, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
1075 EPLL_CON0, "fout_epll", NULL), 1022 EPLL_LOCK, EPLL_CON0, "fout_epll", NULL),
1076 [vpll] = PLL_A(pll_4650c, fout_vpll, "fout_vpll", "mout_vpllsrc", 1023 [vpll] = PLL_A(pll_4650c, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
1077 VPLL_LOCK, VPLL_CON0, "fout_vpll", NULL), 1024 VPLL_LOCK, VPLL_CON0, "fout_vpll", NULL),
1078}; 1025};
1079 1026
1080static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = { 1027static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
1081 [apll] = PLL(pll_35xx, fout_apll, "fout_apll", "fin_pll", 1028 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
1082 APLL_LOCK, APLL_CON0, NULL), 1029 APLL_LOCK, APLL_CON0, NULL),
1083 [mpll] = PLL(pll_35xx, fout_mpll, "fout_mpll", "fin_pll", 1030 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
1084 E4X12_MPLL_LOCK, E4X12_MPLL_CON0, NULL), 1031 E4X12_MPLL_LOCK, E4X12_MPLL_CON0, NULL),
1085 [epll] = PLL(pll_36xx, fout_epll, "fout_epll", "fin_pll", 1032 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
1086 EPLL_LOCK, EPLL_CON0, NULL), 1033 EPLL_LOCK, EPLL_CON0, NULL),
1087 [vpll] = PLL(pll_36xx, fout_vpll, "fout_vpll", "fin_pll", 1034 [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll",
1088 VPLL_LOCK, VPLL_CON0, NULL), 1035 VPLL_LOCK, VPLL_CON0, NULL),
1089}; 1036};
1090 1037
@@ -1098,11 +1045,11 @@ static void __init exynos4_clk_init(struct device_node *np,
1098 panic("%s: failed to map registers\n", __func__); 1045 panic("%s: failed to map registers\n", __func__);
1099 1046
1100 if (exynos4_soc == EXYNOS4210) 1047 if (exynos4_soc == EXYNOS4210)
1101 samsung_clk_init(np, reg_base, nr_clks, 1048 samsung_clk_init(np, reg_base, CLK_NR_CLKS,
1102 exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs), 1049 exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
1103 exynos4210_clk_save, ARRAY_SIZE(exynos4210_clk_save)); 1050 exynos4210_clk_save, ARRAY_SIZE(exynos4210_clk_save));
1104 else 1051 else
1105 samsung_clk_init(np, reg_base, nr_clks, 1052 samsung_clk_init(np, reg_base, CLK_NR_CLKS,
1106 exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs), 1053 exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
1107 exynos4x12_clk_save, ARRAY_SIZE(exynos4x12_clk_save)); 1054 exynos4x12_clk_save, ARRAY_SIZE(exynos4x12_clk_save));
1108 1055
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index adf32343c9f9..ff4beebe1f0b 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -10,6 +10,7 @@
10 * Common Clock Framework support for Exynos5250 SoC. 10 * Common Clock Framework support for Exynos5250 SoC.
11*/ 11*/
12 12
13#include <dt-bindings/clock/exynos5250.h>
13#include <linux/clk.h> 14#include <linux/clk.h>
14#include <linux/clkdev.h> 15#include <linux/clkdev.h>
15#include <linux/clk-provider.h> 16#include <linux/clk-provider.h>
@@ -25,6 +26,7 @@
25#define MPLL_LOCK 0x4000 26#define MPLL_LOCK 0x4000
26#define MPLL_CON0 0x4100 27#define MPLL_CON0 0x4100
27#define SRC_CORE1 0x4204 28#define SRC_CORE1 0x4204
29#define GATE_IP_ACP 0x8800
28#define CPLL_LOCK 0x10020 30#define CPLL_LOCK 0x10020
29#define EPLL_LOCK 0x10030 31#define EPLL_LOCK 0x10030
30#define VPLL_LOCK 0x10040 32#define VPLL_LOCK 0x10040
@@ -35,6 +37,7 @@
35#define GPLL_CON0 0x10150 37#define GPLL_CON0 0x10150
36#define SRC_TOP0 0x10210 38#define SRC_TOP0 0x10210
37#define SRC_TOP2 0x10218 39#define SRC_TOP2 0x10218
40#define SRC_TOP3 0x1021c
38#define SRC_GSCL 0x10220 41#define SRC_GSCL 0x10220
39#define SRC_DISP1_0 0x1022c 42#define SRC_DISP1_0 0x1022c
40#define SRC_MAU 0x10240 43#define SRC_MAU 0x10240
@@ -65,6 +68,7 @@
65#define DIV_PERIC4 0x10568 68#define DIV_PERIC4 0x10568
66#define DIV_PERIC5 0x1056c 69#define DIV_PERIC5 0x1056c
67#define GATE_IP_GSCL 0x10920 70#define GATE_IP_GSCL 0x10920
71#define GATE_IP_DISP1 0x10928
68#define GATE_IP_MFC 0x1092c 72#define GATE_IP_MFC 0x1092c
69#define GATE_IP_GEN 0x10934 73#define GATE_IP_GEN 0x10934
70#define GATE_IP_FSYS 0x10944 74#define GATE_IP_FSYS 0x10944
@@ -74,8 +78,6 @@
74#define BPLL_CON0 0x20110 78#define BPLL_CON0 0x20110
75#define SRC_CDREX 0x20200 79#define SRC_CDREX 0x20200
76#define PLL_DIV2_SEL 0x20a24 80#define PLL_DIV2_SEL 0x20a24
77#define GATE_IP_DISP1 0x10928
78#define GATE_IP_ACP 0x10000
79 81
80/* list of PLLs to be registered */ 82/* list of PLLs to be registered */
81enum exynos5250_plls { 83enum exynos5250_plls {
@@ -84,51 +86,6 @@ enum exynos5250_plls {
84}; 86};
85 87
86/* 88/*
87 * Let each supported clock get a unique id. This id is used to lookup the clock
88 * for device tree based platforms. The clocks are categorized into three
89 * sections: core, sclk gate and bus interface gate clocks.
90 *
91 * When adding a new clock to this list, it is advised to choose a clock
92 * category and add it to the end of that category. That is because the the
93 * device tree source file is referring to these ids and any change in the
94 * sequence number of existing clocks will require corresponding change in the
95 * device tree files. This limitation would go away when pre-processor support
96 * for dtc would be available.
97 */
98enum exynos5250_clks {
99 none,
100
101 /* core clocks */
102 fin_pll, fout_apll, fout_mpll, fout_bpll, fout_gpll, fout_cpll,
103 fout_epll, fout_vpll,
104
105 /* gate for special clocks (sclk) */
106 sclk_cam_bayer = 128, sclk_cam0, sclk_cam1, sclk_gscl_wa, sclk_gscl_wb,
107 sclk_fimd1, sclk_mipi1, sclk_dp, sclk_hdmi, sclk_pixel, sclk_audio0,
108 sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3,
109 sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm,
110 sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
111 div_i2s1, div_i2s2, sclk_hdmiphy,
112
113 /* gate clocks */
114 gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0,
115 smmu_gscl1, smmu_gscl2, smmu_gscl3, mfc, smmu_mfcl, smmu_mfcr, rotator,
116 jpeg, mdma1, smmu_rotator, smmu_jpeg, smmu_mdma1, pdma0, pdma1, sata,
117 usbotg, mipi_hsi, sdmmc0, sdmmc1, sdmmc2, sdmmc3, sromc, usb2, usb3,
118 sata_phyctrl, sata_phyi2c, uart0, uart1, uart2, uart3, uart4, i2c0,
119 i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c_hdmi, adc, spi0, spi1,
120 spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2,
121 hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1,
122 tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
123 wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d,
124
125 /* mux clocks */
126 mout_hdmi = 1024,
127
128 nr_clks,
129};
130
131/*
132 * list of controller registers to be saved and restored during a 89 * list of controller registers to be saved and restored during a
133 * suspend/resume cycle. 90 * suspend/resume cycle.
134 */ 91 */
@@ -138,6 +95,7 @@ static unsigned long exynos5250_clk_regs[] __initdata = {
138 SRC_CORE1, 95 SRC_CORE1,
139 SRC_TOP0, 96 SRC_TOP0,
140 SRC_TOP2, 97 SRC_TOP2,
98 SRC_TOP3,
141 SRC_GSCL, 99 SRC_GSCL,
142 SRC_DISP1_0, 100 SRC_DISP1_0,
143 SRC_MAU, 101 SRC_MAU,
@@ -181,7 +139,7 @@ static unsigned long exynos5250_clk_regs[] __initdata = {
181 139
182/* list of all parent clock list */ 140/* list of all parent clock list */
183PNAME(mout_apll_p) = { "fin_pll", "fout_apll", }; 141PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
184PNAME(mout_cpu_p) = { "mout_apll", "sclk_mpll", }; 142PNAME(mout_cpu_p) = { "mout_apll", "mout_mpll", };
185PNAME(mout_mpll_fout_p) = { "fout_mplldiv2", "fout_mpll" }; 143PNAME(mout_mpll_fout_p) = { "fout_mplldiv2", "fout_mpll" };
186PNAME(mout_mpll_p) = { "fin_pll", "mout_mpll_fout" }; 144PNAME(mout_mpll_p) = { "fin_pll", "mout_mpll_fout" };
187PNAME(mout_bpll_fout_p) = { "fout_bplldiv2", "fout_bpll" }; 145PNAME(mout_bpll_fout_p) = { "fout_bplldiv2", "fout_bpll" };
@@ -190,308 +148,432 @@ PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi27m" };
190PNAME(mout_vpll_p) = { "mout_vpllsrc", "fout_vpll" }; 148PNAME(mout_vpll_p) = { "mout_vpllsrc", "fout_vpll" };
191PNAME(mout_cpll_p) = { "fin_pll", "fout_cpll" }; 149PNAME(mout_cpll_p) = { "fin_pll", "fout_cpll" };
192PNAME(mout_epll_p) = { "fin_pll", "fout_epll" }; 150PNAME(mout_epll_p) = { "fin_pll", "fout_epll" };
193PNAME(mout_mpll_user_p) = { "fin_pll", "sclk_mpll" }; 151PNAME(mout_mpll_user_p) = { "fin_pll", "mout_mpll" };
194PNAME(mout_bpll_user_p) = { "fin_pll", "sclk_bpll" }; 152PNAME(mout_bpll_user_p) = { "fin_pll", "mout_bpll" };
195PNAME(mout_aclk166_p) = { "sclk_cpll", "sclk_mpll_user" }; 153PNAME(mout_aclk166_p) = { "mout_cpll", "mout_mpll_user" };
196PNAME(mout_aclk200_p) = { "sclk_mpll_user", "sclk_bpll_user" }; 154PNAME(mout_aclk200_p) = { "mout_mpll_user", "mout_bpll_user" };
155PNAME(mout_aclk200_sub_p) = { "fin_pll", "div_aclk200" };
156PNAME(mout_aclk266_sub_p) = { "fin_pll", "div_aclk266" };
157PNAME(mout_aclk333_sub_p) = { "fin_pll", "div_aclk333" };
197PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" }; 158PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" };
198PNAME(mout_usb3_p) = { "sclk_mpll_user", "sclk_cpll" }; 159PNAME(mout_usb3_p) = { "mout_mpll_user", "mout_cpll" };
199PNAME(mout_group1_p) = { "fin_pll", "fin_pll", "sclk_hdmi27m", 160PNAME(mout_group1_p) = { "fin_pll", "fin_pll", "sclk_hdmi27m",
200 "sclk_dptxphy", "sclk_uhostphy", "sclk_hdmiphy", 161 "sclk_dptxphy", "sclk_uhostphy", "sclk_hdmiphy",
201 "sclk_mpll_user", "sclk_epll", "sclk_vpll", 162 "mout_mpll_user", "mout_epll", "mout_vpll",
202 "sclk_cpll" }; 163 "mout_cpll", "none", "none",
164 "none", "none", "none",
165 "none" };
203PNAME(mout_audio0_p) = { "cdclk0", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy", 166PNAME(mout_audio0_p) = { "cdclk0", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
204 "sclk_uhostphy", "sclk_hdmiphy", 167 "sclk_uhostphy", "fin_pll",
205 "sclk_mpll_user", "sclk_epll", "sclk_vpll", 168 "mout_mpll_user", "mout_epll", "mout_vpll",
206 "sclk_cpll" }; 169 "mout_cpll", "none", "none",
170 "none", "none", "none",
171 "none" };
207PNAME(mout_audio1_p) = { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy", 172PNAME(mout_audio1_p) = { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
208 "sclk_uhostphy", "sclk_hdmiphy", 173 "sclk_uhostphy", "fin_pll",
209 "sclk_mpll_user", "sclk_epll", "sclk_vpll", 174 "mout_mpll_user", "mout_epll", "mout_vpll",
210 "sclk_cpll" }; 175 "mout_cpll", "none", "none",
176 "none", "none", "none",
177 "none" };
211PNAME(mout_audio2_p) = { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy", 178PNAME(mout_audio2_p) = { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
212 "sclk_uhostphy", "sclk_hdmiphy", 179 "sclk_uhostphy", "fin_pll",
213 "sclk_mpll_user", "sclk_epll", "sclk_vpll", 180 "mout_mpll_user", "mout_epll", "mout_vpll",
214 "sclk_cpll" }; 181 "mout_cpll", "none", "none",
182 "none", "none", "none",
183 "none" };
215PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2", 184PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
216 "spdif_extclk" }; 185 "spdif_extclk" };
217 186
218/* fixed rate clocks generated outside the soc */ 187/* fixed rate clocks generated outside the soc */
219static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = { 188static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = {
220 FRATE(fin_pll, "fin_pll", NULL, CLK_IS_ROOT, 0), 189 FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0),
221}; 190};
222 191
223/* fixed rate clocks generated inside the soc */ 192/* fixed rate clocks generated inside the soc */
224static struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = { 193static struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = {
225 FRATE(sclk_hdmiphy, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000), 194 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
226 FRATE(none, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000), 195 FRATE(0, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000),
227 FRATE(none, "sclk_dptxphy", NULL, CLK_IS_ROOT, 24000000), 196 FRATE(0, "sclk_dptxphy", NULL, CLK_IS_ROOT, 24000000),
228 FRATE(none, "sclk_uhostphy", NULL, CLK_IS_ROOT, 48000000), 197 FRATE(0, "sclk_uhostphy", NULL, CLK_IS_ROOT, 48000000),
229}; 198};
230 199
231static struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = { 200static struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = {
232 FFACTOR(none, "fout_mplldiv2", "fout_mpll", 1, 2, 0), 201 FFACTOR(0, "fout_mplldiv2", "fout_mpll", 1, 2, 0),
233 FFACTOR(none, "fout_bplldiv2", "fout_bpll", 1, 2, 0), 202 FFACTOR(0, "fout_bplldiv2", "fout_bpll", 1, 2, 0),
234}; 203};
235 204
236static struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initdata = { 205static struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initdata = {
237 MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1), 206 MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
238}; 207};
239 208
240static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { 209static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
241 MUX_A(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, "mout_apll"), 210 /*
242 MUX_A(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"), 211 * NOTE: Following table is sorted by (clock domain, register address,
243 MUX(none, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1), 212 * bitfield shift) triplet in ascending order. When adding new entries,
244 MUX_A(none, "sclk_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"), 213 * please make sure that the order is kept, to avoid merge conflicts
245 MUX(none, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1), 214 * and make further work with defined data easier.
246 MUX(none, "sclk_bpll", mout_bpll_p, SRC_CDREX, 0, 1), 215 */
247 MUX(none, "sclk_vpll", mout_vpll_p, SRC_TOP2, 16, 1), 216
248 MUX(none, "sclk_epll", mout_epll_p, SRC_TOP2, 12, 1), 217 /*
249 MUX(none, "sclk_cpll", mout_cpll_p, SRC_TOP2, 8, 1), 218 * CMU_CPU
250 MUX(none, "sclk_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1), 219 */
251 MUX(none, "sclk_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1), 220 MUX_FA(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
252 MUX(none, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1), 221 CLK_SET_RATE_PARENT, 0, "mout_apll"),
253 MUX(none, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1), 222 MUX_A(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"),
254 MUX(none, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1), 223
255 MUX(none, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4), 224 /*
256 MUX(none, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4), 225 * CMU_CORE
257 MUX(none, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4), 226 */
258 MUX(none, "mout_gscl_wa", mout_group1_p, SRC_GSCL, 24, 4), 227 MUX_A(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"),
259 MUX(none, "mout_gscl_wb", mout_group1_p, SRC_GSCL, 28, 4), 228
260 MUX(none, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4), 229 /*
261 MUX(none, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4), 230 * CMU_TOP
262 MUX(none, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4), 231 */
263 MUX(mout_hdmi, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1), 232 MUX(0, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
264 MUX(none, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4), 233 MUX(0, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
265 MUX(none, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4), 234 MUX(0, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
266 MUX(none, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4), 235
267 MUX(none, "mout_mmc2", mout_group1_p, SRC_FSYS, 8, 4), 236 MUX(0, "mout_cpll", mout_cpll_p, SRC_TOP2, 8, 1),
268 MUX(none, "mout_mmc3", mout_group1_p, SRC_FSYS, 12, 4), 237 MUX(0, "mout_epll", mout_epll_p, SRC_TOP2, 12, 1),
269 MUX(none, "mout_sata", mout_aclk200_p, SRC_FSYS, 24, 1), 238 MUX(0, "mout_vpll", mout_vpll_p, SRC_TOP2, 16, 1),
270 MUX(none, "mout_usb3", mout_usb3_p, SRC_FSYS, 28, 1), 239 MUX(0, "mout_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1),
271 MUX(none, "mout_jpeg", mout_group1_p, SRC_GEN, 0, 4), 240 MUX(0, "mout_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1),
272 MUX(none, "mout_uart0", mout_group1_p, SRC_PERIC0, 0, 4), 241
273 MUX(none, "mout_uart1", mout_group1_p, SRC_PERIC0, 4, 4), 242 MUX(0, "mout_aclk200_disp1_sub", mout_aclk200_sub_p, SRC_TOP3, 4, 1),
274 MUX(none, "mout_uart2", mout_group1_p, SRC_PERIC0, 8, 4), 243 MUX(0, "mout_aclk266_gscl_sub", mout_aclk266_sub_p, SRC_TOP3, 8, 1),
275 MUX(none, "mout_uart3", mout_group1_p, SRC_PERIC0, 12, 4), 244 MUX(0, "mout_aclk333_sub", mout_aclk333_sub_p, SRC_TOP3, 24, 1),
276 MUX(none, "mout_pwm", mout_group1_p, SRC_PERIC0, 24, 4), 245
277 MUX(none, "mout_audio1", mout_audio1_p, SRC_PERIC1, 0, 4), 246 MUX(0, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4),
278 MUX(none, "mout_audio2", mout_audio2_p, SRC_PERIC1, 4, 4), 247 MUX(0, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4),
279 MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIC1, 8, 2), 248 MUX(0, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4),
280 MUX(none, "mout_spi0", mout_group1_p, SRC_PERIC1, 16, 4), 249 MUX(0, "mout_gscl_wa", mout_group1_p, SRC_GSCL, 24, 4),
281 MUX(none, "mout_spi1", mout_group1_p, SRC_PERIC1, 20, 4), 250 MUX(0, "mout_gscl_wb", mout_group1_p, SRC_GSCL, 28, 4),
282 MUX(none, "mout_spi2", mout_group1_p, SRC_PERIC1, 24, 4), 251
252 MUX(0, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4),
253 MUX(0, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4),
254 MUX(0, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4),
255 MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1),
256
257 MUX(0, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4),
258
259 MUX(0, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4),
260 MUX(0, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4),
261 MUX(0, "mout_mmc2", mout_group1_p, SRC_FSYS, 8, 4),
262 MUX(0, "mout_mmc3", mout_group1_p, SRC_FSYS, 12, 4),
263 MUX(0, "mout_sata", mout_aclk200_p, SRC_FSYS, 24, 1),
264 MUX(0, "mout_usb3", mout_usb3_p, SRC_FSYS, 28, 1),
265
266 MUX(0, "mout_jpeg", mout_group1_p, SRC_GEN, 0, 4),
267
268 MUX(0, "mout_uart0", mout_group1_p, SRC_PERIC0, 0, 4),
269 MUX(0, "mout_uart1", mout_group1_p, SRC_PERIC0, 4, 4),
270 MUX(0, "mout_uart2", mout_group1_p, SRC_PERIC0, 8, 4),
271 MUX(0, "mout_uart3", mout_group1_p, SRC_PERIC0, 12, 4),
272 MUX(0, "mout_pwm", mout_group1_p, SRC_PERIC0, 24, 4),
273
274 MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 0, 4),
275 MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 4, 4),
276 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC1, 8, 2),
277 MUX(0, "mout_spi0", mout_group1_p, SRC_PERIC1, 16, 4),
278 MUX(0, "mout_spi1", mout_group1_p, SRC_PERIC1, 20, 4),
279 MUX(0, "mout_spi2", mout_group1_p, SRC_PERIC1, 24, 4),
280
281 /*
282 * CMU_CDREX
283 */
284 MUX(0, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1),
285
286 MUX(0, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1),
287 MUX(0, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1),
283}; 288};
284 289
285static struct samsung_div_clock exynos5250_div_clks[] __initdata = { 290static struct samsung_div_clock exynos5250_div_clks[] __initdata = {
286 DIV(none, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 291 /*
287 DIV(none, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 292 * NOTE: Following table is sorted by (clock domain, register address,
288 DIV(none, "aclk66_pre", "sclk_mpll_user", DIV_TOP1, 24, 3), 293 * bitfield shift) triplet in ascending order. When adding new entries,
289 DIV(none, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3), 294 * please make sure that the order is kept, to avoid merge conflicts
290 DIV(none, "aclk266", "sclk_mpll_user", DIV_TOP0, 16, 3), 295 * and make further work with defined data easier.
291 DIV(none, "aclk166", "mout_aclk166", DIV_TOP0, 8, 3), 296 */
292 DIV(none, "aclk333", "mout_aclk333", DIV_TOP0, 20, 3), 297
293 DIV(none, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3), 298 /*
294 DIV(none, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4), 299 * CMU_CPU
295 DIV(none, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4), 300 */
296 DIV(none, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4), 301 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
297 DIV(none, "div_gscl_wa", "mout_gscl_wa", DIV_GSCL, 24, 4), 302 DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
298 DIV(none, "div_gscl_wb", "mout_gscl_wb", DIV_GSCL, 28, 4), 303 DIV_A(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3, "armclk"),
299 DIV(none, "div_fimd1", "mout_fimd1", DIV_DISP1_0, 0, 4), 304
300 DIV(none, "div_mipi1", "mout_mipi1", DIV_DISP1_0, 16, 4), 305 /*
301 DIV(none, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4), 306 * CMU_TOP
302 DIV(none, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4), 307 */
303 DIV(none, "div_audio0", "mout_audio0", DIV_MAU, 0, 4), 308 DIV(0, "div_aclk66", "div_aclk66_pre", DIV_TOP0, 0, 3),
304 DIV(none, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8), 309 DIV(0, "div_aclk166", "mout_aclk166", DIV_TOP0, 8, 3),
305 DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4), 310 DIV(0, "div_aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
306 DIV(none, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4), 311 DIV(0, "div_aclk266", "mout_mpll_user", DIV_TOP0, 16, 3),
307 DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), 312 DIV(0, "div_aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
308 DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4), 313
309 DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4), 314 DIV(0, "div_aclk66_pre", "mout_mpll_user", DIV_TOP1, 24, 3),
310 DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4), 315
311 DIV(none, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4), 316 DIV(0, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4),
312 DIV(none, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4), 317 DIV(0, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4),
313 DIV(none, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4), 318 DIV(0, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4),
314 DIV(none, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4), 319 DIV(0, "div_gscl_wa", "mout_gscl_wa", DIV_GSCL, 24, 4),
315 DIV(none, "div_spi0", "mout_spi0", DIV_PERIC1, 0, 4), 320 DIV(0, "div_gscl_wb", "mout_gscl_wb", DIV_GSCL, 28, 4),
316 DIV(none, "div_spi1", "mout_spi1", DIV_PERIC1, 16, 4), 321
317 DIV(none, "div_spi2", "mout_spi2", DIV_PERIC2, 0, 4), 322 DIV(0, "div_fimd1", "mout_fimd1", DIV_DISP1_0, 0, 4),
318 DIV(none, "div_pwm", "mout_pwm", DIV_PERIC3, 0, 4), 323 DIV(0, "div_mipi1", "mout_mipi1", DIV_DISP1_0, 16, 4),
319 DIV(none, "div_audio1", "mout_audio1", DIV_PERIC4, 0, 4), 324 DIV_F(0, "div_mipi1_pre", "div_mipi1",
320 DIV(none, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8),
321 DIV(none, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4),
322 DIV(none, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8),
323 DIV(div_i2s1, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
324 DIV(div_i2s2, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
325 DIV(sclk_pixel, "div_hdmi_pixel", "sclk_vpll", DIV_DISP1_0, 28, 4),
326 DIV_A(none, "armclk", "div_arm", DIV_CPU0, 28, 3, "armclk"),
327 DIV_F(none, "div_mipi1_pre", "div_mipi1",
328 DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0), 325 DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0),
329 DIV_F(none, "div_mmc_pre0", "div_mmc0", 326 DIV(0, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4),
327 DIV(CLK_SCLK_PIXEL, "div_hdmi_pixel", "mout_vpll", DIV_DISP1_0, 28, 4),
328
329 DIV(0, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4),
330
331 DIV(0, "div_audio0", "mout_audio0", DIV_MAU, 0, 4),
332 DIV(CLK_DIV_PCM0, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8),
333
334 DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
335 DIV(0, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4),
336
337 DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
338 DIV_F(0, "div_mmc_pre0", "div_mmc0",
330 DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0), 339 DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
331 DIV_F(none, "div_mmc_pre1", "div_mmc1", 340 DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
341 DIV_F(0, "div_mmc_pre1", "div_mmc1",
332 DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0), 342 DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
333 DIV_F(none, "div_mmc_pre2", "div_mmc2", 343
344 DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
345 DIV_F(0, "div_mmc_pre2", "div_mmc2",
334 DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0), 346 DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
335 DIV_F(none, "div_mmc_pre3", "div_mmc3", 347 DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
348 DIV_F(0, "div_mmc_pre3", "div_mmc3",
336 DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0), 349 DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0),
337 DIV_F(none, "div_spi_pre0", "div_spi0", 350
351 DIV(0, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
352 DIV(0, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
353 DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
354 DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
355
356 DIV(0, "div_spi0", "mout_spi0", DIV_PERIC1, 0, 4),
357 DIV_F(0, "div_spi_pre0", "div_spi0",
338 DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0), 358 DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0),
339 DIV_F(none, "div_spi_pre1", "div_spi1", 359 DIV(0, "div_spi1", "mout_spi1", DIV_PERIC1, 16, 4),
360 DIV_F(0, "div_spi_pre1", "div_spi1",
340 DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0), 361 DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0),
341 DIV_F(none, "div_spi_pre2", "div_spi2", 362
363 DIV(0, "div_spi2", "mout_spi2", DIV_PERIC2, 0, 4),
364 DIV_F(0, "div_spi_pre2", "div_spi2",
342 DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0), 365 DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0),
366
367 DIV(0, "div_pwm", "mout_pwm", DIV_PERIC3, 0, 4),
368
369 DIV(0, "div_audio1", "mout_audio1", DIV_PERIC4, 0, 4),
370 DIV(0, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8),
371 DIV(0, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4),
372 DIV(0, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8),
373
374 DIV(CLK_DIV_I2S1, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
375 DIV(CLK_DIV_I2S2, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
343}; 376};
344 377
345static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { 378static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
346 GATE(gscl0, "gscl0", "none", GATE_IP_GSCL, 0, 0, 0), 379 /*
347 GATE(gscl1, "gscl1", "none", GATE_IP_GSCL, 1, 0, 0), 380 * NOTE: Following table is sorted by (clock domain, register address,
348 GATE(gscl2, "gscl2", "aclk266", GATE_IP_GSCL, 2, 0, 0), 381 * bitfield shift) triplet in ascending order. When adding new entries,
349 GATE(gscl3, "gscl3", "aclk266", GATE_IP_GSCL, 3, 0, 0), 382 * please make sure that the order is kept, to avoid merge conflicts
350 GATE(gscl_wa, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0), 383 * and make further work with defined data easier.
351 GATE(gscl_wb, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0), 384 */
352 GATE(smmu_gscl0, "smmu_gscl0", "aclk266", GATE_IP_GSCL, 7, 0, 0), 385
353 GATE(smmu_gscl1, "smmu_gscl1", "aclk266", GATE_IP_GSCL, 8, 0, 0), 386 /*
354 GATE(smmu_gscl2, "smmu_gscl2", "aclk266", GATE_IP_GSCL, 9, 0, 0), 387 * CMU_ACP
355 GATE(smmu_gscl3, "smmu_gscl3", "aclk266", GATE_IP_GSCL, 10, 0, 0), 388 */
356 GATE(mfc, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), 389 GATE(CLK_MDMA0, "mdma0", "div_aclk266", GATE_IP_ACP, 1, 0, 0),
357 GATE(smmu_mfcl, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0), 390 GATE(CLK_G2D, "g2d", "div_aclk200", GATE_IP_ACP, 3, 0, 0),
358 GATE(smmu_mfcr, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0), 391 GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "div_aclk266", GATE_IP_ACP, 5, 0, 0),
359 GATE(rotator, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0), 392
360 GATE(jpeg, "jpeg", "aclk166", GATE_IP_GEN, 2, 0, 0), 393 /*
361 GATE(mdma1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0), 394 * CMU_TOP
362 GATE(smmu_rotator, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0), 395 */
363 GATE(smmu_jpeg, "smmu_jpeg", "aclk166", GATE_IP_GEN, 7, 0, 0), 396 GATE(CLK_SCLK_CAM_BAYER, "sclk_cam_bayer", "div_cam_bayer",
364 GATE(smmu_mdma1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0),
365 GATE(pdma0, "pdma0", "aclk200", GATE_IP_FSYS, 1, 0, 0),
366 GATE(pdma1, "pdma1", "aclk200", GATE_IP_FSYS, 2, 0, 0),
367 GATE(sata, "sata", "aclk200", GATE_IP_FSYS, 6, 0, 0),
368 GATE(usbotg, "usbotg", "aclk200", GATE_IP_FSYS, 7, 0, 0),
369 GATE(mipi_hsi, "mipi_hsi", "aclk200", GATE_IP_FSYS, 8, 0, 0),
370 GATE(sdmmc0, "sdmmc0", "aclk200", GATE_IP_FSYS, 12, 0, 0),
371 GATE(sdmmc1, "sdmmc1", "aclk200", GATE_IP_FSYS, 13, 0, 0),
372 GATE(sdmmc2, "sdmmc2", "aclk200", GATE_IP_FSYS, 14, 0, 0),
373 GATE(sdmmc3, "sdmmc3", "aclk200", GATE_IP_FSYS, 15, 0, 0),
374 GATE(sromc, "sromc", "aclk200", GATE_IP_FSYS, 17, 0, 0),
375 GATE(usb2, "usb2", "aclk200", GATE_IP_FSYS, 18, 0, 0),
376 GATE(usb3, "usb3", "aclk200", GATE_IP_FSYS, 19, 0, 0),
377 GATE(sata_phyctrl, "sata_phyctrl", "aclk200", GATE_IP_FSYS, 24, 0, 0),
378 GATE(sata_phyi2c, "sata_phyi2c", "aclk200", GATE_IP_FSYS, 25, 0, 0),
379 GATE(uart0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
380 GATE(uart1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
381 GATE(uart2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
382 GATE(uart3, "uart3", "aclk66", GATE_IP_PERIC, 3, 0, 0),
383 GATE(uart4, "uart4", "aclk66", GATE_IP_PERIC, 4, 0, 0),
384 GATE(i2c0, "i2c0", "aclk66", GATE_IP_PERIC, 6, 0, 0),
385 GATE(i2c1, "i2c1", "aclk66", GATE_IP_PERIC, 7, 0, 0),
386 GATE(i2c2, "i2c2", "aclk66", GATE_IP_PERIC, 8, 0, 0),
387 GATE(i2c3, "i2c3", "aclk66", GATE_IP_PERIC, 9, 0, 0),
388 GATE(i2c4, "i2c4", "aclk66", GATE_IP_PERIC, 10, 0, 0),
389 GATE(i2c5, "i2c5", "aclk66", GATE_IP_PERIC, 11, 0, 0),
390 GATE(i2c6, "i2c6", "aclk66", GATE_IP_PERIC, 12, 0, 0),
391 GATE(i2c7, "i2c7", "aclk66", GATE_IP_PERIC, 13, 0, 0),
392 GATE(i2c_hdmi, "i2c_hdmi", "aclk66", GATE_IP_PERIC, 14, 0, 0),
393 GATE(adc, "adc", "aclk66", GATE_IP_PERIC, 15, 0, 0),
394 GATE(spi0, "spi0", "aclk66", GATE_IP_PERIC, 16, 0, 0),
395 GATE(spi1, "spi1", "aclk66", GATE_IP_PERIC, 17, 0, 0),
396 GATE(spi2, "spi2", "aclk66", GATE_IP_PERIC, 18, 0, 0),
397 GATE(i2s1, "i2s1", "aclk66", GATE_IP_PERIC, 20, 0, 0),
398 GATE(i2s2, "i2s2", "aclk66", GATE_IP_PERIC, 21, 0, 0),
399 GATE(pcm1, "pcm1", "aclk66", GATE_IP_PERIC, 22, 0, 0),
400 GATE(pcm2, "pcm2", "aclk66", GATE_IP_PERIC, 23, 0, 0),
401 GATE(pwm, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0),
402 GATE(spdif, "spdif", "aclk66", GATE_IP_PERIC, 26, 0, 0),
403 GATE(ac97, "ac97", "aclk66", GATE_IP_PERIC, 27, 0, 0),
404 GATE(hsi2c0, "hsi2c0", "aclk66", GATE_IP_PERIC, 28, 0, 0),
405 GATE(hsi2c1, "hsi2c1", "aclk66", GATE_IP_PERIC, 29, 0, 0),
406 GATE(hsi2c2, "hsi2c2", "aclk66", GATE_IP_PERIC, 30, 0, 0),
407 GATE(hsi2c3, "hsi2c3", "aclk66", GATE_IP_PERIC, 31, 0, 0),
408 GATE(chipid, "chipid", "aclk66", GATE_IP_PERIS, 0, 0, 0),
409 GATE(sysreg, "sysreg", "aclk66", GATE_IP_PERIS, 1, 0, 0),
410 GATE(pmu, "pmu", "aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED, 0),
411 GATE(tzpc0, "tzpc0", "aclk66", GATE_IP_PERIS, 6, 0, 0),
412 GATE(tzpc1, "tzpc1", "aclk66", GATE_IP_PERIS, 7, 0, 0),
413 GATE(tzpc2, "tzpc2", "aclk66", GATE_IP_PERIS, 8, 0, 0),
414 GATE(tzpc3, "tzpc3", "aclk66", GATE_IP_PERIS, 9, 0, 0),
415 GATE(tzpc4, "tzpc4", "aclk66", GATE_IP_PERIS, 10, 0, 0),
416 GATE(tzpc5, "tzpc5", "aclk66", GATE_IP_PERIS, 11, 0, 0),
417 GATE(tzpc6, "tzpc6", "aclk66", GATE_IP_PERIS, 12, 0, 0),
418 GATE(tzpc7, "tzpc7", "aclk66", GATE_IP_PERIS, 13, 0, 0),
419 GATE(tzpc8, "tzpc8", "aclk66", GATE_IP_PERIS, 14, 0, 0),
420 GATE(tzpc9, "tzpc9", "aclk66", GATE_IP_PERIS, 15, 0, 0),
421 GATE(hdmi_cec, "hdmi_cec", "aclk66", GATE_IP_PERIS, 16, 0, 0),
422 GATE(mct, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
423 GATE(wdt, "wdt", "aclk66", GATE_IP_PERIS, 19, 0, 0),
424 GATE(rtc, "rtc", "aclk66", GATE_IP_PERIS, 20, 0, 0),
425 GATE(tmu, "tmu", "aclk66", GATE_IP_PERIS, 21, 0, 0),
426 GATE(cmu_top, "cmu_top", "aclk66",
427 GATE_IP_PERIS, 3, CLK_IGNORE_UNUSED, 0),
428 GATE(cmu_core, "cmu_core", "aclk66",
429 GATE_IP_PERIS, 4, CLK_IGNORE_UNUSED, 0),
430 GATE(cmu_mem, "cmu_mem", "aclk66",
431 GATE_IP_PERIS, 5, CLK_IGNORE_UNUSED, 0),
432 GATE(sclk_cam_bayer, "sclk_cam_bayer", "div_cam_bayer",
433 SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0), 397 SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0),
434 GATE(sclk_cam0, "sclk_cam0", "div_cam0", 398 GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0",
435 SRC_MASK_GSCL, 16, CLK_SET_RATE_PARENT, 0), 399 SRC_MASK_GSCL, 16, CLK_SET_RATE_PARENT, 0),
436 GATE(sclk_cam1, "sclk_cam1", "div_cam1", 400 GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
437 SRC_MASK_GSCL, 20, CLK_SET_RATE_PARENT, 0), 401 SRC_MASK_GSCL, 20, CLK_SET_RATE_PARENT, 0),
438 GATE(sclk_gscl_wa, "sclk_gscl_wa", "div_gscl_wa", 402 GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "div_gscl_wa",
439 SRC_MASK_GSCL, 24, CLK_SET_RATE_PARENT, 0), 403 SRC_MASK_GSCL, 24, CLK_SET_RATE_PARENT, 0),
440 GATE(sclk_gscl_wb, "sclk_gscl_wb", "div_gscl_wb", 404 GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "div_gscl_wb",
441 SRC_MASK_GSCL, 28, CLK_SET_RATE_PARENT, 0), 405 SRC_MASK_GSCL, 28, CLK_SET_RATE_PARENT, 0),
442 GATE(sclk_fimd1, "sclk_fimd1", "div_fimd1", 406
407 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1",
443 SRC_MASK_DISP1_0, 0, CLK_SET_RATE_PARENT, 0), 408 SRC_MASK_DISP1_0, 0, CLK_SET_RATE_PARENT, 0),
444 GATE(sclk_mipi1, "sclk_mipi1", "div_mipi1", 409 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "div_mipi1",
445 SRC_MASK_DISP1_0, 12, CLK_SET_RATE_PARENT, 0), 410 SRC_MASK_DISP1_0, 12, CLK_SET_RATE_PARENT, 0),
446 GATE(sclk_dp, "sclk_dp", "div_dp", 411 GATE(CLK_SCLK_DP, "sclk_dp", "div_dp",
447 SRC_MASK_DISP1_0, 16, CLK_SET_RATE_PARENT, 0), 412 SRC_MASK_DISP1_0, 16, CLK_SET_RATE_PARENT, 0),
448 GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", 413 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
449 SRC_MASK_DISP1_0, 20, 0, 0), 414 SRC_MASK_DISP1_0, 20, 0, 0),
450 GATE(sclk_audio0, "sclk_audio0", "div_audio0", 415
416 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0",
451 SRC_MASK_MAU, 0, CLK_SET_RATE_PARENT, 0), 417 SRC_MASK_MAU, 0, CLK_SET_RATE_PARENT, 0),
452 GATE(sclk_mmc0, "sclk_mmc0", "div_mmc_pre0", 418
419 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
453 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0), 420 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
454 GATE(sclk_mmc1, "sclk_mmc1", "div_mmc_pre1", 421 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1",
455 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0), 422 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
456 GATE(sclk_mmc2, "sclk_mmc2", "div_mmc_pre2", 423 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2",
457 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0), 424 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
458 GATE(sclk_mmc3, "sclk_mmc3", "div_mmc_pre3", 425 GATE(CLK_SCLK_MMC3, "sclk_mmc3", "div_mmc_pre3",
459 SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0), 426 SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0),
460 GATE(sclk_sata, "sclk_sata", "div_sata", 427 GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata",
461 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 428 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
462 GATE(sclk_usb3, "sclk_usb3", "div_usb3", 429 GATE(CLK_SCLK_USB3, "sclk_usb3", "div_usb3",
463 SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0), 430 SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0),
464 GATE(sclk_jpeg, "sclk_jpeg", "div_jpeg", 431
432 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_jpeg",
465 SRC_MASK_GEN, 0, CLK_SET_RATE_PARENT, 0), 433 SRC_MASK_GEN, 0, CLK_SET_RATE_PARENT, 0),
466 GATE(sclk_uart0, "sclk_uart0", "div_uart0", 434
435 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
467 SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0), 436 SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
468 GATE(sclk_uart1, "sclk_uart1", "div_uart1", 437 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
469 SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0), 438 SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
470 GATE(sclk_uart2, "sclk_uart2", "div_uart2", 439 GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
471 SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0), 440 SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
472 GATE(sclk_uart3, "sclk_uart3", "div_uart3", 441 GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
473 SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0), 442 SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0),
474 GATE(sclk_pwm, "sclk_pwm", "div_pwm", 443 GATE(CLK_SCLK_PWM, "sclk_pwm", "div_pwm",
475 SRC_MASK_PERIC0, 24, CLK_SET_RATE_PARENT, 0), 444 SRC_MASK_PERIC0, 24, CLK_SET_RATE_PARENT, 0),
476 GATE(sclk_audio1, "sclk_audio1", "div_audio1", 445
446 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1",
477 SRC_MASK_PERIC1, 0, CLK_SET_RATE_PARENT, 0), 447 SRC_MASK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
478 GATE(sclk_audio2, "sclk_audio2", "div_audio2", 448 GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2",
479 SRC_MASK_PERIC1, 4, CLK_SET_RATE_PARENT, 0), 449 SRC_MASK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
480 GATE(sclk_spdif, "sclk_spdif", "mout_spdif", 450 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
481 SRC_MASK_PERIC1, 4, 0, 0), 451 SRC_MASK_PERIC1, 4, 0, 0),
482 GATE(sclk_spi0, "sclk_spi0", "div_spi_pre0", 452 GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0",
483 SRC_MASK_PERIC1, 16, CLK_SET_RATE_PARENT, 0), 453 SRC_MASK_PERIC1, 16, CLK_SET_RATE_PARENT, 0),
484 GATE(sclk_spi1, "sclk_spi1", "div_spi_pre1", 454 GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi_pre1",
485 SRC_MASK_PERIC1, 20, CLK_SET_RATE_PARENT, 0), 455 SRC_MASK_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
486 GATE(sclk_spi2, "sclk_spi2", "div_spi_pre2", 456 GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi_pre2",
487 SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0), 457 SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0),
488 GATE(fimd1, "fimd1", "aclk200", GATE_IP_DISP1, 0, 0, 0), 458
489 GATE(mie1, "mie1", "aclk200", GATE_IP_DISP1, 1, 0, 0), 459 GATE(CLK_GSCL0, "gscl0", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 0, 0,
490 GATE(dsim0, "dsim0", "aclk200", GATE_IP_DISP1, 3, 0, 0), 460 0),
491 GATE(dp, "dp", "aclk200", GATE_IP_DISP1, 4, 0, 0), 461 GATE(CLK_GSCL1, "gscl1", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 1, 0,
492 GATE(mixer, "mixer", "mout_aclk200_disp1", GATE_IP_DISP1, 5, 0, 0), 462 0),
493 GATE(hdmi, "hdmi", "mout_aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), 463 GATE(CLK_GSCL2, "gscl2", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 2, 0,
494 GATE(g2d, "g2d", "aclk200", GATE_IP_ACP, 3, 0, 0), 464 0),
465 GATE(CLK_GSCL3, "gscl3", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 3, 0,
466 0),
467 GATE(CLK_GSCL_WA, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0),
468 GATE(CLK_GSCL_WB, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0),
469 GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "mout_aclk266_gscl_sub",
470 GATE_IP_GSCL, 7, 0, 0),
471 GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "mout_aclk266_gscl_sub",
472 GATE_IP_GSCL, 8, 0, 0),
473 GATE(CLK_SMMU_GSCL2, "smmu_gscl2", "mout_aclk266_gscl_sub",
474 GATE_IP_GSCL, 9, 0, 0),
475 GATE(CLK_SMMU_GSCL3, "smmu_gscl3", "mout_aclk266_gscl_sub",
476 GATE_IP_GSCL, 10, 0, 0),
477
478 GATE(CLK_FIMD1, "fimd1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 0, 0,
479 0),
480 GATE(CLK_MIE1, "mie1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 1, 0,
481 0),
482 GATE(CLK_DSIM0, "dsim0", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 3, 0,
483 0),
484 GATE(CLK_DP, "dp", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 4, 0, 0),
485 GATE(CLK_MIXER, "mixer", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 5, 0,
486 0),
487 GATE(CLK_HDMI, "hdmi", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 6, 0,
488 0),
489
490 GATE(CLK_MFC, "mfc", "mout_aclk333_sub", GATE_IP_MFC, 0, 0, 0),
491 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "mout_aclk333_sub", GATE_IP_MFC, 1, 0,
492 0),
493 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "mout_aclk333_sub", GATE_IP_MFC, 2, 0,
494 0),
495
496 GATE(CLK_ROTATOR, "rotator", "div_aclk266", GATE_IP_GEN, 1, 0, 0),
497 GATE(CLK_JPEG, "jpeg", "div_aclk166", GATE_IP_GEN, 2, 0, 0),
498 GATE(CLK_MDMA1, "mdma1", "div_aclk266", GATE_IP_GEN, 4, 0, 0),
499 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "div_aclk266", GATE_IP_GEN, 6, 0,
500 0),
501 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "div_aclk166", GATE_IP_GEN, 7, 0, 0),
502 GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "div_aclk266", GATE_IP_GEN, 9, 0, 0),
503
504 GATE(CLK_PDMA0, "pdma0", "div_aclk200", GATE_IP_FSYS, 1, 0, 0),
505 GATE(CLK_PDMA1, "pdma1", "div_aclk200", GATE_IP_FSYS, 2, 0, 0),
506 GATE(CLK_SATA, "sata", "div_aclk200", GATE_IP_FSYS, 6, 0, 0),
507 GATE(CLK_USBOTG, "usbotg", "div_aclk200", GATE_IP_FSYS, 7, 0, 0),
508 GATE(CLK_MIPI_HSI, "mipi_hsi", "div_aclk200", GATE_IP_FSYS, 8, 0, 0),
509 GATE(CLK_SDMMC0, "sdmmc0", "div_aclk200", GATE_IP_FSYS, 12, 0, 0),
510 GATE(CLK_SDMMC1, "sdmmc1", "div_aclk200", GATE_IP_FSYS, 13, 0, 0),
511 GATE(CLK_SDMMC2, "sdmmc2", "div_aclk200", GATE_IP_FSYS, 14, 0, 0),
512 GATE(CLK_SDMMC3, "sdmmc3", "div_aclk200", GATE_IP_FSYS, 15, 0, 0),
513 GATE(CLK_SROMC, "sromc", "div_aclk200", GATE_IP_FSYS, 17, 0, 0),
514 GATE(CLK_USB2, "usb2", "div_aclk200", GATE_IP_FSYS, 18, 0, 0),
515 GATE(CLK_USB3, "usb3", "div_aclk200", GATE_IP_FSYS, 19, 0, 0),
516 GATE(CLK_SATA_PHYCTRL, "sata_phyctrl", "div_aclk200",
517 GATE_IP_FSYS, 24, 0, 0),
518 GATE(CLK_SATA_PHYI2C, "sata_phyi2c", "div_aclk200", GATE_IP_FSYS, 25, 0,
519 0),
520
521 GATE(CLK_UART0, "uart0", "div_aclk66", GATE_IP_PERIC, 0, 0, 0),
522 GATE(CLK_UART1, "uart1", "div_aclk66", GATE_IP_PERIC, 1, 0, 0),
523 GATE(CLK_UART2, "uart2", "div_aclk66", GATE_IP_PERIC, 2, 0, 0),
524 GATE(CLK_UART3, "uart3", "div_aclk66", GATE_IP_PERIC, 3, 0, 0),
525 GATE(CLK_UART4, "uart4", "div_aclk66", GATE_IP_PERIC, 4, 0, 0),
526 GATE(CLK_I2C0, "i2c0", "div_aclk66", GATE_IP_PERIC, 6, 0, 0),
527 GATE(CLK_I2C1, "i2c1", "div_aclk66", GATE_IP_PERIC, 7, 0, 0),
528 GATE(CLK_I2C2, "i2c2", "div_aclk66", GATE_IP_PERIC, 8, 0, 0),
529 GATE(CLK_I2C3, "i2c3", "div_aclk66", GATE_IP_PERIC, 9, 0, 0),
530 GATE(CLK_I2C4, "i2c4", "div_aclk66", GATE_IP_PERIC, 10, 0, 0),
531 GATE(CLK_I2C5, "i2c5", "div_aclk66", GATE_IP_PERIC, 11, 0, 0),
532 GATE(CLK_I2C6, "i2c6", "div_aclk66", GATE_IP_PERIC, 12, 0, 0),
533 GATE(CLK_I2C7, "i2c7", "div_aclk66", GATE_IP_PERIC, 13, 0, 0),
534 GATE(CLK_I2C_HDMI, "i2c_hdmi", "div_aclk66", GATE_IP_PERIC, 14, 0, 0),
535 GATE(CLK_ADC, "adc", "div_aclk66", GATE_IP_PERIC, 15, 0, 0),
536 GATE(CLK_SPI0, "spi0", "div_aclk66", GATE_IP_PERIC, 16, 0, 0),
537 GATE(CLK_SPI1, "spi1", "div_aclk66", GATE_IP_PERIC, 17, 0, 0),
538 GATE(CLK_SPI2, "spi2", "div_aclk66", GATE_IP_PERIC, 18, 0, 0),
539 GATE(CLK_I2S1, "i2s1", "div_aclk66", GATE_IP_PERIC, 20, 0, 0),
540 GATE(CLK_I2S2, "i2s2", "div_aclk66", GATE_IP_PERIC, 21, 0, 0),
541 GATE(CLK_PCM1, "pcm1", "div_aclk66", GATE_IP_PERIC, 22, 0, 0),
542 GATE(CLK_PCM2, "pcm2", "div_aclk66", GATE_IP_PERIC, 23, 0, 0),
543 GATE(CLK_PWM, "pwm", "div_aclk66", GATE_IP_PERIC, 24, 0, 0),
544 GATE(CLK_SPDIF, "spdif", "div_aclk66", GATE_IP_PERIC, 26, 0, 0),
545 GATE(CLK_AC97, "ac97", "div_aclk66", GATE_IP_PERIC, 27, 0, 0),
546 GATE(CLK_HSI2C0, "hsi2c0", "div_aclk66", GATE_IP_PERIC, 28, 0, 0),
547 GATE(CLK_HSI2C1, "hsi2c1", "div_aclk66", GATE_IP_PERIC, 29, 0, 0),
548 GATE(CLK_HSI2C2, "hsi2c2", "div_aclk66", GATE_IP_PERIC, 30, 0, 0),
549 GATE(CLK_HSI2C3, "hsi2c3", "div_aclk66", GATE_IP_PERIC, 31, 0, 0),
550
551 GATE(CLK_CHIPID, "chipid", "div_aclk66", GATE_IP_PERIS, 0, 0, 0),
552 GATE(CLK_SYSREG, "sysreg", "div_aclk66",
553 GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
554 GATE(CLK_PMU, "pmu", "div_aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED,
555 0),
556 GATE(CLK_CMU_TOP, "cmu_top", "div_aclk66",
557 GATE_IP_PERIS, 3, CLK_IGNORE_UNUSED, 0),
558 GATE(CLK_CMU_CORE, "cmu_core", "div_aclk66",
559 GATE_IP_PERIS, 4, CLK_IGNORE_UNUSED, 0),
560 GATE(CLK_CMU_MEM, "cmu_mem", "div_aclk66",
561 GATE_IP_PERIS, 5, CLK_IGNORE_UNUSED, 0),
562 GATE(CLK_TZPC0, "tzpc0", "div_aclk66", GATE_IP_PERIS, 6, 0, 0),
563 GATE(CLK_TZPC1, "tzpc1", "div_aclk66", GATE_IP_PERIS, 7, 0, 0),
564 GATE(CLK_TZPC2, "tzpc2", "div_aclk66", GATE_IP_PERIS, 8, 0, 0),
565 GATE(CLK_TZPC3, "tzpc3", "div_aclk66", GATE_IP_PERIS, 9, 0, 0),
566 GATE(CLK_TZPC4, "tzpc4", "div_aclk66", GATE_IP_PERIS, 10, 0, 0),
567 GATE(CLK_TZPC5, "tzpc5", "div_aclk66", GATE_IP_PERIS, 11, 0, 0),
568 GATE(CLK_TZPC6, "tzpc6", "div_aclk66", GATE_IP_PERIS, 12, 0, 0),
569 GATE(CLK_TZPC7, "tzpc7", "div_aclk66", GATE_IP_PERIS, 13, 0, 0),
570 GATE(CLK_TZPC8, "tzpc8", "div_aclk66", GATE_IP_PERIS, 14, 0, 0),
571 GATE(CLK_TZPC9, "tzpc9", "div_aclk66", GATE_IP_PERIS, 15, 0, 0),
572 GATE(CLK_HDMI_CEC, "hdmi_cec", "div_aclk66", GATE_IP_PERIS, 16, 0, 0),
573 GATE(CLK_MCT, "mct", "div_aclk66", GATE_IP_PERIS, 18, 0, 0),
574 GATE(CLK_WDT, "wdt", "div_aclk66", GATE_IP_PERIS, 19, 0, 0),
575 GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0),
576 GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0),
495}; 577};
496 578
497static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = { 579static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = {
@@ -517,20 +599,41 @@ static struct samsung_pll_rate_table epll_24mhz_tbl[] __initdata = {
517 { }, 599 { },
518}; 600};
519 601
602static struct samsung_pll_rate_table apll_24mhz_tbl[] __initdata = {
603 /* sorted in descending order */
604 /* PLL_35XX_RATE(rate, m, p, s) */
605 PLL_35XX_RATE(1700000000, 425, 6, 0),
606 PLL_35XX_RATE(1600000000, 200, 3, 0),
607 PLL_35XX_RATE(1500000000, 250, 4, 0),
608 PLL_35XX_RATE(1400000000, 175, 3, 0),
609 PLL_35XX_RATE(1300000000, 325, 6, 0),
610 PLL_35XX_RATE(1200000000, 200, 4, 0),
611 PLL_35XX_RATE(1100000000, 275, 6, 0),
612 PLL_35XX_RATE(1000000000, 125, 3, 0),
613 PLL_35XX_RATE(900000000, 150, 4, 0),
614 PLL_35XX_RATE(800000000, 100, 3, 0),
615 PLL_35XX_RATE(700000000, 175, 3, 1),
616 PLL_35XX_RATE(600000000, 200, 4, 1),
617 PLL_35XX_RATE(500000000, 125, 3, 1),
618 PLL_35XX_RATE(400000000, 100, 3, 1),
619 PLL_35XX_RATE(300000000, 200, 4, 2),
620 PLL_35XX_RATE(200000000, 100, 3, 2),
621};
622
520static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = { 623static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {
521 [apll] = PLL_A(pll_35xx, fout_apll, "fout_apll", "fin_pll", APLL_LOCK, 624 [apll] = PLL_A(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
522 APLL_CON0, "fout_apll", NULL), 625 APLL_LOCK, APLL_CON0, "fout_apll", NULL),
523 [mpll] = PLL_A(pll_35xx, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK, 626 [mpll] = PLL_A(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
524 MPLL_CON0, "fout_mpll", NULL), 627 MPLL_LOCK, MPLL_CON0, "fout_mpll", NULL),
525 [bpll] = PLL(pll_35xx, fout_bpll, "fout_bpll", "fin_pll", BPLL_LOCK, 628 [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
526 BPLL_CON0, NULL), 629 BPLL_CON0, NULL),
527 [gpll] = PLL(pll_35xx, fout_gpll, "fout_gpll", "fin_pll", GPLL_LOCK, 630 [gpll] = PLL(pll_35xx, CLK_FOUT_GPLL, "fout_gpll", "fin_pll", GPLL_LOCK,
528 GPLL_CON0, NULL), 631 GPLL_CON0, NULL),
529 [cpll] = PLL(pll_35xx, fout_cpll, "fout_cpll", "fin_pll", CPLL_LOCK, 632 [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
530 CPLL_CON0, NULL), 633 CPLL_CON0, NULL),
531 [epll] = PLL(pll_36xx, fout_epll, "fout_epll", "fin_pll", EPLL_LOCK, 634 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
532 EPLL_CON0, NULL), 635 EPLL_CON0, NULL),
533 [vpll] = PLL(pll_36xx, fout_vpll, "fout_vpll", "mout_vpllsrc", 636 [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
534 VPLL_LOCK, VPLL_CON0, NULL), 637 VPLL_LOCK, VPLL_CON0, NULL),
535}; 638};
536 639
@@ -552,7 +655,7 @@ static void __init exynos5250_clk_init(struct device_node *np)
552 panic("%s: unable to determine soc\n", __func__); 655 panic("%s: unable to determine soc\n", __func__);
553 } 656 }
554 657
555 samsung_clk_init(np, reg_base, nr_clks, 658 samsung_clk_init(np, reg_base, CLK_NR_CLKS,
556 exynos5250_clk_regs, ARRAY_SIZE(exynos5250_clk_regs), 659 exynos5250_clk_regs, ARRAY_SIZE(exynos5250_clk_regs),
557 NULL, 0); 660 NULL, 0);
558 samsung_clk_of_register_fixed_ext(exynos5250_fixed_rate_ext_clks, 661 samsung_clk_of_register_fixed_ext(exynos5250_fixed_rate_ext_clks,
@@ -561,8 +664,10 @@ static void __init exynos5250_clk_init(struct device_node *np)
561 samsung_clk_register_mux(exynos5250_pll_pmux_clks, 664 samsung_clk_register_mux(exynos5250_pll_pmux_clks,
562 ARRAY_SIZE(exynos5250_pll_pmux_clks)); 665 ARRAY_SIZE(exynos5250_pll_pmux_clks));
563 666
564 if (_get_rate("fin_pll") == 24 * MHZ) 667 if (_get_rate("fin_pll") == 24 * MHZ) {
565 exynos5250_plls[epll].rate_table = epll_24mhz_tbl; 668 exynos5250_plls[epll].rate_table = epll_24mhz_tbl;
669 exynos5250_plls[apll].rate_table = apll_24mhz_tbl;
670 }
566 671
567 if (_get_rate("mout_vpllsrc") == 24 * MHZ) 672 if (_get_rate("mout_vpllsrc") == 24 * MHZ)
568 exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl; 673 exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl;
@@ -581,6 +686,6 @@ static void __init exynos5250_clk_init(struct device_node *np)
581 ARRAY_SIZE(exynos5250_gate_clks)); 686 ARRAY_SIZE(exynos5250_gate_clks));
582 687
583 pr_info("Exynos5250: clock setup completed, armclk=%ld\n", 688 pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
584 _get_rate("armclk")); 689 _get_rate("div_arm2"));
585} 690}
586CLK_OF_DECLARE(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init); 691CLK_OF_DECLARE(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init);
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 48c4a9350b91..ab4f2f7d88ef 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -10,6 +10,7 @@
10 * Common Clock Framework support for Exynos5420 SoC. 10 * Common Clock Framework support for Exynos5420 SoC.
11*/ 11*/
12 12
13#include <dt-bindings/clock/exynos5420.h>
13#include <linux/clk.h> 14#include <linux/clk.h>
14#include <linux/clkdev.h> 15#include <linux/clkdev.h>
15#include <linux/clk-provider.h> 16#include <linux/clk-provider.h>
@@ -107,48 +108,6 @@ enum exynos5420_plls {
107 nr_plls /* number of PLLs */ 108 nr_plls /* number of PLLs */
108}; 109};
109 110
110enum exynos5420_clks {
111 none,
112
113 /* core clocks */
114 fin_pll, fout_apll, fout_cpll, fout_dpll, fout_epll, fout_rpll,
115 fout_ipll, fout_spll, fout_vpll, fout_mpll, fout_bpll, fout_kpll,
116
117 /* gate for special clocks (sclk) */
118 sclk_uart0 = 128, sclk_uart1, sclk_uart2, sclk_uart3, sclk_mmc0,
119 sclk_mmc1, sclk_mmc2, sclk_spi0, sclk_spi1, sclk_spi2, sclk_i2s1,
120 sclk_i2s2, sclk_pcm1, sclk_pcm2, sclk_spdif, sclk_hdmi, sclk_pixel,
121 sclk_dp1, sclk_mipi1, sclk_fimd1, sclk_maudio0, sclk_maupcm0,
122 sclk_usbd300, sclk_usbd301, sclk_usbphy300, sclk_usbphy301, sclk_unipro,
123 sclk_pwm, sclk_gscl_wa, sclk_gscl_wb, sclk_hdmiphy,
124
125 /* gate clocks */
126 aclk66_peric = 256, uart0, uart1, uart2, uart3, i2c0, i2c1, i2c2, i2c3,
127 i2c4, i2c5, i2c6, i2c7, i2c_hdmi, tsadc, spi0, spi1, spi2, keyif, i2s1,
128 i2s2, pcm1, pcm2, pwm, spdif, i2c8, i2c9, i2c10, aclk66_psgen = 300,
129 chipid, sysreg, tzpc0, tzpc1, tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7,
130 tzpc8, tzpc9, hdmi_cec, seckey, mct, wdt, rtc, tmu, tmu_gpu,
131 pclk66_gpio = 330, aclk200_fsys2 = 350, mmc0, mmc1, mmc2, sromc, ufs,
132 aclk200_fsys = 360, tsi, pdma0, pdma1, rtic, usbh20, usbd300, usbd301,
133 aclk400_mscl = 380, mscl0, mscl1, mscl2, smmu_mscl0, smmu_mscl1,
134 smmu_mscl2, aclk333 = 400, mfc, smmu_mfcl, smmu_mfcr,
135 aclk200_disp1 = 410, dsim1, dp1, hdmi, aclk300_disp1 = 420, fimd1,
136 smmu_fimd1, aclk166 = 430, mixer, aclk266 = 440, rotator, mdma1,
137 smmu_rotator, smmu_mdma1, aclk300_jpeg = 450, jpeg, jpeg2, smmu_jpeg,
138 aclk300_gscl = 460, smmu_gscl0, smmu_gscl1, gscl_wa, gscl_wb, gscl0,
139 gscl1, clk_3aa, aclk266_g2d = 470, sss, slim_sss, mdma0,
140 aclk333_g2d = 480, g2d, aclk333_432_gscl = 490, smmu_3aa, smmu_fimcl0,
141 smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d = 500, g3d, smmu_mixer,
142
143 /* mux clocks */
144 mout_hdmi = 640,
145
146 /* divider clocks */
147 dout_pixel = 768,
148
149 nr_clks,
150};
151
152/* 111/*
153 * list of controller registers to be saved and restored during a 112 * list of controller registers to be saved and restored during a
154 * suspend/resume cycle. 113 * suspend/resume cycle.
@@ -298,225 +257,226 @@ PNAME(maudio0_p) = { "fin_pll", "maudio_clk", "sclk_dpll", "sclk_mpll",
298 257
299/* fixed rate clocks generated outside the soc */ 258/* fixed rate clocks generated outside the soc */
300static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initdata = { 259static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initdata = {
301 FRATE(fin_pll, "fin_pll", NULL, CLK_IS_ROOT, 0), 260 FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0),
302}; 261};
303 262
304/* fixed rate clocks generated inside the soc */ 263/* fixed rate clocks generated inside the soc */
305static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata = { 264static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata = {
306 FRATE(sclk_hdmiphy, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000), 265 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
307 FRATE(none, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000), 266 FRATE(0, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000),
308 FRATE(none, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000), 267 FRATE(0, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000),
309 FRATE(none, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000), 268 FRATE(0, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000),
310 FRATE(none, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000), 269 FRATE(0, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000),
311}; 270};
312 271
313static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initdata = { 272static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initdata = {
314 FFACTOR(none, "sclk_hsic_12m", "fin_pll", 1, 2, 0), 273 FFACTOR(0, "sclk_hsic_12m", "fin_pll", 1, 2, 0),
315}; 274};
316 275
317static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { 276static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
318 MUX(none, "mout_mspll_kfc", mspll_cpu_p, SRC_TOP7, 8, 2), 277 MUX(0, "mout_mspll_kfc", mspll_cpu_p, SRC_TOP7, 8, 2),
319 MUX(none, "mout_mspll_cpu", mspll_cpu_p, SRC_TOP7, 12, 2), 278 MUX(0, "mout_mspll_cpu", mspll_cpu_p, SRC_TOP7, 12, 2),
320 MUX(none, "mout_apll", apll_p, SRC_CPU, 0, 1), 279 MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1),
321 MUX(none, "mout_cpu", cpu_p, SRC_CPU, 16, 1), 280 MUX(0, "mout_cpu", cpu_p, SRC_CPU, 16, 1),
322 MUX(none, "mout_kpll", kpll_p, SRC_KFC, 0, 1), 281 MUX(0, "mout_kpll", kpll_p, SRC_KFC, 0, 1),
323 MUX(none, "mout_cpu_kfc", kfc_p, SRC_KFC, 16, 1), 282 MUX(0, "mout_cpu_kfc", kfc_p, SRC_KFC, 16, 1),
324 283
325 MUX(none, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1), 284 MUX(0, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1),
326 285
327 MUX_A(none, "mout_aclk400_mscl", group1_p, 286 MUX_A(0, "mout_aclk400_mscl", group1_p,
328 SRC_TOP0, 4, 2, "aclk400_mscl"), 287 SRC_TOP0, 4, 2, "aclk400_mscl"),
329 MUX(none, "mout_aclk200", group1_p, SRC_TOP0, 8, 2), 288 MUX(0, "mout_aclk200", group1_p, SRC_TOP0, 8, 2),
330 MUX(none, "mout_aclk200_fsys2", group1_p, SRC_TOP0, 12, 2), 289 MUX(0, "mout_aclk200_fsys2", group1_p, SRC_TOP0, 12, 2),
331 MUX(none, "mout_aclk200_fsys", group1_p, SRC_TOP0, 28, 2), 290 MUX(0, "mout_aclk200_fsys", group1_p, SRC_TOP0, 28, 2),
332 291
333 MUX(none, "mout_aclk333_432_gscl", group4_p, SRC_TOP1, 0, 2), 292 MUX(0, "mout_aclk333_432_gscl", group4_p, SRC_TOP1, 0, 2),
334 MUX(none, "mout_aclk66", group1_p, SRC_TOP1, 8, 2), 293 MUX(0, "mout_aclk66", group1_p, SRC_TOP1, 8, 2),
335 MUX(none, "mout_aclk266", group1_p, SRC_TOP1, 20, 2), 294 MUX(0, "mout_aclk266", group1_p, SRC_TOP1, 20, 2),
336 MUX(none, "mout_aclk166", group1_p, SRC_TOP1, 24, 2), 295 MUX(0, "mout_aclk166", group1_p, SRC_TOP1, 24, 2),
337 MUX(none, "mout_aclk333", group1_p, SRC_TOP1, 28, 2), 296 MUX(0, "mout_aclk333", group1_p, SRC_TOP1, 28, 2),
338 297
339 MUX(none, "mout_aclk333_g2d", group1_p, SRC_TOP2, 8, 2), 298 MUX(0, "mout_aclk333_g2d", group1_p, SRC_TOP2, 8, 2),
340 MUX(none, "mout_aclk266_g2d", group1_p, SRC_TOP2, 12, 2), 299 MUX(0, "mout_aclk266_g2d", group1_p, SRC_TOP2, 12, 2),
341 MUX(none, "mout_aclk_g3d", group5_p, SRC_TOP2, 16, 1), 300 MUX(0, "mout_aclk_g3d", group5_p, SRC_TOP2, 16, 1),
342 MUX(none, "mout_aclk300_jpeg", group1_p, SRC_TOP2, 20, 2), 301 MUX(0, "mout_aclk300_jpeg", group1_p, SRC_TOP2, 20, 2),
343 MUX(none, "mout_aclk300_disp1", group1_p, SRC_TOP2, 24, 2), 302 MUX(0, "mout_aclk300_disp1", group1_p, SRC_TOP2, 24, 2),
344 MUX(none, "mout_aclk300_gscl", group1_p, SRC_TOP2, 28, 2), 303 MUX(0, "mout_aclk300_gscl", group1_p, SRC_TOP2, 28, 2),
345 304
346 MUX(none, "mout_user_aclk400_mscl", user_aclk400_mscl_p, 305 MUX(0, "mout_user_aclk400_mscl", user_aclk400_mscl_p,
347 SRC_TOP3, 4, 1), 306 SRC_TOP3, 4, 1),
348 MUX_A(none, "mout_aclk200_disp1", aclk200_disp1_p, 307 MUX_A(0, "mout_aclk200_disp1", aclk200_disp1_p,
349 SRC_TOP3, 8, 1, "aclk200_disp1"), 308 SRC_TOP3, 8, 1, "aclk200_disp1"),
350 MUX(none, "mout_user_aclk200_fsys2", user_aclk200_fsys2_p, 309 MUX(0, "mout_user_aclk200_fsys2", user_aclk200_fsys2_p,
351 SRC_TOP3, 12, 1), 310 SRC_TOP3, 12, 1),
352 MUX(none, "mout_user_aclk200_fsys", user_aclk200_fsys_p, 311 MUX(0, "mout_user_aclk200_fsys", user_aclk200_fsys_p,
353 SRC_TOP3, 28, 1), 312 SRC_TOP3, 28, 1),
354 313
355 MUX(none, "mout_user_aclk333_432_gscl", user_aclk333_432_gscl_p, 314 MUX(0, "mout_user_aclk333_432_gscl", user_aclk333_432_gscl_p,
356 SRC_TOP4, 0, 1), 315 SRC_TOP4, 0, 1),
357 MUX(none, "mout_aclk66_peric", aclk66_peric_p, SRC_TOP4, 8, 1), 316 MUX(0, "mout_aclk66_peric", aclk66_peric_p, SRC_TOP4, 8, 1),
358 MUX(none, "mout_user_aclk266", user_aclk266_p, SRC_TOP4, 20, 1), 317 MUX(0, "mout_user_aclk266", user_aclk266_p, SRC_TOP4, 20, 1),
359 MUX(none, "mout_user_aclk166", user_aclk166_p, SRC_TOP4, 24, 1), 318 MUX(0, "mout_user_aclk166", user_aclk166_p, SRC_TOP4, 24, 1),
360 MUX(none, "mout_user_aclk333", user_aclk333_p, SRC_TOP4, 28, 1), 319 MUX(0, "mout_user_aclk333", user_aclk333_p, SRC_TOP4, 28, 1),
361 320
362 MUX(none, "mout_aclk66_psgen", aclk66_peric_p, SRC_TOP5, 4, 1), 321 MUX(0, "mout_aclk66_psgen", aclk66_peric_p, SRC_TOP5, 4, 1),
363 MUX(none, "mout_user_aclk333_g2d", user_aclk333_g2d_p, SRC_TOP5, 8, 1), 322 MUX(0, "mout_user_aclk333_g2d", user_aclk333_g2d_p, SRC_TOP5, 8, 1),
364 MUX(none, "mout_user_aclk266_g2d", user_aclk266_g2d_p, SRC_TOP5, 12, 1), 323 MUX(0, "mout_user_aclk266_g2d", user_aclk266_g2d_p, SRC_TOP5, 12, 1),
365 MUX_A(none, "mout_user_aclk_g3d", user_aclk_g3d_p, 324 MUX_A(0, "mout_user_aclk_g3d", user_aclk_g3d_p,
366 SRC_TOP5, 16, 1, "aclkg3d"), 325 SRC_TOP5, 16, 1, "aclkg3d"),
367 MUX(none, "mout_user_aclk300_jpeg", user_aclk300_jpeg_p, 326 MUX(0, "mout_user_aclk300_jpeg", user_aclk300_jpeg_p,
368 SRC_TOP5, 20, 1), 327 SRC_TOP5, 20, 1),
369 MUX(none, "mout_user_aclk300_disp1", user_aclk300_disp1_p, 328 MUX(0, "mout_user_aclk300_disp1", user_aclk300_disp1_p,
370 SRC_TOP5, 24, 1), 329 SRC_TOP5, 24, 1),
371 MUX(none, "mout_user_aclk300_gscl", user_aclk300_gscl_p, 330 MUX(0, "mout_user_aclk300_gscl", user_aclk300_gscl_p,
372 SRC_TOP5, 28, 1), 331 SRC_TOP5, 28, 1),
373 332
374 MUX(none, "sclk_mpll", mpll_p, SRC_TOP6, 0, 1), 333 MUX(0, "sclk_mpll", mpll_p, SRC_TOP6, 0, 1),
375 MUX(none, "sclk_vpll", vpll_p, SRC_TOP6, 4, 1), 334 MUX(0, "sclk_vpll", vpll_p, SRC_TOP6, 4, 1),
376 MUX(none, "sclk_spll", spll_p, SRC_TOP6, 8, 1), 335 MUX(0, "sclk_spll", spll_p, SRC_TOP6, 8, 1),
377 MUX(none, "sclk_ipll", ipll_p, SRC_TOP6, 12, 1), 336 MUX(0, "sclk_ipll", ipll_p, SRC_TOP6, 12, 1),
378 MUX(none, "sclk_rpll", rpll_p, SRC_TOP6, 16, 1), 337 MUX(0, "sclk_rpll", rpll_p, SRC_TOP6, 16, 1),
379 MUX(none, "sclk_epll", epll_p, SRC_TOP6, 20, 1), 338 MUX(0, "sclk_epll", epll_p, SRC_TOP6, 20, 1),
380 MUX(none, "sclk_dpll", dpll_p, SRC_TOP6, 24, 1), 339 MUX(0, "sclk_dpll", dpll_p, SRC_TOP6, 24, 1),
381 MUX(none, "sclk_cpll", cpll_p, SRC_TOP6, 28, 1), 340 MUX(0, "sclk_cpll", cpll_p, SRC_TOP6, 28, 1),
382 341
383 MUX(none, "mout_sw_aclk400_mscl", sw_aclk400_mscl_p, SRC_TOP10, 4, 1), 342 MUX(0, "mout_sw_aclk400_mscl", sw_aclk400_mscl_p, SRC_TOP10, 4, 1),
384 MUX(none, "mout_sw_aclk200", sw_aclk200_p, SRC_TOP10, 8, 1), 343 MUX(0, "mout_sw_aclk200", sw_aclk200_p, SRC_TOP10, 8, 1),
385 MUX(none, "mout_sw_aclk200_fsys2", sw_aclk200_fsys2_p, 344 MUX(0, "mout_sw_aclk200_fsys2", sw_aclk200_fsys2_p,
386 SRC_TOP10, 12, 1), 345 SRC_TOP10, 12, 1),
387 MUX(none, "mout_sw_aclk200_fsys", sw_aclk200_fsys_p, SRC_TOP10, 28, 1), 346 MUX(0, "mout_sw_aclk200_fsys", sw_aclk200_fsys_p, SRC_TOP10, 28, 1),
388 347
389 MUX(none, "mout_sw_aclk333_432_gscl", sw_aclk333_432_gscl_p, 348 MUX(0, "mout_sw_aclk333_432_gscl", sw_aclk333_432_gscl_p,
390 SRC_TOP11, 0, 1), 349 SRC_TOP11, 0, 1),
391 MUX(none, "mout_sw_aclk66", sw_aclk66_p, SRC_TOP11, 8, 1), 350 MUX(0, "mout_sw_aclk66", sw_aclk66_p, SRC_TOP11, 8, 1),
392 MUX(none, "mout_sw_aclk266", sw_aclk266_p, SRC_TOP11, 20, 1), 351 MUX(0, "mout_sw_aclk266", sw_aclk266_p, SRC_TOP11, 20, 1),
393 MUX(none, "mout_sw_aclk166", sw_aclk166_p, SRC_TOP11, 24, 1), 352 MUX(0, "mout_sw_aclk166", sw_aclk166_p, SRC_TOP11, 24, 1),
394 MUX(none, "mout_sw_aclk333", sw_aclk333_p, SRC_TOP11, 28, 1), 353 MUX(0, "mout_sw_aclk333", sw_aclk333_p, SRC_TOP11, 28, 1),
395 354
396 MUX(none, "mout_sw_aclk333_g2d", sw_aclk333_g2d_p, SRC_TOP12, 8, 1), 355 MUX(0, "mout_sw_aclk333_g2d", sw_aclk333_g2d_p, SRC_TOP12, 8, 1),
397 MUX(none, "mout_sw_aclk266_g2d", sw_aclk266_g2d_p, SRC_TOP12, 12, 1), 356 MUX(0, "mout_sw_aclk266_g2d", sw_aclk266_g2d_p, SRC_TOP12, 12, 1),
398 MUX(none, "mout_sw_aclk_g3d", sw_aclk_g3d_p, SRC_TOP12, 16, 1), 357 MUX(0, "mout_sw_aclk_g3d", sw_aclk_g3d_p, SRC_TOP12, 16, 1),
399 MUX(none, "mout_sw_aclk300_jpeg", sw_aclk300_jpeg_p, SRC_TOP12, 20, 1), 358 MUX(0, "mout_sw_aclk300_jpeg", sw_aclk300_jpeg_p, SRC_TOP12, 20, 1),
400 MUX(none, "mout_sw_aclk300_disp1", sw_aclk300_disp1_p, 359 MUX(0, "mout_sw_aclk300_disp1", sw_aclk300_disp1_p,
401 SRC_TOP12, 24, 1), 360 SRC_TOP12, 24, 1),
402 MUX(none, "mout_sw_aclk300_gscl", sw_aclk300_gscl_p, SRC_TOP12, 28, 1), 361 MUX(0, "mout_sw_aclk300_gscl", sw_aclk300_gscl_p, SRC_TOP12, 28, 1),
403 362
404 /* DISP1 Block */ 363 /* DISP1 Block */
405 MUX(none, "mout_fimd1", group3_p, SRC_DISP10, 4, 1), 364 MUX(0, "mout_fimd1", group3_p, SRC_DISP10, 4, 1),
406 MUX(none, "mout_mipi1", group2_p, SRC_DISP10, 16, 3), 365 MUX(0, "mout_mipi1", group2_p, SRC_DISP10, 16, 3),
407 MUX(none, "mout_dp1", group2_p, SRC_DISP10, 20, 3), 366 MUX(0, "mout_dp1", group2_p, SRC_DISP10, 20, 3),
408 MUX(none, "mout_pixel", group2_p, SRC_DISP10, 24, 3), 367 MUX(0, "mout_pixel", group2_p, SRC_DISP10, 24, 3),
409 MUX(mout_hdmi, "mout_hdmi", hdmi_p, SRC_DISP10, 28, 1), 368 MUX(CLK_MOUT_HDMI, "mout_hdmi", hdmi_p, SRC_DISP10, 28, 1),
410 369
411 /* MAU Block */ 370 /* MAU Block */
412 MUX(none, "mout_maudio0", maudio0_p, SRC_MAU, 28, 3), 371 MUX(0, "mout_maudio0", maudio0_p, SRC_MAU, 28, 3),
413 372
414 /* FSYS Block */ 373 /* FSYS Block */
415 MUX(none, "mout_usbd301", group2_p, SRC_FSYS, 4, 3), 374 MUX(0, "mout_usbd301", group2_p, SRC_FSYS, 4, 3),
416 MUX(none, "mout_mmc0", group2_p, SRC_FSYS, 8, 3), 375 MUX(0, "mout_mmc0", group2_p, SRC_FSYS, 8, 3),
417 MUX(none, "mout_mmc1", group2_p, SRC_FSYS, 12, 3), 376 MUX(0, "mout_mmc1", group2_p, SRC_FSYS, 12, 3),
418 MUX(none, "mout_mmc2", group2_p, SRC_FSYS, 16, 3), 377 MUX(0, "mout_mmc2", group2_p, SRC_FSYS, 16, 3),
419 MUX(none, "mout_usbd300", group2_p, SRC_FSYS, 20, 3), 378 MUX(0, "mout_usbd300", group2_p, SRC_FSYS, 20, 3),
420 MUX(none, "mout_unipro", group2_p, SRC_FSYS, 24, 3), 379 MUX(0, "mout_unipro", group2_p, SRC_FSYS, 24, 3),
421 380
422 /* PERIC Block */ 381 /* PERIC Block */
423 MUX(none, "mout_uart0", group2_p, SRC_PERIC0, 4, 3), 382 MUX(0, "mout_uart0", group2_p, SRC_PERIC0, 4, 3),
424 MUX(none, "mout_uart1", group2_p, SRC_PERIC0, 8, 3), 383 MUX(0, "mout_uart1", group2_p, SRC_PERIC0, 8, 3),
425 MUX(none, "mout_uart2", group2_p, SRC_PERIC0, 12, 3), 384 MUX(0, "mout_uart2", group2_p, SRC_PERIC0, 12, 3),
426 MUX(none, "mout_uart3", group2_p, SRC_PERIC0, 16, 3), 385 MUX(0, "mout_uart3", group2_p, SRC_PERIC0, 16, 3),
427 MUX(none, "mout_pwm", group2_p, SRC_PERIC0, 24, 3), 386 MUX(0, "mout_pwm", group2_p, SRC_PERIC0, 24, 3),
428 MUX(none, "mout_spdif", spdif_p, SRC_PERIC0, 28, 3), 387 MUX(0, "mout_spdif", spdif_p, SRC_PERIC0, 28, 3),
429 MUX(none, "mout_audio0", audio0_p, SRC_PERIC1, 8, 3), 388 MUX(0, "mout_audio0", audio0_p, SRC_PERIC1, 8, 3),
430 MUX(none, "mout_audio1", audio1_p, SRC_PERIC1, 12, 3), 389 MUX(0, "mout_audio1", audio1_p, SRC_PERIC1, 12, 3),
431 MUX(none, "mout_audio2", audio2_p, SRC_PERIC1, 16, 3), 390 MUX(0, "mout_audio2", audio2_p, SRC_PERIC1, 16, 3),
432 MUX(none, "mout_spi0", group2_p, SRC_PERIC1, 20, 3), 391 MUX(0, "mout_spi0", group2_p, SRC_PERIC1, 20, 3),
433 MUX(none, "mout_spi1", group2_p, SRC_PERIC1, 24, 3), 392 MUX(0, "mout_spi1", group2_p, SRC_PERIC1, 24, 3),
434 MUX(none, "mout_spi2", group2_p, SRC_PERIC1, 28, 3), 393 MUX(0, "mout_spi2", group2_p, SRC_PERIC1, 28, 3),
435}; 394};
436 395
437static struct samsung_div_clock exynos5420_div_clks[] __initdata = { 396static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
438 DIV(none, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 397 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
439 DIV(none, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 398 DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
440 DIV(none, "armclk2", "div_arm", DIV_CPU0, 28, 3), 399 DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3),
441 DIV(none, "div_kfc", "mout_cpu_kfc", DIV_KFC0, 0, 3), 400 DIV(0, "div_kfc", "mout_cpu_kfc", DIV_KFC0, 0, 3),
442 DIV(none, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3), 401 DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
443 402
444 DIV(none, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3), 403 DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3),
445 DIV(none, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3), 404 DIV(0, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3),
446 DIV(none, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3), 405 DIV(0, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3),
447 DIV(none, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3), 406 DIV(0, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3),
448 DIV(none, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3), 407 DIV(0, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3),
449 408
450 DIV(none, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl", 409 DIV(0, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl",
451 DIV_TOP1, 0, 3), 410 DIV_TOP1, 0, 3),
452 DIV(none, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6), 411 DIV(0, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6),
453 DIV(none, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3), 412 DIV(0, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3),
454 DIV(none, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3), 413 DIV(0, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3),
455 DIV(none, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3), 414 DIV(0, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3),
456 415
457 DIV(none, "dout_aclk333_g2d", "mout_aclk333_g2d", DIV_TOP2, 8, 3), 416 DIV(0, "dout_aclk333_g2d", "mout_aclk333_g2d", DIV_TOP2, 8, 3),
458 DIV(none, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3), 417 DIV(0, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3),
459 DIV(none, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3), 418 DIV(0, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3),
460 DIV(none, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3), 419 DIV(0, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3),
461 DIV_A(none, "dout_aclk300_disp1", "mout_aclk300_disp1", 420 DIV_A(0, "dout_aclk300_disp1", "mout_aclk300_disp1",
462 DIV_TOP2, 24, 3, "aclk300_disp1"), 421 DIV_TOP2, 24, 3, "aclk300_disp1"),
463 DIV(none, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3), 422 DIV(0, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3),
464 423
465 /* DISP1 Block */ 424 /* DISP1 Block */
466 DIV(none, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4), 425 DIV(0, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4),
467 DIV(none, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), 426 DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
468 DIV(none, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), 427 DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
469 DIV(dout_pixel, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), 428 DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
470 429
471 /* Audio Block */ 430 /* Audio Block */
472 DIV(none, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), 431 DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
473 DIV(none, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8), 432 DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
474 433
475 /* USB3.0 */ 434 /* USB3.0 */
476 DIV(none, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4), 435 DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
477 DIV(none, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4), 436 DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
478 DIV(none, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4), 437 DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
479 DIV(none, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4), 438 DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
480 439
481 /* MMC */ 440 /* MMC */
482 DIV(none, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10), 441 DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
483 DIV(none, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10), 442 DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),
484 DIV(none, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10), 443 DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10),
485 444
486 DIV(none, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8), 445 DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8),
487 446
488 /* UART and PWM */ 447 /* UART and PWM */
489 DIV(none, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4), 448 DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4),
490 DIV(none, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4), 449 DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4),
491 DIV(none, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4), 450 DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4),
492 DIV(none, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4), 451 DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4),
493 DIV(none, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4), 452 DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4),
494 453
495 /* SPI */ 454 /* SPI */
496 DIV(none, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4), 455 DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4),
497 DIV(none, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4), 456 DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4),
498 DIV(none, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4), 457 DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4),
499 458
500 /* PCM */ 459 /* PCM */
501 DIV(none, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8), 460 DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8),
502 DIV(none, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8), 461 DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8),
503 462
504 /* Audio - I2S */ 463 /* Audio - I2S */
505 DIV(none, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6), 464 DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6),
506 DIV(none, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6), 465 DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6),
507 DIV(none, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4), 466 DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4),
508 DIV(none, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4), 467 DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4),
509 DIV(none, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4), 468 DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4),
510 469
511 /* SPI Pre-Ratio */ 470 /* SPI Pre-Ratio */
512 DIV(none, "dout_pre_spi0", "dout_spi0", DIV_PERIC4, 8, 8), 471 DIV(0, "dout_pre_spi0", "dout_spi0", DIV_PERIC4, 8, 8),
513 DIV(none, "dout_pre_spi1", "dout_spi1", DIV_PERIC4, 16, 8), 472 DIV(0, "dout_pre_spi1", "dout_spi1", DIV_PERIC4, 16, 8),
514 DIV(none, "dout_pre_spi2", "dout_spi2", DIV_PERIC4, 24, 8), 473 DIV(0, "dout_pre_spi2", "dout_spi2", DIV_PERIC4, 24, 8),
515}; 474};
516 475
517static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { 476static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
518 /* TODO: Re-verify the CG bits for all the gate clocks */ 477 /* TODO: Re-verify the CG bits for all the gate clocks */
519 GATE_A(mct, "pclk_st", "aclk66_psgen", GATE_BUS_PERIS1, 2, 0, 0, "mct"), 478 GATE_A(CLK_MCT, "pclk_st", "aclk66_psgen", GATE_BUS_PERIS1, 2, 0, 0,
479 "mct"),
520 480
521 GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys", 481 GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",
522 GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0), 482 GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0),
@@ -545,217 +505,227 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
545 GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0), 505 GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0),
546 506
547 /* sclk */ 507 /* sclk */
548 GATE(sclk_uart0, "sclk_uart0", "dout_uart0", 508 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0",
549 GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0), 509 GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
550 GATE(sclk_uart1, "sclk_uart1", "dout_uart1", 510 GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1",
551 GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0), 511 GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
552 GATE(sclk_uart2, "sclk_uart2", "dout_uart2", 512 GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2",
553 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0), 513 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
554 GATE(sclk_uart3, "sclk_uart3", "dout_uart3", 514 GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3",
555 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0), 515 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0),
556 GATE(sclk_spi0, "sclk_spi0", "dout_pre_spi0", 516 GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_pre_spi0",
557 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0), 517 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
558 GATE(sclk_spi1, "sclk_spi1", "dout_pre_spi1", 518 GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_pre_spi1",
559 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0), 519 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
560 GATE(sclk_spi2, "sclk_spi2", "dout_pre_spi2", 520 GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_pre_spi2",
561 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), 521 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
562 GATE(sclk_spdif, "sclk_spdif", "mout_spdif", 522 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
563 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0), 523 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0),
564 GATE(sclk_pwm, "sclk_pwm", "dout_pwm", 524 GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm",
565 GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), 525 GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
566 GATE(sclk_pcm1, "sclk_pcm1", "dout_pcm1", 526 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1",
567 GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0), 527 GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0),
568 GATE(sclk_pcm2, "sclk_pcm2", "dout_pcm2", 528 GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2",
569 GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0), 529 GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0),
570 GATE(sclk_i2s1, "sclk_i2s1", "dout_i2s1", 530 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1",
571 GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0), 531 GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0),
572 GATE(sclk_i2s2, "sclk_i2s2", "dout_i2s2", 532 GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2",
573 GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0), 533 GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0),
574 534
575 GATE(sclk_mmc0, "sclk_mmc0", "dout_mmc0", 535 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0",
576 GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0), 536 GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
577 GATE(sclk_mmc1, "sclk_mmc1", "dout_mmc1", 537 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1",
578 GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0), 538 GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
579 GATE(sclk_mmc2, "sclk_mmc2", "dout_mmc2", 539 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2",
580 GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), 540 GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
581 GATE(sclk_usbphy301, "sclk_usbphy301", "dout_usbphy301", 541 GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301",
582 GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0), 542 GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
583 GATE(sclk_usbphy300, "sclk_usbphy300", "dout_usbphy300", 543 GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300",
584 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0), 544 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
585 GATE(sclk_usbd300, "sclk_usbd300", "dout_usbd300", 545 GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300",
586 GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0), 546 GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
587 GATE(sclk_usbd301, "sclk_usbd301", "dout_usbd301", 547 GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
588 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0), 548 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
589 549
590 GATE(sclk_usbd301, "sclk_unipro", "dout_unipro", 550 GATE(CLK_SCLK_USBD301, "sclk_unipro", "dout_unipro",
591 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 551 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
592 552
593 GATE(sclk_gscl_wa, "sclk_gscl_wa", "aclK333_432_gscl", 553 GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "aclK333_432_gscl",
594 GATE_TOP_SCLK_GSCL, 6, CLK_SET_RATE_PARENT, 0), 554 GATE_TOP_SCLK_GSCL, 6, CLK_SET_RATE_PARENT, 0),
595 GATE(sclk_gscl_wb, "sclk_gscl_wb", "aclk333_432_gscl", 555 GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "aclk333_432_gscl",
596 GATE_TOP_SCLK_GSCL, 7, CLK_SET_RATE_PARENT, 0), 556 GATE_TOP_SCLK_GSCL, 7, CLK_SET_RATE_PARENT, 0),
597 557
598 /* Display */ 558 /* Display */
599 GATE(sclk_fimd1, "sclk_fimd1", "dout_fimd1", 559 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1",
600 GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0), 560 GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0),
601 GATE(sclk_mipi1, "sclk_mipi1", "dout_mipi1", 561 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1",
602 GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0), 562 GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
603 GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", 563 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
604 GATE_TOP_SCLK_DISP1, 9, CLK_SET_RATE_PARENT, 0), 564 GATE_TOP_SCLK_DISP1, 9, CLK_SET_RATE_PARENT, 0),
605 GATE(sclk_pixel, "sclk_pixel", "dout_hdmi_pixel", 565 GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel",
606 GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0), 566 GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
607 GATE(sclk_dp1, "sclk_dp1", "dout_dp1", 567 GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1",
608 GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0), 568 GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
609 569
610 /* Maudio Block */ 570 /* Maudio Block */
611 GATE(sclk_maudio0, "sclk_maudio0", "dout_maudio0", 571 GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
612 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0), 572 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
613 GATE(sclk_maupcm0, "sclk_maupcm0", "dout_maupcm0", 573 GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
614 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0), 574 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
615 /* FSYS */ 575 /* FSYS */
616 GATE(tsi, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0), 576 GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
617 GATE(pdma0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0), 577 GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
618 GATE(pdma1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0), 578 GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
619 GATE(ufs, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0), 579 GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
620 GATE(rtic, "rtic", "aclk200_fsys", GATE_BUS_FSYS0, 5, 0, 0), 580 GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_BUS_FSYS0, 5, 0, 0),
621 GATE(mmc0, "mmc0", "aclk200_fsys2", GATE_BUS_FSYS0, 12, 0, 0), 581 GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_BUS_FSYS0, 12, 0, 0),
622 GATE(mmc1, "mmc1", "aclk200_fsys2", GATE_BUS_FSYS0, 13, 0, 0), 582 GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_BUS_FSYS0, 13, 0, 0),
623 GATE(mmc2, "mmc2", "aclk200_fsys2", GATE_BUS_FSYS0, 14, 0, 0), 583 GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_BUS_FSYS0, 14, 0, 0),
624 GATE(sromc, "sromc", "aclk200_fsys2", 584 GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
625 GATE_BUS_FSYS0, 19, CLK_IGNORE_UNUSED, 0), 585 GATE_BUS_FSYS0, 19, CLK_IGNORE_UNUSED, 0),
626 GATE(usbh20, "usbh20", "aclk200_fsys", GATE_BUS_FSYS0, 20, 0, 0), 586 GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_BUS_FSYS0, 20, 0, 0),
627 GATE(usbd300, "usbd300", "aclk200_fsys", GATE_BUS_FSYS0, 21, 0, 0), 587 GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_BUS_FSYS0, 21, 0, 0),
628 GATE(usbd301, "usbd301", "aclk200_fsys", GATE_BUS_FSYS0, 28, 0, 0), 588 GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_BUS_FSYS0, 28, 0, 0),
629 589
630 /* UART */ 590 /* UART */
631 GATE(uart0, "uart0", "aclk66_peric", GATE_BUS_PERIC, 4, 0, 0), 591 GATE(CLK_UART0, "uart0", "aclk66_peric", GATE_BUS_PERIC, 4, 0, 0),
632 GATE(uart1, "uart1", "aclk66_peric", GATE_BUS_PERIC, 5, 0, 0), 592 GATE(CLK_UART1, "uart1", "aclk66_peric", GATE_BUS_PERIC, 5, 0, 0),
633 GATE_A(uart2, "uart2", "aclk66_peric", 593 GATE_A(CLK_UART2, "uart2", "aclk66_peric",
634 GATE_BUS_PERIC, 6, CLK_IGNORE_UNUSED, 0, "uart2"), 594 GATE_BUS_PERIC, 6, CLK_IGNORE_UNUSED, 0, "uart2"),
635 GATE(uart3, "uart3", "aclk66_peric", GATE_BUS_PERIC, 7, 0, 0), 595 GATE(CLK_UART3, "uart3", "aclk66_peric", GATE_BUS_PERIC, 7, 0, 0),
636 /* I2C */ 596 /* I2C */
637 GATE(i2c0, "i2c0", "aclk66_peric", GATE_BUS_PERIC, 9, 0, 0), 597 GATE(CLK_I2C0, "i2c0", "aclk66_peric", GATE_BUS_PERIC, 9, 0, 0),
638 GATE(i2c1, "i2c1", "aclk66_peric", GATE_BUS_PERIC, 10, 0, 0), 598 GATE(CLK_I2C1, "i2c1", "aclk66_peric", GATE_BUS_PERIC, 10, 0, 0),
639 GATE(i2c2, "i2c2", "aclk66_peric", GATE_BUS_PERIC, 11, 0, 0), 599 GATE(CLK_I2C2, "i2c2", "aclk66_peric", GATE_BUS_PERIC, 11, 0, 0),
640 GATE(i2c3, "i2c3", "aclk66_peric", GATE_BUS_PERIC, 12, 0, 0), 600 GATE(CLK_I2C3, "i2c3", "aclk66_peric", GATE_BUS_PERIC, 12, 0, 0),
641 GATE(i2c4, "i2c4", "aclk66_peric", GATE_BUS_PERIC, 13, 0, 0), 601 GATE(CLK_I2C4, "i2c4", "aclk66_peric", GATE_BUS_PERIC, 13, 0, 0),
642 GATE(i2c5, "i2c5", "aclk66_peric", GATE_BUS_PERIC, 14, 0, 0), 602 GATE(CLK_I2C5, "i2c5", "aclk66_peric", GATE_BUS_PERIC, 14, 0, 0),
643 GATE(i2c6, "i2c6", "aclk66_peric", GATE_BUS_PERIC, 15, 0, 0), 603 GATE(CLK_I2C6, "i2c6", "aclk66_peric", GATE_BUS_PERIC, 15, 0, 0),
644 GATE(i2c7, "i2c7", "aclk66_peric", GATE_BUS_PERIC, 16, 0, 0), 604 GATE(CLK_I2C7, "i2c7", "aclk66_peric", GATE_BUS_PERIC, 16, 0, 0),
645 GATE(i2c_hdmi, "i2c_hdmi", "aclk66_peric", GATE_BUS_PERIC, 17, 0, 0), 605 GATE(CLK_I2C_HDMI, "i2c_hdmi", "aclk66_peric", GATE_BUS_PERIC, 17, 0,
646 GATE(tsadc, "tsadc", "aclk66_peric", GATE_BUS_PERIC, 18, 0, 0), 606 0),
607 GATE(CLK_TSADC, "tsadc", "aclk66_peric", GATE_BUS_PERIC, 18, 0, 0),
647 /* SPI */ 608 /* SPI */
648 GATE(spi0, "spi0", "aclk66_peric", GATE_BUS_PERIC, 19, 0, 0), 609 GATE(CLK_SPI0, "spi0", "aclk66_peric", GATE_BUS_PERIC, 19, 0, 0),
649 GATE(spi1, "spi1", "aclk66_peric", GATE_BUS_PERIC, 20, 0, 0), 610 GATE(CLK_SPI1, "spi1", "aclk66_peric", GATE_BUS_PERIC, 20, 0, 0),
650 GATE(spi2, "spi2", "aclk66_peric", GATE_BUS_PERIC, 21, 0, 0), 611 GATE(CLK_SPI2, "spi2", "aclk66_peric", GATE_BUS_PERIC, 21, 0, 0),
651 GATE(keyif, "keyif", "aclk66_peric", GATE_BUS_PERIC, 22, 0, 0), 612 GATE(CLK_KEYIF, "keyif", "aclk66_peric", GATE_BUS_PERIC, 22, 0, 0),
652 /* I2S */ 613 /* I2S */
653 GATE(i2s1, "i2s1", "aclk66_peric", GATE_BUS_PERIC, 23, 0, 0), 614 GATE(CLK_I2S1, "i2s1", "aclk66_peric", GATE_BUS_PERIC, 23, 0, 0),
654 GATE(i2s2, "i2s2", "aclk66_peric", GATE_BUS_PERIC, 24, 0, 0), 615 GATE(CLK_I2S2, "i2s2", "aclk66_peric", GATE_BUS_PERIC, 24, 0, 0),
655 /* PCM */ 616 /* PCM */
656 GATE(pcm1, "pcm1", "aclk66_peric", GATE_BUS_PERIC, 25, 0, 0), 617 GATE(CLK_PCM1, "pcm1", "aclk66_peric", GATE_BUS_PERIC, 25, 0, 0),
657 GATE(pcm2, "pcm2", "aclk66_peric", GATE_BUS_PERIC, 26, 0, 0), 618 GATE(CLK_PCM2, "pcm2", "aclk66_peric", GATE_BUS_PERIC, 26, 0, 0),
658 /* PWM */ 619 /* PWM */
659 GATE(pwm, "pwm", "aclk66_peric", GATE_BUS_PERIC, 27, 0, 0), 620 GATE(CLK_PWM, "pwm", "aclk66_peric", GATE_BUS_PERIC, 27, 0, 0),
660 /* SPDIF */ 621 /* SPDIF */
661 GATE(spdif, "spdif", "aclk66_peric", GATE_BUS_PERIC, 29, 0, 0), 622 GATE(CLK_SPDIF, "spdif", "aclk66_peric", GATE_BUS_PERIC, 29, 0, 0),
662 623
663 GATE(i2c8, "i2c8", "aclk66_peric", GATE_BUS_PERIC1, 0, 0, 0), 624 GATE(CLK_I2C8, "i2c8", "aclk66_peric", GATE_BUS_PERIC1, 0, 0, 0),
664 GATE(i2c9, "i2c9", "aclk66_peric", GATE_BUS_PERIC1, 1, 0, 0), 625 GATE(CLK_I2C9, "i2c9", "aclk66_peric", GATE_BUS_PERIC1, 1, 0, 0),
665 GATE(i2c10, "i2c10", "aclk66_peric", GATE_BUS_PERIC1, 2, 0, 0), 626 GATE(CLK_I2C10, "i2c10", "aclk66_peric", GATE_BUS_PERIC1, 2, 0, 0),
666 627
667 GATE(chipid, "chipid", "aclk66_psgen", 628 GATE(CLK_CHIPID, "chipid", "aclk66_psgen",
668 GATE_BUS_PERIS0, 12, CLK_IGNORE_UNUSED, 0), 629 GATE_BUS_PERIS0, 12, CLK_IGNORE_UNUSED, 0),
669 GATE(sysreg, "sysreg", "aclk66_psgen", 630 GATE(CLK_SYSREG, "sysreg", "aclk66_psgen",
670 GATE_BUS_PERIS0, 13, CLK_IGNORE_UNUSED, 0), 631 GATE_BUS_PERIS0, 13, CLK_IGNORE_UNUSED, 0),
671 GATE(tzpc0, "tzpc0", "aclk66_psgen", GATE_BUS_PERIS0, 18, 0, 0), 632 GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_BUS_PERIS0, 18, 0, 0),
672 GATE(tzpc1, "tzpc1", "aclk66_psgen", GATE_BUS_PERIS0, 19, 0, 0), 633 GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_BUS_PERIS0, 19, 0, 0),
673 GATE(tzpc2, "tzpc2", "aclk66_psgen", GATE_BUS_PERIS0, 20, 0, 0), 634 GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_BUS_PERIS0, 20, 0, 0),
674 GATE(tzpc3, "tzpc3", "aclk66_psgen", GATE_BUS_PERIS0, 21, 0, 0), 635 GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_BUS_PERIS0, 21, 0, 0),
675 GATE(tzpc4, "tzpc4", "aclk66_psgen", GATE_BUS_PERIS0, 22, 0, 0), 636 GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_BUS_PERIS0, 22, 0, 0),
676 GATE(tzpc5, "tzpc5", "aclk66_psgen", GATE_BUS_PERIS0, 23, 0, 0), 637 GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_BUS_PERIS0, 23, 0, 0),
677 GATE(tzpc6, "tzpc6", "aclk66_psgen", GATE_BUS_PERIS0, 24, 0, 0), 638 GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_BUS_PERIS0, 24, 0, 0),
678 GATE(tzpc7, "tzpc7", "aclk66_psgen", GATE_BUS_PERIS0, 25, 0, 0), 639 GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_BUS_PERIS0, 25, 0, 0),
679 GATE(tzpc8, "tzpc8", "aclk66_psgen", GATE_BUS_PERIS0, 26, 0, 0), 640 GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_BUS_PERIS0, 26, 0, 0),
680 GATE(tzpc9, "tzpc9", "aclk66_psgen", GATE_BUS_PERIS0, 27, 0, 0), 641 GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_BUS_PERIS0, 27, 0, 0),
681 642
682 GATE(hdmi_cec, "hdmi_cec", "aclk66_psgen", GATE_BUS_PERIS1, 0, 0, 0), 643 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_BUS_PERIS1, 0, 0,
683 GATE(seckey, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0), 644 0),
684 GATE(wdt, "wdt", "aclk66_psgen", GATE_BUS_PERIS1, 3, 0, 0), 645 GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
685 GATE(rtc, "rtc", "aclk66_psgen", GATE_BUS_PERIS1, 4, 0, 0), 646 GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_BUS_PERIS1, 3, 0, 0),
686 GATE(tmu, "tmu", "aclk66_psgen", GATE_BUS_PERIS1, 5, 0, 0), 647 GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_BUS_PERIS1, 4, 0, 0),
687 GATE(tmu_gpu, "tmu_gpu", "aclk66_psgen", GATE_BUS_PERIS1, 6, 0, 0), 648 GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_BUS_PERIS1, 5, 0, 0),
688 649 GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_BUS_PERIS1, 6, 0, 0),
689 GATE(gscl0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0), 650
690 GATE(gscl1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0), 651 GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
691 GATE(clk_3aa, "clk_3aa", "aclk300_gscl", GATE_IP_GSCL0, 4, 0, 0), 652 GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
692 653 GATE(CLK_CLK_3AA, "clk_3aa", "aclk300_gscl", GATE_IP_GSCL0, 4, 0, 0),
693 GATE(smmu_3aa, "smmu_3aa", "aclk333_432_gscl", GATE_IP_GSCL1, 2, 0, 0), 654
694 GATE(smmu_fimcl0, "smmu_fimcl0", "aclk333_432_gscl", 655 GATE(CLK_SMMU_3AA, "smmu_3aa", "aclk333_432_gscl", GATE_IP_GSCL1, 2, 0,
656 0),
657 GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "aclk333_432_gscl",
695 GATE_IP_GSCL1, 3, 0, 0), 658 GATE_IP_GSCL1, 3, 0, 0),
696 GATE(smmu_fimcl1, "smmu_fimcl1", "aclk333_432_gscl", 659 GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "aclk333_432_gscl",
697 GATE_IP_GSCL1, 4, 0, 0), 660 GATE_IP_GSCL1, 4, 0, 0),
698 GATE(smmu_gscl0, "smmu_gscl0", "aclk300_gscl", GATE_IP_GSCL1, 6, 0, 0), 661 GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "aclk300_gscl", GATE_IP_GSCL1, 6, 0,
699 GATE(smmu_gscl1, "smmu_gscl1", "aclk300_gscl", GATE_IP_GSCL1, 7, 0, 0), 662 0),
700 GATE(gscl_wa, "gscl_wa", "aclk300_gscl", GATE_IP_GSCL1, 12, 0, 0), 663 GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "aclk300_gscl", GATE_IP_GSCL1, 7, 0,
701 GATE(gscl_wb, "gscl_wb", "aclk300_gscl", GATE_IP_GSCL1, 13, 0, 0), 664 0),
702 GATE(smmu_fimcl3, "smmu_fimcl3,", "aclk333_432_gscl", 665 GATE(CLK_GSCL_WA, "gscl_wa", "aclk300_gscl", GATE_IP_GSCL1, 12, 0, 0),
666 GATE(CLK_GSCL_WB, "gscl_wb", "aclk300_gscl", GATE_IP_GSCL1, 13, 0, 0),
667 GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "aclk333_432_gscl",
703 GATE_IP_GSCL1, 16, 0, 0), 668 GATE_IP_GSCL1, 16, 0, 0),
704 GATE(fimc_lite3, "fimc_lite3", "aclk333_432_gscl", 669 GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
705 GATE_IP_GSCL1, 17, 0, 0), 670 GATE_IP_GSCL1, 17, 0, 0),
706 671
707 GATE(fimd1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0), 672 GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
708 GATE(dsim1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0), 673 GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
709 GATE(dp1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0), 674 GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
710 GATE(mixer, "mixer", "aclk166", GATE_IP_DISP1, 5, 0, 0), 675 GATE(CLK_MIXER, "mixer", "aclk166", GATE_IP_DISP1, 5, 0, 0),
711 GATE(hdmi, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), 676 GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
712 GATE(smmu_fimd1, "smmu_fimd1", "aclk300_disp1", GATE_IP_DISP1, 8, 0, 0), 677 GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk300_disp1", GATE_IP_DISP1, 8, 0,
713 678 0),
714 GATE(mfc, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), 679
715 GATE(smmu_mfcl, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0), 680 GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
716 GATE(smmu_mfcr, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0), 681 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0),
717 682 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0),
718 GATE(g3d, "g3d", "aclkg3d", GATE_IP_G3D, 9, 0, 0), 683
719 684 GATE(CLK_G3D, "g3d", "aclkg3d", GATE_IP_G3D, 9, 0, 0),
720 GATE(rotator, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0), 685
721 GATE(jpeg, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0), 686 GATE(CLK_ROTATOR, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0),
722 GATE(jpeg2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0), 687 GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
723 GATE(mdma1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0), 688 GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
724 GATE(smmu_rotator, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0), 689 GATE(CLK_MDMA1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
725 GATE(smmu_jpeg, "smmu_jpeg", "aclk300_jpeg", GATE_IP_GEN, 7, 0, 0), 690 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0),
726 GATE(smmu_mdma1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0), 691 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk300_jpeg", GATE_IP_GEN, 7, 0, 0),
727 692 GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0),
728 GATE(mscl0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0), 693
729 GATE(mscl1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0), 694 GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
730 GATE(mscl2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0), 695 GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
731 GATE(smmu_mscl0, "smmu_mscl0", "aclk400_mscl", GATE_IP_MSCL, 8, 0, 0), 696 GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
732 GATE(smmu_mscl1, "smmu_mscl1", "aclk400_mscl", GATE_IP_MSCL, 9, 0, 0), 697 GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "aclk400_mscl", GATE_IP_MSCL, 8, 0,
733 GATE(smmu_mscl2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0, 0), 698 0),
734 GATE(smmu_mixer, "smmu_mixer", "aclk200_disp1", GATE_IP_DISP1, 9, 0, 0), 699 GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "aclk400_mscl", GATE_IP_MSCL, 9, 0,
700 0),
701 GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0,
702 0),
703 GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", GATE_IP_DISP1, 9, 0,
704 0),
735}; 705};
736 706
737static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = { 707static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = {
738 [apll] = PLL(pll_2550, fout_apll, "fout_apll", "fin_pll", APLL_LOCK, 708 [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
739 APLL_CON0, NULL), 709 APLL_CON0, NULL),
740 [cpll] = PLL(pll_2550, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK, 710 [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
741 MPLL_CON0, NULL), 711 CPLL_CON0, NULL),
742 [dpll] = PLL(pll_2550, fout_dpll, "fout_dpll", "fin_pll", DPLL_LOCK, 712 [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK,
743 DPLL_CON0, NULL), 713 DPLL_CON0, NULL),
744 [epll] = PLL(pll_2650, fout_epll, "fout_epll", "fin_pll", EPLL_LOCK, 714 [epll] = PLL(pll_2650, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
745 EPLL_CON0, NULL), 715 EPLL_CON0, NULL),
746 [rpll] = PLL(pll_2650, fout_rpll, "fout_rpll", "fin_pll", RPLL_LOCK, 716 [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK,
747 RPLL_CON0, NULL), 717 RPLL_CON0, NULL),
748 [ipll] = PLL(pll_2550, fout_ipll, "fout_ipll", "fin_pll", IPLL_LOCK, 718 [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK,
749 IPLL_CON0, NULL), 719 IPLL_CON0, NULL),
750 [spll] = PLL(pll_2550, fout_spll, "fout_spll", "fin_pll", SPLL_LOCK, 720 [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK,
751 SPLL_CON0, NULL), 721 SPLL_CON0, NULL),
752 [vpll] = PLL(pll_2550, fout_vpll, "fout_vpll", "fin_pll", VPLL_LOCK, 722 [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK,
753 VPLL_CON0, NULL), 723 VPLL_CON0, NULL),
754 [mpll] = PLL(pll_2550, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK, 724 [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
755 MPLL_CON0, NULL), 725 MPLL_CON0, NULL),
756 [bpll] = PLL(pll_2550, fout_bpll, "fout_bpll", "fin_pll", BPLL_LOCK, 726 [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
757 BPLL_CON0, NULL), 727 BPLL_CON0, NULL),
758 [kpll] = PLL(pll_2550, fout_kpll, "fout_kpll", "fin_pll", KPLL_LOCK, 728 [kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
759 KPLL_CON0, NULL), 729 KPLL_CON0, NULL),
760}; 730};
761 731
@@ -777,7 +747,7 @@ static void __init exynos5420_clk_init(struct device_node *np)
777 panic("%s: unable to determine soc\n", __func__); 747 panic("%s: unable to determine soc\n", __func__);
778 } 748 }
779 749
780 samsung_clk_init(np, reg_base, nr_clks, 750 samsung_clk_init(np, reg_base, CLK_NR_CLKS,
781 exynos5420_clk_regs, ARRAY_SIZE(exynos5420_clk_regs), 751 exynos5420_clk_regs, ARRAY_SIZE(exynos5420_clk_regs),
782 NULL, 0); 752 NULL, 0);
783 samsung_clk_of_register_fixed_ext(exynos5420_fixed_rate_ext_clks, 753 samsung_clk_of_register_fixed_ext(exynos5420_fixed_rate_ext_clks,
diff --git a/drivers/clk/samsung/clk-exynos5440.c b/drivers/clk/samsung/clk-exynos5440.c
index f8658945bfd2..cbc15b56891d 100644
--- a/drivers/clk/samsung/clk-exynos5440.c
+++ b/drivers/clk/samsung/clk-exynos5440.c
@@ -9,6 +9,7 @@
9 * Common Clock Framework support for Exynos5440 SoC. 9 * Common Clock Framework support for Exynos5440 SoC.
10*/ 10*/
11 11
12#include <dt-bindings/clock/exynos5440.h>
12#include <linux/clk.h> 13#include <linux/clk.h>
13#include <linux/clkdev.h> 14#include <linux/clkdev.h>
14#include <linux/clk-provider.h> 15#include <linux/clk-provider.h>
@@ -22,79 +23,65 @@
22#define CPU_CLK_STATUS 0xfc 23#define CPU_CLK_STATUS 0xfc
23#define MISC_DOUT1 0x558 24#define MISC_DOUT1 0x558
24 25
25/*
26 * Let each supported clock get a unique id. This id is used to lookup the clock
27 * for device tree based platforms.
28 */
29enum exynos5440_clks {
30 none, xtal, arm_clk,
31
32 spi_baud = 16, pb0_250, pr0_250, pr1_250, b_250, b_125, b_200, sata,
33 usb, gmac0, cs250, pb0_250_o, pr0_250_o, pr1_250_o, b_250_o, b_125_o,
34 b_200_o, sata_o, usb_o, gmac0_o, cs250_o,
35
36 nr_clks,
37};
38
39/* parent clock name list */ 26/* parent clock name list */
40PNAME(mout_armclk_p) = { "cplla", "cpllb" }; 27PNAME(mout_armclk_p) = { "cplla", "cpllb" };
41PNAME(mout_spi_p) = { "div125", "div200" }; 28PNAME(mout_spi_p) = { "div125", "div200" };
42 29
43/* fixed rate clocks generated outside the soc */ 30/* fixed rate clocks generated outside the soc */
44static struct samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[] __initdata = { 31static struct samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[] __initdata = {
45 FRATE(none, "xtal", NULL, CLK_IS_ROOT, 0), 32 FRATE(0, "xtal", NULL, CLK_IS_ROOT, 0),
46}; 33};
47 34
48/* fixed rate clocks */ 35/* fixed rate clocks */
49static struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata = { 36static struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata = {
50 FRATE(none, "ppll", NULL, CLK_IS_ROOT, 1000000000), 37 FRATE(0, "ppll", NULL, CLK_IS_ROOT, 1000000000),
51 FRATE(none, "usb_phy0", NULL, CLK_IS_ROOT, 60000000), 38 FRATE(0, "usb_phy0", NULL, CLK_IS_ROOT, 60000000),
52 FRATE(none, "usb_phy1", NULL, CLK_IS_ROOT, 60000000), 39 FRATE(0, "usb_phy1", NULL, CLK_IS_ROOT, 60000000),
53 FRATE(none, "usb_ohci12", NULL, CLK_IS_ROOT, 12000000), 40 FRATE(0, "usb_ohci12", NULL, CLK_IS_ROOT, 12000000),
54 FRATE(none, "usb_ohci48", NULL, CLK_IS_ROOT, 48000000), 41 FRATE(0, "usb_ohci48", NULL, CLK_IS_ROOT, 48000000),
55}; 42};
56 43
57/* fixed factor clocks */ 44/* fixed factor clocks */
58static struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initdata = { 45static struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initdata = {
59 FFACTOR(none, "div250", "ppll", 1, 4, 0), 46 FFACTOR(0, "div250", "ppll", 1, 4, 0),
60 FFACTOR(none, "div200", "ppll", 1, 5, 0), 47 FFACTOR(0, "div200", "ppll", 1, 5, 0),
61 FFACTOR(none, "div125", "div250", 1, 2, 0), 48 FFACTOR(0, "div125", "div250", 1, 2, 0),
62}; 49};
63 50
64/* mux clocks */ 51/* mux clocks */
65static struct samsung_mux_clock exynos5440_mux_clks[] __initdata = { 52static struct samsung_mux_clock exynos5440_mux_clks[] __initdata = {
66 MUX(none, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1), 53 MUX(0, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1),
67 MUX_A(arm_clk, "arm_clk", mout_armclk_p, 54 MUX_A(CLK_ARM_CLK, "arm_clk", mout_armclk_p,
68 CPU_CLK_STATUS, 0, 1, "armclk"), 55 CPU_CLK_STATUS, 0, 1, "armclk"),
69}; 56};
70 57
71/* divider clocks */ 58/* divider clocks */
72static struct samsung_div_clock exynos5440_div_clks[] __initdata = { 59static struct samsung_div_clock exynos5440_div_clks[] __initdata = {
73 DIV(spi_baud, "div_spi", "mout_spi", MISC_DOUT1, 3, 2), 60 DIV(CLK_SPI_BAUD, "div_spi", "mout_spi", MISC_DOUT1, 3, 2),
74}; 61};
75 62
76/* gate clocks */ 63/* gate clocks */
77static struct samsung_gate_clock exynos5440_gate_clks[] __initdata = { 64static struct samsung_gate_clock exynos5440_gate_clks[] __initdata = {
78 GATE(pb0_250, "pb0_250", "div250", CLKEN_OV_VAL, 3, 0, 0), 65 GATE(CLK_PB0_250, "pb0_250", "div250", CLKEN_OV_VAL, 3, 0, 0),
79 GATE(pr0_250, "pr0_250", "div250", CLKEN_OV_VAL, 4, 0, 0), 66 GATE(CLK_PR0_250, "pr0_250", "div250", CLKEN_OV_VAL, 4, 0, 0),
80 GATE(pr1_250, "pr1_250", "div250", CLKEN_OV_VAL, 5, 0, 0), 67 GATE(CLK_PR1_250, "pr1_250", "div250", CLKEN_OV_VAL, 5, 0, 0),
81 GATE(b_250, "b_250", "div250", CLKEN_OV_VAL, 9, 0, 0), 68 GATE(CLK_B_250, "b_250", "div250", CLKEN_OV_VAL, 9, 0, 0),
82 GATE(b_125, "b_125", "div125", CLKEN_OV_VAL, 10, 0, 0), 69 GATE(CLK_B_125, "b_125", "div125", CLKEN_OV_VAL, 10, 0, 0),
83 GATE(b_200, "b_200", "div200", CLKEN_OV_VAL, 11, 0, 0), 70 GATE(CLK_B_200, "b_200", "div200", CLKEN_OV_VAL, 11, 0, 0),
84 GATE(sata, "sata", "div200", CLKEN_OV_VAL, 12, 0, 0), 71 GATE(CLK_SATA, "sata", "div200", CLKEN_OV_VAL, 12, 0, 0),
85 GATE(usb, "usb", "div200", CLKEN_OV_VAL, 13, 0, 0), 72 GATE(CLK_USB, "usb", "div200", CLKEN_OV_VAL, 13, 0, 0),
86 GATE(gmac0, "gmac0", "div200", CLKEN_OV_VAL, 14, 0, 0), 73 GATE(CLK_GMAC0, "gmac0", "div200", CLKEN_OV_VAL, 14, 0, 0),
87 GATE(cs250, "cs250", "div250", CLKEN_OV_VAL, 19, 0, 0), 74 GATE(CLK_CS250, "cs250", "div250", CLKEN_OV_VAL, 19, 0, 0),
88 GATE(pb0_250_o, "pb0_250_o", "pb0_250", CLKEN_OV_VAL, 3, 0, 0), 75 GATE(CLK_PB0_250_O, "pb0_250_o", "pb0_250", CLKEN_OV_VAL, 3, 0, 0),
89 GATE(pr0_250_o, "pr0_250_o", "pr0_250", CLKEN_OV_VAL, 4, 0, 0), 76 GATE(CLK_PR0_250_O, "pr0_250_o", "pr0_250", CLKEN_OV_VAL, 4, 0, 0),
90 GATE(pr1_250_o, "pr1_250_o", "pr1_250", CLKEN_OV_VAL, 5, 0, 0), 77 GATE(CLK_PR1_250_O, "pr1_250_o", "pr1_250", CLKEN_OV_VAL, 5, 0, 0),
91 GATE(b_250_o, "b_250_o", "b_250", CLKEN_OV_VAL, 9, 0, 0), 78 GATE(CLK_B_250_O, "b_250_o", "b_250", CLKEN_OV_VAL, 9, 0, 0),
92 GATE(b_125_o, "b_125_o", "b_125", CLKEN_OV_VAL, 10, 0, 0), 79 GATE(CLK_B_125_O, "b_125_o", "b_125", CLKEN_OV_VAL, 10, 0, 0),
93 GATE(b_200_o, "b_200_o", "b_200", CLKEN_OV_VAL, 11, 0, 0), 80 GATE(CLK_B_200_O, "b_200_o", "b_200", CLKEN_OV_VAL, 11, 0, 0),
94 GATE(sata_o, "sata_o", "sata", CLKEN_OV_VAL, 12, 0, 0), 81 GATE(CLK_SATA_O, "sata_o", "sata", CLKEN_OV_VAL, 12, 0, 0),
95 GATE(usb_o, "usb_o", "usb", CLKEN_OV_VAL, 13, 0, 0), 82 GATE(CLK_USB_O, "usb_o", "usb", CLKEN_OV_VAL, 13, 0, 0),
96 GATE(gmac0_o, "gmac0_o", "gmac", CLKEN_OV_VAL, 14, 0, 0), 83 GATE(CLK_GMAC0_O, "gmac0_o", "gmac", CLKEN_OV_VAL, 14, 0, 0),
97 GATE(cs250_o, "cs250_o", "cs250", CLKEN_OV_VAL, 19, 0, 0), 84 GATE(CLK_CS250_O, "cs250_o", "cs250", CLKEN_OV_VAL, 19, 0, 0),
98}; 85};
99 86
100static struct of_device_id ext_clk_match[] __initdata = { 87static struct of_device_id ext_clk_match[] __initdata = {
@@ -114,7 +101,7 @@ static void __init exynos5440_clk_init(struct device_node *np)
114 return; 101 return;
115 } 102 }
116 103
117 samsung_clk_init(np, reg_base, nr_clks, NULL, 0, NULL, 0); 104 samsung_clk_init(np, reg_base, CLK_NR_CLKS, NULL, 0, NULL, 0);
118 samsung_clk_of_register_fixed_ext(exynos5440_fixed_rate_ext_clks, 105 samsung_clk_of_register_fixed_ext(exynos5440_fixed_rate_ext_clks,
119 ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match); 106 ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match);
120 107
diff --git a/drivers/clk/shmobile/Makefile b/drivers/clk/shmobile/Makefile
new file mode 100644
index 000000000000..9ecef140dba7
--- /dev/null
+++ b/drivers/clk/shmobile/Makefile
@@ -0,0 +1,7 @@
1obj-$(CONFIG_ARCH_EMEV2) += clk-emev2.o
2obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o
3obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o
4obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += clk-div6.o
5obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += clk-mstp.o
6# for emply built-in.o
7obj-n := dummy
diff --git a/drivers/clk/shmobile/clk-div6.c b/drivers/clk/shmobile/clk-div6.c
new file mode 100644
index 000000000000..aac4756ec52e
--- /dev/null
+++ b/drivers/clk/shmobile/clk-div6.c
@@ -0,0 +1,185 @@
1/*
2 * r8a7790 Common Clock Framework support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 *
6 * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 */
12
13#include <linux/clk-provider.h>
14#include <linux/clkdev.h>
15#include <linux/init.h>
16#include <linux/io.h>
17#include <linux/kernel.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20
21#define CPG_DIV6_CKSTP BIT(8)
22#define CPG_DIV6_DIV(d) ((d) & 0x3f)
23#define CPG_DIV6_DIV_MASK 0x3f
24
25/**
26 * struct div6_clock - MSTP gating clock
27 * @hw: handle between common and hardware-specific interfaces
28 * @reg: IO-remapped register
29 * @div: divisor value (1-64)
30 */
31struct div6_clock {
32 struct clk_hw hw;
33 void __iomem *reg;
34 unsigned int div;
35};
36
37#define to_div6_clock(_hw) container_of(_hw, struct div6_clock, hw)
38
39static int cpg_div6_clock_enable(struct clk_hw *hw)
40{
41 struct div6_clock *clock = to_div6_clock(hw);
42
43 clk_writel(CPG_DIV6_DIV(clock->div - 1), clock->reg);
44
45 return 0;
46}
47
48static void cpg_div6_clock_disable(struct clk_hw *hw)
49{
50 struct div6_clock *clock = to_div6_clock(hw);
51
52 /* DIV6 clocks require the divisor field to be non-zero when stopping
53 * the clock.
54 */
55 clk_writel(CPG_DIV6_CKSTP | CPG_DIV6_DIV(CPG_DIV6_DIV_MASK),
56 clock->reg);
57}
58
59static int cpg_div6_clock_is_enabled(struct clk_hw *hw)
60{
61 struct div6_clock *clock = to_div6_clock(hw);
62
63 return !(clk_readl(clock->reg) & CPG_DIV6_CKSTP);
64}
65
66static unsigned long cpg_div6_clock_recalc_rate(struct clk_hw *hw,
67 unsigned long parent_rate)
68{
69 struct div6_clock *clock = to_div6_clock(hw);
70 unsigned int div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;
71
72 return parent_rate / div;
73}
74
75static unsigned int cpg_div6_clock_calc_div(unsigned long rate,
76 unsigned long parent_rate)
77{
78 unsigned int div;
79
80 div = DIV_ROUND_CLOSEST(parent_rate, rate);
81 return clamp_t(unsigned int, div, 1, 64);
82}
83
84static long cpg_div6_clock_round_rate(struct clk_hw *hw, unsigned long rate,
85 unsigned long *parent_rate)
86{
87 unsigned int div = cpg_div6_clock_calc_div(rate, *parent_rate);
88
89 return *parent_rate / div;
90}
91
92static int cpg_div6_clock_set_rate(struct clk_hw *hw, unsigned long rate,
93 unsigned long parent_rate)
94{
95 struct div6_clock *clock = to_div6_clock(hw);
96 unsigned int div = cpg_div6_clock_calc_div(rate, parent_rate);
97
98 clock->div = div;
99
100 /* Only program the new divisor if the clock isn't stopped. */
101 if (!(clk_readl(clock->reg) & CPG_DIV6_CKSTP))
102 clk_writel(CPG_DIV6_DIV(clock->div - 1), clock->reg);
103
104 return 0;
105}
106
107static const struct clk_ops cpg_div6_clock_ops = {
108 .enable = cpg_div6_clock_enable,
109 .disable = cpg_div6_clock_disable,
110 .is_enabled = cpg_div6_clock_is_enabled,
111 .recalc_rate = cpg_div6_clock_recalc_rate,
112 .round_rate = cpg_div6_clock_round_rate,
113 .set_rate = cpg_div6_clock_set_rate,
114};
115
116static void __init cpg_div6_clock_init(struct device_node *np)
117{
118 struct clk_init_data init;
119 struct div6_clock *clock;
120 const char *parent_name;
121 const char *name;
122 struct clk *clk;
123 int ret;
124
125 clock = kzalloc(sizeof(*clock), GFP_KERNEL);
126 if (!clock) {
127 pr_err("%s: failed to allocate %s DIV6 clock\n",
128 __func__, np->name);
129 return;
130 }
131
132 /* Remap the clock register and read the divisor. Disabling the
133 * clock overwrites the divisor, so we need to cache its value for the
134 * enable operation.
135 */
136 clock->reg = of_iomap(np, 0);
137 if (clock->reg == NULL) {
138 pr_err("%s: failed to map %s DIV6 clock register\n",
139 __func__, np->name);
140 goto error;
141 }
142
143 clock->div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;
144
145 /* Parse the DT properties. */
146 ret = of_property_read_string(np, "clock-output-names", &name);
147 if (ret < 0) {
148 pr_err("%s: failed to get %s DIV6 clock output name\n",
149 __func__, np->name);
150 goto error;
151 }
152
153 parent_name = of_clk_get_parent_name(np, 0);
154 if (parent_name == NULL) {
155 pr_err("%s: failed to get %s DIV6 clock parent name\n",
156 __func__, np->name);
157 goto error;
158 }
159
160 /* Register the clock. */
161 init.name = name;
162 init.ops = &cpg_div6_clock_ops;
163 init.flags = CLK_IS_BASIC;
164 init.parent_names = &parent_name;
165 init.num_parents = 1;
166
167 clock->hw.init = &init;
168
169 clk = clk_register(NULL, &clock->hw);
170 if (IS_ERR(clk)) {
171 pr_err("%s: failed to register %s DIV6 clock (%ld)\n",
172 __func__, np->name, PTR_ERR(clk));
173 goto error;
174 }
175
176 of_clk_add_provider(np, of_clk_src_simple_get, clk);
177
178 return;
179
180error:
181 if (clock->reg)
182 iounmap(clock->reg);
183 kfree(clock);
184}
185CLK_OF_DECLARE(cpg_div6_clk, "renesas,cpg-div6-clock", cpg_div6_clock_init);
diff --git a/drivers/clk/shmobile/clk-emev2.c b/drivers/clk/shmobile/clk-emev2.c
new file mode 100644
index 000000000000..6c7c929c7765
--- /dev/null
+++ b/drivers/clk/shmobile/clk-emev2.c
@@ -0,0 +1,104 @@
1/*
2 * EMMA Mobile EV2 common clock framework support
3 *
4 * Copyright (C) 2013 Takashi Yoshii <takashi.yoshii.ze@renesas.com>
5 * Copyright (C) 2012 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/clk-provider.h>
21#include <linux/clkdev.h>
22#include <linux/io.h>
23#include <linux/of.h>
24#include <linux/of_address.h>
25
26/* EMEV2 SMU registers */
27#define USIAU0_RSTCTRL 0x094
28#define USIBU1_RSTCTRL 0x0ac
29#define USIBU2_RSTCTRL 0x0b0
30#define USIBU3_RSTCTRL 0x0b4
31#define STI_RSTCTRL 0x124
32#define STI_CLKSEL 0x688
33
34static DEFINE_SPINLOCK(lock);
35
36/* not pretty, but hey */
37void __iomem *smu_base;
38
39static void __init emev2_smu_write(unsigned long value, int offs)
40{
41 BUG_ON(!smu_base || (offs >= PAGE_SIZE));
42 writel_relaxed(value, smu_base + offs);
43}
44
45static const struct of_device_id smu_id[] __initconst = {
46 { .compatible = "renesas,emev2-smu", },
47 {},
48};
49
50static void __init emev2_smu_init(void)
51{
52 struct device_node *np;
53
54 np = of_find_matching_node(NULL, smu_id);
55 BUG_ON(!np);
56 smu_base = of_iomap(np, 0);
57 BUG_ON(!smu_base);
58 of_node_put(np);
59
60 /* setup STI timer to run on 32.768 kHz and deassert reset */
61 emev2_smu_write(0, STI_CLKSEL);
62 emev2_smu_write(1, STI_RSTCTRL);
63
64 /* deassert reset for UART0->UART3 */
65 emev2_smu_write(2, USIAU0_RSTCTRL);
66 emev2_smu_write(2, USIBU1_RSTCTRL);
67 emev2_smu_write(2, USIBU2_RSTCTRL);
68 emev2_smu_write(2, USIBU3_RSTCTRL);
69}
70
71static void __init emev2_smu_clkdiv_init(struct device_node *np)
72{
73 u32 reg[2];
74 struct clk *clk;
75 const char *parent_name = of_clk_get_parent_name(np, 0);
76 if (WARN_ON(of_property_read_u32_array(np, "reg", reg, 2)))
77 return;
78 if (!smu_base)
79 emev2_smu_init();
80 clk = clk_register_divider(NULL, np->name, parent_name, 0,
81 smu_base + reg[0], reg[1], 8, 0, &lock);
82 of_clk_add_provider(np, of_clk_src_simple_get, clk);
83 clk_register_clkdev(clk, np->name, NULL);
84 pr_debug("## %s %s %p\n", __func__, np->name, clk);
85}
86CLK_OF_DECLARE(emev2_smu_clkdiv, "renesas,emev2-smu-clkdiv",
87 emev2_smu_clkdiv_init);
88
89static void __init emev2_smu_gclk_init(struct device_node *np)
90{
91 u32 reg[2];
92 struct clk *clk;
93 const char *parent_name = of_clk_get_parent_name(np, 0);
94 if (WARN_ON(of_property_read_u32_array(np, "reg", reg, 2)))
95 return;
96 if (!smu_base)
97 emev2_smu_init();
98 clk = clk_register_gate(NULL, np->name, parent_name, 0,
99 smu_base + reg[0], reg[1], 0, &lock);
100 of_clk_add_provider(np, of_clk_src_simple_get, clk);
101 clk_register_clkdev(clk, np->name, NULL);
102 pr_debug("## %s %s %p\n", __func__, np->name, clk);
103}
104CLK_OF_DECLARE(emev2_smu_gclk, "renesas,emev2-smu-gclk", emev2_smu_gclk_init);
diff --git a/drivers/clk/shmobile/clk-mstp.c b/drivers/clk/shmobile/clk-mstp.c
new file mode 100644
index 000000000000..42d5912b1d25
--- /dev/null
+++ b/drivers/clk/shmobile/clk-mstp.c
@@ -0,0 +1,233 @@
1/*
2 * R-Car MSTP clocks
3 *
4 * Copyright (C) 2013 Ideas On Board SPRL
5 *
6 * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 */
12
13#include <linux/clk-provider.h>
14#include <linux/clkdev.h>
15#include <linux/io.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18#include <linux/spinlock.h>
19
20/*
21 * MSTP clocks. We can't use standard gate clocks as we need to poll on the
22 * status register when enabling the clock.
23 */
24
25#define MSTP_MAX_CLOCKS 32
26
27/**
28 * struct mstp_clock_group - MSTP gating clocks group
29 *
30 * @data: clocks in this group
31 * @smstpcr: module stop control register
32 * @mstpsr: module stop status register (optional)
33 * @lock: protects writes to SMSTPCR
34 */
35struct mstp_clock_group {
36 struct clk_onecell_data data;
37 void __iomem *smstpcr;
38 void __iomem *mstpsr;
39 spinlock_t lock;
40};
41
42/**
43 * struct mstp_clock - MSTP gating clock
44 * @hw: handle between common and hardware-specific interfaces
45 * @bit_index: control bit index
46 * @group: MSTP clocks group
47 */
48struct mstp_clock {
49 struct clk_hw hw;
50 u32 bit_index;
51 struct mstp_clock_group *group;
52};
53
54#define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
55
56static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
57{
58 struct mstp_clock *clock = to_mstp_clock(hw);
59 struct mstp_clock_group *group = clock->group;
60 u32 bitmask = BIT(clock->bit_index);
61 unsigned long flags;
62 unsigned int i;
63 u32 value;
64
65 spin_lock_irqsave(&group->lock, flags);
66
67 value = clk_readl(group->smstpcr);
68 if (enable)
69 value &= ~bitmask;
70 else
71 value |= bitmask;
72 clk_writel(value, group->smstpcr);
73
74 spin_unlock_irqrestore(&group->lock, flags);
75
76 if (!enable || !group->mstpsr)
77 return 0;
78
79 for (i = 1000; i > 0; --i) {
80 if (!(clk_readl(group->mstpsr) & bitmask))
81 break;
82 cpu_relax();
83 }
84
85 if (!i) {
86 pr_err("%s: failed to enable %p[%d]\n", __func__,
87 group->smstpcr, clock->bit_index);
88 return -ETIMEDOUT;
89 }
90
91 return 0;
92}
93
94static int cpg_mstp_clock_enable(struct clk_hw *hw)
95{
96 return cpg_mstp_clock_endisable(hw, true);
97}
98
99static void cpg_mstp_clock_disable(struct clk_hw *hw)
100{
101 cpg_mstp_clock_endisable(hw, false);
102}
103
104static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
105{
106 struct mstp_clock *clock = to_mstp_clock(hw);
107 struct mstp_clock_group *group = clock->group;
108 u32 value;
109
110 if (group->mstpsr)
111 value = clk_readl(group->mstpsr);
112 else
113 value = clk_readl(group->smstpcr);
114
115 return !!(value & BIT(clock->bit_index));
116}
117
118static const struct clk_ops cpg_mstp_clock_ops = {
119 .enable = cpg_mstp_clock_enable,
120 .disable = cpg_mstp_clock_disable,
121 .is_enabled = cpg_mstp_clock_is_enabled,
122};
123
124static struct clk * __init
125cpg_mstp_clock_register(const char *name, const char *parent_name,
126 unsigned int index, struct mstp_clock_group *group)
127{
128 struct clk_init_data init;
129 struct mstp_clock *clock;
130 struct clk *clk;
131
132 clock = kzalloc(sizeof(*clock), GFP_KERNEL);
133 if (!clock) {
134 pr_err("%s: failed to allocate MSTP clock.\n", __func__);
135 return ERR_PTR(-ENOMEM);
136 }
137
138 init.name = name;
139 init.ops = &cpg_mstp_clock_ops;
140 init.flags = CLK_IS_BASIC;
141 init.parent_names = &parent_name;
142 init.num_parents = 1;
143
144 clock->bit_index = index;
145 clock->group = group;
146 clock->hw.init = &init;
147
148 clk = clk_register(NULL, &clock->hw);
149
150 if (IS_ERR(clk))
151 kfree(clock);
152
153 return clk;
154}
155
156static void __init cpg_mstp_clocks_init(struct device_node *np)
157{
158 struct mstp_clock_group *group;
159 struct clk **clks;
160 unsigned int i;
161
162 group = kzalloc(sizeof(*group), GFP_KERNEL);
163 clks = kmalloc(MSTP_MAX_CLOCKS * sizeof(*clks), GFP_KERNEL);
164 if (group == NULL || clks == NULL) {
165 kfree(group);
166 kfree(clks);
167 pr_err("%s: failed to allocate group\n", __func__);
168 return;
169 }
170
171 spin_lock_init(&group->lock);
172 group->data.clks = clks;
173
174 group->smstpcr = of_iomap(np, 0);
175 group->mstpsr = of_iomap(np, 1);
176
177 if (group->smstpcr == NULL) {
178 pr_err("%s: failed to remap SMSTPCR\n", __func__);
179 kfree(group);
180 kfree(clks);
181 return;
182 }
183
184 for (i = 0; i < MSTP_MAX_CLOCKS; ++i)
185 clks[i] = ERR_PTR(-ENOENT);
186
187 for (i = 0; i < MSTP_MAX_CLOCKS; ++i) {
188 const char *parent_name;
189 const char *name;
190 u32 clkidx;
191 int ret;
192
193 /* Skip clocks with no name. */
194 ret = of_property_read_string_index(np, "clock-output-names",
195 i, &name);
196 if (ret < 0 || strlen(name) == 0)
197 continue;
198
199 parent_name = of_clk_get_parent_name(np, i);
200 ret = of_property_read_u32_index(np, "renesas,clock-indices", i,
201 &clkidx);
202 if (parent_name == NULL || ret < 0)
203 break;
204
205 if (clkidx >= MSTP_MAX_CLOCKS) {
206 pr_err("%s: invalid clock %s %s index %u)\n",
207 __func__, np->name, name, clkidx);
208 continue;
209 }
210
211 clks[clkidx] = cpg_mstp_clock_register(name, parent_name,
212 clkidx, group);
213 if (!IS_ERR(clks[clkidx])) {
214 group->data.clk_num = max(group->data.clk_num,
215 clkidx + 1);
216 /*
217 * Register a clkdev to let board code retrieve the
218 * clock by name and register aliases for non-DT
219 * devices.
220 *
221 * FIXME: Remove this when all devices that require a
222 * clock will be instantiated from DT.
223 */
224 clk_register_clkdev(clks[clkidx], name, NULL);
225 } else {
226 pr_err("%s: failed to register %s %s clock (%ld)\n",
227 __func__, np->name, name, PTR_ERR(clks[clkidx]));
228 }
229 }
230
231 of_clk_add_provider(np, of_clk_src_onecell_get, &group->data);
232}
233CLK_OF_DECLARE(cpg_mstp_clks, "renesas,cpg-mstp-clocks", cpg_mstp_clocks_init);
diff --git a/drivers/clk/shmobile/clk-rcar-gen2.c b/drivers/clk/shmobile/clk-rcar-gen2.c
new file mode 100644
index 000000000000..a59ec217a124
--- /dev/null
+++ b/drivers/clk/shmobile/clk-rcar-gen2.c
@@ -0,0 +1,298 @@
1/*
2 * rcar_gen2 Core CPG Clocks
3 *
4 * Copyright (C) 2013 Ideas On Board SPRL
5 *
6 * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 */
12
13#include <linux/clk-provider.h>
14#include <linux/clkdev.h>
15#include <linux/clk/shmobile.h>
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/math64.h>
19#include <linux/of.h>
20#include <linux/of_address.h>
21#include <linux/spinlock.h>
22
23struct rcar_gen2_cpg {
24 struct clk_onecell_data data;
25 spinlock_t lock;
26 void __iomem *reg;
27};
28
29#define CPG_SDCKCR 0x00000074
30#define CPG_PLL0CR 0x000000d8
31#define CPG_FRQCRC 0x000000e0
32#define CPG_FRQCRC_ZFC_MASK (0x1f << 8)
33#define CPG_FRQCRC_ZFC_SHIFT 8
34
35/* -----------------------------------------------------------------------------
36 * Z Clock
37 *
38 * Traits of this clock:
39 * prepare - clk_prepare only ensures that parents are prepared
40 * enable - clk_enable only ensures that parents are enabled
41 * rate - rate is adjustable. clk->rate = parent->rate * mult / 32
42 * parent - fixed parent. No clk_set_parent support
43 */
44
45struct cpg_z_clk {
46 struct clk_hw hw;
47 void __iomem *reg;
48};
49
50#define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw)
51
52static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
53 unsigned long parent_rate)
54{
55 struct cpg_z_clk *zclk = to_z_clk(hw);
56 unsigned int mult;
57 unsigned int val;
58
59 val = (clk_readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK)
60 >> CPG_FRQCRC_ZFC_SHIFT;
61 mult = 32 - val;
62
63 return div_u64((u64)parent_rate * mult, 32);
64}
65
66static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,
67 unsigned long *parent_rate)
68{
69 unsigned long prate = *parent_rate;
70 unsigned int mult;
71
72 if (!prate)
73 prate = 1;
74
75 mult = div_u64((u64)rate * 32, prate);
76 mult = clamp(mult, 1U, 32U);
77
78 return *parent_rate / 32 * mult;
79}
80
81static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
82 unsigned long parent_rate)
83{
84 struct cpg_z_clk *zclk = to_z_clk(hw);
85 unsigned int mult;
86 u32 val;
87
88 mult = div_u64((u64)rate * 32, parent_rate);
89 mult = clamp(mult, 1U, 32U);
90
91 val = clk_readl(zclk->reg);
92 val &= ~CPG_FRQCRC_ZFC_MASK;
93 val |= (32 - mult) << CPG_FRQCRC_ZFC_SHIFT;
94 clk_writel(val, zclk->reg);
95
96 return 0;
97}
98
99static const struct clk_ops cpg_z_clk_ops = {
100 .recalc_rate = cpg_z_clk_recalc_rate,
101 .round_rate = cpg_z_clk_round_rate,
102 .set_rate = cpg_z_clk_set_rate,
103};
104
105static struct clk * __init cpg_z_clk_register(struct rcar_gen2_cpg *cpg)
106{
107 static const char *parent_name = "pll0";
108 struct clk_init_data init;
109 struct cpg_z_clk *zclk;
110 struct clk *clk;
111
112 zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);
113 if (!zclk)
114 return ERR_PTR(-ENOMEM);
115
116 init.name = "z";
117 init.ops = &cpg_z_clk_ops;
118 init.flags = 0;
119 init.parent_names = &parent_name;
120 init.num_parents = 1;
121
122 zclk->reg = cpg->reg + CPG_FRQCRC;
123 zclk->hw.init = &init;
124
125 clk = clk_register(NULL, &zclk->hw);
126 if (IS_ERR(clk))
127 kfree(zclk);
128
129 return clk;
130}
131
132/* -----------------------------------------------------------------------------
133 * CPG Clock Data
134 */
135
136/*
137 * MD EXTAL PLL0 PLL1 PLL3
138 * 14 13 19 (MHz) *1 *1
139 *---------------------------------------------------
140 * 0 0 0 15 x 1 x172/2 x208/2 x106
141 * 0 0 1 15 x 1 x172/2 x208/2 x88
142 * 0 1 0 20 x 1 x130/2 x156/2 x80
143 * 0 1 1 20 x 1 x130/2 x156/2 x66
144 * 1 0 0 26 / 2 x200/2 x240/2 x122
145 * 1 0 1 26 / 2 x200/2 x240/2 x102
146 * 1 1 0 30 / 2 x172/2 x208/2 x106
147 * 1 1 1 30 / 2 x172/2 x208/2 x88
148 *
149 * *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2)
150 */
151#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
152 (((md) & BIT(13)) >> 12) | \
153 (((md) & BIT(19)) >> 19))
154struct cpg_pll_config {
155 unsigned int extal_div;
156 unsigned int pll1_mult;
157 unsigned int pll3_mult;
158};
159
160static const struct cpg_pll_config cpg_pll_configs[8] __initconst = {
161 { 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 },
162 { 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 },
163};
164
165/* SDHI divisors */
166static const struct clk_div_table cpg_sdh_div_table[] = {
167 { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
168 { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
169 { 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 },
170};
171
172static const struct clk_div_table cpg_sd01_div_table[] = {
173 { 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 },
174 { 10, 36 }, { 11, 48 }, { 12, 10 }, { 0, 0 },
175};
176
177/* -----------------------------------------------------------------------------
178 * Initialization
179 */
180
181static u32 cpg_mode __initdata;
182
183static struct clk * __init
184rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg,
185 const struct cpg_pll_config *config,
186 const char *name)
187{
188 const struct clk_div_table *table = NULL;
189 const char *parent_name = "main";
190 unsigned int shift;
191 unsigned int mult = 1;
192 unsigned int div = 1;
193
194 if (!strcmp(name, "main")) {
195 parent_name = of_clk_get_parent_name(np, 0);
196 div = config->extal_div;
197 } else if (!strcmp(name, "pll0")) {
198 /* PLL0 is a configurable multiplier clock. Register it as a
199 * fixed factor clock for now as there's no generic multiplier
200 * clock implementation and we currently have no need to change
201 * the multiplier value.
202 */
203 u32 value = clk_readl(cpg->reg + CPG_PLL0CR);
204 mult = ((value >> 24) & ((1 << 7) - 1)) + 1;
205 } else if (!strcmp(name, "pll1")) {
206 mult = config->pll1_mult / 2;
207 } else if (!strcmp(name, "pll3")) {
208 mult = config->pll3_mult;
209 } else if (!strcmp(name, "lb")) {
210 div = cpg_mode & BIT(18) ? 36 : 24;
211 } else if (!strcmp(name, "qspi")) {
212 div = (cpg_mode & (BIT(3) | BIT(2) | BIT(1))) == BIT(2)
213 ? 16 : 20;
214 } else if (!strcmp(name, "sdh")) {
215 table = cpg_sdh_div_table;
216 shift = 8;
217 } else if (!strcmp(name, "sd0")) {
218 table = cpg_sd01_div_table;
219 shift = 4;
220 } else if (!strcmp(name, "sd1")) {
221 table = cpg_sd01_div_table;
222 shift = 0;
223 } else if (!strcmp(name, "z")) {
224 return cpg_z_clk_register(cpg);
225 } else {
226 return ERR_PTR(-EINVAL);
227 }
228
229 if (!table)
230 return clk_register_fixed_factor(NULL, name, parent_name, 0,
231 mult, div);
232 else
233 return clk_register_divider_table(NULL, name, parent_name, 0,
234 cpg->reg + CPG_SDCKCR, shift,
235 4, 0, table, &cpg->lock);
236}
237
238static void __init rcar_gen2_cpg_clocks_init(struct device_node *np)
239{
240 const struct cpg_pll_config *config;
241 struct rcar_gen2_cpg *cpg;
242 struct clk **clks;
243 unsigned int i;
244 int num_clks;
245
246 num_clks = of_property_count_strings(np, "clock-output-names");
247 if (num_clks < 0) {
248 pr_err("%s: failed to count clocks\n", __func__);
249 return;
250 }
251
252 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
253 clks = kzalloc(num_clks * sizeof(*clks), GFP_KERNEL);
254 if (cpg == NULL || clks == NULL) {
255 /* We're leaking memory on purpose, there's no point in cleaning
256 * up as the system won't boot anyway.
257 */
258 pr_err("%s: failed to allocate cpg\n", __func__);
259 return;
260 }
261
262 spin_lock_init(&cpg->lock);
263
264 cpg->data.clks = clks;
265 cpg->data.clk_num = num_clks;
266
267 cpg->reg = of_iomap(np, 0);
268 if (WARN_ON(cpg->reg == NULL))
269 return;
270
271 config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
272
273 for (i = 0; i < num_clks; ++i) {
274 const char *name;
275 struct clk *clk;
276
277 of_property_read_string_index(np, "clock-output-names", i,
278 &name);
279
280 clk = rcar_gen2_cpg_register_clock(np, cpg, config, name);
281 if (IS_ERR(clk))
282 pr_err("%s: failed to register %s %s clock (%ld)\n",
283 __func__, np->name, name, PTR_ERR(clk));
284 else
285 cpg->data.clks[i] = clk;
286 }
287
288 of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
289}
290CLK_OF_DECLARE(rcar_gen2_cpg_clks, "renesas,rcar-gen2-cpg-clocks",
291 rcar_gen2_cpg_clocks_init);
292
293void __init rcar_gen2_clocks_init(u32 mode)
294{
295 cpg_mode = mode;
296
297 of_clk_init(NULL);
298}
diff --git a/drivers/clk/sirf/Makefile b/drivers/clk/sirf/Makefile
new file mode 100644
index 000000000000..36b8e203f6e7
--- /dev/null
+++ b/drivers/clk/sirf/Makefile
@@ -0,0 +1,5 @@
1#
2# Makefile for sirf specific clk
3#
4
5obj-$(CONFIG_ARCH_SIRF) += clk-prima2.o clk-atlas6.o
diff --git a/drivers/clk/sirf/atlas6.h b/drivers/clk/sirf/atlas6.h
new file mode 100644
index 000000000000..376217f3bf8f
--- /dev/null
+++ b/drivers/clk/sirf/atlas6.h
@@ -0,0 +1,31 @@
1#define SIRFSOC_CLKC_CLK_EN0 0x0000
2#define SIRFSOC_CLKC_CLK_EN1 0x0004
3#define SIRFSOC_CLKC_REF_CFG 0x0020
4#define SIRFSOC_CLKC_CPU_CFG 0x0024
5#define SIRFSOC_CLKC_MEM_CFG 0x0028
6#define SIRFSOC_CLKC_MEMDIV_CFG 0x002C
7#define SIRFSOC_CLKC_SYS_CFG 0x0030
8#define SIRFSOC_CLKC_IO_CFG 0x0034
9#define SIRFSOC_CLKC_DSP_CFG 0x0038
10#define SIRFSOC_CLKC_GFX_CFG 0x003c
11#define SIRFSOC_CLKC_MM_CFG 0x0040
12#define SIRFSOC_CLKC_GFX2D_CFG 0x0040
13#define SIRFSOC_CLKC_LCD_CFG 0x0044
14#define SIRFSOC_CLKC_MMC01_CFG 0x0048
15#define SIRFSOC_CLKC_MMC23_CFG 0x004C
16#define SIRFSOC_CLKC_MMC45_CFG 0x0050
17#define SIRFSOC_CLKC_NAND_CFG 0x0054
18#define SIRFSOC_CLKC_NANDDIV_CFG 0x0058
19#define SIRFSOC_CLKC_PLL1_CFG0 0x0080
20#define SIRFSOC_CLKC_PLL2_CFG0 0x0084
21#define SIRFSOC_CLKC_PLL3_CFG0 0x0088
22#define SIRFSOC_CLKC_PLL1_CFG1 0x008c
23#define SIRFSOC_CLKC_PLL2_CFG1 0x0090
24#define SIRFSOC_CLKC_PLL3_CFG1 0x0094
25#define SIRFSOC_CLKC_PLL1_CFG2 0x0098
26#define SIRFSOC_CLKC_PLL2_CFG2 0x009c
27#define SIRFSOC_CLKC_PLL3_CFG2 0x00A0
28#define SIRFSOC_USBPHY_PLL_CTRL 0x0008
29#define SIRFSOC_USBPHY_PLL_POWERDOWN BIT(1)
30#define SIRFSOC_USBPHY_PLL_BYPASS BIT(2)
31#define SIRFSOC_USBPHY_PLL_LOCK BIT(3)
diff --git a/drivers/clk/sirf/clk-atlas6.c b/drivers/clk/sirf/clk-atlas6.c
new file mode 100644
index 000000000000..f9f4a15a64ab
--- /dev/null
+++ b/drivers/clk/sirf/clk-atlas6.c
@@ -0,0 +1,152 @@
1/*
2 * Clock tree for CSR SiRFatlasVI
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/module.h>
10#include <linux/bitops.h>
11#include <linux/io.h>
12#include <linux/clk.h>
13#include <linux/clkdev.h>
14#include <linux/clk-provider.h>
15#include <linux/of_address.h>
16#include <linux/syscore_ops.h>
17
18#include "atlas6.h"
19#include "clk-common.c"
20
21static struct clk_dmn clk_mmc01 = {
22 .regofs = SIRFSOC_CLKC_MMC01_CFG,
23 .enable_bit = 59,
24 .hw = {
25 .init = &clk_mmc01_init,
26 },
27};
28
29static struct clk_dmn clk_mmc23 = {
30 .regofs = SIRFSOC_CLKC_MMC23_CFG,
31 .enable_bit = 60,
32 .hw = {
33 .init = &clk_mmc23_init,
34 },
35};
36
37static struct clk_dmn clk_mmc45 = {
38 .regofs = SIRFSOC_CLKC_MMC45_CFG,
39 .enable_bit = 61,
40 .hw = {
41 .init = &clk_mmc45_init,
42 },
43};
44
45static struct clk_init_data clk_nand_init = {
46 .name = "nand",
47 .ops = &dmn_ops,
48 .parent_names = dmn_clk_parents,
49 .num_parents = ARRAY_SIZE(dmn_clk_parents),
50};
51
52static struct clk_dmn clk_nand = {
53 .regofs = SIRFSOC_CLKC_NAND_CFG,
54 .enable_bit = 34,
55 .hw = {
56 .init = &clk_nand_init,
57 },
58};
59
60enum atlas6_clk_index {
61 /* 0 1 2 3 4 5 6 7 8 9 */
62 rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps,
63 mf, io, cpu, uart0, uart1, uart2, tsc, i2c0, i2c1, spi0,
64 spi1, pwmc, efuse, pulse, dmac0, dmac1, nand, audio, usp0, usp1,
65 usp2, vip, gfx, gfx2d, lcd, vpp, mmc01, mmc23, mmc45, usbpll,
66 usb0, usb1, cphif, maxclk,
67};
68
69static __initdata struct clk_hw *atlas6_clk_hw_array[maxclk] = {
70 NULL, /* dummy */
71 NULL,
72 &clk_pll1.hw,
73 &clk_pll2.hw,
74 &clk_pll3.hw,
75 &clk_mem.hw,
76 &clk_sys.hw,
77 &clk_security.hw,
78 &clk_dsp.hw,
79 &clk_gps.hw,
80 &clk_mf.hw,
81 &clk_io.hw,
82 &clk_cpu.hw,
83 &clk_uart0.hw,
84 &clk_uart1.hw,
85 &clk_uart2.hw,
86 &clk_tsc.hw,
87 &clk_i2c0.hw,
88 &clk_i2c1.hw,
89 &clk_spi0.hw,
90 &clk_spi1.hw,
91 &clk_pwmc.hw,
92 &clk_efuse.hw,
93 &clk_pulse.hw,
94 &clk_dmac0.hw,
95 &clk_dmac1.hw,
96 &clk_nand.hw,
97 &clk_audio.hw,
98 &clk_usp0.hw,
99 &clk_usp1.hw,
100 &clk_usp2.hw,
101 &clk_vip.hw,
102 &clk_gfx.hw,
103 &clk_gfx2d.hw,
104 &clk_lcd.hw,
105 &clk_vpp.hw,
106 &clk_mmc01.hw,
107 &clk_mmc23.hw,
108 &clk_mmc45.hw,
109 &usb_pll_clk_hw,
110 &clk_usb0.hw,
111 &clk_usb1.hw,
112 &clk_cphif.hw,
113};
114
115static struct clk *atlas6_clks[maxclk];
116
117static void __init atlas6_clk_init(struct device_node *np)
118{
119 struct device_node *rscnp;
120 int i;
121
122 rscnp = of_find_compatible_node(NULL, NULL, "sirf,prima2-rsc");
123 sirfsoc_rsc_vbase = of_iomap(rscnp, 0);
124 if (!sirfsoc_rsc_vbase)
125 panic("unable to map rsc registers\n");
126 of_node_put(rscnp);
127
128 sirfsoc_clk_vbase = of_iomap(np, 0);
129 if (!sirfsoc_clk_vbase)
130 panic("unable to map clkc registers\n");
131
132 /* These are always available (RTC and 26MHz OSC)*/
133 atlas6_clks[rtc] = clk_register_fixed_rate(NULL, "rtc", NULL,
134 CLK_IS_ROOT, 32768);
135 atlas6_clks[osc] = clk_register_fixed_rate(NULL, "osc", NULL,
136 CLK_IS_ROOT, 26000000);
137
138 for (i = pll1; i < maxclk; i++) {
139 atlas6_clks[i] = clk_register(NULL, atlas6_clk_hw_array[i]);
140 BUG_ON(!atlas6_clks[i]);
141 }
142 clk_register_clkdev(atlas6_clks[cpu], NULL, "cpu");
143 clk_register_clkdev(atlas6_clks[io], NULL, "io");
144 clk_register_clkdev(atlas6_clks[mem], NULL, "mem");
145 clk_register_clkdev(atlas6_clks[mem], NULL, "osc");
146
147 clk_data.clks = atlas6_clks;
148 clk_data.clk_num = maxclk;
149
150 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
151}
152CLK_OF_DECLARE(atlas6_clk, "sirf,atlas6-clkc", atlas6_clk_init);
diff --git a/drivers/clk/clk-prima2.c b/drivers/clk/sirf/clk-common.c
index 6c15e3316137..7dde6a82f514 100644
--- a/drivers/clk/clk-prima2.c
+++ b/drivers/clk/sirf/clk-common.c
@@ -1,51 +1,18 @@
1/* 1/*
2 * Clock tree for CSR SiRFprimaII 2 * common clks module for all SiRF SoCs
3 * 3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. 4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 * 5 *
6 * Licensed under GPLv2 or later. 6 * Licensed under GPLv2 or later.
7 */ 7 */
8 8
9#include <linux/module.h>
10#include <linux/bitops.h>
11#include <linux/io.h>
12#include <linux/clk.h>
13#include <linux/clkdev.h>
14#include <linux/clk-provider.h>
15#include <linux/of_address.h>
16#include <linux/syscore_ops.h>
17
18#define SIRFSOC_CLKC_CLK_EN0 0x0000
19#define SIRFSOC_CLKC_CLK_EN1 0x0004
20#define SIRFSOC_CLKC_REF_CFG 0x0014
21#define SIRFSOC_CLKC_CPU_CFG 0x0018
22#define SIRFSOC_CLKC_MEM_CFG 0x001c
23#define SIRFSOC_CLKC_SYS_CFG 0x0020
24#define SIRFSOC_CLKC_IO_CFG 0x0024
25#define SIRFSOC_CLKC_DSP_CFG 0x0028
26#define SIRFSOC_CLKC_GFX_CFG 0x002c
27#define SIRFSOC_CLKC_MM_CFG 0x0030
28#define SIRFSOC_CLKC_LCD_CFG 0x0034
29#define SIRFSOC_CLKC_MMC_CFG 0x0038
30#define SIRFSOC_CLKC_PLL1_CFG0 0x0040
31#define SIRFSOC_CLKC_PLL2_CFG0 0x0044
32#define SIRFSOC_CLKC_PLL3_CFG0 0x0048
33#define SIRFSOC_CLKC_PLL1_CFG1 0x004c
34#define SIRFSOC_CLKC_PLL2_CFG1 0x0050
35#define SIRFSOC_CLKC_PLL3_CFG1 0x0054
36#define SIRFSOC_CLKC_PLL1_CFG2 0x0058
37#define SIRFSOC_CLKC_PLL2_CFG2 0x005c
38#define SIRFSOC_CLKC_PLL3_CFG2 0x0060
39#define SIRFSOC_USBPHY_PLL_CTRL 0x0008
40#define SIRFSOC_USBPHY_PLL_POWERDOWN BIT(1)
41#define SIRFSOC_USBPHY_PLL_BYPASS BIT(2)
42#define SIRFSOC_USBPHY_PLL_LOCK BIT(3)
43
44static void *sirfsoc_clk_vbase, *sirfsoc_rsc_vbase;
45
46#define KHZ 1000 9#define KHZ 1000
47#define MHZ (KHZ * KHZ) 10#define MHZ (KHZ * KHZ)
48 11
12static void *sirfsoc_clk_vbase;
13static void *sirfsoc_rsc_vbase;
14static struct clk_onecell_data clk_data;
15
49/* 16/*
50 * SiRFprimaII clock controller 17 * SiRFprimaII clock controller
51 * - 2 oscillators: osc-26MHz, rtc-32.768KHz 18 * - 2 oscillators: osc-26MHz, rtc-32.768KHz
@@ -127,6 +94,7 @@ static long pll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
127 unsigned long *parent_rate) 94 unsigned long *parent_rate)
128{ 95{
129 unsigned long fin, nf, nr, od; 96 unsigned long fin, nf, nr, od;
97 u64 dividend;
130 98
131 /* 99 /*
132 * fout = fin * nf / (nr * od); 100 * fout = fin * nf / (nr * od);
@@ -147,7 +115,10 @@ static long pll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
147 nr = BIT(6); 115 nr = BIT(6);
148 od = 1; 116 od = 1;
149 117
150 return fin * nf / (nr * od); 118 dividend = (u64)fin * nf;
119 do_div(dividend, nr * od);
120
121 return (long)dividend;
151} 122}
152 123
153static int pll_clk_set_rate(struct clk_hw *hw, unsigned long rate, 124static int pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -186,6 +157,30 @@ static int pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
186 return 0; 157 return 0;
187} 158}
188 159
160static long cpu_clk_round_rate(struct clk_hw *hw, unsigned long rate,
161 unsigned long *parent_rate)
162{
163 /*
164 * SiRF SoC has not cpu clock control,
165 * So bypass to it's parent pll.
166 */
167 struct clk *parent_clk = clk_get_parent(hw->clk);
168 struct clk *pll_parent_clk = clk_get_parent(parent_clk);
169 unsigned long pll_parent_rate = clk_get_rate(pll_parent_clk);
170 return pll_clk_round_rate(__clk_get_hw(parent_clk), rate, &pll_parent_rate);
171}
172
173static unsigned long cpu_clk_recalc_rate(struct clk_hw *hw,
174 unsigned long parent_rate)
175{
176 /*
177 * SiRF SoC has not cpu clock control,
178 * So return the parent pll rate.
179 */
180 struct clk *parent_clk = clk_get_parent(hw->clk);
181 return __clk_get_rate(parent_clk);
182}
183
189static struct clk_ops std_pll_ops = { 184static struct clk_ops std_pll_ops = {
190 .recalc_rate = pll_clk_recalc_rate, 185 .recalc_rate = pll_clk_recalc_rate,
191 .round_rate = pll_clk_round_rate, 186 .round_rate = pll_clk_round_rate,
@@ -403,6 +398,42 @@ static int dmn_clk_set_rate(struct clk_hw *hw, unsigned long rate,
403 return 0; 398 return 0;
404} 399}
405 400
401static int cpu_clk_set_rate(struct clk_hw *hw, unsigned long rate,
402 unsigned long parent_rate)
403{
404 int ret1, ret2;
405 struct clk *cur_parent;
406
407 if (rate == clk_get_rate(clk_pll1.hw.clk)) {
408 ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk);
409 return ret1;
410 }
411
412 if (rate == clk_get_rate(clk_pll2.hw.clk)) {
413 ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk);
414 return ret1;
415 }
416
417 if (rate == clk_get_rate(clk_pll3.hw.clk)) {
418 ret1 = clk_set_parent(hw->clk, clk_pll3.hw.clk);
419 return ret1;
420 }
421
422 cur_parent = clk_get_parent(hw->clk);
423
424 /* switch to tmp pll before setting parent clock's rate */
425 if (cur_parent == clk_pll1.hw.clk) {
426 ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk);
427 BUG_ON(ret1);
428 }
429
430 ret2 = clk_set_rate(clk_pll1.hw.clk, rate);
431
432 ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk);
433
434 return ret2 ? ret2 : ret1;
435}
436
406static struct clk_ops msi_ops = { 437static struct clk_ops msi_ops = {
407 .set_rate = dmn_clk_set_rate, 438 .set_rate = dmn_clk_set_rate,
408 .round_rate = dmn_clk_round_rate, 439 .round_rate = dmn_clk_round_rate,
@@ -457,6 +488,9 @@ static struct clk_dmn clk_io = {
457static struct clk_ops cpu_ops = { 488static struct clk_ops cpu_ops = {
458 .set_parent = dmn_clk_set_parent, 489 .set_parent = dmn_clk_set_parent,
459 .get_parent = dmn_clk_get_parent, 490 .get_parent = dmn_clk_get_parent,
491 .set_rate = cpu_clk_set_rate,
492 .round_rate = cpu_clk_round_rate,
493 .recalc_rate = cpu_clk_recalc_rate,
460}; 494};
461 495
462static struct clk_init_data clk_cpu_init = { 496static struct clk_init_data clk_cpu_init = {
@@ -532,6 +566,11 @@ static struct clk_dmn clk_mm = {
532 }, 566 },
533}; 567};
534 568
569/*
570 * for atlas6, gfx2d holds the bit of prima2's clk_mm
571 */
572#define clk_gfx2d clk_mm
573
535static struct clk_init_data clk_lcd_init = { 574static struct clk_init_data clk_lcd_init = {
536 .name = "lcd", 575 .name = "lcd",
537 .ops = &dmn_ops, 576 .ops = &dmn_ops,
@@ -569,14 +608,6 @@ static struct clk_init_data clk_mmc01_init = {
569 .num_parents = ARRAY_SIZE(dmn_clk_parents), 608 .num_parents = ARRAY_SIZE(dmn_clk_parents),
570}; 609};
571 610
572static struct clk_dmn clk_mmc01 = {
573 .regofs = SIRFSOC_CLKC_MMC_CFG,
574 .enable_bit = 59,
575 .hw = {
576 .init = &clk_mmc01_init,
577 },
578};
579
580static struct clk_init_data clk_mmc23_init = { 611static struct clk_init_data clk_mmc23_init = {
581 .name = "mmc23", 612 .name = "mmc23",
582 .ops = &dmn_ops, 613 .ops = &dmn_ops,
@@ -584,14 +615,6 @@ static struct clk_init_data clk_mmc23_init = {
584 .num_parents = ARRAY_SIZE(dmn_clk_parents), 615 .num_parents = ARRAY_SIZE(dmn_clk_parents),
585}; 616};
586 617
587static struct clk_dmn clk_mmc23 = {
588 .regofs = SIRFSOC_CLKC_MMC_CFG,
589 .enable_bit = 60,
590 .hw = {
591 .init = &clk_mmc23_init,
592 },
593};
594
595static struct clk_init_data clk_mmc45_init = { 618static struct clk_init_data clk_mmc45_init = {
596 .name = "mmc45", 619 .name = "mmc45",
597 .ops = &dmn_ops, 620 .ops = &dmn_ops,
@@ -599,14 +622,6 @@ static struct clk_init_data clk_mmc45_init = {
599 .num_parents = ARRAY_SIZE(dmn_clk_parents), 622 .num_parents = ARRAY_SIZE(dmn_clk_parents),
600}; 623};
601 624
602static struct clk_dmn clk_mmc45 = {
603 .regofs = SIRFSOC_CLKC_MMC_CFG,
604 .enable_bit = 61,
605 .hw = {
606 .init = &clk_mmc45_init,
607 },
608};
609
610/* 625/*
611 * peripheral controllers in io domain 626 * peripheral controllers in io domain
612 */ 627 */
@@ -667,6 +682,20 @@ static struct clk_ops ios_ops = {
667 .disable = std_clk_disable, 682 .disable = std_clk_disable,
668}; 683};
669 684
685static struct clk_init_data clk_cphif_init = {
686 .name = "cphif",
687 .ops = &ios_ops,
688 .parent_names = std_clk_io_parents,
689 .num_parents = ARRAY_SIZE(std_clk_io_parents),
690};
691
692static struct clk_std clk_cphif = {
693 .enable_bit = 20,
694 .hw = {
695 .init = &clk_cphif_init,
696 },
697};
698
670static struct clk_init_data clk_dmac0_init = { 699static struct clk_init_data clk_dmac0_init = {
671 .name = "dmac0", 700 .name = "dmac0",
672 .ops = &ios_ops, 701 .ops = &ios_ops,
@@ -695,20 +724,6 @@ static struct clk_std clk_dmac1 = {
695 }, 724 },
696}; 725};
697 726
698static struct clk_init_data clk_nand_init = {
699 .name = "nand",
700 .ops = &ios_ops,
701 .parent_names = std_clk_io_parents,
702 .num_parents = ARRAY_SIZE(std_clk_io_parents),
703};
704
705static struct clk_std clk_nand = {
706 .enable_bit = 34,
707 .hw = {
708 .init = &clk_nand_init,
709 },
710};
711
712static struct clk_init_data clk_audio_init = { 727static struct clk_init_data clk_audio_init = {
713 .name = "audio", 728 .name = "audio",
714 .ops = &ios_ops, 729 .ops = &ios_ops,
@@ -970,7 +985,7 @@ static const char *std_clk_sys_parents[] = {
970}; 985};
971 986
972static struct clk_init_data clk_security_init = { 987static struct clk_init_data clk_security_init = {
973 .name = "mf", 988 .name = "security",
974 .ops = &ios_ops, 989 .ops = &ios_ops,
975 .parent_names = std_clk_sys_parents, 990 .parent_names = std_clk_sys_parents,
976 .num_parents = ARRAY_SIZE(std_clk_sys_parents), 991 .num_parents = ARRAY_SIZE(std_clk_sys_parents),
@@ -1014,96 +1029,3 @@ static struct clk_std clk_usb1 = {
1014 .init = &clk_usb1_init, 1029 .init = &clk_usb1_init,
1015 }, 1030 },
1016}; 1031};
1017
1018enum prima2_clk_index {
1019 /* 0 1 2 3 4 5 6 7 8 9 */
1020 rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps,
1021 mf, io, cpu, uart0, uart1, uart2, tsc, i2c0, i2c1, spi0,
1022 spi1, pwmc, efuse, pulse, dmac0, dmac1, nand, audio, usp0, usp1,
1023 usp2, vip, gfx, mm, lcd, vpp, mmc01, mmc23, mmc45, usbpll,
1024 usb0, usb1, maxclk,
1025};
1026
1027static struct clk_hw *prima2_clk_hw_array[maxclk] __initdata = {
1028 NULL, /* dummy */
1029 NULL,
1030 &clk_pll1.hw,
1031 &clk_pll2.hw,
1032 &clk_pll3.hw,
1033 &clk_mem.hw,
1034 &clk_sys.hw,
1035 &clk_security.hw,
1036 &clk_dsp.hw,
1037 &clk_gps.hw,
1038 &clk_mf.hw,
1039 &clk_io.hw,
1040 &clk_cpu.hw,
1041 &clk_uart0.hw,
1042 &clk_uart1.hw,
1043 &clk_uart2.hw,
1044 &clk_tsc.hw,
1045 &clk_i2c0.hw,
1046 &clk_i2c1.hw,
1047 &clk_spi0.hw,
1048 &clk_spi1.hw,
1049 &clk_pwmc.hw,
1050 &clk_efuse.hw,
1051 &clk_pulse.hw,
1052 &clk_dmac0.hw,
1053 &clk_dmac1.hw,
1054 &clk_nand.hw,
1055 &clk_audio.hw,
1056 &clk_usp0.hw,
1057 &clk_usp1.hw,
1058 &clk_usp2.hw,
1059 &clk_vip.hw,
1060 &clk_gfx.hw,
1061 &clk_mm.hw,
1062 &clk_lcd.hw,
1063 &clk_vpp.hw,
1064 &clk_mmc01.hw,
1065 &clk_mmc23.hw,
1066 &clk_mmc45.hw,
1067 &usb_pll_clk_hw,
1068 &clk_usb0.hw,
1069 &clk_usb1.hw,
1070};
1071
1072static struct clk *prima2_clks[maxclk];
1073static struct clk_onecell_data clk_data;
1074
1075static void __init sirfsoc_clk_init(struct device_node *np)
1076{
1077 struct device_node *rscnp;
1078 int i;
1079
1080 rscnp = of_find_compatible_node(NULL, NULL, "sirf,prima2-rsc");
1081 sirfsoc_rsc_vbase = of_iomap(rscnp, 0);
1082 if (!sirfsoc_rsc_vbase)
1083 panic("unable to map rsc registers\n");
1084 of_node_put(rscnp);
1085
1086 sirfsoc_clk_vbase = of_iomap(np, 0);
1087 if (!sirfsoc_clk_vbase)
1088 panic("unable to map clkc registers\n");
1089
1090 /* These are always available (RTC and 26MHz OSC)*/
1091 prima2_clks[rtc] = clk_register_fixed_rate(NULL, "rtc", NULL,
1092 CLK_IS_ROOT, 32768);
1093 prima2_clks[osc]= clk_register_fixed_rate(NULL, "osc", NULL,
1094 CLK_IS_ROOT, 26000000);
1095
1096 for (i = pll1; i < maxclk; i++) {
1097 prima2_clks[i] = clk_register(NULL, prima2_clk_hw_array[i]);
1098 BUG_ON(IS_ERR(prima2_clks[i]));
1099 }
1100 clk_register_clkdev(prima2_clks[cpu], NULL, "cpu");
1101 clk_register_clkdev(prima2_clks[io], NULL, "io");
1102 clk_register_clkdev(prima2_clks[mem], NULL, "mem");
1103
1104 clk_data.clks = prima2_clks;
1105 clk_data.clk_num = maxclk;
1106
1107 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
1108}
1109CLK_OF_DECLARE(sirfsoc_clk, "sirf,prima2-clkc", sirfsoc_clk_init);
diff --git a/drivers/clk/sirf/clk-prima2.c b/drivers/clk/sirf/clk-prima2.c
new file mode 100644
index 000000000000..7adc5c70c7ff
--- /dev/null
+++ b/drivers/clk/sirf/clk-prima2.c
@@ -0,0 +1,151 @@
1/*
2 * Clock tree for CSR SiRFprimaII
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/module.h>
10#include <linux/bitops.h>
11#include <linux/io.h>
12#include <linux/clk.h>
13#include <linux/clkdev.h>
14#include <linux/clk-provider.h>
15#include <linux/of_address.h>
16#include <linux/syscore_ops.h>
17
18#include "prima2.h"
19#include "clk-common.c"
20
21static struct clk_dmn clk_mmc01 = {
22 .regofs = SIRFSOC_CLKC_MMC_CFG,
23 .enable_bit = 59,
24 .hw = {
25 .init = &clk_mmc01_init,
26 },
27};
28
29static struct clk_dmn clk_mmc23 = {
30 .regofs = SIRFSOC_CLKC_MMC_CFG,
31 .enable_bit = 60,
32 .hw = {
33 .init = &clk_mmc23_init,
34 },
35};
36
37static struct clk_dmn clk_mmc45 = {
38 .regofs = SIRFSOC_CLKC_MMC_CFG,
39 .enable_bit = 61,
40 .hw = {
41 .init = &clk_mmc45_init,
42 },
43};
44
45static struct clk_init_data clk_nand_init = {
46 .name = "nand",
47 .ops = &ios_ops,
48 .parent_names = std_clk_io_parents,
49 .num_parents = ARRAY_SIZE(std_clk_io_parents),
50};
51
52static struct clk_std clk_nand = {
53 .enable_bit = 34,
54 .hw = {
55 .init = &clk_nand_init,
56 },
57};
58
59enum prima2_clk_index {
60 /* 0 1 2 3 4 5 6 7 8 9 */
61 rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps,
62 mf, io, cpu, uart0, uart1, uart2, tsc, i2c0, i2c1, spi0,
63 spi1, pwmc, efuse, pulse, dmac0, dmac1, nand, audio, usp0, usp1,
64 usp2, vip, gfx, mm, lcd, vpp, mmc01, mmc23, mmc45, usbpll,
65 usb0, usb1, cphif, maxclk,
66};
67
68static __initdata struct clk_hw *prima2_clk_hw_array[maxclk] = {
69 NULL, /* dummy */
70 NULL,
71 &clk_pll1.hw,
72 &clk_pll2.hw,
73 &clk_pll3.hw,
74 &clk_mem.hw,
75 &clk_sys.hw,
76 &clk_security.hw,
77 &clk_dsp.hw,
78 &clk_gps.hw,
79 &clk_mf.hw,
80 &clk_io.hw,
81 &clk_cpu.hw,
82 &clk_uart0.hw,
83 &clk_uart1.hw,
84 &clk_uart2.hw,
85 &clk_tsc.hw,
86 &clk_i2c0.hw,
87 &clk_i2c1.hw,
88 &clk_spi0.hw,
89 &clk_spi1.hw,
90 &clk_pwmc.hw,
91 &clk_efuse.hw,
92 &clk_pulse.hw,
93 &clk_dmac0.hw,
94 &clk_dmac1.hw,
95 &clk_nand.hw,
96 &clk_audio.hw,
97 &clk_usp0.hw,
98 &clk_usp1.hw,
99 &clk_usp2.hw,
100 &clk_vip.hw,
101 &clk_gfx.hw,
102 &clk_mm.hw,
103 &clk_lcd.hw,
104 &clk_vpp.hw,
105 &clk_mmc01.hw,
106 &clk_mmc23.hw,
107 &clk_mmc45.hw,
108 &usb_pll_clk_hw,
109 &clk_usb0.hw,
110 &clk_usb1.hw,
111 &clk_cphif.hw,
112};
113
114static struct clk *prima2_clks[maxclk];
115
116static void __init prima2_clk_init(struct device_node *np)
117{
118 struct device_node *rscnp;
119 int i;
120
121 rscnp = of_find_compatible_node(NULL, NULL, "sirf,prima2-rsc");
122 sirfsoc_rsc_vbase = of_iomap(rscnp, 0);
123 if (!sirfsoc_rsc_vbase)
124 panic("unable to map rsc registers\n");
125 of_node_put(rscnp);
126
127 sirfsoc_clk_vbase = of_iomap(np, 0);
128 if (!sirfsoc_clk_vbase)
129 panic("unable to map clkc registers\n");
130
131 /* These are always available (RTC and 26MHz OSC)*/
132 prima2_clks[rtc] = clk_register_fixed_rate(NULL, "rtc", NULL,
133 CLK_IS_ROOT, 32768);
134 prima2_clks[osc] = clk_register_fixed_rate(NULL, "osc", NULL,
135 CLK_IS_ROOT, 26000000);
136
137 for (i = pll1; i < maxclk; i++) {
138 prima2_clks[i] = clk_register(NULL, prima2_clk_hw_array[i]);
139 BUG_ON(!prima2_clks[i]);
140 }
141 clk_register_clkdev(prima2_clks[cpu], NULL, "cpu");
142 clk_register_clkdev(prima2_clks[io], NULL, "io");
143 clk_register_clkdev(prima2_clks[mem], NULL, "mem");
144 clk_register_clkdev(prima2_clks[mem], NULL, "osc");
145
146 clk_data.clks = prima2_clks;
147 clk_data.clk_num = maxclk;
148
149 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
150}
151CLK_OF_DECLARE(prima2_clk, "sirf,prima2-clkc", prima2_clk_init);
diff --git a/drivers/clk/sirf/prima2.h b/drivers/clk/sirf/prima2.h
new file mode 100644
index 000000000000..01bc3854a058
--- /dev/null
+++ b/drivers/clk/sirf/prima2.h
@@ -0,0 +1,25 @@
1#define SIRFSOC_CLKC_CLK_EN0 0x0000
2#define SIRFSOC_CLKC_CLK_EN1 0x0004
3#define SIRFSOC_CLKC_REF_CFG 0x0014
4#define SIRFSOC_CLKC_CPU_CFG 0x0018
5#define SIRFSOC_CLKC_MEM_CFG 0x001c
6#define SIRFSOC_CLKC_SYS_CFG 0x0020
7#define SIRFSOC_CLKC_IO_CFG 0x0024
8#define SIRFSOC_CLKC_DSP_CFG 0x0028
9#define SIRFSOC_CLKC_GFX_CFG 0x002c
10#define SIRFSOC_CLKC_MM_CFG 0x0030
11#define SIRFSOC_CLKC_LCD_CFG 0x0034
12#define SIRFSOC_CLKC_MMC_CFG 0x0038
13#define SIRFSOC_CLKC_PLL1_CFG0 0x0040
14#define SIRFSOC_CLKC_PLL2_CFG0 0x0044
15#define SIRFSOC_CLKC_PLL3_CFG0 0x0048
16#define SIRFSOC_CLKC_PLL1_CFG1 0x004c
17#define SIRFSOC_CLKC_PLL2_CFG1 0x0050
18#define SIRFSOC_CLKC_PLL3_CFG1 0x0054
19#define SIRFSOC_CLKC_PLL1_CFG2 0x0058
20#define SIRFSOC_CLKC_PLL2_CFG2 0x005c
21#define SIRFSOC_CLKC_PLL3_CFG2 0x0060
22#define SIRFSOC_USBPHY_PLL_CTRL 0x0008
23#define SIRFSOC_USBPHY_PLL_POWERDOWN BIT(1)
24#define SIRFSOC_USBPHY_PLL_BYPASS BIT(2)
25#define SIRFSOC_USBPHY_PLL_LOCK BIT(3)
diff --git a/drivers/clk/socfpga/clk.c b/drivers/clk/socfpga/clk.c
index 81dd31a686df..5983a26a8c5f 100644
--- a/drivers/clk/socfpga/clk.c
+++ b/drivers/clk/socfpga/clk.c
@@ -121,9 +121,7 @@ static __init struct clk *socfpga_clk_init(struct device_node *node,
121 int rc; 121 int rc;
122 u32 fixed_div; 122 u32 fixed_div;
123 123
124 rc = of_property_read_u32(node, "reg", &reg); 124 of_property_read_u32(node, "reg", &reg);
125 if (WARN_ON(rc))
126 return NULL;
127 125
128 socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL); 126 socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
129 if (WARN_ON(!socfpga_clk)) 127 if (WARN_ON(!socfpga_clk))
@@ -292,7 +290,7 @@ static void __init socfpga_gate_clk_init(struct device_node *node,
292 socfpga_clk->shift = div_reg[1]; 290 socfpga_clk->shift = div_reg[1];
293 socfpga_clk->width = div_reg[2]; 291 socfpga_clk->width = div_reg[2];
294 } else { 292 } else {
295 socfpga_clk->div_reg = 0; 293 socfpga_clk->div_reg = NULL;
296 } 294 }
297 295
298 of_property_read_string(node, "clock-output-names", &clk_name); 296 of_property_read_string(node, "clock-output-names", &clk_name);
diff --git a/drivers/clk/spear/clk-frac-synth.c b/drivers/clk/spear/clk-frac-synth.c
index 958aa3ad1d60..dffd4ce6c8b5 100644
--- a/drivers/clk/spear/clk-frac-synth.c
+++ b/drivers/clk/spear/clk-frac-synth.c
@@ -116,7 +116,7 @@ static int clk_frac_set_rate(struct clk_hw *hw, unsigned long drate,
116 return 0; 116 return 0;
117} 117}
118 118
119struct clk_ops clk_frac_ops = { 119static struct clk_ops clk_frac_ops = {
120 .recalc_rate = clk_frac_recalc_rate, 120 .recalc_rate = clk_frac_recalc_rate,
121 .round_rate = clk_frac_round_rate, 121 .round_rate = clk_frac_round_rate,
122 .set_rate = clk_frac_set_rate, 122 .set_rate = clk_frac_set_rate,
diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c
index 88523f91d9b7..9e232644f07e 100644
--- a/drivers/clk/sunxi/clk-factors.c
+++ b/drivers/clk/sunxi/clk-factors.c
@@ -30,17 +30,9 @@
30 * parent - fixed parent. No clk_set_parent support 30 * parent - fixed parent. No clk_set_parent support
31 */ 31 */
32 32
33struct clk_factors {
34 struct clk_hw hw;
35 void __iomem *reg;
36 struct clk_factors_config *config;
37 void (*get_factors) (u32 *rate, u32 parent, u8 *n, u8 *k, u8 *m, u8 *p);
38 spinlock_t *lock;
39};
40
41#define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw) 33#define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
42 34
43#define SETMASK(len, pos) (((-1U) >> (31-len)) << (pos)) 35#define SETMASK(len, pos) (((1U << (len)) - 1) << (pos))
44#define CLRMASK(len, pos) (~(SETMASK(len, pos))) 36#define CLRMASK(len, pos) (~(SETMASK(len, pos)))
45#define FACTOR_GET(bit, len, reg) (((reg) & SETMASK(len, bit)) >> (bit)) 37#define FACTOR_GET(bit, len, reg) (((reg) & SETMASK(len, bit)) >> (bit))
46 38
@@ -88,7 +80,7 @@ static long clk_factors_round_rate(struct clk_hw *hw, unsigned long rate,
88static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate, 80static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate,
89 unsigned long parent_rate) 81 unsigned long parent_rate)
90{ 82{
91 u8 n, k, m, p; 83 u8 n = 0, k = 0, m = 0, p = 0;
92 u32 reg; 84 u32 reg;
93 struct clk_factors *factors = to_clk_factors(hw); 85 struct clk_factors *factors = to_clk_factors(hw);
94 struct clk_factors_config *config = factors->config; 86 struct clk_factors_config *config = factors->config;
@@ -120,61 +112,8 @@ static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate,
120 return 0; 112 return 0;
121} 113}
122 114
123static const struct clk_ops clk_factors_ops = { 115const struct clk_ops clk_factors_ops = {
124 .recalc_rate = clk_factors_recalc_rate, 116 .recalc_rate = clk_factors_recalc_rate,
125 .round_rate = clk_factors_round_rate, 117 .round_rate = clk_factors_round_rate,
126 .set_rate = clk_factors_set_rate, 118 .set_rate = clk_factors_set_rate,
127}; 119};
128
129/**
130 * clk_register_factors - register a factors clock with
131 * the clock framework
132 * @dev: device registering this clock
133 * @name: name of this clock
134 * @parent_name: name of clock's parent
135 * @flags: framework-specific flags
136 * @reg: register address to adjust factors
137 * @config: shift and width of factors n, k, m and p
138 * @get_factors: function to calculate the factors for a given frequency
139 * @lock: shared register lock for this clock
140 */
141struct clk *clk_register_factors(struct device *dev, const char *name,
142 const char *parent_name,
143 unsigned long flags, void __iomem *reg,
144 struct clk_factors_config *config,
145 void (*get_factors)(u32 *rate, u32 parent,
146 u8 *n, u8 *k, u8 *m, u8 *p),
147 spinlock_t *lock)
148{
149 struct clk_factors *factors;
150 struct clk *clk;
151 struct clk_init_data init;
152
153 /* allocate the factors */
154 factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
155 if (!factors) {
156 pr_err("%s: could not allocate factors clk\n", __func__);
157 return ERR_PTR(-ENOMEM);
158 }
159
160 init.name = name;
161 init.ops = &clk_factors_ops;
162 init.flags = flags;
163 init.parent_names = (parent_name ? &parent_name : NULL);
164 init.num_parents = (parent_name ? 1 : 0);
165
166 /* struct clk_factors assignments */
167 factors->reg = reg;
168 factors->config = config;
169 factors->lock = lock;
170 factors->hw.init = &init;
171 factors->get_factors = get_factors;
172
173 /* register the clock */
174 clk = clk_register(dev, &factors->hw);
175
176 if (IS_ERR(clk))
177 kfree(factors);
178
179 return clk;
180}
diff --git a/drivers/clk/sunxi/clk-factors.h b/drivers/clk/sunxi/clk-factors.h
index f49851cc4380..02e1a43ebac7 100644
--- a/drivers/clk/sunxi/clk-factors.h
+++ b/drivers/clk/sunxi/clk-factors.h
@@ -17,11 +17,13 @@ struct clk_factors_config {
17 u8 pwidth; 17 u8 pwidth;
18}; 18};
19 19
20struct clk *clk_register_factors(struct device *dev, const char *name, 20struct clk_factors {
21 const char *parent_name, 21 struct clk_hw hw;
22 unsigned long flags, void __iomem *reg, 22 void __iomem *reg;
23 struct clk_factors_config *config, 23 struct clk_factors_config *config;
24 void (*get_factors) (u32 *rate, u32 parent_rate, 24 void (*get_factors) (u32 *rate, u32 parent, u8 *n, u8 *k, u8 *m, u8 *p);
25 u8 *n, u8 *k, u8 *m, u8 *p), 25 spinlock_t *lock;
26 spinlock_t *lock); 26};
27
28extern const struct clk_ops clk_factors_ops;
27#endif 29#endif
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 9bbd03514540..659e4ea31893 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -23,6 +23,9 @@
23 23
24static DEFINE_SPINLOCK(clk_lock); 24static DEFINE_SPINLOCK(clk_lock);
25 25
26/* Maximum number of parents our clocks have */
27#define SUNXI_MAX_PARENTS 5
28
26/** 29/**
27 * sun4i_osc_clk_setup() - Setup function for gatable oscillator 30 * sun4i_osc_clk_setup() - Setup function for gatable oscillator
28 */ 31 */
@@ -37,18 +40,16 @@ static void __init sun4i_osc_clk_setup(struct device_node *node)
37 const char *clk_name = node->name; 40 const char *clk_name = node->name;
38 u32 rate; 41 u32 rate;
39 42
43 if (of_property_read_u32(node, "clock-frequency", &rate))
44 return;
45
40 /* allocate fixed-rate and gate clock structs */ 46 /* allocate fixed-rate and gate clock structs */
41 fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL); 47 fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
42 if (!fixed) 48 if (!fixed)
43 return; 49 return;
44 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); 50 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
45 if (!gate) { 51 if (!gate)
46 kfree(fixed); 52 goto err_free_fixed;
47 return;
48 }
49
50 if (of_property_read_u32(node, "clock-frequency", &rate))
51 return;
52 53
53 /* set up gate and fixed rate properties */ 54 /* set up gate and fixed rate properties */
54 gate->reg = of_iomap(node, 0); 55 gate->reg = of_iomap(node, 0);
@@ -63,10 +64,18 @@ static void __init sun4i_osc_clk_setup(struct device_node *node)
63 &gate->hw, &clk_gate_ops, 64 &gate->hw, &clk_gate_ops,
64 CLK_IS_ROOT); 65 CLK_IS_ROOT);
65 66
66 if (!IS_ERR(clk)) { 67 if (IS_ERR(clk))
67 of_clk_add_provider(node, of_clk_src_simple_get, clk); 68 goto err_free_gate;
68 clk_register_clkdev(clk, clk_name, NULL); 69
69 } 70 of_clk_add_provider(node, of_clk_src_simple_get, clk);
71 clk_register_clkdev(clk, clk_name, NULL);
72
73 return;
74
75err_free_gate:
76 kfree(gate);
77err_free_fixed:
78 kfree(fixed);
70} 79}
71CLK_OF_DECLARE(sun4i_osc, "allwinner,sun4i-osc-clk", sun4i_osc_clk_setup); 80CLK_OF_DECLARE(sun4i_osc, "allwinner,sun4i-osc-clk", sun4i_osc_clk_setup);
72 81
@@ -209,6 +218,40 @@ static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate,
209} 218}
210 219
211/** 220/**
221 * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
222 * PLL5 rate is calculated as follows
223 * rate = parent_rate * n * (k + 1)
224 * parent_rate is always 24Mhz
225 */
226
227static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate,
228 u8 *n, u8 *k, u8 *m, u8 *p)
229{
230 u8 div;
231
232 /* Normalize value to a parent_rate multiple (24M) */
233 div = *freq / parent_rate;
234 *freq = parent_rate * div;
235
236 /* we were called to round the frequency, we can now return */
237 if (n == NULL)
238 return;
239
240 if (div < 31)
241 *k = 0;
242 else if (div / 2 < 31)
243 *k = 1;
244 else if (div / 3 < 31)
245 *k = 2;
246 else
247 *k = 3;
248
249 *n = DIV_ROUND_UP(div, (*k+1));
250}
251
252
253
254/**
212 * sun4i_get_apb1_factors() - calculates m, p factors for APB1 255 * sun4i_get_apb1_factors() - calculates m, p factors for APB1
213 * APB1 rate is calculated as follows 256 * APB1 rate is calculated as follows
214 * rate = (parent_rate >> p) / (m + 1); 257 * rate = (parent_rate >> p) / (m + 1);
@@ -252,10 +295,96 @@ static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate,
252 295
253 296
254/** 297/**
298 * sun4i_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
299 * MMC rate is calculated as follows
300 * rate = (parent_rate >> p) / (m + 1);
301 */
302
303static void sun4i_get_mod0_factors(u32 *freq, u32 parent_rate,
304 u8 *n, u8 *k, u8 *m, u8 *p)
305{
306 u8 div, calcm, calcp;
307
308 /* These clocks can only divide, so we will never be able to achieve
309 * frequencies higher than the parent frequency */
310 if (*freq > parent_rate)
311 *freq = parent_rate;
312
313 div = parent_rate / *freq;
314
315 if (div < 16)
316 calcp = 0;
317 else if (div / 2 < 16)
318 calcp = 1;
319 else if (div / 4 < 16)
320 calcp = 2;
321 else
322 calcp = 3;
323
324 calcm = DIV_ROUND_UP(div, 1 << calcp);
325
326 *freq = (parent_rate >> calcp) / calcm;
327
328 /* we were called to round the frequency, we can now return */
329 if (n == NULL)
330 return;
331
332 *m = calcm - 1;
333 *p = calcp;
334}
335
336
337
338/**
339 * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
340 * CLK_OUT rate is calculated as follows
341 * rate = (parent_rate >> p) / (m + 1);
342 */
343
344static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
345 u8 *n, u8 *k, u8 *m, u8 *p)
346{
347 u8 div, calcm, calcp;
348
349 /* These clocks can only divide, so we will never be able to achieve
350 * frequencies higher than the parent frequency */
351 if (*freq > parent_rate)
352 *freq = parent_rate;
353
354 div = parent_rate / *freq;
355
356 if (div < 32)
357 calcp = 0;
358 else if (div / 2 < 32)
359 calcp = 1;
360 else if (div / 4 < 32)
361 calcp = 2;
362 else
363 calcp = 3;
364
365 calcm = DIV_ROUND_UP(div, 1 << calcp);
366
367 *freq = (parent_rate >> calcp) / calcm;
368
369 /* we were called to round the frequency, we can now return */
370 if (n == NULL)
371 return;
372
373 *m = calcm - 1;
374 *p = calcp;
375}
376
377
378
379/**
255 * sunxi_factors_clk_setup() - Setup function for factor clocks 380 * sunxi_factors_clk_setup() - Setup function for factor clocks
256 */ 381 */
257 382
383#define SUNXI_FACTORS_MUX_MASK 0x3
384
258struct factors_data { 385struct factors_data {
386 int enable;
387 int mux;
259 struct clk_factors_config *table; 388 struct clk_factors_config *table;
260 void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p); 389 void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p);
261}; 390};
@@ -280,6 +409,13 @@ static struct clk_factors_config sun6i_a31_pll1_config = {
280 .mwidth = 2, 409 .mwidth = 2,
281}; 410};
282 411
412static struct clk_factors_config sun4i_pll5_config = {
413 .nshift = 8,
414 .nwidth = 5,
415 .kshift = 4,
416 .kwidth = 2,
417};
418
283static struct clk_factors_config sun4i_apb1_config = { 419static struct clk_factors_config sun4i_apb1_config = {
284 .mshift = 0, 420 .mshift = 0,
285 .mwidth = 5, 421 .mwidth = 5,
@@ -287,40 +423,143 @@ static struct clk_factors_config sun4i_apb1_config = {
287 .pwidth = 2, 423 .pwidth = 2,
288}; 424};
289 425
426/* user manual says "n" but it's really "p" */
427static struct clk_factors_config sun4i_mod0_config = {
428 .mshift = 0,
429 .mwidth = 4,
430 .pshift = 16,
431 .pwidth = 2,
432};
433
434/* user manual says "n" but it's really "p" */
435static struct clk_factors_config sun7i_a20_out_config = {
436 .mshift = 8,
437 .mwidth = 5,
438 .pshift = 20,
439 .pwidth = 2,
440};
441
290static const struct factors_data sun4i_pll1_data __initconst = { 442static const struct factors_data sun4i_pll1_data __initconst = {
443 .enable = 31,
291 .table = &sun4i_pll1_config, 444 .table = &sun4i_pll1_config,
292 .getter = sun4i_get_pll1_factors, 445 .getter = sun4i_get_pll1_factors,
293}; 446};
294 447
295static const struct factors_data sun6i_a31_pll1_data __initconst = { 448static const struct factors_data sun6i_a31_pll1_data __initconst = {
449 .enable = 31,
296 .table = &sun6i_a31_pll1_config, 450 .table = &sun6i_a31_pll1_config,
297 .getter = sun6i_a31_get_pll1_factors, 451 .getter = sun6i_a31_get_pll1_factors,
298}; 452};
299 453
454static const struct factors_data sun4i_pll5_data __initconst = {
455 .enable = 31,
456 .table = &sun4i_pll5_config,
457 .getter = sun4i_get_pll5_factors,
458};
459
300static const struct factors_data sun4i_apb1_data __initconst = { 460static const struct factors_data sun4i_apb1_data __initconst = {
301 .table = &sun4i_apb1_config, 461 .table = &sun4i_apb1_config,
302 .getter = sun4i_get_apb1_factors, 462 .getter = sun4i_get_apb1_factors,
303}; 463};
304 464
305static void __init sunxi_factors_clk_setup(struct device_node *node, 465static const struct factors_data sun4i_mod0_data __initconst = {
306 struct factors_data *data) 466 .enable = 31,
467 .mux = 24,
468 .table = &sun4i_mod0_config,
469 .getter = sun4i_get_mod0_factors,
470};
471
472static const struct factors_data sun7i_a20_out_data __initconst = {
473 .enable = 31,
474 .mux = 24,
475 .table = &sun7i_a20_out_config,
476 .getter = sun7i_a20_get_out_factors,
477};
478
479static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
480 const struct factors_data *data)
307{ 481{
308 struct clk *clk; 482 struct clk *clk;
483 struct clk_factors *factors;
484 struct clk_gate *gate = NULL;
485 struct clk_mux *mux = NULL;
486 struct clk_hw *gate_hw = NULL;
487 struct clk_hw *mux_hw = NULL;
309 const char *clk_name = node->name; 488 const char *clk_name = node->name;
310 const char *parent; 489 const char *parents[SUNXI_MAX_PARENTS];
311 void *reg; 490 void *reg;
491 int i = 0;
312 492
313 reg = of_iomap(node, 0); 493 reg = of_iomap(node, 0);
314 494
315 parent = of_clk_get_parent_name(node, 0); 495 /* if we have a mux, we will have >1 parents */
496 while (i < SUNXI_MAX_PARENTS &&
497 (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
498 i++;
499
500 /* Nodes should be providing the name via clock-output-names
501 * but originally our dts didn't, and so we used node->name.
502 * The new, better nodes look like clk@deadbeef, so we pull the
503 * name just in this case */
504 if (!strcmp("clk", clk_name)) {
505 of_property_read_string_index(node, "clock-output-names",
506 0, &clk_name);
507 }
508
509 factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
510 if (!factors)
511 return NULL;
512
513 /* Add a gate if this factor clock can be gated */
514 if (data->enable) {
515 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
516 if (!gate) {
517 kfree(factors);
518 return NULL;
519 }
520
521 /* set up gate properties */
522 gate->reg = reg;
523 gate->bit_idx = data->enable;
524 gate->lock = &clk_lock;
525 gate_hw = &gate->hw;
526 }
527
528 /* Add a mux if this factor clock can be muxed */
529 if (data->mux) {
530 mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
531 if (!mux) {
532 kfree(factors);
533 kfree(gate);
534 return NULL;
535 }
536
537 /* set up gate properties */
538 mux->reg = reg;
539 mux->shift = data->mux;
540 mux->mask = SUNXI_FACTORS_MUX_MASK;
541 mux->lock = &clk_lock;
542 mux_hw = &mux->hw;
543 }
316 544
317 clk = clk_register_factors(NULL, clk_name, parent, 0, reg, 545 /* set up factors properties */
318 data->table, data->getter, &clk_lock); 546 factors->reg = reg;
547 factors->config = data->table;
548 factors->get_factors = data->getter;
549 factors->lock = &clk_lock;
550
551 clk = clk_register_composite(NULL, clk_name,
552 parents, i,
553 mux_hw, &clk_mux_ops,
554 &factors->hw, &clk_factors_ops,
555 gate_hw, &clk_gate_ops, 0);
319 556
320 if (!IS_ERR(clk)) { 557 if (!IS_ERR(clk)) {
321 of_clk_add_provider(node, of_clk_src_simple_get, clk); 558 of_clk_add_provider(node, of_clk_src_simple_get, clk);
322 clk_register_clkdev(clk, clk_name, NULL); 559 clk_register_clkdev(clk, clk_name, NULL);
323 } 560 }
561
562 return clk;
324} 563}
325 564
326 565
@@ -352,13 +591,14 @@ static void __init sunxi_mux_clk_setup(struct device_node *node,
352{ 591{
353 struct clk *clk; 592 struct clk *clk;
354 const char *clk_name = node->name; 593 const char *clk_name = node->name;
355 const char *parents[5]; 594 const char *parents[SUNXI_MAX_PARENTS];
356 void *reg; 595 void *reg;
357 int i = 0; 596 int i = 0;
358 597
359 reg = of_iomap(node, 0); 598 reg = of_iomap(node, 0);
360 599
361 while (i < 5 && (parents[i] = of_clk_get_parent_name(node, i)) != NULL) 600 while (i < SUNXI_MAX_PARENTS &&
601 (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
362 i++; 602 i++;
363 603
364 clk = clk_register_mux(NULL, clk_name, parents, i, 604 clk = clk_register_mux(NULL, clk_name, parents, i,
@@ -555,11 +795,186 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
555 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 795 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
556} 796}
557 797
798
799
800/**
801 * sunxi_divs_clk_setup() helper data
802 */
803
804#define SUNXI_DIVS_MAX_QTY 2
805#define SUNXI_DIVISOR_WIDTH 2
806
807struct divs_data {
808 const struct factors_data *factors; /* data for the factor clock */
809 struct {
810 u8 fixed; /* is it a fixed divisor? if not... */
811 struct clk_div_table *table; /* is it a table based divisor? */
812 u8 shift; /* otherwise it's a normal divisor with this shift */
813 u8 pow; /* is it power-of-two based? */
814 u8 gate; /* is it independently gateable? */
815 } div[SUNXI_DIVS_MAX_QTY];
816};
817
818static struct clk_div_table pll6_sata_tbl[] = {
819 { .val = 0, .div = 6, },
820 { .val = 1, .div = 12, },
821 { .val = 2, .div = 18, },
822 { .val = 3, .div = 24, },
823 { } /* sentinel */
824};
825
826static const struct divs_data pll5_divs_data __initconst = {
827 .factors = &sun4i_pll5_data,
828 .div = {
829 { .shift = 0, .pow = 0, }, /* M, DDR */
830 { .shift = 16, .pow = 1, }, /* P, other */
831 }
832};
833
834static const struct divs_data pll6_divs_data __initconst = {
835 .factors = &sun4i_pll5_data,
836 .div = {
837 { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
838 { .fixed = 2 }, /* P, other */
839 }
840};
841
842/**
843 * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
844 *
845 * These clocks look something like this
846 * ________________________
847 * | ___divisor 1---|----> to consumer
848 * parent >--| pll___/___divisor 2---|----> to consumer
849 * | \_______________|____> to consumer
850 * |________________________|
851 */
852
853static void __init sunxi_divs_clk_setup(struct device_node *node,
854 struct divs_data *data)
855{
856 struct clk_onecell_data *clk_data;
857 const char *parent = node->name;
858 const char *clk_name;
859 struct clk **clks, *pclk;
860 struct clk_hw *gate_hw, *rate_hw;
861 const struct clk_ops *rate_ops;
862 struct clk_gate *gate = NULL;
863 struct clk_fixed_factor *fix_factor;
864 struct clk_divider *divider;
865 void *reg;
866 int i = 0;
867 int flags, clkflags;
868
869 /* Set up factor clock that we will be dividing */
870 pclk = sunxi_factors_clk_setup(node, data->factors);
871
872 reg = of_iomap(node, 0);
873
874 clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
875 if (!clk_data)
876 return;
877
878 clks = kzalloc(SUNXI_DIVS_MAX_QTY * sizeof(struct clk *), GFP_KERNEL);
879 if (!clks)
880 goto free_clkdata;
881
882 clk_data->clks = clks;
883
884 /* It's not a good idea to have automatic reparenting changing
885 * our RAM clock! */
886 clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
887
888 for (i = 0; i < SUNXI_DIVS_MAX_QTY; i++) {
889 if (of_property_read_string_index(node, "clock-output-names",
890 i, &clk_name) != 0)
891 break;
892
893 gate_hw = NULL;
894 rate_hw = NULL;
895 rate_ops = NULL;
896
897 /* If this leaf clock can be gated, create a gate */
898 if (data->div[i].gate) {
899 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
900 if (!gate)
901 goto free_clks;
902
903 gate->reg = reg;
904 gate->bit_idx = data->div[i].gate;
905 gate->lock = &clk_lock;
906
907 gate_hw = &gate->hw;
908 }
909
910 /* Leaves can be fixed or configurable divisors */
911 if (data->div[i].fixed) {
912 fix_factor = kzalloc(sizeof(*fix_factor), GFP_KERNEL);
913 if (!fix_factor)
914 goto free_gate;
915
916 fix_factor->mult = 1;
917 fix_factor->div = data->div[i].fixed;
918
919 rate_hw = &fix_factor->hw;
920 rate_ops = &clk_fixed_factor_ops;
921 } else {
922 divider = kzalloc(sizeof(*divider), GFP_KERNEL);
923 if (!divider)
924 goto free_gate;
925
926 flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0;
927
928 divider->reg = reg;
929 divider->shift = data->div[i].shift;
930 divider->width = SUNXI_DIVISOR_WIDTH;
931 divider->flags = flags;
932 divider->lock = &clk_lock;
933 divider->table = data->div[i].table;
934
935 rate_hw = &divider->hw;
936 rate_ops = &clk_divider_ops;
937 }
938
939 /* Wrap the (potential) gate and the divisor on a composite
940 * clock to unify them */
941 clks[i] = clk_register_composite(NULL, clk_name, &parent, 1,
942 NULL, NULL,
943 rate_hw, rate_ops,
944 gate_hw, &clk_gate_ops,
945 clkflags);
946
947 WARN_ON(IS_ERR(clk_data->clks[i]));
948 clk_register_clkdev(clks[i], clk_name, NULL);
949 }
950
951 /* The last clock available on the getter is the parent */
952 clks[i++] = pclk;
953
954 /* Adjust to the real max */
955 clk_data->clk_num = i;
956
957 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
958
959 return;
960
961free_gate:
962 kfree(gate);
963free_clks:
964 kfree(clks);
965free_clkdata:
966 kfree(clk_data);
967}
968
969
970
558/* Matches for factors clocks */ 971/* Matches for factors clocks */
559static const struct of_device_id clk_factors_match[] __initconst = { 972static const struct of_device_id clk_factors_match[] __initconst = {
560 {.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,}, 973 {.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,},
561 {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,}, 974 {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
562 {.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,}, 975 {.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
976 {.compatible = "allwinner,sun4i-mod0-clk", .data = &sun4i_mod0_data,},
977 {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
563 {} 978 {}
564}; 979};
565 980
@@ -572,6 +987,13 @@ static const struct of_device_id clk_div_match[] __initconst = {
572 {} 987 {}
573}; 988};
574 989
990/* Matches for divided outputs */
991static const struct of_device_id clk_divs_match[] __initconst = {
992 {.compatible = "allwinner,sun4i-pll5-clk", .data = &pll5_divs_data,},
993 {.compatible = "allwinner,sun4i-pll6-clk", .data = &pll6_divs_data,},
994 {}
995};
996
575/* Matches for mux clocks */ 997/* Matches for mux clocks */
576static const struct of_device_id clk_mux_match[] __initconst = { 998static const struct of_device_id clk_mux_match[] __initconst = {
577 {.compatible = "allwinner,sun4i-cpu-clk", .data = &sun4i_cpu_mux_data,}, 999 {.compatible = "allwinner,sun4i-cpu-clk", .data = &sun4i_cpu_mux_data,},
@@ -616,7 +1038,32 @@ static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_mat
616 } 1038 }
617} 1039}
618 1040
619static void __init sunxi_init_clocks(struct device_node *np) 1041/**
1042 * System clock protection
1043 *
1044 * By enabling these critical clocks, we prevent their accidental gating
1045 * by the framework
1046 */
1047static void __init sunxi_clock_protect(void)
1048{
1049 struct clk *clk;
1050
1051 /* memory bus clock - sun5i+ */
1052 clk = clk_get(NULL, "mbus");
1053 if (!IS_ERR(clk)) {
1054 clk_prepare_enable(clk);
1055 clk_put(clk);
1056 }
1057
1058 /* DDR clock - sun4i+ */
1059 clk = clk_get(NULL, "pll5_ddr");
1060 if (!IS_ERR(clk)) {
1061 clk_prepare_enable(clk);
1062 clk_put(clk);
1063 }
1064}
1065
1066static void __init sunxi_init_clocks(void)
620{ 1067{
621 /* Register factor clocks */ 1068 /* Register factor clocks */
622 of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup); 1069 of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup);
@@ -624,11 +1071,17 @@ static void __init sunxi_init_clocks(struct device_node *np)
624 /* Register divider clocks */ 1071 /* Register divider clocks */
625 of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup); 1072 of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup);
626 1073
1074 /* Register divided output clocks */
1075 of_sunxi_table_clock_setup(clk_divs_match, sunxi_divs_clk_setup);
1076
627 /* Register mux clocks */ 1077 /* Register mux clocks */
628 of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup); 1078 of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
629 1079
630 /* Register gate clocks */ 1080 /* Register gate clocks */
631 of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup); 1081 of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
1082
1083 /* Enable core system clocks */
1084 sunxi_clock_protect();
632} 1085}
633CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sunxi_init_clocks); 1086CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sunxi_init_clocks);
634CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sunxi_init_clocks); 1087CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sunxi_init_clocks);
diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
index f49fac2d193a..f7dfb72884a4 100644
--- a/drivers/clk/tegra/Makefile
+++ b/drivers/clk/tegra/Makefile
@@ -6,7 +6,12 @@ obj-y += clk-periph-gate.o
6obj-y += clk-pll.o 6obj-y += clk-pll.o
7obj-y += clk-pll-out.o 7obj-y += clk-pll-out.o
8obj-y += clk-super.o 8obj-y += clk-super.o
9 9obj-y += clk-tegra-audio.o
10obj-y += clk-tegra-periph.o
11obj-y += clk-tegra-pmc.o
12obj-y += clk-tegra-fixed.o
13obj-y += clk-tegra-super-gen4.o
10obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o 14obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o
11obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o 15obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o
12obj-$(CONFIG_ARCH_TEGRA_114_SOC) += clk-tegra114.o 16obj-$(CONFIG_ARCH_TEGRA_114_SOC) += clk-tegra114.o
17obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124.o
diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h
new file mode 100644
index 000000000000..cf0c323f2c36
--- /dev/null
+++ b/drivers/clk/tegra/clk-id.h
@@ -0,0 +1,235 @@
1/*
2 * This header provides IDs for clocks common between several Tegra SoCs
3 */
4#ifndef _TEGRA_CLK_ID_H
5#define _TEGRA_CLK_ID_H
6
7enum clk_id {
8 tegra_clk_actmon,
9 tegra_clk_adx,
10 tegra_clk_adx1,
11 tegra_clk_afi,
12 tegra_clk_amx,
13 tegra_clk_amx1,
14 tegra_clk_apbdma,
15 tegra_clk_apbif,
16 tegra_clk_audio0,
17 tegra_clk_audio0_2x,
18 tegra_clk_audio0_mux,
19 tegra_clk_audio1,
20 tegra_clk_audio1_2x,
21 tegra_clk_audio1_mux,
22 tegra_clk_audio2,
23 tegra_clk_audio2_2x,
24 tegra_clk_audio2_mux,
25 tegra_clk_audio3,
26 tegra_clk_audio3_2x,
27 tegra_clk_audio3_mux,
28 tegra_clk_audio4,
29 tegra_clk_audio4_2x,
30 tegra_clk_audio4_mux,
31 tegra_clk_blink,
32 tegra_clk_bsea,
33 tegra_clk_bsev,
34 tegra_clk_cclk_g,
35 tegra_clk_cclk_lp,
36 tegra_clk_cilab,
37 tegra_clk_cilcd,
38 tegra_clk_cile,
39 tegra_clk_clk_32k,
40 tegra_clk_clk72Mhz,
41 tegra_clk_clk_m,
42 tegra_clk_clk_m_div2,
43 tegra_clk_clk_m_div4,
44 tegra_clk_clk_out_1,
45 tegra_clk_clk_out_1_mux,
46 tegra_clk_clk_out_2,
47 tegra_clk_clk_out_2_mux,
48 tegra_clk_clk_out_3,
49 tegra_clk_clk_out_3_mux,
50 tegra_clk_cml0,
51 tegra_clk_cml1,
52 tegra_clk_csi,
53 tegra_clk_csite,
54 tegra_clk_csus,
55 tegra_clk_cve,
56 tegra_clk_dam0,
57 tegra_clk_dam1,
58 tegra_clk_dam2,
59 tegra_clk_d_audio,
60 tegra_clk_dds,
61 tegra_clk_dfll_ref,
62 tegra_clk_dfll_soc,
63 tegra_clk_disp1,
64 tegra_clk_disp2,
65 tegra_clk_dp2,
66 tegra_clk_dpaux,
67 tegra_clk_dsia,
68 tegra_clk_dsialp,
69 tegra_clk_dsia_mux,
70 tegra_clk_dsib,
71 tegra_clk_dsiblp,
72 tegra_clk_dsib_mux,
73 tegra_clk_dtv,
74 tegra_clk_emc,
75 tegra_clk_entropy,
76 tegra_clk_epp,
77 tegra_clk_epp_8,
78 tegra_clk_extern1,
79 tegra_clk_extern2,
80 tegra_clk_extern3,
81 tegra_clk_fuse,
82 tegra_clk_fuse_burn,
83 tegra_clk_gpu,
84 tegra_clk_gr2d,
85 tegra_clk_gr2d_8,
86 tegra_clk_gr3d,
87 tegra_clk_gr3d_8,
88 tegra_clk_hclk,
89 tegra_clk_hda,
90 tegra_clk_hda2codec_2x,
91 tegra_clk_hda2hdmi,
92 tegra_clk_hdmi,
93 tegra_clk_hdmi_audio,
94 tegra_clk_host1x,
95 tegra_clk_host1x_8,
96 tegra_clk_i2c1,
97 tegra_clk_i2c2,
98 tegra_clk_i2c3,
99 tegra_clk_i2c4,
100 tegra_clk_i2c5,
101 tegra_clk_i2c6,
102 tegra_clk_i2cslow,
103 tegra_clk_i2s0,
104 tegra_clk_i2s0_sync,
105 tegra_clk_i2s1,
106 tegra_clk_i2s1_sync,
107 tegra_clk_i2s2,
108 tegra_clk_i2s2_sync,
109 tegra_clk_i2s3,
110 tegra_clk_i2s3_sync,
111 tegra_clk_i2s4,
112 tegra_clk_i2s4_sync,
113 tegra_clk_isp,
114 tegra_clk_isp_8,
115 tegra_clk_ispb,
116 tegra_clk_kbc,
117 tegra_clk_kfuse,
118 tegra_clk_la,
119 tegra_clk_mipi,
120 tegra_clk_mipi_cal,
121 tegra_clk_mpe,
122 tegra_clk_mselect,
123 tegra_clk_msenc,
124 tegra_clk_ndflash,
125 tegra_clk_ndflash_8,
126 tegra_clk_ndspeed,
127 tegra_clk_ndspeed_8,
128 tegra_clk_nor,
129 tegra_clk_owr,
130 tegra_clk_pcie,
131 tegra_clk_pclk,
132 tegra_clk_pll_a,
133 tegra_clk_pll_a_out0,
134 tegra_clk_pll_c,
135 tegra_clk_pll_c2,
136 tegra_clk_pll_c3,
137 tegra_clk_pll_c4,
138 tegra_clk_pll_c_out1,
139 tegra_clk_pll_d,
140 tegra_clk_pll_d2,
141 tegra_clk_pll_d2_out0,
142 tegra_clk_pll_d_out0,
143 tegra_clk_pll_dp,
144 tegra_clk_pll_e_out0,
145 tegra_clk_pll_m,
146 tegra_clk_pll_m_out1,
147 tegra_clk_pll_p,
148 tegra_clk_pll_p_out1,
149 tegra_clk_pll_p_out2,
150 tegra_clk_pll_p_out2_int,
151 tegra_clk_pll_p_out3,
152 tegra_clk_pll_p_out4,
153 tegra_clk_pll_p_out5,
154 tegra_clk_pll_ref,
155 tegra_clk_pll_re_out,
156 tegra_clk_pll_re_vco,
157 tegra_clk_pll_u,
158 tegra_clk_pll_u_12m,
159 tegra_clk_pll_u_480m,
160 tegra_clk_pll_u_48m,
161 tegra_clk_pll_u_60m,
162 tegra_clk_pll_x,
163 tegra_clk_pll_x_out0,
164 tegra_clk_pwm,
165 tegra_clk_rtc,
166 tegra_clk_sata,
167 tegra_clk_sata_cold,
168 tegra_clk_sata_oob,
169 tegra_clk_sbc1,
170 tegra_clk_sbc1_8,
171 tegra_clk_sbc2,
172 tegra_clk_sbc2_8,
173 tegra_clk_sbc3,
174 tegra_clk_sbc3_8,
175 tegra_clk_sbc4,
176 tegra_clk_sbc4_8,
177 tegra_clk_sbc5,
178 tegra_clk_sbc5_8,
179 tegra_clk_sbc6,
180 tegra_clk_sbc6_8,
181 tegra_clk_sclk,
182 tegra_clk_sdmmc1,
183 tegra_clk_sdmmc2,
184 tegra_clk_sdmmc3,
185 tegra_clk_sdmmc4,
186 tegra_clk_se,
187 tegra_clk_soc_therm,
188 tegra_clk_sor0,
189 tegra_clk_sor0_lvds,
190 tegra_clk_spdif,
191 tegra_clk_spdif_2x,
192 tegra_clk_spdif_in,
193 tegra_clk_spdif_in_sync,
194 tegra_clk_spdif_mux,
195 tegra_clk_spdif_out,
196 tegra_clk_timer,
197 tegra_clk_trace,
198 tegra_clk_tsec,
199 tegra_clk_tsensor,
200 tegra_clk_tvdac,
201 tegra_clk_tvo,
202 tegra_clk_uarta,
203 tegra_clk_uartb,
204 tegra_clk_uartc,
205 tegra_clk_uartd,
206 tegra_clk_uarte,
207 tegra_clk_usb2,
208 tegra_clk_usb3,
209 tegra_clk_usbd,
210 tegra_clk_vcp,
211 tegra_clk_vde,
212 tegra_clk_vde_8,
213 tegra_clk_vfir,
214 tegra_clk_vi,
215 tegra_clk_vi_8,
216 tegra_clk_vi_9,
217 tegra_clk_vic03,
218 tegra_clk_vim2_clk,
219 tegra_clk_vimclk_sync,
220 tegra_clk_vi_sensor,
221 tegra_clk_vi_sensor2,
222 tegra_clk_vi_sensor_8,
223 tegra_clk_xusb_dev,
224 tegra_clk_xusb_dev_src,
225 tegra_clk_xusb_falcon_src,
226 tegra_clk_xusb_fs_src,
227 tegra_clk_xusb_host,
228 tegra_clk_xusb_host_src,
229 tegra_clk_xusb_hs_src,
230 tegra_clk_xusb_ss,
231 tegra_clk_xusb_ss_src,
232 tegra_clk_max,
233};
234
235#endif /* _TEGRA_CLK_ID_H */
diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c
index bafee9895a24..f38f33e3c65d 100644
--- a/drivers/clk/tegra/clk-periph-gate.c
+++ b/drivers/clk/tegra/clk-periph-gate.c
@@ -151,12 +151,16 @@ const struct clk_ops tegra_clk_periph_gate_ops = {
151 151
152struct clk *tegra_clk_register_periph_gate(const char *name, 152struct clk *tegra_clk_register_periph_gate(const char *name,
153 const char *parent_name, u8 gate_flags, void __iomem *clk_base, 153 const char *parent_name, u8 gate_flags, void __iomem *clk_base,
154 unsigned long flags, int clk_num, 154 unsigned long flags, int clk_num, int *enable_refcnt)
155 struct tegra_clk_periph_regs *pregs, int *enable_refcnt)
156{ 155{
157 struct tegra_clk_periph_gate *gate; 156 struct tegra_clk_periph_gate *gate;
158 struct clk *clk; 157 struct clk *clk;
159 struct clk_init_data init; 158 struct clk_init_data init;
159 struct tegra_clk_periph_regs *pregs;
160
161 pregs = get_reg_bank(clk_num);
162 if (!pregs)
163 return ERR_PTR(-EINVAL);
160 164
161 gate = kzalloc(sizeof(*gate), GFP_KERNEL); 165 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
162 if (!gate) { 166 if (!gate) {
diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c
index b2309d37a963..679103bda2b0 100644
--- a/drivers/clk/tegra/clk-periph.c
+++ b/drivers/clk/tegra/clk-periph.c
@@ -162,7 +162,7 @@ const struct clk_ops tegra_clk_periph_ops = {
162 .disable = clk_periph_disable, 162 .disable = clk_periph_disable,
163}; 163};
164 164
165const struct clk_ops tegra_clk_periph_nodiv_ops = { 165static const struct clk_ops tegra_clk_periph_nodiv_ops = {
166 .get_parent = clk_periph_get_parent, 166 .get_parent = clk_periph_get_parent,
167 .set_parent = clk_periph_set_parent, 167 .set_parent = clk_periph_set_parent,
168 .is_enabled = clk_periph_is_enabled, 168 .is_enabled = clk_periph_is_enabled,
@@ -170,27 +170,50 @@ const struct clk_ops tegra_clk_periph_nodiv_ops = {
170 .disable = clk_periph_disable, 170 .disable = clk_periph_disable,
171}; 171};
172 172
173const struct clk_ops tegra_clk_periph_no_gate_ops = {
174 .get_parent = clk_periph_get_parent,
175 .set_parent = clk_periph_set_parent,
176 .recalc_rate = clk_periph_recalc_rate,
177 .round_rate = clk_periph_round_rate,
178 .set_rate = clk_periph_set_rate,
179};
180
173static struct clk *_tegra_clk_register_periph(const char *name, 181static struct clk *_tegra_clk_register_periph(const char *name,
174 const char **parent_names, int num_parents, 182 const char **parent_names, int num_parents,
175 struct tegra_clk_periph *periph, 183 struct tegra_clk_periph *periph,
176 void __iomem *clk_base, u32 offset, bool div, 184 void __iomem *clk_base, u32 offset,
177 unsigned long flags) 185 unsigned long flags)
178{ 186{
179 struct clk *clk; 187 struct clk *clk;
180 struct clk_init_data init; 188 struct clk_init_data init;
189 struct tegra_clk_periph_regs *bank;
190 bool div = !(periph->gate.flags & TEGRA_PERIPH_NO_DIV);
191
192 if (periph->gate.flags & TEGRA_PERIPH_NO_DIV) {
193 flags |= CLK_SET_RATE_PARENT;
194 init.ops = &tegra_clk_periph_nodiv_ops;
195 } else if (periph->gate.flags & TEGRA_PERIPH_NO_GATE)
196 init.ops = &tegra_clk_periph_no_gate_ops;
197 else
198 init.ops = &tegra_clk_periph_ops;
181 199
182 init.name = name; 200 init.name = name;
183 init.ops = div ? &tegra_clk_periph_ops : &tegra_clk_periph_nodiv_ops;
184 init.flags = flags; 201 init.flags = flags;
185 init.parent_names = parent_names; 202 init.parent_names = parent_names;
186 init.num_parents = num_parents; 203 init.num_parents = num_parents;
187 204
205 bank = get_reg_bank(periph->gate.clk_num);
206 if (!bank)
207 return ERR_PTR(-EINVAL);
208
188 /* Data in .init is copied by clk_register(), so stack variable OK */ 209 /* Data in .init is copied by clk_register(), so stack variable OK */
189 periph->hw.init = &init; 210 periph->hw.init = &init;
190 periph->magic = TEGRA_CLK_PERIPH_MAGIC; 211 periph->magic = TEGRA_CLK_PERIPH_MAGIC;
191 periph->mux.reg = clk_base + offset; 212 periph->mux.reg = clk_base + offset;
192 periph->divider.reg = div ? (clk_base + offset) : NULL; 213 periph->divider.reg = div ? (clk_base + offset) : NULL;
193 periph->gate.clk_base = clk_base; 214 periph->gate.clk_base = clk_base;
215 periph->gate.regs = bank;
216 periph->gate.enable_refcnt = periph_clk_enb_refcnt;
194 217
195 clk = clk_register(NULL, &periph->hw); 218 clk = clk_register(NULL, &periph->hw);
196 if (IS_ERR(clk)) 219 if (IS_ERR(clk))
@@ -209,7 +232,7 @@ struct clk *tegra_clk_register_periph(const char *name,
209 u32 offset, unsigned long flags) 232 u32 offset, unsigned long flags)
210{ 233{
211 return _tegra_clk_register_periph(name, parent_names, num_parents, 234 return _tegra_clk_register_periph(name, parent_names, num_parents,
212 periph, clk_base, offset, true, flags); 235 periph, clk_base, offset, flags);
213} 236}
214 237
215struct clk *tegra_clk_register_periph_nodiv(const char *name, 238struct clk *tegra_clk_register_periph_nodiv(const char *name,
@@ -217,6 +240,7 @@ struct clk *tegra_clk_register_periph_nodiv(const char *name,
217 struct tegra_clk_periph *periph, void __iomem *clk_base, 240 struct tegra_clk_periph *periph, void __iomem *clk_base,
218 u32 offset) 241 u32 offset)
219{ 242{
243 periph->gate.flags |= TEGRA_PERIPH_NO_DIV;
220 return _tegra_clk_register_periph(name, parent_names, num_parents, 244 return _tegra_clk_register_periph(name, parent_names, num_parents,
221 periph, clk_base, offset, false, CLK_SET_RATE_PARENT); 245 periph, clk_base, offset, CLK_SET_RATE_PARENT);
222} 246}
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 197074a57754..0d20241e0770 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -77,7 +77,23 @@
77#define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT) 77#define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT)
78 78
79#define PLLE_SS_CTRL 0x68 79#define PLLE_SS_CTRL 0x68
80#define PLLE_SS_DISABLE (7 << 10) 80#define PLLE_SS_CNTL_BYPASS_SS BIT(10)
81#define PLLE_SS_CNTL_INTERP_RESET BIT(11)
82#define PLLE_SS_CNTL_SSC_BYP BIT(12)
83#define PLLE_SS_CNTL_CENTER BIT(14)
84#define PLLE_SS_CNTL_INVERT BIT(15)
85#define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\
86 PLLE_SS_CNTL_SSC_BYP)
87#define PLLE_SS_MAX_MASK 0x1ff
88#define PLLE_SS_MAX_VAL 0x25
89#define PLLE_SS_INC_MASK (0xff << 16)
90#define PLLE_SS_INC_VAL (0x1 << 16)
91#define PLLE_SS_INCINTRV_MASK (0x3f << 24)
92#define PLLE_SS_INCINTRV_VAL (0x20 << 24)
93#define PLLE_SS_COEFFICIENTS_MASK \
94 (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK)
95#define PLLE_SS_COEFFICIENTS_VAL \
96 (PLLE_SS_MAX_VAL | PLLE_SS_INC_VAL | PLLE_SS_INCINTRV_VAL)
81 97
82#define PLLE_AUX_PLLP_SEL BIT(2) 98#define PLLE_AUX_PLLP_SEL BIT(2)
83#define PLLE_AUX_ENABLE_SWCTL BIT(4) 99#define PLLE_AUX_ENABLE_SWCTL BIT(4)
@@ -121,6 +137,36 @@
121#define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5) 137#define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
122#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4) 138#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
123 139
140#define PLLSS_MISC_KCP 0
141#define PLLSS_MISC_KVCO 0
142#define PLLSS_MISC_SETUP 0
143#define PLLSS_EN_SDM 0
144#define PLLSS_EN_SSC 0
145#define PLLSS_EN_DITHER2 0
146#define PLLSS_EN_DITHER 1
147#define PLLSS_SDM_RESET 0
148#define PLLSS_CLAMP 0
149#define PLLSS_SDM_SSC_MAX 0
150#define PLLSS_SDM_SSC_MIN 0
151#define PLLSS_SDM_SSC_STEP 0
152#define PLLSS_SDM_DIN 0
153#define PLLSS_MISC_DEFAULT ((PLLSS_MISC_KCP << 25) | \
154 (PLLSS_MISC_KVCO << 24) | \
155 PLLSS_MISC_SETUP)
156#define PLLSS_CFG_DEFAULT ((PLLSS_EN_SDM << 31) | \
157 (PLLSS_EN_SSC << 30) | \
158 (PLLSS_EN_DITHER2 << 29) | \
159 (PLLSS_EN_DITHER << 28) | \
160 (PLLSS_SDM_RESET) << 27 | \
161 (PLLSS_CLAMP << 22))
162#define PLLSS_CTRL1_DEFAULT \
163 ((PLLSS_SDM_SSC_MAX << 16) | PLLSS_SDM_SSC_MIN)
164#define PLLSS_CTRL2_DEFAULT \
165 ((PLLSS_SDM_SSC_STEP << 16) | PLLSS_SDM_DIN)
166#define PLLSS_LOCK_OVERRIDE BIT(24)
167#define PLLSS_REF_SRC_SEL_SHIFT 25
168#define PLLSS_REF_SRC_SEL_MASK (3 << PLLSS_REF_SRC_SEL_SHIFT)
169
124#define pll_readl(offset, p) readl_relaxed(p->clk_base + offset) 170#define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
125#define pll_readl_base(p) pll_readl(p->params->base_reg, p) 171#define pll_readl_base(p) pll_readl(p->params->base_reg, p)
126#define pll_readl_misc(p) pll_readl(p->params->misc_reg, p) 172#define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
@@ -134,7 +180,7 @@
134#define mask(w) ((1 << (w)) - 1) 180#define mask(w) ((1 << (w)) - 1)
135#define divm_mask(p) mask(p->params->div_nmp->divm_width) 181#define divm_mask(p) mask(p->params->div_nmp->divm_width)
136#define divn_mask(p) mask(p->params->div_nmp->divn_width) 182#define divn_mask(p) mask(p->params->div_nmp->divn_width)
137#define divp_mask(p) (p->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK : \ 183#define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
138 mask(p->params->div_nmp->divp_width)) 184 mask(p->params->div_nmp->divp_width))
139 185
140#define divm_max(p) (divm_mask(p)) 186#define divm_max(p) (divm_mask(p))
@@ -154,10 +200,10 @@ static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
154{ 200{
155 u32 val; 201 u32 val;
156 202
157 if (!(pll->flags & TEGRA_PLL_USE_LOCK)) 203 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK))
158 return; 204 return;
159 205
160 if (!(pll->flags & TEGRA_PLL_HAS_LOCK_ENABLE)) 206 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
161 return; 207 return;
162 208
163 val = pll_readl_misc(pll); 209 val = pll_readl_misc(pll);
@@ -171,13 +217,13 @@ static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
171 u32 val, lock_mask; 217 u32 val, lock_mask;
172 void __iomem *lock_addr; 218 void __iomem *lock_addr;
173 219
174 if (!(pll->flags & TEGRA_PLL_USE_LOCK)) { 220 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) {
175 udelay(pll->params->lock_delay); 221 udelay(pll->params->lock_delay);
176 return 0; 222 return 0;
177 } 223 }
178 224
179 lock_addr = pll->clk_base; 225 lock_addr = pll->clk_base;
180 if (pll->flags & TEGRA_PLL_LOCK_MISC) 226 if (pll->params->flags & TEGRA_PLL_LOCK_MISC)
181 lock_addr += pll->params->misc_reg; 227 lock_addr += pll->params->misc_reg;
182 else 228 else
183 lock_addr += pll->params->base_reg; 229 lock_addr += pll->params->base_reg;
@@ -204,7 +250,7 @@ static int clk_pll_is_enabled(struct clk_hw *hw)
204 struct tegra_clk_pll *pll = to_clk_pll(hw); 250 struct tegra_clk_pll *pll = to_clk_pll(hw);
205 u32 val; 251 u32 val;
206 252
207 if (pll->flags & TEGRA_PLLM) { 253 if (pll->params->flags & TEGRA_PLLM) {
208 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); 254 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
209 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) 255 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)
210 return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0; 256 return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0;
@@ -223,12 +269,12 @@ static void _clk_pll_enable(struct clk_hw *hw)
223 clk_pll_enable_lock(pll); 269 clk_pll_enable_lock(pll);
224 270
225 val = pll_readl_base(pll); 271 val = pll_readl_base(pll);
226 if (pll->flags & TEGRA_PLL_BYPASS) 272 if (pll->params->flags & TEGRA_PLL_BYPASS)
227 val &= ~PLL_BASE_BYPASS; 273 val &= ~PLL_BASE_BYPASS;
228 val |= PLL_BASE_ENABLE; 274 val |= PLL_BASE_ENABLE;
229 pll_writel_base(val, pll); 275 pll_writel_base(val, pll);
230 276
231 if (pll->flags & TEGRA_PLLM) { 277 if (pll->params->flags & TEGRA_PLLM) {
232 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); 278 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
233 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; 279 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
234 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); 280 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
@@ -241,12 +287,12 @@ static void _clk_pll_disable(struct clk_hw *hw)
241 u32 val; 287 u32 val;
242 288
243 val = pll_readl_base(pll); 289 val = pll_readl_base(pll);
244 if (pll->flags & TEGRA_PLL_BYPASS) 290 if (pll->params->flags & TEGRA_PLL_BYPASS)
245 val &= ~PLL_BASE_BYPASS; 291 val &= ~PLL_BASE_BYPASS;
246 val &= ~PLL_BASE_ENABLE; 292 val &= ~PLL_BASE_ENABLE;
247 pll_writel_base(val, pll); 293 pll_writel_base(val, pll);
248 294
249 if (pll->flags & TEGRA_PLLM) { 295 if (pll->params->flags & TEGRA_PLLM) {
250 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); 296 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
251 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; 297 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
252 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); 298 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
@@ -326,7 +372,7 @@ static int _get_table_rate(struct clk_hw *hw,
326 struct tegra_clk_pll *pll = to_clk_pll(hw); 372 struct tegra_clk_pll *pll = to_clk_pll(hw);
327 struct tegra_clk_pll_freq_table *sel; 373 struct tegra_clk_pll_freq_table *sel;
328 374
329 for (sel = pll->freq_table; sel->input_rate != 0; sel++) 375 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)
330 if (sel->input_rate == parent_rate && 376 if (sel->input_rate == parent_rate &&
331 sel->output_rate == rate) 377 sel->output_rate == rate)
332 break; 378 break;
@@ -389,12 +435,11 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
389 if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) || 435 if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
390 (1 << p_div) > divp_max(pll) 436 (1 << p_div) > divp_max(pll)
391 || cfg->output_rate > pll->params->vco_max) { 437 || cfg->output_rate > pll->params->vco_max) {
392 pr_err("%s: Failed to set %s rate %lu\n",
393 __func__, __clk_get_name(hw->clk), rate);
394 WARN_ON(1);
395 return -EINVAL; 438 return -EINVAL;
396 } 439 }
397 440
441 cfg->output_rate >>= p_div;
442
398 if (pll->params->pdiv_tohw) { 443 if (pll->params->pdiv_tohw) {
399 ret = _p_div_to_hw(hw, 1 << p_div); 444 ret = _p_div_to_hw(hw, 1 << p_div);
400 if (ret < 0) 445 if (ret < 0)
@@ -414,7 +459,7 @@ static void _update_pll_mnp(struct tegra_clk_pll *pll,
414 struct tegra_clk_pll_params *params = pll->params; 459 struct tegra_clk_pll_params *params = pll->params;
415 struct div_nmp *div_nmp = params->div_nmp; 460 struct div_nmp *div_nmp = params->div_nmp;
416 461
417 if ((pll->flags & TEGRA_PLLM) && 462 if ((params->flags & TEGRA_PLLM) &&
418 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & 463 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
419 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) { 464 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
420 val = pll_override_readl(params->pmc_divp_reg, pll); 465 val = pll_override_readl(params->pmc_divp_reg, pll);
@@ -450,7 +495,7 @@ static void _get_pll_mnp(struct tegra_clk_pll *pll,
450 struct tegra_clk_pll_params *params = pll->params; 495 struct tegra_clk_pll_params *params = pll->params;
451 struct div_nmp *div_nmp = params->div_nmp; 496 struct div_nmp *div_nmp = params->div_nmp;
452 497
453 if ((pll->flags & TEGRA_PLLM) && 498 if ((params->flags & TEGRA_PLLM) &&
454 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & 499 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
455 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) { 500 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
456 val = pll_override_readl(params->pmc_divp_reg, pll); 501 val = pll_override_readl(params->pmc_divp_reg, pll);
@@ -479,11 +524,11 @@ static void _update_pll_cpcon(struct tegra_clk_pll *pll,
479 val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT); 524 val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
480 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT; 525 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
481 526
482 if (pll->flags & TEGRA_PLL_SET_LFCON) { 527 if (pll->params->flags & TEGRA_PLL_SET_LFCON) {
483 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT); 528 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
484 if (cfg->n >= PLLDU_LFCON_SET_DIVN) 529 if (cfg->n >= PLLDU_LFCON_SET_DIVN)
485 val |= 1 << PLL_MISC_LFCON_SHIFT; 530 val |= 1 << PLL_MISC_LFCON_SHIFT;
486 } else if (pll->flags & TEGRA_PLL_SET_DCCON) { 531 } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) {
487 val &= ~(1 << PLL_MISC_DCCON_SHIFT); 532 val &= ~(1 << PLL_MISC_DCCON_SHIFT);
488 if (rate >= (pll->params->vco_max >> 1)) 533 if (rate >= (pll->params->vco_max >> 1))
489 val |= 1 << PLL_MISC_DCCON_SHIFT; 534 val |= 1 << PLL_MISC_DCCON_SHIFT;
@@ -505,7 +550,7 @@ static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
505 550
506 _update_pll_mnp(pll, cfg); 551 _update_pll_mnp(pll, cfg);
507 552
508 if (pll->flags & TEGRA_PLL_HAS_CPCON) 553 if (pll->params->flags & TEGRA_PLL_HAS_CPCON)
509 _update_pll_cpcon(pll, cfg, rate); 554 _update_pll_cpcon(pll, cfg, rate);
510 555
511 if (state) { 556 if (state) {
@@ -524,11 +569,11 @@ static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
524 unsigned long flags = 0; 569 unsigned long flags = 0;
525 int ret = 0; 570 int ret = 0;
526 571
527 if (pll->flags & TEGRA_PLL_FIXED) { 572 if (pll->params->flags & TEGRA_PLL_FIXED) {
528 if (rate != pll->fixed_rate) { 573 if (rate != pll->params->fixed_rate) {
529 pr_err("%s: Can not change %s fixed rate %lu to %lu\n", 574 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
530 __func__, __clk_get_name(hw->clk), 575 __func__, __clk_get_name(hw->clk),
531 pll->fixed_rate, rate); 576 pll->params->fixed_rate, rate);
532 return -EINVAL; 577 return -EINVAL;
533 } 578 }
534 return 0; 579 return 0;
@@ -536,6 +581,8 @@ static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
536 581
537 if (_get_table_rate(hw, &cfg, rate, parent_rate) && 582 if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
538 _calc_rate(hw, &cfg, rate, parent_rate)) { 583 _calc_rate(hw, &cfg, rate, parent_rate)) {
584 pr_err("%s: Failed to set %s rate %lu\n", __func__,
585 __clk_get_name(hw->clk), rate);
539 WARN_ON(1); 586 WARN_ON(1);
540 return -EINVAL; 587 return -EINVAL;
541 } 588 }
@@ -559,18 +606,16 @@ static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
559 struct tegra_clk_pll *pll = to_clk_pll(hw); 606 struct tegra_clk_pll *pll = to_clk_pll(hw);
560 struct tegra_clk_pll_freq_table cfg; 607 struct tegra_clk_pll_freq_table cfg;
561 608
562 if (pll->flags & TEGRA_PLL_FIXED) 609 if (pll->params->flags & TEGRA_PLL_FIXED)
563 return pll->fixed_rate; 610 return pll->params->fixed_rate;
564 611
565 /* PLLM is used for memory; we do not change rate */ 612 /* PLLM is used for memory; we do not change rate */
566 if (pll->flags & TEGRA_PLLM) 613 if (pll->params->flags & TEGRA_PLLM)
567 return __clk_get_rate(hw->clk); 614 return __clk_get_rate(hw->clk);
568 615
569 if (_get_table_rate(hw, &cfg, rate, *prate) && 616 if (_get_table_rate(hw, &cfg, rate, *prate) &&
570 _calc_rate(hw, &cfg, rate, *prate)) { 617 _calc_rate(hw, &cfg, rate, *prate))
571 WARN_ON(1);
572 return -EINVAL; 618 return -EINVAL;
573 }
574 619
575 return cfg.output_rate; 620 return cfg.output_rate;
576} 621}
@@ -586,17 +631,19 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
586 631
587 val = pll_readl_base(pll); 632 val = pll_readl_base(pll);
588 633
589 if ((pll->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS)) 634 if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
590 return parent_rate; 635 return parent_rate;
591 636
592 if ((pll->flags & TEGRA_PLL_FIXED) && !(val & PLL_BASE_OVERRIDE)) { 637 if ((pll->params->flags & TEGRA_PLL_FIXED) &&
638 !(val & PLL_BASE_OVERRIDE)) {
593 struct tegra_clk_pll_freq_table sel; 639 struct tegra_clk_pll_freq_table sel;
594 if (_get_table_rate(hw, &sel, pll->fixed_rate, parent_rate)) { 640 if (_get_table_rate(hw, &sel, pll->params->fixed_rate,
641 parent_rate)) {
595 pr_err("Clock %s has unknown fixed frequency\n", 642 pr_err("Clock %s has unknown fixed frequency\n",
596 __clk_get_name(hw->clk)); 643 __clk_get_name(hw->clk));
597 BUG(); 644 BUG();
598 } 645 }
599 return pll->fixed_rate; 646 return pll->params->fixed_rate;
600 } 647 }
601 648
602 _get_pll_mnp(pll, &cfg); 649 _get_pll_mnp(pll, &cfg);
@@ -664,7 +711,7 @@ static int clk_plle_enable(struct clk_hw *hw)
664 u32 val; 711 u32 val;
665 int err; 712 int err;
666 713
667 if (_get_table_rate(hw, &sel, pll->fixed_rate, input_rate)) 714 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
668 return -EINVAL; 715 return -EINVAL;
669 716
670 clk_pll_disable(hw); 717 clk_pll_disable(hw);
@@ -680,7 +727,7 @@ static int clk_plle_enable(struct clk_hw *hw)
680 return err; 727 return err;
681 } 728 }
682 729
683 if (pll->flags & TEGRA_PLLE_CONFIGURE) { 730 if (pll->params->flags & TEGRA_PLLE_CONFIGURE) {
684 /* configure dividers */ 731 /* configure dividers */
685 val = pll_readl_base(pll); 732 val = pll_readl_base(pll);
686 val &= ~(divm_mask(pll) | divn_mask(pll) | divp_mask(pll)); 733 val &= ~(divm_mask(pll) | divn_mask(pll) | divp_mask(pll));
@@ -744,7 +791,7 @@ const struct clk_ops tegra_clk_plle_ops = {
744 .enable = clk_plle_enable, 791 .enable = clk_plle_enable,
745}; 792};
746 793
747#ifdef CONFIG_ARCH_TEGRA_114_SOC 794#if defined(CONFIG_ARCH_TEGRA_114_SOC) || defined(CONFIG_ARCH_TEGRA_124_SOC)
748 795
749static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params, 796static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
750 unsigned long parent_rate) 797 unsigned long parent_rate)
@@ -755,6 +802,48 @@ static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
755 return 1; 802 return 1;
756} 803}
757 804
805static unsigned long _clip_vco_min(unsigned long vco_min,
806 unsigned long parent_rate)
807{
808 return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate;
809}
810
811static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
812 void __iomem *clk_base,
813 unsigned long parent_rate)
814{
815 u32 val;
816 u32 step_a, step_b;
817
818 switch (parent_rate) {
819 case 12000000:
820 case 13000000:
821 case 26000000:
822 step_a = 0x2B;
823 step_b = 0x0B;
824 break;
825 case 16800000:
826 step_a = 0x1A;
827 step_b = 0x09;
828 break;
829 case 19200000:
830 step_a = 0x12;
831 step_b = 0x08;
832 break;
833 default:
834 pr_err("%s: Unexpected reference rate %lu\n",
835 __func__, parent_rate);
836 WARN_ON(1);
837 return -EINVAL;
838 }
839
840 val = step_a << pll_params->stepa_shift;
841 val |= step_b << pll_params->stepb_shift;
842 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
843
844 return 0;
845}
846
758static int clk_pll_iddq_enable(struct clk_hw *hw) 847static int clk_pll_iddq_enable(struct clk_hw *hw)
759{ 848{
760 struct tegra_clk_pll *pll = to_clk_pll(hw); 849 struct tegra_clk_pll *pll = to_clk_pll(hw);
@@ -1173,7 +1262,7 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw)
1173 unsigned long flags = 0; 1262 unsigned long flags = 0;
1174 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); 1263 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
1175 1264
1176 if (_get_table_rate(hw, &sel, pll->fixed_rate, input_rate)) 1265 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
1177 return -EINVAL; 1266 return -EINVAL;
1178 1267
1179 if (pll->lock) 1268 if (pll->lock)
@@ -1217,6 +1306,18 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw)
1217 if (ret < 0) 1306 if (ret < 0)
1218 goto out; 1307 goto out;
1219 1308
1309 val = pll_readl(PLLE_SS_CTRL, pll);
1310 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
1311 val &= ~PLLE_SS_COEFFICIENTS_MASK;
1312 val |= PLLE_SS_COEFFICIENTS_VAL;
1313 pll_writel(val, PLLE_SS_CTRL, pll);
1314 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
1315 pll_writel(val, PLLE_SS_CTRL, pll);
1316 udelay(1);
1317 val &= ~PLLE_SS_CNTL_INTERP_RESET;
1318 pll_writel(val, PLLE_SS_CTRL, pll);
1319 udelay(1);
1320
1220 /* TODO: enable hw control of xusb brick pll */ 1321 /* TODO: enable hw control of xusb brick pll */
1221 1322
1222out: 1323out:
@@ -1248,9 +1349,8 @@ static void clk_plle_tegra114_disable(struct clk_hw *hw)
1248#endif 1349#endif
1249 1350
1250static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base, 1351static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
1251 void __iomem *pmc, unsigned long fixed_rate, 1352 void __iomem *pmc, struct tegra_clk_pll_params *pll_params,
1252 struct tegra_clk_pll_params *pll_params, u32 pll_flags, 1353 spinlock_t *lock)
1253 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
1254{ 1354{
1255 struct tegra_clk_pll *pll; 1355 struct tegra_clk_pll *pll;
1256 1356
@@ -1261,10 +1361,7 @@ static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
1261 pll->clk_base = clk_base; 1361 pll->clk_base = clk_base;
1262 pll->pmc = pmc; 1362 pll->pmc = pmc;
1263 1363
1264 pll->freq_table = freq_table;
1265 pll->params = pll_params; 1364 pll->params = pll_params;
1266 pll->fixed_rate = fixed_rate;
1267 pll->flags = pll_flags;
1268 pll->lock = lock; 1365 pll->lock = lock;
1269 1366
1270 if (!pll_params->div_nmp) 1367 if (!pll_params->div_nmp)
@@ -1293,17 +1390,15 @@ static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
1293 1390
1294struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, 1391struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
1295 void __iomem *clk_base, void __iomem *pmc, 1392 void __iomem *clk_base, void __iomem *pmc,
1296 unsigned long flags, unsigned long fixed_rate, 1393 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1297 struct tegra_clk_pll_params *pll_params, u32 pll_flags, 1394 spinlock_t *lock)
1298 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
1299{ 1395{
1300 struct tegra_clk_pll *pll; 1396 struct tegra_clk_pll *pll;
1301 struct clk *clk; 1397 struct clk *clk;
1302 1398
1303 pll_flags |= TEGRA_PLL_BYPASS; 1399 pll_params->flags |= TEGRA_PLL_BYPASS;
1304 pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE; 1400 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1305 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags, 1401 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1306 freq_table, lock);
1307 if (IS_ERR(pll)) 1402 if (IS_ERR(pll))
1308 return ERR_CAST(pll); 1403 return ERR_CAST(pll);
1309 1404
@@ -1317,17 +1412,15 @@ struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
1317 1412
1318struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, 1413struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
1319 void __iomem *clk_base, void __iomem *pmc, 1414 void __iomem *clk_base, void __iomem *pmc,
1320 unsigned long flags, unsigned long fixed_rate, 1415 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1321 struct tegra_clk_pll_params *pll_params, u32 pll_flags, 1416 spinlock_t *lock)
1322 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
1323{ 1417{
1324 struct tegra_clk_pll *pll; 1418 struct tegra_clk_pll *pll;
1325 struct clk *clk; 1419 struct clk *clk;
1326 1420
1327 pll_flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS; 1421 pll_params->flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS;
1328 pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE; 1422 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1329 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags, 1423 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1330 freq_table, lock);
1331 if (IS_ERR(pll)) 1424 if (IS_ERR(pll))
1332 return ERR_CAST(pll); 1425 return ERR_CAST(pll);
1333 1426
@@ -1339,8 +1432,8 @@ struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
1339 return clk; 1432 return clk;
1340} 1433}
1341 1434
1342#ifdef CONFIG_ARCH_TEGRA_114_SOC 1435#if defined(CONFIG_ARCH_TEGRA_114_SOC) || defined(CONFIG_ARCH_TEGRA_124_SOC)
1343const struct clk_ops tegra_clk_pllxc_ops = { 1436static const struct clk_ops tegra_clk_pllxc_ops = {
1344 .is_enabled = clk_pll_is_enabled, 1437 .is_enabled = clk_pll_is_enabled,
1345 .enable = clk_pll_iddq_enable, 1438 .enable = clk_pll_iddq_enable,
1346 .disable = clk_pll_iddq_disable, 1439 .disable = clk_pll_iddq_disable,
@@ -1349,7 +1442,7 @@ const struct clk_ops tegra_clk_pllxc_ops = {
1349 .set_rate = clk_pllxc_set_rate, 1442 .set_rate = clk_pllxc_set_rate,
1350}; 1443};
1351 1444
1352const struct clk_ops tegra_clk_pllm_ops = { 1445static const struct clk_ops tegra_clk_pllm_ops = {
1353 .is_enabled = clk_pll_is_enabled, 1446 .is_enabled = clk_pll_is_enabled,
1354 .enable = clk_pll_iddq_enable, 1447 .enable = clk_pll_iddq_enable,
1355 .disable = clk_pll_iddq_disable, 1448 .disable = clk_pll_iddq_disable,
@@ -1358,7 +1451,7 @@ const struct clk_ops tegra_clk_pllm_ops = {
1358 .set_rate = clk_pllm_set_rate, 1451 .set_rate = clk_pllm_set_rate,
1359}; 1452};
1360 1453
1361const struct clk_ops tegra_clk_pllc_ops = { 1454static const struct clk_ops tegra_clk_pllc_ops = {
1362 .is_enabled = clk_pll_is_enabled, 1455 .is_enabled = clk_pll_is_enabled,
1363 .enable = clk_pllc_enable, 1456 .enable = clk_pllc_enable,
1364 .disable = clk_pllc_disable, 1457 .disable = clk_pllc_disable,
@@ -1367,7 +1460,7 @@ const struct clk_ops tegra_clk_pllc_ops = {
1367 .set_rate = clk_pllc_set_rate, 1460 .set_rate = clk_pllc_set_rate,
1368}; 1461};
1369 1462
1370const struct clk_ops tegra_clk_pllre_ops = { 1463static const struct clk_ops tegra_clk_pllre_ops = {
1371 .is_enabled = clk_pll_is_enabled, 1464 .is_enabled = clk_pll_is_enabled,
1372 .enable = clk_pll_iddq_enable, 1465 .enable = clk_pll_iddq_enable,
1373 .disable = clk_pll_iddq_disable, 1466 .disable = clk_pll_iddq_disable,
@@ -1376,7 +1469,7 @@ const struct clk_ops tegra_clk_pllre_ops = {
1376 .set_rate = clk_pllre_set_rate, 1469 .set_rate = clk_pllre_set_rate,
1377}; 1470};
1378 1471
1379const struct clk_ops tegra_clk_plle_tegra114_ops = { 1472static const struct clk_ops tegra_clk_plle_tegra114_ops = {
1380 .is_enabled = clk_pll_is_enabled, 1473 .is_enabled = clk_pll_is_enabled,
1381 .enable = clk_plle_tegra114_enable, 1474 .enable = clk_plle_tegra114_enable,
1382 .disable = clk_plle_tegra114_disable, 1475 .disable = clk_plle_tegra114_disable,
@@ -1386,21 +1479,46 @@ const struct clk_ops tegra_clk_plle_tegra114_ops = {
1386 1479
1387struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, 1480struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
1388 void __iomem *clk_base, void __iomem *pmc, 1481 void __iomem *clk_base, void __iomem *pmc,
1389 unsigned long flags, unsigned long fixed_rate, 1482 unsigned long flags,
1390 struct tegra_clk_pll_params *pll_params, 1483 struct tegra_clk_pll_params *pll_params,
1391 u32 pll_flags,
1392 struct tegra_clk_pll_freq_table *freq_table,
1393 spinlock_t *lock) 1484 spinlock_t *lock)
1394{ 1485{
1395 struct tegra_clk_pll *pll; 1486 struct tegra_clk_pll *pll;
1396 struct clk *clk; 1487 struct clk *clk, *parent;
1488 unsigned long parent_rate;
1489 int err;
1490 u32 val, val_iddq;
1491
1492 parent = __clk_lookup(parent_name);
1493 if (!parent) {
1494 WARN(1, "parent clk %s of %s must be registered first\n",
1495 name, parent_name);
1496 return ERR_PTR(-EINVAL);
1497 }
1397 1498
1398 if (!pll_params->pdiv_tohw) 1499 if (!pll_params->pdiv_tohw)
1399 return ERR_PTR(-EINVAL); 1500 return ERR_PTR(-EINVAL);
1400 1501
1401 pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE; 1502 parent_rate = __clk_get_rate(parent);
1402 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags, 1503
1403 freq_table, lock); 1504 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1505
1506 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);
1507 if (err)
1508 return ERR_PTR(err);
1509
1510 val = readl_relaxed(clk_base + pll_params->base_reg);
1511 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
1512
1513 if (val & PLL_BASE_ENABLE)
1514 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
1515 else {
1516 val_iddq |= BIT(pll_params->iddq_bit_idx);
1517 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
1518 }
1519
1520 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1521 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1404 if (IS_ERR(pll)) 1522 if (IS_ERR(pll))
1405 return ERR_CAST(pll); 1523 return ERR_CAST(pll);
1406 1524
@@ -1414,19 +1532,19 @@ struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
1414 1532
1415struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, 1533struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
1416 void __iomem *clk_base, void __iomem *pmc, 1534 void __iomem *clk_base, void __iomem *pmc,
1417 unsigned long flags, unsigned long fixed_rate, 1535 unsigned long flags,
1418 struct tegra_clk_pll_params *pll_params, 1536 struct tegra_clk_pll_params *pll_params,
1419 u32 pll_flags,
1420 struct tegra_clk_pll_freq_table *freq_table,
1421 spinlock_t *lock, unsigned long parent_rate) 1537 spinlock_t *lock, unsigned long parent_rate)
1422{ 1538{
1423 u32 val; 1539 u32 val;
1424 struct tegra_clk_pll *pll; 1540 struct tegra_clk_pll *pll;
1425 struct clk *clk; 1541 struct clk *clk;
1426 1542
1427 pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_LOCK_MISC; 1543 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_LOCK_MISC;
1428 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags, 1544
1429 freq_table, lock); 1545 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1546
1547 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1430 if (IS_ERR(pll)) 1548 if (IS_ERR(pll))
1431 return ERR_CAST(pll); 1549 return ERR_CAST(pll);
1432 1550
@@ -1461,23 +1579,32 @@ struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
1461 1579
1462struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, 1580struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
1463 void __iomem *clk_base, void __iomem *pmc, 1581 void __iomem *clk_base, void __iomem *pmc,
1464 unsigned long flags, unsigned long fixed_rate, 1582 unsigned long flags,
1465 struct tegra_clk_pll_params *pll_params, 1583 struct tegra_clk_pll_params *pll_params,
1466 u32 pll_flags,
1467 struct tegra_clk_pll_freq_table *freq_table,
1468 spinlock_t *lock) 1584 spinlock_t *lock)
1469{ 1585{
1470 struct tegra_clk_pll *pll; 1586 struct tegra_clk_pll *pll;
1471 struct clk *clk; 1587 struct clk *clk, *parent;
1588 unsigned long parent_rate;
1472 1589
1473 if (!pll_params->pdiv_tohw) 1590 if (!pll_params->pdiv_tohw)
1474 return ERR_PTR(-EINVAL); 1591 return ERR_PTR(-EINVAL);
1475 1592
1476 pll_flags |= TEGRA_PLL_BYPASS; 1593 parent = __clk_lookup(parent_name);
1477 pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE; 1594 if (!parent) {
1478 pll_flags |= TEGRA_PLLM; 1595 WARN(1, "parent clk %s of %s must be registered first\n",
1479 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags, 1596 name, parent_name);
1480 freq_table, lock); 1597 return ERR_PTR(-EINVAL);
1598 }
1599
1600 parent_rate = __clk_get_rate(parent);
1601
1602 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1603
1604 pll_params->flags |= TEGRA_PLL_BYPASS;
1605 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1606 pll_params->flags |= TEGRA_PLLM;
1607 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1481 if (IS_ERR(pll)) 1608 if (IS_ERR(pll))
1482 return ERR_CAST(pll); 1609 return ERR_CAST(pll);
1483 1610
@@ -1491,10 +1618,8 @@ struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
1491 1618
1492struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, 1619struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
1493 void __iomem *clk_base, void __iomem *pmc, 1620 void __iomem *clk_base, void __iomem *pmc,
1494 unsigned long flags, unsigned long fixed_rate, 1621 unsigned long flags,
1495 struct tegra_clk_pll_params *pll_params, 1622 struct tegra_clk_pll_params *pll_params,
1496 u32 pll_flags,
1497 struct tegra_clk_pll_freq_table *freq_table,
1498 spinlock_t *lock) 1623 spinlock_t *lock)
1499{ 1624{
1500 struct clk *parent, *clk; 1625 struct clk *parent, *clk;
@@ -1507,20 +1632,21 @@ struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
1507 return ERR_PTR(-EINVAL); 1632 return ERR_PTR(-EINVAL);
1508 1633
1509 parent = __clk_lookup(parent_name); 1634 parent = __clk_lookup(parent_name);
1510 if (IS_ERR(parent)) { 1635 if (!parent) {
1511 WARN(1, "parent clk %s of %s must be registered first\n", 1636 WARN(1, "parent clk %s of %s must be registered first\n",
1512 name, parent_name); 1637 name, parent_name);
1513 return ERR_PTR(-EINVAL); 1638 return ERR_PTR(-EINVAL);
1514 } 1639 }
1515 1640
1516 pll_flags |= TEGRA_PLL_BYPASS; 1641 parent_rate = __clk_get_rate(parent);
1517 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags, 1642
1518 freq_table, lock); 1643 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1644
1645 pll_params->flags |= TEGRA_PLL_BYPASS;
1646 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1519 if (IS_ERR(pll)) 1647 if (IS_ERR(pll))
1520 return ERR_CAST(pll); 1648 return ERR_CAST(pll);
1521 1649
1522 parent_rate = __clk_get_rate(parent);
1523
1524 /* 1650 /*
1525 * Most of PLLC register fields are shadowed, and can not be read 1651 * Most of PLLC register fields are shadowed, and can not be read
1526 * directly from PLL h/w. Hence, actual PLLC boot state is unknown. 1652 * directly from PLL h/w. Hence, actual PLLC boot state is unknown.
@@ -1567,17 +1693,15 @@ struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
1567struct clk *tegra_clk_register_plle_tegra114(const char *name, 1693struct clk *tegra_clk_register_plle_tegra114(const char *name,
1568 const char *parent_name, 1694 const char *parent_name,
1569 void __iomem *clk_base, unsigned long flags, 1695 void __iomem *clk_base, unsigned long flags,
1570 unsigned long fixed_rate,
1571 struct tegra_clk_pll_params *pll_params, 1696 struct tegra_clk_pll_params *pll_params,
1572 struct tegra_clk_pll_freq_table *freq_table,
1573 spinlock_t *lock) 1697 spinlock_t *lock)
1574{ 1698{
1575 struct tegra_clk_pll *pll; 1699 struct tegra_clk_pll *pll;
1576 struct clk *clk; 1700 struct clk *clk;
1577 u32 val, val_aux; 1701 u32 val, val_aux;
1578 1702
1579 pll = _tegra_init_pll(clk_base, NULL, fixed_rate, pll_params, 1703 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1580 TEGRA_PLL_HAS_LOCK_ENABLE, freq_table, lock); 1704 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1581 if (IS_ERR(pll)) 1705 if (IS_ERR(pll))
1582 return ERR_CAST(pll); 1706 return ERR_CAST(pll);
1583 1707
@@ -1587,11 +1711,13 @@ struct clk *tegra_clk_register_plle_tegra114(const char *name,
1587 val_aux = pll_readl(pll_params->aux_reg, pll); 1711 val_aux = pll_readl(pll_params->aux_reg, pll);
1588 1712
1589 if (val & PLL_BASE_ENABLE) { 1713 if (val & PLL_BASE_ENABLE) {
1590 if (!(val_aux & PLLE_AUX_PLLRE_SEL)) 1714 if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
1715 (val_aux & PLLE_AUX_PLLP_SEL))
1591 WARN(1, "pll_e enabled with unsupported parent %s\n", 1716 WARN(1, "pll_e enabled with unsupported parent %s\n",
1592 (val & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : "pll_ref"); 1717 (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
1718 "pll_re_vco");
1593 } else { 1719 } else {
1594 val_aux |= PLLE_AUX_PLLRE_SEL; 1720 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
1595 pll_writel(val, pll_params->aux_reg, pll); 1721 pll_writel(val, pll_params->aux_reg, pll);
1596 } 1722 }
1597 1723
@@ -1603,3 +1729,92 @@ struct clk *tegra_clk_register_plle_tegra114(const char *name,
1603 return clk; 1729 return clk;
1604} 1730}
1605#endif 1731#endif
1732
1733#ifdef CONFIG_ARCH_TEGRA_124_SOC
1734static const struct clk_ops tegra_clk_pllss_ops = {
1735 .is_enabled = clk_pll_is_enabled,
1736 .enable = clk_pll_iddq_enable,
1737 .disable = clk_pll_iddq_disable,
1738 .recalc_rate = clk_pll_recalc_rate,
1739 .round_rate = clk_pll_ramp_round_rate,
1740 .set_rate = clk_pllxc_set_rate,
1741};
1742
1743struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
1744 void __iomem *clk_base, unsigned long flags,
1745 struct tegra_clk_pll_params *pll_params,
1746 spinlock_t *lock)
1747{
1748 struct tegra_clk_pll *pll;
1749 struct clk *clk, *parent;
1750 struct tegra_clk_pll_freq_table cfg;
1751 unsigned long parent_rate;
1752 u32 val;
1753 int i;
1754
1755 if (!pll_params->div_nmp)
1756 return ERR_PTR(-EINVAL);
1757
1758 parent = __clk_lookup(parent_name);
1759 if (!parent) {
1760 WARN(1, "parent clk %s of %s must be registered first\n",
1761 name, parent_name);
1762 return ERR_PTR(-EINVAL);
1763 }
1764
1765 pll_params->flags = TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_USE_LOCK;
1766 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1767 if (IS_ERR(pll))
1768 return ERR_CAST(pll);
1769
1770 val = pll_readl_base(pll);
1771 val &= ~PLLSS_REF_SRC_SEL_MASK;
1772 pll_writel_base(val, pll);
1773
1774 parent_rate = __clk_get_rate(parent);
1775
1776 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1777
1778 /* initialize PLL to minimum rate */
1779
1780 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
1781 cfg.n = cfg.m * pll_params->vco_min / parent_rate;
1782
1783 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)
1784 ;
1785 if (!i) {
1786 kfree(pll);
1787 return ERR_PTR(-EINVAL);
1788 }
1789
1790 cfg.p = pll_params->pdiv_tohw[i-1].hw_val;
1791
1792 _update_pll_mnp(pll, &cfg);
1793
1794 pll_writel_misc(PLLSS_MISC_DEFAULT, pll);
1795 pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);
1796 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);
1797 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);
1798
1799 val = pll_readl_base(pll);
1800 if (val & PLL_BASE_ENABLE) {
1801 if (val & BIT(pll_params->iddq_bit_idx)) {
1802 WARN(1, "%s is on but IDDQ set\n", name);
1803 kfree(pll);
1804 return ERR_PTR(-EINVAL);
1805 }
1806 } else
1807 val |= BIT(pll_params->iddq_bit_idx);
1808
1809 val &= ~PLLSS_LOCK_OVERRIDE;
1810 pll_writel_base(val, pll);
1811
1812 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1813 &tegra_clk_pllss_ops);
1814
1815 if (IS_ERR(clk))
1816 kfree(pll);
1817
1818 return clk;
1819}
1820#endif
diff --git a/drivers/clk/tegra/clk-tegra-audio.c b/drivers/clk/tegra/clk-tegra-audio.c
new file mode 100644
index 000000000000..5c38aab2c5b8
--- /dev/null
+++ b/drivers/clk/tegra/clk-tegra-audio.c
@@ -0,0 +1,215 @@
1/*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/clk-provider.h>
20#include <linux/of.h>
21#include <linux/of_address.h>
22#include <linux/delay.h>
23#include <linux/export.h>
24#include <linux/clk/tegra.h>
25
26#include "clk.h"
27#include "clk-id.h"
28
29#define AUDIO_SYNC_CLK_I2S0 0x4a0
30#define AUDIO_SYNC_CLK_I2S1 0x4a4
31#define AUDIO_SYNC_CLK_I2S2 0x4a8
32#define AUDIO_SYNC_CLK_I2S3 0x4ac
33#define AUDIO_SYNC_CLK_I2S4 0x4b0
34#define AUDIO_SYNC_CLK_SPDIF 0x4b4
35
36#define AUDIO_SYNC_DOUBLER 0x49c
37
38#define PLLA_OUT 0xb4
39
40struct tegra_sync_source_initdata {
41 char *name;
42 unsigned long rate;
43 unsigned long max_rate;
44 int clk_id;
45};
46
47#define SYNC(_name) \
48 {\
49 .name = #_name,\
50 .rate = 24000000,\
51 .max_rate = 24000000,\
52 .clk_id = tegra_clk_ ## _name,\
53 }
54
55struct tegra_audio_clk_initdata {
56 char *gate_name;
57 char *mux_name;
58 u32 offset;
59 int gate_clk_id;
60 int mux_clk_id;
61};
62
63#define AUDIO(_name, _offset) \
64 {\
65 .gate_name = #_name,\
66 .mux_name = #_name"_mux",\
67 .offset = _offset,\
68 .gate_clk_id = tegra_clk_ ## _name,\
69 .mux_clk_id = tegra_clk_ ## _name ## _mux,\
70 }
71
72struct tegra_audio2x_clk_initdata {
73 char *parent;
74 char *gate_name;
75 char *name_2x;
76 char *div_name;
77 int clk_id;
78 int clk_num;
79 u8 div_offset;
80};
81
82#define AUDIO2X(_name, _num, _offset) \
83 {\
84 .parent = #_name,\
85 .gate_name = #_name"_2x",\
86 .name_2x = #_name"_doubler",\
87 .div_name = #_name"_div",\
88 .clk_id = tegra_clk_ ## _name ## _2x,\
89 .clk_num = _num,\
90 .div_offset = _offset,\
91 }
92
93static DEFINE_SPINLOCK(clk_doubler_lock);
94
95static const char *mux_audio_sync_clk[] = { "spdif_in_sync", "i2s0_sync",
96 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",
97};
98
99static struct tegra_sync_source_initdata sync_source_clks[] __initdata = {
100 SYNC(spdif_in_sync),
101 SYNC(i2s0_sync),
102 SYNC(i2s1_sync),
103 SYNC(i2s2_sync),
104 SYNC(i2s3_sync),
105 SYNC(i2s4_sync),
106 SYNC(vimclk_sync),
107};
108
109static struct tegra_audio_clk_initdata audio_clks[] = {
110 AUDIO(audio0, AUDIO_SYNC_CLK_I2S0),
111 AUDIO(audio1, AUDIO_SYNC_CLK_I2S1),
112 AUDIO(audio2, AUDIO_SYNC_CLK_I2S2),
113 AUDIO(audio3, AUDIO_SYNC_CLK_I2S3),
114 AUDIO(audio4, AUDIO_SYNC_CLK_I2S4),
115 AUDIO(spdif, AUDIO_SYNC_CLK_SPDIF),
116};
117
118static struct tegra_audio2x_clk_initdata audio2x_clks[] = {
119 AUDIO2X(audio0, 113, 24),
120 AUDIO2X(audio1, 114, 25),
121 AUDIO2X(audio2, 115, 26),
122 AUDIO2X(audio3, 116, 27),
123 AUDIO2X(audio4, 117, 28),
124 AUDIO2X(spdif, 118, 29),
125};
126
127void __init tegra_audio_clk_init(void __iomem *clk_base,
128 void __iomem *pmc_base, struct tegra_clk *tegra_clks,
129 struct tegra_clk_pll_params *pll_a_params)
130{
131 struct clk *clk;
132 struct clk **dt_clk;
133 int i;
134
135 /* PLLA */
136 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_a, tegra_clks);
137 if (dt_clk) {
138 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base,
139 pmc_base, 0, pll_a_params, NULL);
140 *dt_clk = clk;
141 }
142
143 /* PLLA_OUT0 */
144 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_a_out0, tegra_clks);
145 if (dt_clk) {
146 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
147 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
148 8, 8, 1, NULL);
149 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
150 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
151 CLK_SET_RATE_PARENT, 0, NULL);
152 *dt_clk = clk;
153 }
154
155 for (i = 0; i < ARRAY_SIZE(sync_source_clks); i++) {
156 struct tegra_sync_source_initdata *data;
157
158 data = &sync_source_clks[i];
159
160 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
161 if (!dt_clk)
162 continue;
163
164 clk = tegra_clk_register_sync_source(data->name,
165 data->rate, data->max_rate);
166 *dt_clk = clk;
167 }
168
169 for (i = 0; i < ARRAY_SIZE(audio_clks); i++) {
170 struct tegra_audio_clk_initdata *data;
171
172 data = &audio_clks[i];
173 dt_clk = tegra_lookup_dt_id(data->mux_clk_id, tegra_clks);
174
175 if (!dt_clk)
176 continue;
177 clk = clk_register_mux(NULL, data->mux_name, mux_audio_sync_clk,
178 ARRAY_SIZE(mux_audio_sync_clk),
179 CLK_SET_RATE_NO_REPARENT,
180 clk_base + data->offset, 0, 3, 0,
181 NULL);
182 *dt_clk = clk;
183
184 dt_clk = tegra_lookup_dt_id(data->gate_clk_id, tegra_clks);
185 if (!dt_clk)
186 continue;
187
188 clk = clk_register_gate(NULL, data->gate_name, data->mux_name,
189 0, clk_base + data->offset, 4,
190 CLK_GATE_SET_TO_DISABLE, NULL);
191 *dt_clk = clk;
192 }
193
194 for (i = 0; i < ARRAY_SIZE(audio2x_clks); i++) {
195 struct tegra_audio2x_clk_initdata *data;
196
197 data = &audio2x_clks[i];
198 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
199 if (!dt_clk)
200 continue;
201
202 clk = clk_register_fixed_factor(NULL, data->name_2x,
203 data->parent, CLK_SET_RATE_PARENT, 2, 1);
204 clk = tegra_clk_register_divider(data->div_name,
205 data->name_2x, clk_base + AUDIO_SYNC_DOUBLER,
206 0, 0, data->div_offset, 1, 0,
207 &clk_doubler_lock);
208 clk = tegra_clk_register_periph_gate(data->gate_name,
209 data->div_name, TEGRA_PERIPH_NO_RESET,
210 clk_base, CLK_SET_RATE_PARENT, data->clk_num,
211 periph_clk_enb_refcnt);
212 *dt_clk = clk;
213 }
214}
215
diff --git a/drivers/clk/tegra/clk-tegra-fixed.c b/drivers/clk/tegra/clk-tegra-fixed.c
new file mode 100644
index 000000000000..f3b773833429
--- /dev/null
+++ b/drivers/clk/tegra/clk-tegra-fixed.c
@@ -0,0 +1,111 @@
1/*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/clk-provider.h>
20#include <linux/of.h>
21#include <linux/of_address.h>
22#include <linux/delay.h>
23#include <linux/export.h>
24#include <linux/clk/tegra.h>
25
26#include "clk.h"
27#include "clk-id.h"
28
29#define OSC_CTRL 0x50
30#define OSC_CTRL_OSC_FREQ_SHIFT 28
31#define OSC_CTRL_PLL_REF_DIV_SHIFT 26
32
33int __init tegra_osc_clk_init(void __iomem *clk_base,
34 struct tegra_clk *tegra_clks,
35 unsigned long *input_freqs, int num,
36 unsigned long *osc_freq,
37 unsigned long *pll_ref_freq)
38{
39 struct clk *clk;
40 struct clk **dt_clk;
41 u32 val, pll_ref_div;
42 unsigned osc_idx;
43
44 val = readl_relaxed(clk_base + OSC_CTRL);
45 osc_idx = val >> OSC_CTRL_OSC_FREQ_SHIFT;
46
47 if (osc_idx < num)
48 *osc_freq = input_freqs[osc_idx];
49 else
50 *osc_freq = 0;
51
52 if (!*osc_freq) {
53 WARN_ON(1);
54 return -EINVAL;
55 }
56
57 dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m, tegra_clks);
58 if (!dt_clk)
59 return 0;
60
61 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT,
62 *osc_freq);
63 *dt_clk = clk;
64
65 /* pll_ref */
66 val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3;
67 pll_ref_div = 1 << val;
68 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_ref, tegra_clks);
69 if (!dt_clk)
70 return 0;
71
72 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
73 0, 1, pll_ref_div);
74 *dt_clk = clk;
75
76 if (pll_ref_freq)
77 *pll_ref_freq = *osc_freq / pll_ref_div;
78
79 return 0;
80}
81
82void __init tegra_fixed_clk_init(struct tegra_clk *tegra_clks)
83{
84 struct clk *clk;
85 struct clk **dt_clk;
86
87 /* clk_32k */
88 dt_clk = tegra_lookup_dt_id(tegra_clk_clk_32k, tegra_clks);
89 if (dt_clk) {
90 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL,
91 CLK_IS_ROOT, 32768);
92 *dt_clk = clk;
93 }
94
95 /* clk_m_div2 */
96 dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div2, tegra_clks);
97 if (dt_clk) {
98 clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
99 CLK_SET_RATE_PARENT, 1, 2);
100 *dt_clk = clk;
101 }
102
103 /* clk_m_div4 */
104 dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div4, tegra_clks);
105 if (dt_clk) {
106 clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
107 CLK_SET_RATE_PARENT, 1, 4);
108 *dt_clk = clk;
109 }
110}
111
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
new file mode 100644
index 000000000000..5c35885f4a7c
--- /dev/null
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -0,0 +1,674 @@
1/*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/clk-provider.h>
20#include <linux/clkdev.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/delay.h>
24#include <linux/export.h>
25#include <linux/clk/tegra.h>
26
27#include "clk.h"
28#include "clk-id.h"
29
30#define CLK_SOURCE_I2S0 0x1d8
31#define CLK_SOURCE_I2S1 0x100
32#define CLK_SOURCE_I2S2 0x104
33#define CLK_SOURCE_NDFLASH 0x160
34#define CLK_SOURCE_I2S3 0x3bc
35#define CLK_SOURCE_I2S4 0x3c0
36#define CLK_SOURCE_SPDIF_OUT 0x108
37#define CLK_SOURCE_SPDIF_IN 0x10c
38#define CLK_SOURCE_PWM 0x110
39#define CLK_SOURCE_ADX 0x638
40#define CLK_SOURCE_ADX1 0x670
41#define CLK_SOURCE_AMX 0x63c
42#define CLK_SOURCE_AMX1 0x674
43#define CLK_SOURCE_HDA 0x428
44#define CLK_SOURCE_HDA2CODEC_2X 0x3e4
45#define CLK_SOURCE_SBC1 0x134
46#define CLK_SOURCE_SBC2 0x118
47#define CLK_SOURCE_SBC3 0x11c
48#define CLK_SOURCE_SBC4 0x1b4
49#define CLK_SOURCE_SBC5 0x3c8
50#define CLK_SOURCE_SBC6 0x3cc
51#define CLK_SOURCE_SATA_OOB 0x420
52#define CLK_SOURCE_SATA 0x424
53#define CLK_SOURCE_NDSPEED 0x3f8
54#define CLK_SOURCE_VFIR 0x168
55#define CLK_SOURCE_SDMMC1 0x150
56#define CLK_SOURCE_SDMMC2 0x154
57#define CLK_SOURCE_SDMMC3 0x1bc
58#define CLK_SOURCE_SDMMC4 0x164
59#define CLK_SOURCE_CVE 0x140
60#define CLK_SOURCE_TVO 0x188
61#define CLK_SOURCE_TVDAC 0x194
62#define CLK_SOURCE_VDE 0x1c8
63#define CLK_SOURCE_CSITE 0x1d4
64#define CLK_SOURCE_LA 0x1f8
65#define CLK_SOURCE_TRACE 0x634
66#define CLK_SOURCE_OWR 0x1cc
67#define CLK_SOURCE_NOR 0x1d0
68#define CLK_SOURCE_MIPI 0x174
69#define CLK_SOURCE_I2C1 0x124
70#define CLK_SOURCE_I2C2 0x198
71#define CLK_SOURCE_I2C3 0x1b8
72#define CLK_SOURCE_I2C4 0x3c4
73#define CLK_SOURCE_I2C5 0x128
74#define CLK_SOURCE_I2C6 0x65c
75#define CLK_SOURCE_UARTA 0x178
76#define CLK_SOURCE_UARTB 0x17c
77#define CLK_SOURCE_UARTC 0x1a0
78#define CLK_SOURCE_UARTD 0x1c0
79#define CLK_SOURCE_UARTE 0x1c4
80#define CLK_SOURCE_3D 0x158
81#define CLK_SOURCE_2D 0x15c
82#define CLK_SOURCE_MPE 0x170
83#define CLK_SOURCE_UARTE 0x1c4
84#define CLK_SOURCE_VI_SENSOR 0x1a8
85#define CLK_SOURCE_VI 0x148
86#define CLK_SOURCE_EPP 0x16c
87#define CLK_SOURCE_MSENC 0x1f0
88#define CLK_SOURCE_TSEC 0x1f4
89#define CLK_SOURCE_HOST1X 0x180
90#define CLK_SOURCE_HDMI 0x18c
91#define CLK_SOURCE_DISP1 0x138
92#define CLK_SOURCE_DISP2 0x13c
93#define CLK_SOURCE_CILAB 0x614
94#define CLK_SOURCE_CILCD 0x618
95#define CLK_SOURCE_CILE 0x61c
96#define CLK_SOURCE_DSIALP 0x620
97#define CLK_SOURCE_DSIBLP 0x624
98#define CLK_SOURCE_TSENSOR 0x3b8
99#define CLK_SOURCE_D_AUDIO 0x3d0
100#define CLK_SOURCE_DAM0 0x3d8
101#define CLK_SOURCE_DAM1 0x3dc
102#define CLK_SOURCE_DAM2 0x3e0
103#define CLK_SOURCE_ACTMON 0x3e8
104#define CLK_SOURCE_EXTERN1 0x3ec
105#define CLK_SOURCE_EXTERN2 0x3f0
106#define CLK_SOURCE_EXTERN3 0x3f4
107#define CLK_SOURCE_I2CSLOW 0x3fc
108#define CLK_SOURCE_SE 0x42c
109#define CLK_SOURCE_MSELECT 0x3b4
110#define CLK_SOURCE_DFLL_REF 0x62c
111#define CLK_SOURCE_DFLL_SOC 0x630
112#define CLK_SOURCE_SOC_THERM 0x644
113#define CLK_SOURCE_XUSB_HOST_SRC 0x600
114#define CLK_SOURCE_XUSB_FALCON_SRC 0x604
115#define CLK_SOURCE_XUSB_FS_SRC 0x608
116#define CLK_SOURCE_XUSB_SS_SRC 0x610
117#define CLK_SOURCE_XUSB_DEV_SRC 0x60c
118#define CLK_SOURCE_ISP 0x144
119#define CLK_SOURCE_SOR0 0x414
120#define CLK_SOURCE_DPAUX 0x418
121#define CLK_SOURCE_SATA_OOB 0x420
122#define CLK_SOURCE_SATA 0x424
123#define CLK_SOURCE_ENTROPY 0x628
124#define CLK_SOURCE_VI_SENSOR2 0x658
125#define CLK_SOURCE_HDMI_AUDIO 0x668
126#define CLK_SOURCE_VIC03 0x678
127#define CLK_SOURCE_CLK72MHZ 0x66c
128
129#define MASK(x) (BIT(x) - 1)
130
131#define MUX(_name, _parents, _offset, \
132 _clk_num, _gate_flags, _clk_id) \
133 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
134 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
135 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
136 NULL)
137
138#define MUX_FLAGS(_name, _parents, _offset,\
139 _clk_num, _gate_flags, _clk_id, flags)\
140 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
141 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
142 _clk_num, _gate_flags, _clk_id, _parents##_idx, flags,\
143 NULL)
144
145#define MUX8(_name, _parents, _offset, \
146 _clk_num, _gate_flags, _clk_id) \
147 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
148 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
149 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
150 NULL)
151
152#define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock) \
153 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
154 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
155 0, TEGRA_PERIPH_NO_GATE, _clk_id,\
156 _parents##_idx, 0, _lock)
157
158#define INT(_name, _parents, _offset, \
159 _clk_num, _gate_flags, _clk_id) \
160 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
161 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
162 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
163 _clk_id, _parents##_idx, 0, NULL)
164
165#define INT_FLAGS(_name, _parents, _offset,\
166 _clk_num, _gate_flags, _clk_id, flags)\
167 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
168 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
169 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
170 _clk_id, _parents##_idx, flags, NULL)
171
172#define INT8(_name, _parents, _offset,\
173 _clk_num, _gate_flags, _clk_id) \
174 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
175 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
176 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
177 _clk_id, _parents##_idx, 0, NULL)
178
179#define UART(_name, _parents, _offset,\
180 _clk_num, _clk_id) \
181 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
182 30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART| \
183 TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\
184 _parents##_idx, 0, NULL)
185
186#define I2C(_name, _parents, _offset,\
187 _clk_num, _clk_id) \
188 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
189 30, MASK(2), 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP,\
190 _clk_num, 0, _clk_id, _parents##_idx, 0, NULL)
191
192#define XUSB(_name, _parents, _offset, \
193 _clk_num, _gate_flags, _clk_id) \
194 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
195 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
196 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
197 _clk_id, _parents##_idx, 0, NULL)
198
199#define AUDIO(_name, _offset, _clk_num,\
200 _gate_flags, _clk_id) \
201 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, mux_d_audio_clk, \
202 _offset, 16, 0xE01F, 0, 0, 8, 1, \
203 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags, \
204 _clk_id, mux_d_audio_clk_idx, 0, NULL)
205
206#define NODIV(_name, _parents, _offset, \
207 _mux_shift, _mux_mask, _clk_num, \
208 _gate_flags, _clk_id, _lock) \
209 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
210 _mux_shift, _mux_mask, 0, 0, 0, 0, 0,\
211 _clk_num, (_gate_flags) | TEGRA_PERIPH_NO_DIV,\
212 _clk_id, _parents##_idx, 0, _lock)
213
214#define GATE(_name, _parent_name, \
215 _clk_num, _gate_flags, _clk_id, _flags) \
216 { \
217 .name = _name, \
218 .clk_id = _clk_id, \
219 .p.parent_name = _parent_name, \
220 .periph = TEGRA_CLK_PERIPH(0, 0, 0, 0, 0, 0, 0, \
221 _clk_num, _gate_flags, 0, NULL), \
222 .flags = _flags \
223 }
224
225#define PLLP_BASE 0xa0
226#define PLLP_MISC 0xac
227#define PLLP_OUTA 0xa4
228#define PLLP_OUTB 0xa8
229#define PLLP_OUTC 0x67c
230
231#define PLL_BASE_LOCK BIT(27)
232#define PLL_MISC_LOCK_ENABLE 18
233
234static DEFINE_SPINLOCK(PLLP_OUTA_lock);
235static DEFINE_SPINLOCK(PLLP_OUTB_lock);
236static DEFINE_SPINLOCK(PLLP_OUTC_lock);
237static DEFINE_SPINLOCK(sor0_lock);
238
239#define MUX_I2S_SPDIF(_id) \
240static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \
241 #_id, "pll_p",\
242 "clk_m"};
243MUX_I2S_SPDIF(audio0)
244MUX_I2S_SPDIF(audio1)
245MUX_I2S_SPDIF(audio2)
246MUX_I2S_SPDIF(audio3)
247MUX_I2S_SPDIF(audio4)
248MUX_I2S_SPDIF(audio)
249
250#define mux_pllaout0_audio0_2x_pllp_clkm_idx NULL
251#define mux_pllaout0_audio1_2x_pllp_clkm_idx NULL
252#define mux_pllaout0_audio2_2x_pllp_clkm_idx NULL
253#define mux_pllaout0_audio3_2x_pllp_clkm_idx NULL
254#define mux_pllaout0_audio4_2x_pllp_clkm_idx NULL
255#define mux_pllaout0_audio_2x_pllp_clkm_idx NULL
256
257static const char *mux_pllp_pllc_pllm_clkm[] = {
258 "pll_p", "pll_c", "pll_m", "clk_m"
259};
260#define mux_pllp_pllc_pllm_clkm_idx NULL
261
262static const char *mux_pllp_pllc_pllm[] = { "pll_p", "pll_c", "pll_m" };
263#define mux_pllp_pllc_pllm_idx NULL
264
265static const char *mux_pllp_pllc_clk32_clkm[] = {
266 "pll_p", "pll_c", "clk_32k", "clk_m"
267};
268#define mux_pllp_pllc_clk32_clkm_idx NULL
269
270static const char *mux_plla_pllc_pllp_clkm[] = {
271 "pll_a_out0", "pll_c", "pll_p", "clk_m"
272};
273#define mux_plla_pllc_pllp_clkm_idx mux_pllp_pllc_pllm_clkm_idx
274
275static const char *mux_pllp_pllc2_c_c3_pllm_clkm[] = {
276 "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_m", "clk_m"
277};
278static u32 mux_pllp_pllc2_c_c3_pllm_clkm_idx[] = {
279 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
280};
281
282static const char *mux_pllp_clkm[] = {
283 "pll_p", "clk_m"
284};
285static u32 mux_pllp_clkm_idx[] = {
286 [0] = 0, [1] = 3,
287};
288
289static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = {
290 "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0"
291};
292#define mux_pllm_pllc2_c_c3_pllp_plla_idx mux_pllp_pllc2_c_c3_pllm_clkm_idx
293
294static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
295 "pll_p", "pll_m", "pll_d_out0", "pll_a_out0", "pll_c",
296 "pll_d2_out0", "clk_m"
297};
298#define mux_pllp_pllm_plld_plla_pllc_plld2_clkm_idx NULL
299
300static const char *mux_pllm_pllc_pllp_plla[] = {
301 "pll_m", "pll_c", "pll_p", "pll_a_out0"
302};
303#define mux_pllm_pllc_pllp_plla_idx mux_pllp_pllc_pllm_clkm_idx
304
305static const char *mux_pllp_pllc_clkm[] = {
306 "pll_p", "pll_c", "pll_m"
307};
308static u32 mux_pllp_pllc_clkm_idx[] = {
309 [0] = 0, [1] = 1, [2] = 3,
310};
311
312static const char *mux_pllp_pllc_clkm_clk32[] = {
313 "pll_p", "pll_c", "clk_m", "clk_32k"
314};
315#define mux_pllp_pllc_clkm_clk32_idx NULL
316
317static const char *mux_plla_clk32_pllp_clkm_plle[] = {
318 "pll_a_out0", "clk_32k", "pll_p", "clk_m", "pll_e_out0"
319};
320#define mux_plla_clk32_pllp_clkm_plle_idx NULL
321
322static const char *mux_clkm_pllp_pllc_pllre[] = {
323 "clk_m", "pll_p", "pll_c", "pll_re_out"
324};
325static u32 mux_clkm_pllp_pllc_pllre_idx[] = {
326 [0] = 0, [1] = 1, [2] = 3, [3] = 5,
327};
328
329static const char *mux_clkm_48M_pllp_480M[] = {
330 "clk_m", "pll_u_48M", "pll_p", "pll_u_480M"
331};
332#define mux_clkm_48M_pllp_480M_idx NULL
333
334static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = {
335 "clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref"
336};
337static u32 mux_clkm_pllre_clk32_480M_pllc_ref_idx[] = {
338 [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 4, [5] = 7,
339};
340
341static const char *mux_d_audio_clk[] = {
342 "pll_a_out0", "pll_p", "clk_m", "spdif_in_sync", "i2s0_sync",
343 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",
344};
345static u32 mux_d_audio_clk_idx[] = {
346 [0] = 0, [1] = 0x8000, [2] = 0xc000, [3] = 0xE000, [4] = 0xE001,
347 [5] = 0xE002, [6] = 0xE003, [7] = 0xE004, [8] = 0xE005, [9] = 0xE007,
348};
349
350static const char *mux_pllp_plld_pllc_clkm[] = {
351 "pll_p", "pll_d_out0", "pll_c", "clk_m"
352};
353#define mux_pllp_plld_pllc_clkm_idx NULL
354static const char *mux_pllm_pllc_pllp_plla_clkm_pllc4[] = {
355 "pll_m", "pll_c", "pll_p", "pll_a_out0", "clk_m", "pll_c4",
356};
357static u32 mux_pllm_pllc_pllp_plla_clkm_pllc4_idx[] = {
358 [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 6, [5] = 7,
359};
360
361static const char *mux_pllp_clkm1[] = {
362 "pll_p", "clk_m",
363};
364#define mux_pllp_clkm1_idx NULL
365
366static const char *mux_pllp3_pllc_clkm[] = {
367 "pll_p_out3", "pll_c", "pll_c2", "clk_m",
368};
369#define mux_pllp3_pllc_clkm_idx NULL
370
371static const char *mux_pllm_pllc_pllp_plla_pllc2_c3_clkm[] = {
372 "pll_m", "pll_c", "pll_p", "pll_a", "pll_c2", "pll_c3", "clk_m"
373};
374static u32 mux_pllm_pllc_pllp_plla_pllc2_c3_clkm_idx[] = {
375 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
376};
377
378static const char *mux_pllm_pllc2_c_c3_pllp_plla_pllc4[] = {
379 "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0", "pll_c4",
380};
381static u32 mux_pllm_pllc2_c_c3_pllp_plla_pllc4_idx[] = {
382 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6, [6] = 7,
383};
384
385static const char *mux_clkm_plldp_sor0lvds[] = {
386 "clk_m", "pll_dp", "sor0_lvds",
387};
388#define mux_clkm_plldp_sor0lvds_idx NULL
389
390static struct tegra_periph_init_data periph_clks[] = {
391 AUDIO("d_audio", CLK_SOURCE_D_AUDIO, 106, TEGRA_PERIPH_ON_APB, tegra_clk_d_audio),
392 AUDIO("dam0", CLK_SOURCE_DAM0, 108, TEGRA_PERIPH_ON_APB, tegra_clk_dam0),
393 AUDIO("dam1", CLK_SOURCE_DAM1, 109, TEGRA_PERIPH_ON_APB, tegra_clk_dam1),
394 AUDIO("dam2", CLK_SOURCE_DAM2, 110, TEGRA_PERIPH_ON_APB, tegra_clk_dam2),
395 I2C("i2c1", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, tegra_clk_i2c1),
396 I2C("i2c2", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, tegra_clk_i2c2),
397 I2C("i2c3", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, tegra_clk_i2c3),
398 I2C("i2c4", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, tegra_clk_i2c4),
399 I2C("i2c5", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, tegra_clk_i2c5),
400 INT("vde", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde),
401 INT("vi", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi),
402 INT("epp", mux_pllm_pllc_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp),
403 INT("host1x", mux_pllm_pllc_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x),
404 INT("mpe", mux_pllm_pllc_pllp_plla, CLK_SOURCE_MPE, 60, 0, tegra_clk_mpe),
405 INT("2d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d),
406 INT("3d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d),
407 INT8("vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde_8),
408 INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_8),
409 INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla_pllc4, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_9),
410 INT8("epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp_8),
411 INT8("msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, TEGRA_PERIPH_WAR_1005168, tegra_clk_msenc),
412 INT8("tsec", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, 0, tegra_clk_tsec),
413 INT8("host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x_8),
414 INT8("se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, TEGRA_PERIPH_ON_APB, tegra_clk_se),
415 INT8("2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d_8),
416 INT8("3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d_8),
417 INT8("vic03", mux_pllm_pllc_pllp_plla_pllc2_c3_clkm, CLK_SOURCE_VIC03, 178, 0, tegra_clk_vic03),
418 INT_FLAGS("mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, 0, tegra_clk_mselect, CLK_IGNORE_UNUSED),
419 MUX("i2s0", mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, TEGRA_PERIPH_ON_APB, tegra_clk_i2s0),
420 MUX("i2s1", mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, tegra_clk_i2s1),
421 MUX("i2s2", mux_pllaout0_audio2_2x_pllp_clkm, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, tegra_clk_i2s2),
422 MUX("i2s3", mux_pllaout0_audio3_2x_pllp_clkm, CLK_SOURCE_I2S3, 101, TEGRA_PERIPH_ON_APB, tegra_clk_i2s3),
423 MUX("i2s4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, TEGRA_PERIPH_ON_APB, tegra_clk_i2s4),
424 MUX("spdif_out", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_out),
425 MUX("spdif_in", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_in),
426 MUX("pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, TEGRA_PERIPH_ON_APB, tegra_clk_pwm),
427 MUX("adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, TEGRA_PERIPH_ON_APB, tegra_clk_adx),
428 MUX("amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, TEGRA_PERIPH_ON_APB, tegra_clk_amx),
429 MUX("hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, TEGRA_PERIPH_ON_APB, tegra_clk_hda),
430 MUX("hda2codec_2x", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, tegra_clk_hda2codec_2x),
431 MUX("vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, TEGRA_PERIPH_ON_APB, tegra_clk_vfir),
432 MUX("sdmmc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, 0, tegra_clk_sdmmc1),
433 MUX("sdmmc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, 0, tegra_clk_sdmmc2),
434 MUX("sdmmc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, 0, tegra_clk_sdmmc3),
435 MUX("sdmmc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, 0, tegra_clk_sdmmc4),
436 MUX("la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, TEGRA_PERIPH_ON_APB, tegra_clk_la),
437 MUX("trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, TEGRA_PERIPH_ON_APB, tegra_clk_trace),
438 MUX("owr", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr),
439 MUX("nor", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, 0, tegra_clk_nor),
440 MUX("mipi", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_MIPI, 50, TEGRA_PERIPH_ON_APB, tegra_clk_mipi),
441 MUX("vi_sensor", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor),
442 MUX("cilab", mux_pllp_pllc_clkm, CLK_SOURCE_CILAB, 144, 0, tegra_clk_cilab),
443 MUX("cilcd", mux_pllp_pllc_clkm, CLK_SOURCE_CILCD, 145, 0, tegra_clk_cilcd),
444 MUX("cile", mux_pllp_pllc_clkm, CLK_SOURCE_CILE, 146, 0, tegra_clk_cile),
445 MUX("dsialp", mux_pllp_pllc_clkm, CLK_SOURCE_DSIALP, 147, 0, tegra_clk_dsialp),
446 MUX("dsiblp", mux_pllp_pllc_clkm, CLK_SOURCE_DSIBLP, 148, 0, tegra_clk_dsiblp),
447 MUX("tsensor", mux_pllp_pllc_clkm_clk32, CLK_SOURCE_TSENSOR, 100, TEGRA_PERIPH_ON_APB, tegra_clk_tsensor),
448 MUX("actmon", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_ACTMON, 119, 0, tegra_clk_actmon),
449 MUX("dfll_ref", mux_pllp_clkm, CLK_SOURCE_DFLL_REF, 155, TEGRA_PERIPH_ON_APB, tegra_clk_dfll_ref),
450 MUX("dfll_soc", mux_pllp_clkm, CLK_SOURCE_DFLL_SOC, 155, TEGRA_PERIPH_ON_APB, tegra_clk_dfll_soc),
451 MUX("i2cslow", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_I2CSLOW, 81, TEGRA_PERIPH_ON_APB, tegra_clk_i2cslow),
452 MUX("sbc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1),
453 MUX("sbc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2),
454 MUX("sbc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3),
455 MUX("sbc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4),
456 MUX("sbc5", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, tegra_clk_sbc5),
457 MUX("sbc6", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, tegra_clk_sbc6),
458 MUX("cve", mux_pllp_plld_pllc_clkm, CLK_SOURCE_CVE, 49, 0, tegra_clk_cve),
459 MUX("tvo", mux_pllp_plld_pllc_clkm, CLK_SOURCE_TVO, 49, 0, tegra_clk_tvo),
460 MUX("tvdac", mux_pllp_plld_pllc_clkm, CLK_SOURCE_TVDAC, 53, 0, tegra_clk_tvdac),
461 MUX("ndflash", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash),
462 MUX("ndspeed", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed),
463 MUX("sata_oob", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA_OOB, 123, TEGRA_PERIPH_ON_APB, tegra_clk_sata_oob),
464 MUX("sata", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA, 124, TEGRA_PERIPH_ON_APB, tegra_clk_sata),
465 MUX("adx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX1, 180, TEGRA_PERIPH_ON_APB, tegra_clk_adx1),
466 MUX("amx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX1, 185, TEGRA_PERIPH_ON_APB, tegra_clk_amx1),
467 MUX("vi_sensor2", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR2, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor2),
468 MUX8("sbc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1_8),
469 MUX8("sbc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2_8),
470 MUX8("sbc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3_8),
471 MUX8("sbc4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4_8),
472 MUX8("sbc5", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, tegra_clk_sbc5_8),
473 MUX8("sbc6", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, tegra_clk_sbc6_8),
474 MUX8("ndflash", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash_8),
475 MUX8("ndspeed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed_8),
476 MUX8("hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, 0, tegra_clk_hdmi),
477 MUX8("extern1", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, 0, tegra_clk_extern1),
478 MUX8("extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, 0, tegra_clk_extern2),
479 MUX8("extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, 0, tegra_clk_extern3),
480 MUX8("soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm),
481 MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_8),
482 MUX8("isp", mux_pllm_pllc_pllp_plla_clkm_pllc4, CLK_SOURCE_ISP, 23, TEGRA_PERIPH_ON_APB, tegra_clk_isp_8),
483 MUX8("entropy", mux_pllp_clkm1, CLK_SOURCE_ENTROPY, 149, 0, tegra_clk_entropy),
484 MUX8("hdmi_audio", mux_pllp3_pllc_clkm, CLK_SOURCE_HDMI_AUDIO, 176, TEGRA_PERIPH_NO_RESET, tegra_clk_hdmi_audio),
485 MUX8("clk72mhz", mux_pllp3_pllc_clkm, CLK_SOURCE_CLK72MHZ, 177, TEGRA_PERIPH_NO_RESET, tegra_clk_clk72Mhz),
486 MUX8_NOGATE_LOCK("sor0_lvds", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_SOR0, tegra_clk_sor0_lvds, &sor0_lock),
487 MUX_FLAGS("csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_csite, CLK_IGNORE_UNUSED),
488 NODIV("disp1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, tegra_clk_disp1, NULL),
489 NODIV("disp2", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, tegra_clk_disp2, NULL),
490 NODIV("sor0", mux_clkm_plldp_sor0lvds, CLK_SOURCE_SOR0, 14, 3, 182, 0, tegra_clk_sor0, &sor0_lock),
491 UART("uarta", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, tegra_clk_uarta),
492 UART("uartb", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, tegra_clk_uartb),
493 UART("uartc", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, tegra_clk_uartc),
494 UART("uartd", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, tegra_clk_uartd),
495 UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 65, tegra_clk_uarte),
496 XUSB("xusb_host_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src),
497 XUSB("xusb_falcon_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src),
498 XUSB("xusb_fs_src", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_fs_src),
499 XUSB("xusb_ss_src", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ss_src),
500 XUSB("xusb_dev_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src),
501};
502
503static struct tegra_periph_init_data gate_clks[] = {
504 GATE("rtc", "clk_32k", 4, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_rtc, 0),
505 GATE("timer", "clk_m", 5, 0, tegra_clk_timer, 0),
506 GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0),
507 GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0),
508 GATE("apbdma", "clk_m", 34, 0, tegra_clk_apbdma, 0),
509 GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),
510 GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0),
511 GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0),
512 GATE("kfuse", "clk_m", 40, TEGRA_PERIPH_ON_APB, tegra_clk_kfuse, 0),
513 GATE("apbif", "clk_m", 107, TEGRA_PERIPH_ON_APB, tegra_clk_apbif, 0),
514 GATE("hda2hdmi", "clk_m", 128, TEGRA_PERIPH_ON_APB, tegra_clk_hda2hdmi, 0),
515 GATE("bsea", "clk_m", 62, 0, tegra_clk_bsea, 0),
516 GATE("bsev", "clk_m", 63, 0, tegra_clk_bsev, 0),
517 GATE("mipi-cal", "clk_m", 56, 0, tegra_clk_mipi_cal, 0),
518 GATE("usbd", "clk_m", 22, 0, tegra_clk_usbd, 0),
519 GATE("usb2", "clk_m", 58, 0, tegra_clk_usb2, 0),
520 GATE("usb3", "clk_m", 59, 0, tegra_clk_usb3, 0),
521 GATE("csi", "pll_p_out3", 52, 0, tegra_clk_csi, 0),
522 GATE("afi", "clk_m", 72, 0, tegra_clk_afi, 0),
523 GATE("csus", "clk_m", 92, TEGRA_PERIPH_NO_RESET, tegra_clk_csus, 0),
524 GATE("dds", "clk_m", 150, TEGRA_PERIPH_ON_APB, tegra_clk_dds, 0),
525 GATE("dp2", "clk_m", 152, TEGRA_PERIPH_ON_APB, tegra_clk_dp2, 0),
526 GATE("dtv", "clk_m", 79, TEGRA_PERIPH_ON_APB, tegra_clk_dtv, 0),
527 GATE("xusb_host", "xusb_host_src", 89, 0, tegra_clk_xusb_host, 0),
528 GATE("xusb_ss", "xusb_ss_src", 156, 0, tegra_clk_xusb_ss, 0),
529 GATE("xusb_dev", "xusb_dev_src", 95, 0, tegra_clk_xusb_dev, 0),
530 GATE("dsia", "dsia_mux", 48, 0, tegra_clk_dsia, 0),
531 GATE("dsib", "dsib_mux", 82, 0, tegra_clk_dsib, 0),
532 GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IGNORE_UNUSED),
533 GATE("sata_cold", "clk_m", 129, TEGRA_PERIPH_ON_APB, tegra_clk_sata_cold, 0),
534 GATE("ispb", "clk_m", 3, 0, tegra_clk_ispb, 0),
535 GATE("vim2_clk", "clk_m", 11, 0, tegra_clk_vim2_clk, 0),
536 GATE("pcie", "clk_m", 70, 0, tegra_clk_pcie, 0),
537 GATE("dpaux", "clk_m", 181, 0, tegra_clk_dpaux, 0),
538 GATE("gpu", "pll_ref", 184, 0, tegra_clk_gpu, 0),
539};
540
541struct pll_out_data {
542 char *div_name;
543 char *pll_out_name;
544 u32 offset;
545 int clk_id;
546 u8 div_shift;
547 u8 div_flags;
548 u8 rst_shift;
549 spinlock_t *lock;
550};
551
552#define PLL_OUT(_num, _offset, _div_shift, _div_flags, _rst_shift, _id) \
553 {\
554 .div_name = "pll_p_out" #_num "_div",\
555 .pll_out_name = "pll_p_out" #_num,\
556 .offset = _offset,\
557 .div_shift = _div_shift,\
558 .div_flags = _div_flags | TEGRA_DIVIDER_FIXED |\
559 TEGRA_DIVIDER_ROUND_UP,\
560 .rst_shift = _rst_shift,\
561 .clk_id = tegra_clk_ ## _id,\
562 .lock = &_offset ##_lock,\
563 }
564
565static struct pll_out_data pllp_out_clks[] = {
566 PLL_OUT(1, PLLP_OUTA, 8, 0, 0, pll_p_out1),
567 PLL_OUT(2, PLLP_OUTA, 24, 0, 16, pll_p_out2),
568 PLL_OUT(2, PLLP_OUTA, 24, TEGRA_DIVIDER_INT, 16, pll_p_out2_int),
569 PLL_OUT(3, PLLP_OUTB, 8, 0, 0, pll_p_out3),
570 PLL_OUT(4, PLLP_OUTB, 24, 0, 16, pll_p_out4),
571 PLL_OUT(5, PLLP_OUTC, 24, 0, 16, pll_p_out5),
572};
573
574static void __init periph_clk_init(void __iomem *clk_base,
575 struct tegra_clk *tegra_clks)
576{
577 int i;
578 struct clk *clk;
579 struct clk **dt_clk;
580
581 for (i = 0; i < ARRAY_SIZE(periph_clks); i++) {
582 struct tegra_clk_periph_regs *bank;
583 struct tegra_periph_init_data *data;
584
585 data = periph_clks + i;
586
587 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
588 if (!dt_clk)
589 continue;
590
591 bank = get_reg_bank(data->periph.gate.clk_num);
592 if (!bank)
593 continue;
594
595 data->periph.gate.regs = bank;
596 clk = tegra_clk_register_periph(data->name,
597 data->p.parent_names, data->num_parents,
598 &data->periph, clk_base, data->offset,
599 data->flags);
600 *dt_clk = clk;
601 }
602}
603
604static void __init gate_clk_init(void __iomem *clk_base,
605 struct tegra_clk *tegra_clks)
606{
607 int i;
608 struct clk *clk;
609 struct clk **dt_clk;
610
611 for (i = 0; i < ARRAY_SIZE(gate_clks); i++) {
612 struct tegra_periph_init_data *data;
613
614 data = gate_clks + i;
615
616 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
617 if (!dt_clk)
618 continue;
619
620 clk = tegra_clk_register_periph_gate(data->name,
621 data->p.parent_name, data->periph.gate.flags,
622 clk_base, data->flags,
623 data->periph.gate.clk_num,
624 periph_clk_enb_refcnt);
625 *dt_clk = clk;
626 }
627}
628
629static void __init init_pllp(void __iomem *clk_base, void __iomem *pmc_base,
630 struct tegra_clk *tegra_clks,
631 struct tegra_clk_pll_params *pll_params)
632{
633 struct clk *clk;
634 struct clk **dt_clk;
635 int i;
636
637 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p, tegra_clks);
638 if (dt_clk) {
639 /* PLLP */
640 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base,
641 pmc_base, 0, pll_params, NULL);
642 clk_register_clkdev(clk, "pll_p", NULL);
643 *dt_clk = clk;
644 }
645
646 for (i = 0; i < ARRAY_SIZE(pllp_out_clks); i++) {
647 struct pll_out_data *data;
648
649 data = pllp_out_clks + i;
650
651 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
652 if (!dt_clk)
653 continue;
654
655 clk = tegra_clk_register_divider(data->div_name, "pll_p",
656 clk_base + data->offset, 0, data->div_flags,
657 data->div_shift, 8, 1, data->lock);
658 clk = tegra_clk_register_pll_out(data->pll_out_name,
659 data->div_name, clk_base + data->offset,
660 data->rst_shift + 1, data->rst_shift,
661 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
662 data->lock);
663 *dt_clk = clk;
664 }
665}
666
667void __init tegra_periph_clk_init(void __iomem *clk_base,
668 void __iomem *pmc_base, struct tegra_clk *tegra_clks,
669 struct tegra_clk_pll_params *pll_params)
670{
671 init_pllp(clk_base, pmc_base, tegra_clks, pll_params);
672 periph_clk_init(clk_base, tegra_clks);
673 gate_clk_init(clk_base, tegra_clks);
674}
diff --git a/drivers/clk/tegra/clk-tegra-pmc.c b/drivers/clk/tegra/clk-tegra-pmc.c
new file mode 100644
index 000000000000..08b21c1ee867
--- /dev/null
+++ b/drivers/clk/tegra/clk-tegra-pmc.c
@@ -0,0 +1,132 @@
1/*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/clk-provider.h>
20#include <linux/clkdev.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/delay.h>
24#include <linux/export.h>
25#include <linux/clk/tegra.h>
26
27#include "clk.h"
28#include "clk-id.h"
29
30#define PMC_CLK_OUT_CNTRL 0x1a8
31#define PMC_DPD_PADS_ORIDE 0x1c
32#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
33#define PMC_CTRL 0
34#define PMC_CTRL_BLINK_ENB 7
35#define PMC_BLINK_TIMER 0x40
36
37struct pmc_clk_init_data {
38 char *mux_name;
39 char *gate_name;
40 const char **parents;
41 int num_parents;
42 int mux_id;
43 int gate_id;
44 char *dev_name;
45 u8 mux_shift;
46 u8 gate_shift;
47};
48
49#define PMC_CLK(_num, _mux_shift, _gate_shift)\
50 {\
51 .mux_name = "clk_out_" #_num "_mux",\
52 .gate_name = "clk_out_" #_num,\
53 .parents = clk_out ##_num ##_parents,\
54 .num_parents = ARRAY_SIZE(clk_out ##_num ##_parents),\
55 .mux_id = tegra_clk_clk_out_ ##_num ##_mux,\
56 .gate_id = tegra_clk_clk_out_ ##_num,\
57 .dev_name = "extern" #_num,\
58 .mux_shift = _mux_shift,\
59 .gate_shift = _gate_shift,\
60 }
61
62static DEFINE_SPINLOCK(clk_out_lock);
63
64static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
65 "clk_m_div4", "extern1",
66};
67
68static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
69 "clk_m_div4", "extern2",
70};
71
72static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
73 "clk_m_div4", "extern3",
74};
75
76static struct pmc_clk_init_data pmc_clks[] = {
77 PMC_CLK(1, 6, 2),
78 PMC_CLK(2, 14, 10),
79 PMC_CLK(3, 22, 18),
80};
81
82void __init tegra_pmc_clk_init(void __iomem *pmc_base,
83 struct tegra_clk *tegra_clks)
84{
85 struct clk *clk;
86 struct clk **dt_clk;
87 int i;
88
89 for (i = 0; i < ARRAY_SIZE(pmc_clks); i++) {
90 struct pmc_clk_init_data *data;
91
92 data = pmc_clks + i;
93
94 dt_clk = tegra_lookup_dt_id(data->mux_id, tegra_clks);
95 if (!dt_clk)
96 continue;
97
98 clk = clk_register_mux(NULL, data->mux_name, data->parents,
99 data->num_parents, CLK_SET_RATE_NO_REPARENT,
100 pmc_base + PMC_CLK_OUT_CNTRL, data->mux_shift,
101 3, 0, &clk_out_lock);
102 *dt_clk = clk;
103
104
105 dt_clk = tegra_lookup_dt_id(data->gate_id, tegra_clks);
106 if (!dt_clk)
107 continue;
108
109 clk = clk_register_gate(NULL, data->gate_name, data->mux_name,
110 0, pmc_base + PMC_CLK_OUT_CNTRL,
111 data->gate_shift, 0, &clk_out_lock);
112 *dt_clk = clk;
113 clk_register_clkdev(clk, data->dev_name, data->gate_name);
114 }
115
116 /* blink */
117 writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
118 clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
119 pmc_base + PMC_DPD_PADS_ORIDE,
120 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
121
122 dt_clk = tegra_lookup_dt_id(tegra_clk_blink, tegra_clks);
123 if (!dt_clk)
124 return;
125
126 clk = clk_register_gate(NULL, "blink", "blink_override", 0,
127 pmc_base + PMC_CTRL,
128 PMC_CTRL_BLINK_ENB, 0, NULL);
129 clk_register_clkdev(clk, "blink", NULL);
130 *dt_clk = clk;
131}
132
diff --git a/drivers/clk/tegra/clk-tegra-super-gen4.c b/drivers/clk/tegra/clk-tegra-super-gen4.c
new file mode 100644
index 000000000000..05dce4aa2c11
--- /dev/null
+++ b/drivers/clk/tegra/clk-tegra-super-gen4.c
@@ -0,0 +1,149 @@
1/*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/clk-provider.h>
20#include <linux/of.h>
21#include <linux/of_address.h>
22#include <linux/delay.h>
23#include <linux/export.h>
24#include <linux/clk/tegra.h>
25
26#include "clk.h"
27#include "clk-id.h"
28
29#define PLLX_BASE 0xe0
30#define PLLX_MISC 0xe4
31#define PLLX_MISC2 0x514
32#define PLLX_MISC3 0x518
33
34#define CCLKG_BURST_POLICY 0x368
35#define CCLKLP_BURST_POLICY 0x370
36#define SCLK_BURST_POLICY 0x028
37#define SYSTEM_CLK_RATE 0x030
38
39static DEFINE_SPINLOCK(sysrate_lock);
40
41static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
42 "pll_p", "pll_p_out2", "unused",
43 "clk_32k", "pll_m_out1" };
44
45static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
46 "pll_p", "pll_p_out4", "unused",
47 "unused", "pll_x" };
48
49static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
50 "pll_p", "pll_p_out4", "unused",
51 "unused", "pll_x", "pll_x_out0" };
52
53static void __init tegra_sclk_init(void __iomem *clk_base,
54 struct tegra_clk *tegra_clks)
55{
56 struct clk *clk;
57 struct clk **dt_clk;
58
59 /* SCLK */
60 dt_clk = tegra_lookup_dt_id(tegra_clk_sclk, tegra_clks);
61 if (dt_clk) {
62 clk = tegra_clk_register_super_mux("sclk", sclk_parents,
63 ARRAY_SIZE(sclk_parents),
64 CLK_SET_RATE_PARENT,
65 clk_base + SCLK_BURST_POLICY,
66 0, 4, 0, 0, NULL);
67 *dt_clk = clk;
68 }
69
70 /* HCLK */
71 dt_clk = tegra_lookup_dt_id(tegra_clk_hclk, tegra_clks);
72 if (dt_clk) {
73 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
74 clk_base + SYSTEM_CLK_RATE, 4, 2, 0,
75 &sysrate_lock);
76 clk = clk_register_gate(NULL, "hclk", "hclk_div",
77 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
78 clk_base + SYSTEM_CLK_RATE,
79 7, CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
80 *dt_clk = clk;
81 }
82
83 /* PCLK */
84 dt_clk = tegra_lookup_dt_id(tegra_clk_pclk, tegra_clks);
85 if (!dt_clk)
86 return;
87
88 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
89 clk_base + SYSTEM_CLK_RATE, 0, 2, 0,
90 &sysrate_lock);
91 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT |
92 CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE,
93 3, CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
94 *dt_clk = clk;
95}
96
97void __init tegra_super_clk_gen4_init(void __iomem *clk_base,
98 void __iomem *pmc_base,
99 struct tegra_clk *tegra_clks,
100 struct tegra_clk_pll_params *params)
101{
102 struct clk *clk;
103 struct clk **dt_clk;
104
105 /* CCLKG */
106 dt_clk = tegra_lookup_dt_id(tegra_clk_cclk_g, tegra_clks);
107 if (dt_clk) {
108 clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents,
109 ARRAY_SIZE(cclk_g_parents),
110 CLK_SET_RATE_PARENT,
111 clk_base + CCLKG_BURST_POLICY,
112 0, 4, 0, 0, NULL);
113 *dt_clk = clk;
114 }
115
116 /* CCLKLP */
117 dt_clk = tegra_lookup_dt_id(tegra_clk_cclk_lp, tegra_clks);
118 if (dt_clk) {
119 clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents,
120 ARRAY_SIZE(cclk_lp_parents),
121 CLK_SET_RATE_PARENT,
122 clk_base + CCLKLP_BURST_POLICY,
123 0, 4, 8, 9, NULL);
124 *dt_clk = clk;
125 }
126
127 tegra_sclk_init(clk_base, tegra_clks);
128
129#if defined(CONFIG_ARCH_TEGRA_114_SOC) || defined(CONFIG_ARCH_TEGRA_124_SOC)
130 /* PLLX */
131 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_x, tegra_clks);
132 if (!dt_clk)
133 return;
134
135 clk = tegra_clk_register_pllxc("pll_x", "pll_ref", clk_base,
136 pmc_base, CLK_IGNORE_UNUSED, params, NULL);
137 *dt_clk = clk;
138
139 /* PLLX_OUT0 */
140
141 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_x_out0, tegra_clks);
142 if (!dt_clk)
143 return;
144 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
145 CLK_SET_RATE_PARENT, 1, 2);
146 *dt_clk = clk;
147#endif
148}
149
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 9467da7dee49..29b912582e3d 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -23,30 +23,15 @@
23#include <linux/delay.h> 23#include <linux/delay.h>
24#include <linux/export.h> 24#include <linux/export.h>
25#include <linux/clk/tegra.h> 25#include <linux/clk/tegra.h>
26#include <dt-bindings/clock/tegra114-car.h>
26 27
27#include "clk.h" 28#include "clk.h"
29#include "clk-id.h"
28 30
29#define RST_DEVICES_L 0x004
30#define RST_DEVICES_H 0x008
31#define RST_DEVICES_U 0x00C
32#define RST_DFLL_DVCO 0x2F4 31#define RST_DFLL_DVCO 0x2F4
33#define RST_DEVICES_V 0x358
34#define RST_DEVICES_W 0x35C
35#define RST_DEVICES_X 0x28C
36#define RST_DEVICES_SET_L 0x300
37#define RST_DEVICES_CLR_L 0x304
38#define RST_DEVICES_SET_H 0x308
39#define RST_DEVICES_CLR_H 0x30c
40#define RST_DEVICES_SET_U 0x310
41#define RST_DEVICES_CLR_U 0x314
42#define RST_DEVICES_SET_V 0x430
43#define RST_DEVICES_CLR_V 0x434
44#define RST_DEVICES_SET_W 0x438
45#define RST_DEVICES_CLR_W 0x43c
46#define CPU_FINETRIM_SELECT 0x4d4 /* override default prop dlys */ 32#define CPU_FINETRIM_SELECT 0x4d4 /* override default prop dlys */
47#define CPU_FINETRIM_DR 0x4d8 /* rise->rise prop dly A */ 33#define CPU_FINETRIM_DR 0x4d8 /* rise->rise prop dly A */
48#define CPU_FINETRIM_R 0x4e4 /* rise->rise prop dly inc A */ 34#define CPU_FINETRIM_R 0x4e4 /* rise->rise prop dly inc A */
49#define RST_DEVICES_NUM 5
50 35
51/* RST_DFLL_DVCO bitfields */ 36/* RST_DFLL_DVCO bitfields */
52#define DVFS_DFLL_RESET_SHIFT 0 37#define DVFS_DFLL_RESET_SHIFT 0
@@ -73,25 +58,7 @@
73#define CPU_FINETRIM_R_FCPU_6_SHIFT 10 /* ftop */ 58#define CPU_FINETRIM_R_FCPU_6_SHIFT 10 /* ftop */
74#define CPU_FINETRIM_R_FCPU_6_MASK (0x3 << CPU_FINETRIM_R_FCPU_6_SHIFT) 59#define CPU_FINETRIM_R_FCPU_6_MASK (0x3 << CPU_FINETRIM_R_FCPU_6_SHIFT)
75 60
76#define CLK_OUT_ENB_L 0x010 61#define TEGRA114_CLK_PERIPH_BANKS 5
77#define CLK_OUT_ENB_H 0x014
78#define CLK_OUT_ENB_U 0x018
79#define CLK_OUT_ENB_V 0x360
80#define CLK_OUT_ENB_W 0x364
81#define CLK_OUT_ENB_X 0x280
82#define CLK_OUT_ENB_SET_L 0x320
83#define CLK_OUT_ENB_CLR_L 0x324
84#define CLK_OUT_ENB_SET_H 0x328
85#define CLK_OUT_ENB_CLR_H 0x32c
86#define CLK_OUT_ENB_SET_U 0x330
87#define CLK_OUT_ENB_CLR_U 0x334
88#define CLK_OUT_ENB_SET_V 0x440
89#define CLK_OUT_ENB_CLR_V 0x444
90#define CLK_OUT_ENB_SET_W 0x448
91#define CLK_OUT_ENB_CLR_W 0x44c
92#define CLK_OUT_ENB_SET_X 0x284
93#define CLK_OUT_ENB_CLR_X 0x288
94#define CLK_OUT_ENB_NUM 6
95 62
96#define PLLC_BASE 0x80 63#define PLLC_BASE 0x80
97#define PLLC_MISC2 0x88 64#define PLLC_MISC2 0x88
@@ -139,25 +106,6 @@
139#define PLLE_AUX 0x48c 106#define PLLE_AUX 0x48c
140#define PLLC_OUT 0x84 107#define PLLC_OUT 0x84
141#define PLLM_OUT 0x94 108#define PLLM_OUT 0x94
142#define PLLP_OUTA 0xa4
143#define PLLP_OUTB 0xa8
144#define PLLA_OUT 0xb4
145
146#define AUDIO_SYNC_CLK_I2S0 0x4a0
147#define AUDIO_SYNC_CLK_I2S1 0x4a4
148#define AUDIO_SYNC_CLK_I2S2 0x4a8
149#define AUDIO_SYNC_CLK_I2S3 0x4ac
150#define AUDIO_SYNC_CLK_I2S4 0x4b0
151#define AUDIO_SYNC_CLK_SPDIF 0x4b4
152
153#define AUDIO_SYNC_DOUBLER 0x49c
154
155#define PMC_CLK_OUT_CNTRL 0x1a8
156#define PMC_DPD_PADS_ORIDE 0x1c
157#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
158#define PMC_CTRL 0
159#define PMC_CTRL_BLINK_ENB 7
160#define PMC_BLINK_TIMER 0x40
161 109
162#define OSC_CTRL 0x50 110#define OSC_CTRL 0x50
163#define OSC_CTRL_OSC_FREQ_SHIFT 28 111#define OSC_CTRL_OSC_FREQ_SHIFT 28
@@ -166,9 +114,6 @@
166#define PLLXC_SW_MAX_P 6 114#define PLLXC_SW_MAX_P 6
167 115
168#define CCLKG_BURST_POLICY 0x368 116#define CCLKG_BURST_POLICY 0x368
169#define CCLKLP_BURST_POLICY 0x370
170#define SCLK_BURST_POLICY 0x028
171#define SYSTEM_CLK_RATE 0x030
172 117
173#define UTMIP_PLL_CFG2 0x488 118#define UTMIP_PLL_CFG2 0x488
174#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6) 119#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
@@ -196,91 +141,8 @@
196#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1) 141#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
197#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0) 142#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
198 143
199#define CLK_SOURCE_I2S0 0x1d8
200#define CLK_SOURCE_I2S1 0x100
201#define CLK_SOURCE_I2S2 0x104
202#define CLK_SOURCE_NDFLASH 0x160
203#define CLK_SOURCE_I2S3 0x3bc
204#define CLK_SOURCE_I2S4 0x3c0
205#define CLK_SOURCE_SPDIF_OUT 0x108
206#define CLK_SOURCE_SPDIF_IN 0x10c
207#define CLK_SOURCE_PWM 0x110
208#define CLK_SOURCE_ADX 0x638
209#define CLK_SOURCE_AMX 0x63c
210#define CLK_SOURCE_HDA 0x428
211#define CLK_SOURCE_HDA2CODEC_2X 0x3e4
212#define CLK_SOURCE_SBC1 0x134
213#define CLK_SOURCE_SBC2 0x118
214#define CLK_SOURCE_SBC3 0x11c
215#define CLK_SOURCE_SBC4 0x1b4
216#define CLK_SOURCE_SBC5 0x3c8
217#define CLK_SOURCE_SBC6 0x3cc
218#define CLK_SOURCE_SATA_OOB 0x420
219#define CLK_SOURCE_SATA 0x424
220#define CLK_SOURCE_NDSPEED 0x3f8
221#define CLK_SOURCE_VFIR 0x168
222#define CLK_SOURCE_SDMMC1 0x150
223#define CLK_SOURCE_SDMMC2 0x154
224#define CLK_SOURCE_SDMMC3 0x1bc
225#define CLK_SOURCE_SDMMC4 0x164
226#define CLK_SOURCE_VDE 0x1c8
227#define CLK_SOURCE_CSITE 0x1d4 144#define CLK_SOURCE_CSITE 0x1d4
228#define CLK_SOURCE_LA 0x1f8
229#define CLK_SOURCE_TRACE 0x634
230#define CLK_SOURCE_OWR 0x1cc
231#define CLK_SOURCE_NOR 0x1d0
232#define CLK_SOURCE_MIPI 0x174
233#define CLK_SOURCE_I2C1 0x124
234#define CLK_SOURCE_I2C2 0x198
235#define CLK_SOURCE_I2C3 0x1b8
236#define CLK_SOURCE_I2C4 0x3c4
237#define CLK_SOURCE_I2C5 0x128
238#define CLK_SOURCE_UARTA 0x178
239#define CLK_SOURCE_UARTB 0x17c
240#define CLK_SOURCE_UARTC 0x1a0
241#define CLK_SOURCE_UARTD 0x1c0
242#define CLK_SOURCE_UARTE 0x1c4
243#define CLK_SOURCE_UARTA_DBG 0x178
244#define CLK_SOURCE_UARTB_DBG 0x17c
245#define CLK_SOURCE_UARTC_DBG 0x1a0
246#define CLK_SOURCE_UARTD_DBG 0x1c0
247#define CLK_SOURCE_UARTE_DBG 0x1c4
248#define CLK_SOURCE_3D 0x158
249#define CLK_SOURCE_2D 0x15c
250#define CLK_SOURCE_VI_SENSOR 0x1a8
251#define CLK_SOURCE_VI 0x148
252#define CLK_SOURCE_EPP 0x16c
253#define CLK_SOURCE_MSENC 0x1f0
254#define CLK_SOURCE_TSEC 0x1f4
255#define CLK_SOURCE_HOST1X 0x180
256#define CLK_SOURCE_HDMI 0x18c
257#define CLK_SOURCE_DISP1 0x138
258#define CLK_SOURCE_DISP2 0x13c
259#define CLK_SOURCE_CILAB 0x614
260#define CLK_SOURCE_CILCD 0x618
261#define CLK_SOURCE_CILE 0x61c
262#define CLK_SOURCE_DSIALP 0x620
263#define CLK_SOURCE_DSIBLP 0x624
264#define CLK_SOURCE_TSENSOR 0x3b8
265#define CLK_SOURCE_D_AUDIO 0x3d0
266#define CLK_SOURCE_DAM0 0x3d8
267#define CLK_SOURCE_DAM1 0x3dc
268#define CLK_SOURCE_DAM2 0x3e0
269#define CLK_SOURCE_ACTMON 0x3e8
270#define CLK_SOURCE_EXTERN1 0x3ec
271#define CLK_SOURCE_EXTERN2 0x3f0
272#define CLK_SOURCE_EXTERN3 0x3f4
273#define CLK_SOURCE_I2CSLOW 0x3fc
274#define CLK_SOURCE_SE 0x42c
275#define CLK_SOURCE_MSELECT 0x3b4
276#define CLK_SOURCE_DFLL_REF 0x62c
277#define CLK_SOURCE_DFLL_SOC 0x630
278#define CLK_SOURCE_SOC_THERM 0x644
279#define CLK_SOURCE_XUSB_HOST_SRC 0x600
280#define CLK_SOURCE_XUSB_FALCON_SRC 0x604
281#define CLK_SOURCE_XUSB_FS_SRC 0x608
282#define CLK_SOURCE_XUSB_SS_SRC 0x610 145#define CLK_SOURCE_XUSB_SS_SRC 0x610
283#define CLK_SOURCE_XUSB_DEV_SRC 0x60c
284#define CLK_SOURCE_EMC 0x19c 146#define CLK_SOURCE_EMC 0x19c
285 147
286/* PLLM override registers */ 148/* PLLM override registers */
@@ -298,19 +160,13 @@ static struct cpu_clk_suspend_context {
298} tegra114_cpu_clk_sctx; 160} tegra114_cpu_clk_sctx;
299#endif 161#endif
300 162
301static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
302
303static void __iomem *clk_base; 163static void __iomem *clk_base;
304static void __iomem *pmc_base; 164static void __iomem *pmc_base;
305 165
306static DEFINE_SPINLOCK(pll_d_lock); 166static DEFINE_SPINLOCK(pll_d_lock);
307static DEFINE_SPINLOCK(pll_d2_lock); 167static DEFINE_SPINLOCK(pll_d2_lock);
308static DEFINE_SPINLOCK(pll_u_lock); 168static DEFINE_SPINLOCK(pll_u_lock);
309static DEFINE_SPINLOCK(pll_div_lock);
310static DEFINE_SPINLOCK(pll_re_lock); 169static DEFINE_SPINLOCK(pll_re_lock);
311static DEFINE_SPINLOCK(clk_doubler_lock);
312static DEFINE_SPINLOCK(clk_out_lock);
313static DEFINE_SPINLOCK(sysrate_lock);
314 170
315static struct div_nmp pllxc_nmp = { 171static struct div_nmp pllxc_nmp = {
316 .divm_shift = 0, 172 .divm_shift = 0,
@@ -370,6 +226,8 @@ static struct tegra_clk_pll_params pll_c_params = {
370 .stepb_shift = 9, 226 .stepb_shift = 9,
371 .pdiv_tohw = pllxc_p, 227 .pdiv_tohw = pllxc_p,
372 .div_nmp = &pllxc_nmp, 228 .div_nmp = &pllxc_nmp,
229 .freq_table = pll_c_freq_table,
230 .flags = TEGRA_PLL_USE_LOCK,
373}; 231};
374 232
375static struct div_nmp pllcx_nmp = { 233static struct div_nmp pllcx_nmp = {
@@ -417,6 +275,8 @@ static struct tegra_clk_pll_params pll_c2_params = {
417 .ext_misc_reg[0] = 0x4f0, 275 .ext_misc_reg[0] = 0x4f0,
418 .ext_misc_reg[1] = 0x4f4, 276 .ext_misc_reg[1] = 0x4f4,
419 .ext_misc_reg[2] = 0x4f8, 277 .ext_misc_reg[2] = 0x4f8,
278 .freq_table = pll_cx_freq_table,
279 .flags = TEGRA_PLL_USE_LOCK,
420}; 280};
421 281
422static struct tegra_clk_pll_params pll_c3_params = { 282static struct tegra_clk_pll_params pll_c3_params = {
@@ -437,6 +297,8 @@ static struct tegra_clk_pll_params pll_c3_params = {
437 .ext_misc_reg[0] = 0x504, 297 .ext_misc_reg[0] = 0x504,
438 .ext_misc_reg[1] = 0x508, 298 .ext_misc_reg[1] = 0x508,
439 .ext_misc_reg[2] = 0x50c, 299 .ext_misc_reg[2] = 0x50c,
300 .freq_table = pll_cx_freq_table,
301 .flags = TEGRA_PLL_USE_LOCK,
440}; 302};
441 303
442static struct div_nmp pllm_nmp = { 304static struct div_nmp pllm_nmp = {
@@ -483,6 +345,8 @@ static struct tegra_clk_pll_params pll_m_params = {
483 .div_nmp = &pllm_nmp, 345 .div_nmp = &pllm_nmp,
484 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE, 346 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
485 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2, 347 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
348 .freq_table = pll_m_freq_table,
349 .flags = TEGRA_PLL_USE_LOCK,
486}; 350};
487 351
488static struct div_nmp pllp_nmp = { 352static struct div_nmp pllp_nmp = {
@@ -516,6 +380,9 @@ static struct tegra_clk_pll_params pll_p_params = {
516 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 380 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
517 .lock_delay = 300, 381 .lock_delay = 300,
518 .div_nmp = &pllp_nmp, 382 .div_nmp = &pllp_nmp,
383 .freq_table = pll_p_freq_table,
384 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK,
385 .fixed_rate = 408000000,
519}; 386};
520 387
521static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 388static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
@@ -543,6 +410,8 @@ static struct tegra_clk_pll_params pll_a_params = {
543 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 410 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
544 .lock_delay = 300, 411 .lock_delay = 300,
545 .div_nmp = &pllp_nmp, 412 .div_nmp = &pllp_nmp,
413 .freq_table = pll_a_freq_table,
414 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
546}; 415};
547 416
548static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 417static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
@@ -579,6 +448,9 @@ static struct tegra_clk_pll_params pll_d_params = {
579 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 448 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
580 .lock_delay = 1000, 449 .lock_delay = 1000,
581 .div_nmp = &pllp_nmp, 450 .div_nmp = &pllp_nmp,
451 .freq_table = pll_d_freq_table,
452 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
453 TEGRA_PLL_USE_LOCK,
582}; 454};
583 455
584static struct tegra_clk_pll_params pll_d2_params = { 456static struct tegra_clk_pll_params pll_d2_params = {
@@ -594,6 +466,9 @@ static struct tegra_clk_pll_params pll_d2_params = {
594 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 466 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
595 .lock_delay = 1000, 467 .lock_delay = 1000,
596 .div_nmp = &pllp_nmp, 468 .div_nmp = &pllp_nmp,
469 .freq_table = pll_d_freq_table,
470 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
471 TEGRA_PLL_USE_LOCK,
597}; 472};
598 473
599static struct pdiv_map pllu_p[] = { 474static struct pdiv_map pllu_p[] = {
@@ -634,6 +509,9 @@ static struct tegra_clk_pll_params pll_u_params = {
634 .lock_delay = 1000, 509 .lock_delay = 1000,
635 .pdiv_tohw = pllu_p, 510 .pdiv_tohw = pllu_p,
636 .div_nmp = &pllu_nmp, 511 .div_nmp = &pllu_nmp,
512 .freq_table = pll_u_freq_table,
513 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
514 TEGRA_PLL_USE_LOCK,
637}; 515};
638 516
639static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 517static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
@@ -667,12 +545,15 @@ static struct tegra_clk_pll_params pll_x_params = {
667 .stepb_shift = 24, 545 .stepb_shift = 24,
668 .pdiv_tohw = pllxc_p, 546 .pdiv_tohw = pllxc_p,
669 .div_nmp = &pllxc_nmp, 547 .div_nmp = &pllxc_nmp,
548 .freq_table = pll_x_freq_table,
549 .flags = TEGRA_PLL_USE_LOCK,
670}; 550};
671 551
672static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 552static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
673 /* PLLE special case: use cpcon field to store cml divider value */ 553 /* PLLE special case: use cpcon field to store cml divider value */
674 {336000000, 100000000, 100, 21, 16, 11}, 554 {336000000, 100000000, 100, 21, 16, 11},
675 {312000000, 100000000, 200, 26, 24, 13}, 555 {312000000, 100000000, 200, 26, 24, 13},
556 {12000000, 100000000, 200, 1, 24, 13},
676 {0, 0, 0, 0, 0, 0}, 557 {0, 0, 0, 0, 0, 0},
677}; 558};
678 559
@@ -699,6 +580,9 @@ static struct tegra_clk_pll_params pll_e_params = {
699 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 580 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
700 .lock_delay = 300, 581 .lock_delay = 300,
701 .div_nmp = &plle_nmp, 582 .div_nmp = &plle_nmp,
583 .freq_table = pll_e_freq_table,
584 .flags = TEGRA_PLL_FIXED,
585 .fixed_rate = 100000000,
702}; 586};
703 587
704static struct div_nmp pllre_nmp = { 588static struct div_nmp pllre_nmp = {
@@ -725,53 +609,7 @@ static struct tegra_clk_pll_params pll_re_vco_params = {
725 .iddq_reg = PLLRE_MISC, 609 .iddq_reg = PLLRE_MISC,
726 .iddq_bit_idx = PLLRE_IDDQ_BIT, 610 .iddq_bit_idx = PLLRE_IDDQ_BIT,
727 .div_nmp = &pllre_nmp, 611 .div_nmp = &pllre_nmp,
728}; 612 .flags = TEGRA_PLL_USE_LOCK,
729
730/* Peripheral clock registers */
731
732static struct tegra_clk_periph_regs periph_l_regs = {
733 .enb_reg = CLK_OUT_ENB_L,
734 .enb_set_reg = CLK_OUT_ENB_SET_L,
735 .enb_clr_reg = CLK_OUT_ENB_CLR_L,
736 .rst_reg = RST_DEVICES_L,
737 .rst_set_reg = RST_DEVICES_SET_L,
738 .rst_clr_reg = RST_DEVICES_CLR_L,
739};
740
741static struct tegra_clk_periph_regs periph_h_regs = {
742 .enb_reg = CLK_OUT_ENB_H,
743 .enb_set_reg = CLK_OUT_ENB_SET_H,
744 .enb_clr_reg = CLK_OUT_ENB_CLR_H,
745 .rst_reg = RST_DEVICES_H,
746 .rst_set_reg = RST_DEVICES_SET_H,
747 .rst_clr_reg = RST_DEVICES_CLR_H,
748};
749
750static struct tegra_clk_periph_regs periph_u_regs = {
751 .enb_reg = CLK_OUT_ENB_U,
752 .enb_set_reg = CLK_OUT_ENB_SET_U,
753 .enb_clr_reg = CLK_OUT_ENB_CLR_U,
754 .rst_reg = RST_DEVICES_U,
755 .rst_set_reg = RST_DEVICES_SET_U,
756 .rst_clr_reg = RST_DEVICES_CLR_U,
757};
758
759static struct tegra_clk_periph_regs periph_v_regs = {
760 .enb_reg = CLK_OUT_ENB_V,
761 .enb_set_reg = CLK_OUT_ENB_SET_V,
762 .enb_clr_reg = CLK_OUT_ENB_CLR_V,
763 .rst_reg = RST_DEVICES_V,
764 .rst_set_reg = RST_DEVICES_SET_V,
765 .rst_clr_reg = RST_DEVICES_CLR_V,
766};
767
768static struct tegra_clk_periph_regs periph_w_regs = {
769 .enb_reg = CLK_OUT_ENB_W,
770 .enb_set_reg = CLK_OUT_ENB_SET_W,
771 .enb_clr_reg = CLK_OUT_ENB_CLR_W,
772 .rst_reg = RST_DEVICES_W,
773 .rst_set_reg = RST_DEVICES_SET_W,
774 .rst_clr_reg = RST_DEVICES_CLR_W,
775}; 613};
776 614
777/* possible OSC frequencies in Hz */ 615/* possible OSC frequencies in Hz */
@@ -787,120 +625,6 @@ static unsigned long tegra114_input_freq[] = {
787 625
788#define MASK(x) (BIT(x) - 1) 626#define MASK(x) (BIT(x) - 1)
789 627
790#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \
791 _clk_num, _regs, _gate_flags, _clk_id) \
792 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
793 30, MASK(2), 0, 0, 8, 1, 0, _regs, _clk_num, \
794 periph_clk_enb_refcnt, _gate_flags, _clk_id, \
795 _parents##_idx, 0)
796
797#define TEGRA_INIT_DATA_MUX_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\
798 _clk_num, _regs, _gate_flags, _clk_id, flags)\
799 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
800 30, MASK(2), 0, 0, 8, 1, 0, _regs, _clk_num, \
801 periph_clk_enb_refcnt, _gate_flags, _clk_id, \
802 _parents##_idx, flags)
803
804#define TEGRA_INIT_DATA_MUX8(_name, _con_id, _dev_id, _parents, _offset, \
805 _clk_num, _regs, _gate_flags, _clk_id) \
806 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
807 29, MASK(3), 0, 0, 8, 1, 0, _regs, _clk_num, \
808 periph_clk_enb_refcnt, _gate_flags, _clk_id, \
809 _parents##_idx, 0)
810
811#define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \
812 _clk_num, _regs, _gate_flags, _clk_id) \
813 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
814 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\
815 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
816 _clk_id, _parents##_idx, 0)
817
818#define TEGRA_INIT_DATA_INT_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\
819 _clk_num, _regs, _gate_flags, _clk_id, flags)\
820 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
821 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\
822 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
823 _clk_id, _parents##_idx, flags)
824
825#define TEGRA_INIT_DATA_INT8(_name, _con_id, _dev_id, _parents, _offset,\
826 _clk_num, _regs, _gate_flags, _clk_id) \
827 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
828 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\
829 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
830 _clk_id, _parents##_idx, 0)
831
832#define TEGRA_INIT_DATA_UART(_name, _con_id, _dev_id, _parents, _offset,\
833 _clk_num, _regs, _clk_id) \
834 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
835 30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART, _regs,\
836 _clk_num, periph_clk_enb_refcnt, 0, _clk_id, \
837 _parents##_idx, 0)
838
839#define TEGRA_INIT_DATA_I2C(_name, _con_id, _dev_id, _parents, _offset,\
840 _clk_num, _regs, _clk_id) \
841 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
842 30, MASK(2), 0, 0, 16, 0, 0, _regs, _clk_num, \
843 periph_clk_enb_refcnt, 0, _clk_id, _parents##_idx, 0)
844
845#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \
846 _mux_shift, _mux_mask, _clk_num, _regs, \
847 _gate_flags, _clk_id) \
848 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
849 _mux_shift, _mux_mask, 0, 0, 0, 0, 0, _regs, \
850 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
851 _clk_id, _parents##_idx, 0)
852
853#define TEGRA_INIT_DATA_XUSB(_name, _con_id, _dev_id, _parents, _offset, \
854 _clk_num, _regs, _gate_flags, _clk_id) \
855 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset, \
856 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs, \
857 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
858 _clk_id, _parents##_idx, 0)
859
860#define TEGRA_INIT_DATA_AUDIO(_name, _con_id, _dev_id, _offset, _clk_num,\
861 _regs, _gate_flags, _clk_id) \
862 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, mux_d_audio_clk, \
863 _offset, 16, 0xE01F, 0, 0, 8, 1, 0, _regs, _clk_num, \
864 periph_clk_enb_refcnt, _gate_flags , _clk_id, \
865 mux_d_audio_clk_idx, 0)
866
867enum tegra114_clk {
868 rtc = 4, timer = 5, uarta = 6, sdmmc2 = 9, i2s1 = 11, i2c1 = 12,
869 ndflash = 13, sdmmc1 = 14, sdmmc4 = 15, pwm = 17, i2s2 = 18, epp = 19,
870 gr_2d = 21, usbd = 22, isp = 23, gr_3d = 24, disp2 = 26, disp1 = 27,
871 host1x = 28, vcp = 29, i2s0 = 30, apbdma = 34, kbc = 36, kfuse = 40,
872 sbc1 = 41, nor = 42, sbc2 = 44, sbc3 = 46, i2c5 = 47, dsia = 48,
873 mipi = 50, hdmi = 51, csi = 52, i2c2 = 54, uartc = 55, mipi_cal = 56,
874 emc, usb2, usb3, vde = 61, bsea = 62, bsev = 63, uartd = 65,
875 i2c3 = 67, sbc4 = 68, sdmmc3 = 69, owr = 71, csite = 73,
876 la = 76, trace = 77, soc_therm = 78, dtv = 79, ndspeed = 80,
877 i2cslow = 81, dsib = 82, tsec = 83, xusb_host = 89, msenc = 91,
878 csus = 92, mselect = 99, tsensor = 100, i2s3 = 101, i2s4 = 102,
879 i2c4 = 103, sbc5 = 104, sbc6 = 105, d_audio, apbif = 107, dam0, dam1,
880 dam2, hda2codec_2x = 111, audio0_2x = 113, audio1_2x, audio2_2x,
881 audio3_2x, audio4_2x, spdif_2x, actmon = 119, extern1 = 120,
882 extern2 = 121, extern3 = 122, hda = 125, se = 127, hda2hdmi = 128,
883 cilab = 144, cilcd = 145, cile = 146, dsialp = 147, dsiblp = 148,
884 dds = 150, dp2 = 152, amx = 153, adx = 154, xusb_ss = 156, uartb = 192,
885 vfir, spdif_in, spdif_out, vi, vi_sensor, fuse, fuse_burn, clk_32k,
886 clk_m, clk_m_div2, clk_m_div4, pll_ref, pll_c, pll_c_out1, pll_c2,
887 pll_c3, pll_m, pll_m_out1, pll_p, pll_p_out1, pll_p_out2, pll_p_out3,
888 pll_p_out4, pll_a, pll_a_out0, pll_d, pll_d_out0, pll_d2, pll_d2_out0,
889 pll_u, pll_u_480M, pll_u_60M, pll_u_48M, pll_u_12M, pll_x, pll_x_out0,
890 pll_re_vco, pll_re_out, pll_e_out0, spdif_in_sync, i2s0_sync,
891 i2s1_sync, i2s2_sync, i2s3_sync, i2s4_sync, vimclk_sync, audio0,
892 audio1, audio2, audio3, audio4, spdif, clk_out_1, clk_out_2, clk_out_3,
893 blink, xusb_host_src = 252, xusb_falcon_src, xusb_fs_src, xusb_ss_src,
894 xusb_dev_src, xusb_dev, xusb_hs_src, sclk, hclk, pclk, cclk_g, cclk_lp,
895 dfll_ref = 264, dfll_soc,
896
897 /* Mux clocks */
898
899 audio0_mux = 300, audio1_mux, audio2_mux, audio3_mux, audio4_mux,
900 spdif_mux, clk_out_1_mux, clk_out_2_mux, clk_out_3_mux, dsia_mux,
901 dsib_mux, clk_max,
902};
903
904struct utmi_clk_param { 628struct utmi_clk_param {
905 /* Oscillator Frequency in KHz */ 629 /* Oscillator Frequency in KHz */
906 u32 osc_frequency; 630 u32 osc_frequency;
@@ -934,122 +658,11 @@ static const struct utmi_clk_param utmi_parameters[] = {
934 658
935/* peripheral mux definitions */ 659/* peripheral mux definitions */
936 660
937#define MUX_I2S_SPDIF(_id) \
938static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \
939 #_id, "pll_p",\
940 "clk_m"};
941MUX_I2S_SPDIF(audio0)
942MUX_I2S_SPDIF(audio1)
943MUX_I2S_SPDIF(audio2)
944MUX_I2S_SPDIF(audio3)
945MUX_I2S_SPDIF(audio4)
946MUX_I2S_SPDIF(audio)
947
948#define mux_pllaout0_audio0_2x_pllp_clkm_idx NULL
949#define mux_pllaout0_audio1_2x_pllp_clkm_idx NULL
950#define mux_pllaout0_audio2_2x_pllp_clkm_idx NULL
951#define mux_pllaout0_audio3_2x_pllp_clkm_idx NULL
952#define mux_pllaout0_audio4_2x_pllp_clkm_idx NULL
953#define mux_pllaout0_audio_2x_pllp_clkm_idx NULL
954
955static const char *mux_pllp_pllc_pllm_clkm[] = {
956 "pll_p", "pll_c", "pll_m", "clk_m"
957};
958#define mux_pllp_pllc_pllm_clkm_idx NULL
959
960static const char *mux_pllp_pllc_pllm[] = { "pll_p", "pll_c", "pll_m" };
961#define mux_pllp_pllc_pllm_idx NULL
962
963static const char *mux_pllp_pllc_clk32_clkm[] = {
964 "pll_p", "pll_c", "clk_32k", "clk_m"
965};
966#define mux_pllp_pllc_clk32_clkm_idx NULL
967
968static const char *mux_plla_pllc_pllp_clkm[] = {
969 "pll_a_out0", "pll_c", "pll_p", "clk_m"
970};
971#define mux_plla_pllc_pllp_clkm_idx mux_pllp_pllc_pllm_clkm_idx
972
973static const char *mux_pllp_pllc2_c_c3_pllm_clkm[] = {
974 "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_m", "clk_m"
975};
976static u32 mux_pllp_pllc2_c_c3_pllm_clkm_idx[] = {
977 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
978};
979
980static const char *mux_pllp_clkm[] = {
981 "pll_p", "clk_m"
982};
983static u32 mux_pllp_clkm_idx[] = {
984 [0] = 0, [1] = 3,
985};
986
987static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = {
988 "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0"
989};
990#define mux_pllm_pllc2_c_c3_pllp_plla_idx mux_pllp_pllc2_c_c3_pllm_clkm_idx
991
992static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
993 "pll_p", "pll_m", "pll_d_out0", "pll_a_out0", "pll_c",
994 "pll_d2_out0", "clk_m"
995};
996#define mux_pllp_pllm_plld_plla_pllc_plld2_clkm_idx NULL
997
998static const char *mux_pllm_pllc_pllp_plla[] = {
999 "pll_m", "pll_c", "pll_p", "pll_a_out0"
1000};
1001#define mux_pllm_pllc_pllp_plla_idx mux_pllp_pllc_pllm_clkm_idx
1002
1003static const char *mux_pllp_pllc_clkm[] = {
1004 "pll_p", "pll_c", "pll_m"
1005};
1006static u32 mux_pllp_pllc_clkm_idx[] = {
1007 [0] = 0, [1] = 1, [2] = 3,
1008};
1009
1010static const char *mux_pllp_pllc_clkm_clk32[] = {
1011 "pll_p", "pll_c", "clk_m", "clk_32k"
1012};
1013#define mux_pllp_pllc_clkm_clk32_idx NULL
1014
1015static const char *mux_plla_clk32_pllp_clkm_plle[] = {
1016 "pll_a_out0", "clk_32k", "pll_p", "clk_m", "pll_e_out0"
1017};
1018#define mux_plla_clk32_pllp_clkm_plle_idx NULL
1019
1020static const char *mux_clkm_pllp_pllc_pllre[] = {
1021 "clk_m", "pll_p", "pll_c", "pll_re_out"
1022};
1023static u32 mux_clkm_pllp_pllc_pllre_idx[] = {
1024 [0] = 0, [1] = 1, [2] = 3, [3] = 5,
1025};
1026
1027static const char *mux_clkm_48M_pllp_480M[] = {
1028 "clk_m", "pll_u_48M", "pll_p", "pll_u_480M"
1029};
1030#define mux_clkm_48M_pllp_480M_idx NULL
1031
1032static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = {
1033 "clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref"
1034};
1035static u32 mux_clkm_pllre_clk32_480M_pllc_ref_idx[] = {
1036 [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 4, [5] = 7,
1037};
1038
1039static const char *mux_plld_out0_plld2_out0[] = { 661static const char *mux_plld_out0_plld2_out0[] = {
1040 "pll_d_out0", "pll_d2_out0", 662 "pll_d_out0", "pll_d2_out0",
1041}; 663};
1042#define mux_plld_out0_plld2_out0_idx NULL 664#define mux_plld_out0_plld2_out0_idx NULL
1043 665
1044static const char *mux_d_audio_clk[] = {
1045 "pll_a_out0", "pll_p", "clk_m", "spdif_in_sync", "i2s0_sync",
1046 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",
1047};
1048static u32 mux_d_audio_clk_idx[] = {
1049 [0] = 0, [1] = 0x8000, [2] = 0xc000, [3] = 0xE000, [4] = 0xE001,
1050 [5] = 0xE002, [6] = 0xE003, [7] = 0xE004, [8] = 0xE005, [9] = 0xE007,
1051};
1052
1053static const char *mux_pllmcp_clkm[] = { 666static const char *mux_pllmcp_clkm[] = {
1054 "pll_m_out0", "pll_c_out0", "pll_p_out0", "clk_m", "pll_m_ud", 667 "pll_m_out0", "pll_c_out0", "pll_p_out0", "clk_m", "pll_m_ud",
1055}; 668};
@@ -1064,8 +677,253 @@ static const struct clk_div_table pll_re_div_table[] = {
1064 { .val = 0, .div = 0 }, 677 { .val = 0, .div = 0 },
1065}; 678};
1066 679
1067static struct clk *clks[clk_max]; 680static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
1068static struct clk_onecell_data clk_data; 681 [tegra_clk_rtc] = { .dt_id = TEGRA114_CLK_RTC, .present = true },
682 [tegra_clk_timer] = { .dt_id = TEGRA114_CLK_TIMER, .present = true },
683 [tegra_clk_uarta] = { .dt_id = TEGRA114_CLK_UARTA, .present = true },
684 [tegra_clk_uartd] = { .dt_id = TEGRA114_CLK_UARTD, .present = true },
685 [tegra_clk_sdmmc2] = { .dt_id = TEGRA114_CLK_SDMMC2, .present = true },
686 [tegra_clk_i2s1] = { .dt_id = TEGRA114_CLK_I2S1, .present = true },
687 [tegra_clk_i2c1] = { .dt_id = TEGRA114_CLK_I2C1, .present = true },
688 [tegra_clk_ndflash] = { .dt_id = TEGRA114_CLK_NDFLASH, .present = true },
689 [tegra_clk_sdmmc1] = { .dt_id = TEGRA114_CLK_SDMMC1, .present = true },
690 [tegra_clk_sdmmc4] = { .dt_id = TEGRA114_CLK_SDMMC4, .present = true },
691 [tegra_clk_pwm] = { .dt_id = TEGRA114_CLK_PWM, .present = true },
692 [tegra_clk_i2s0] = { .dt_id = TEGRA114_CLK_I2S0, .present = true },
693 [tegra_clk_i2s2] = { .dt_id = TEGRA114_CLK_I2S2, .present = true },
694 [tegra_clk_epp_8] = { .dt_id = TEGRA114_CLK_EPP, .present = true },
695 [tegra_clk_gr2d_8] = { .dt_id = TEGRA114_CLK_GR2D, .present = true },
696 [tegra_clk_usbd] = { .dt_id = TEGRA114_CLK_USBD, .present = true },
697 [tegra_clk_isp] = { .dt_id = TEGRA114_CLK_ISP, .present = true },
698 [tegra_clk_gr3d_8] = { .dt_id = TEGRA114_CLK_GR3D, .present = true },
699 [tegra_clk_disp2] = { .dt_id = TEGRA114_CLK_DISP2, .present = true },
700 [tegra_clk_disp1] = { .dt_id = TEGRA114_CLK_DISP1, .present = true },
701 [tegra_clk_host1x_8] = { .dt_id = TEGRA114_CLK_HOST1X, .present = true },
702 [tegra_clk_vcp] = { .dt_id = TEGRA114_CLK_VCP, .present = true },
703 [tegra_clk_apbdma] = { .dt_id = TEGRA114_CLK_APBDMA, .present = true },
704 [tegra_clk_kbc] = { .dt_id = TEGRA114_CLK_KBC, .present = true },
705 [tegra_clk_kfuse] = { .dt_id = TEGRA114_CLK_KFUSE, .present = true },
706 [tegra_clk_sbc1_8] = { .dt_id = TEGRA114_CLK_SBC1, .present = true },
707 [tegra_clk_nor] = { .dt_id = TEGRA114_CLK_NOR, .present = true },
708 [tegra_clk_sbc2_8] = { .dt_id = TEGRA114_CLK_SBC2, .present = true },
709 [tegra_clk_sbc3_8] = { .dt_id = TEGRA114_CLK_SBC3, .present = true },
710 [tegra_clk_i2c5] = { .dt_id = TEGRA114_CLK_I2C5, .present = true },
711 [tegra_clk_dsia] = { .dt_id = TEGRA114_CLK_DSIA, .present = true },
712 [tegra_clk_mipi] = { .dt_id = TEGRA114_CLK_MIPI, .present = true },
713 [tegra_clk_hdmi] = { .dt_id = TEGRA114_CLK_HDMI, .present = true },
714 [tegra_clk_csi] = { .dt_id = TEGRA114_CLK_CSI, .present = true },
715 [tegra_clk_i2c2] = { .dt_id = TEGRA114_CLK_I2C2, .present = true },
716 [tegra_clk_uartc] = { .dt_id = TEGRA114_CLK_UARTC, .present = true },
717 [tegra_clk_mipi_cal] = { .dt_id = TEGRA114_CLK_MIPI_CAL, .present = true },
718 [tegra_clk_emc] = { .dt_id = TEGRA114_CLK_EMC, .present = true },
719 [tegra_clk_usb2] = { .dt_id = TEGRA114_CLK_USB2, .present = true },
720 [tegra_clk_usb3] = { .dt_id = TEGRA114_CLK_USB3, .present = true },
721 [tegra_clk_vde_8] = { .dt_id = TEGRA114_CLK_VDE, .present = true },
722 [tegra_clk_bsea] = { .dt_id = TEGRA114_CLK_BSEA, .present = true },
723 [tegra_clk_bsev] = { .dt_id = TEGRA114_CLK_BSEV, .present = true },
724 [tegra_clk_i2c3] = { .dt_id = TEGRA114_CLK_I2C3, .present = true },
725 [tegra_clk_sbc4_8] = { .dt_id = TEGRA114_CLK_SBC4, .present = true },
726 [tegra_clk_sdmmc3] = { .dt_id = TEGRA114_CLK_SDMMC3, .present = true },
727 [tegra_clk_owr] = { .dt_id = TEGRA114_CLK_OWR, .present = true },
728 [tegra_clk_csite] = { .dt_id = TEGRA114_CLK_CSITE, .present = true },
729 [tegra_clk_la] = { .dt_id = TEGRA114_CLK_LA, .present = true },
730 [tegra_clk_trace] = { .dt_id = TEGRA114_CLK_TRACE, .present = true },
731 [tegra_clk_soc_therm] = { .dt_id = TEGRA114_CLK_SOC_THERM, .present = true },
732 [tegra_clk_dtv] = { .dt_id = TEGRA114_CLK_DTV, .present = true },
733 [tegra_clk_ndspeed] = { .dt_id = TEGRA114_CLK_NDSPEED, .present = true },
734 [tegra_clk_i2cslow] = { .dt_id = TEGRA114_CLK_I2CSLOW, .present = true },
735 [tegra_clk_dsib] = { .dt_id = TEGRA114_CLK_DSIB, .present = true },
736 [tegra_clk_tsec] = { .dt_id = TEGRA114_CLK_TSEC, .present = true },
737 [tegra_clk_xusb_host] = { .dt_id = TEGRA114_CLK_XUSB_HOST, .present = true },
738 [tegra_clk_msenc] = { .dt_id = TEGRA114_CLK_MSENC, .present = true },
739 [tegra_clk_csus] = { .dt_id = TEGRA114_CLK_CSUS, .present = true },
740 [tegra_clk_mselect] = { .dt_id = TEGRA114_CLK_MSELECT, .present = true },
741 [tegra_clk_tsensor] = { .dt_id = TEGRA114_CLK_TSENSOR, .present = true },
742 [tegra_clk_i2s3] = { .dt_id = TEGRA114_CLK_I2S3, .present = true },
743 [tegra_clk_i2s4] = { .dt_id = TEGRA114_CLK_I2S4, .present = true },
744 [tegra_clk_i2c4] = { .dt_id = TEGRA114_CLK_I2C4, .present = true },
745 [tegra_clk_sbc5_8] = { .dt_id = TEGRA114_CLK_SBC5, .present = true },
746 [tegra_clk_sbc6_8] = { .dt_id = TEGRA114_CLK_SBC6, .present = true },
747 [tegra_clk_d_audio] = { .dt_id = TEGRA114_CLK_D_AUDIO, .present = true },
748 [tegra_clk_apbif] = { .dt_id = TEGRA114_CLK_APBIF, .present = true },
749 [tegra_clk_dam0] = { .dt_id = TEGRA114_CLK_DAM0, .present = true },
750 [tegra_clk_dam1] = { .dt_id = TEGRA114_CLK_DAM1, .present = true },
751 [tegra_clk_dam2] = { .dt_id = TEGRA114_CLK_DAM2, .present = true },
752 [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA114_CLK_HDA2CODEC_2X, .present = true },
753 [tegra_clk_audio0_2x] = { .dt_id = TEGRA114_CLK_AUDIO0_2X, .present = true },
754 [tegra_clk_audio1_2x] = { .dt_id = TEGRA114_CLK_AUDIO1_2X, .present = true },
755 [tegra_clk_audio2_2x] = { .dt_id = TEGRA114_CLK_AUDIO2_2X, .present = true },
756 [tegra_clk_audio3_2x] = { .dt_id = TEGRA114_CLK_AUDIO3_2X, .present = true },
757 [tegra_clk_audio4_2x] = { .dt_id = TEGRA114_CLK_AUDIO4_2X, .present = true },
758 [tegra_clk_spdif_2x] = { .dt_id = TEGRA114_CLK_SPDIF_2X, .present = true },
759 [tegra_clk_actmon] = { .dt_id = TEGRA114_CLK_ACTMON, .present = true },
760 [tegra_clk_extern1] = { .dt_id = TEGRA114_CLK_EXTERN1, .present = true },
761 [tegra_clk_extern2] = { .dt_id = TEGRA114_CLK_EXTERN2, .present = true },
762 [tegra_clk_extern3] = { .dt_id = TEGRA114_CLK_EXTERN3, .present = true },
763 [tegra_clk_hda] = { .dt_id = TEGRA114_CLK_HDA, .present = true },
764 [tegra_clk_se] = { .dt_id = TEGRA114_CLK_SE, .present = true },
765 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA114_CLK_HDA2HDMI, .present = true },
766 [tegra_clk_cilab] = { .dt_id = TEGRA114_CLK_CILAB, .present = true },
767 [tegra_clk_cilcd] = { .dt_id = TEGRA114_CLK_CILCD, .present = true },
768 [tegra_clk_cile] = { .dt_id = TEGRA114_CLK_CILE, .present = true },
769 [tegra_clk_dsialp] = { .dt_id = TEGRA114_CLK_DSIALP, .present = true },
770 [tegra_clk_dsiblp] = { .dt_id = TEGRA114_CLK_DSIBLP, .present = true },
771 [tegra_clk_dds] = { .dt_id = TEGRA114_CLK_DDS, .present = true },
772 [tegra_clk_dp2] = { .dt_id = TEGRA114_CLK_DP2, .present = true },
773 [tegra_clk_amx] = { .dt_id = TEGRA114_CLK_AMX, .present = true },
774 [tegra_clk_adx] = { .dt_id = TEGRA114_CLK_ADX, .present = true },
775 [tegra_clk_xusb_ss] = { .dt_id = TEGRA114_CLK_XUSB_SS, .present = true },
776 [tegra_clk_uartb] = { .dt_id = TEGRA114_CLK_UARTB, .present = true },
777 [tegra_clk_vfir] = { .dt_id = TEGRA114_CLK_VFIR, .present = true },
778 [tegra_clk_spdif_in] = { .dt_id = TEGRA114_CLK_SPDIF_IN, .present = true },
779 [tegra_clk_spdif_out] = { .dt_id = TEGRA114_CLK_SPDIF_OUT, .present = true },
780 [tegra_clk_vi_8] = { .dt_id = TEGRA114_CLK_VI, .present = true },
781 [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA114_CLK_VI_SENSOR, .present = true },
782 [tegra_clk_fuse] = { .dt_id = TEGRA114_CLK_FUSE, .present = true },
783 [tegra_clk_fuse_burn] = { .dt_id = TEGRA114_CLK_FUSE_BURN, .present = true },
784 [tegra_clk_clk_32k] = { .dt_id = TEGRA114_CLK_CLK_32K, .present = true },
785 [tegra_clk_clk_m] = { .dt_id = TEGRA114_CLK_CLK_M, .present = true },
786 [tegra_clk_clk_m_div2] = { .dt_id = TEGRA114_CLK_CLK_M_DIV2, .present = true },
787 [tegra_clk_clk_m_div4] = { .dt_id = TEGRA114_CLK_CLK_M_DIV4, .present = true },
788 [tegra_clk_pll_ref] = { .dt_id = TEGRA114_CLK_PLL_REF, .present = true },
789 [tegra_clk_pll_c] = { .dt_id = TEGRA114_CLK_PLL_C, .present = true },
790 [tegra_clk_pll_c_out1] = { .dt_id = TEGRA114_CLK_PLL_C_OUT1, .present = true },
791 [tegra_clk_pll_c2] = { .dt_id = TEGRA114_CLK_PLL_C2, .present = true },
792 [tegra_clk_pll_c3] = { .dt_id = TEGRA114_CLK_PLL_C3, .present = true },
793 [tegra_clk_pll_m] = { .dt_id = TEGRA114_CLK_PLL_M, .present = true },
794 [tegra_clk_pll_m_out1] = { .dt_id = TEGRA114_CLK_PLL_M_OUT1, .present = true },
795 [tegra_clk_pll_p] = { .dt_id = TEGRA114_CLK_PLL_P, .present = true },
796 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA114_CLK_PLL_P_OUT1, .present = true },
797 [tegra_clk_pll_p_out2_int] = { .dt_id = TEGRA114_CLK_PLL_P_OUT2, .present = true },
798 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA114_CLK_PLL_P_OUT3, .present = true },
799 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA114_CLK_PLL_P_OUT4, .present = true },
800 [tegra_clk_pll_a] = { .dt_id = TEGRA114_CLK_PLL_A, .present = true },
801 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA114_CLK_PLL_A_OUT0, .present = true },
802 [tegra_clk_pll_d] = { .dt_id = TEGRA114_CLK_PLL_D, .present = true },
803 [tegra_clk_pll_d_out0] = { .dt_id = TEGRA114_CLK_PLL_D_OUT0, .present = true },
804 [tegra_clk_pll_d2] = { .dt_id = TEGRA114_CLK_PLL_D2, .present = true },
805 [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA114_CLK_PLL_D2_OUT0, .present = true },
806 [tegra_clk_pll_u] = { .dt_id = TEGRA114_CLK_PLL_U, .present = true },
807 [tegra_clk_pll_u_480m] = { .dt_id = TEGRA114_CLK_PLL_U_480M, .present = true },
808 [tegra_clk_pll_u_60m] = { .dt_id = TEGRA114_CLK_PLL_U_60M, .present = true },
809 [tegra_clk_pll_u_48m] = { .dt_id = TEGRA114_CLK_PLL_U_48M, .present = true },
810 [tegra_clk_pll_u_12m] = { .dt_id = TEGRA114_CLK_PLL_U_12M, .present = true },
811 [tegra_clk_pll_x] = { .dt_id = TEGRA114_CLK_PLL_X, .present = true },
812 [tegra_clk_pll_x_out0] = { .dt_id = TEGRA114_CLK_PLL_X_OUT0, .present = true },
813 [tegra_clk_pll_re_vco] = { .dt_id = TEGRA114_CLK_PLL_RE_VCO, .present = true },
814 [tegra_clk_pll_re_out] = { .dt_id = TEGRA114_CLK_PLL_RE_OUT, .present = true },
815 [tegra_clk_pll_e_out0] = { .dt_id = TEGRA114_CLK_PLL_E_OUT0, .present = true },
816 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA114_CLK_SPDIF_IN_SYNC, .present = true },
817 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA114_CLK_I2S0_SYNC, .present = true },
818 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA114_CLK_I2S1_SYNC, .present = true },
819 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA114_CLK_I2S2_SYNC, .present = true },
820 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA114_CLK_I2S3_SYNC, .present = true },
821 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA114_CLK_I2S4_SYNC, .present = true },
822 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA114_CLK_VIMCLK_SYNC, .present = true },
823 [tegra_clk_audio0] = { .dt_id = TEGRA114_CLK_AUDIO0, .present = true },
824 [tegra_clk_audio1] = { .dt_id = TEGRA114_CLK_AUDIO1, .present = true },
825 [tegra_clk_audio2] = { .dt_id = TEGRA114_CLK_AUDIO2, .present = true },
826 [tegra_clk_audio3] = { .dt_id = TEGRA114_CLK_AUDIO3, .present = true },
827 [tegra_clk_audio4] = { .dt_id = TEGRA114_CLK_AUDIO4, .present = true },
828 [tegra_clk_spdif] = { .dt_id = TEGRA114_CLK_SPDIF, .present = true },
829 [tegra_clk_clk_out_1] = { .dt_id = TEGRA114_CLK_CLK_OUT_1, .present = true },
830 [tegra_clk_clk_out_2] = { .dt_id = TEGRA114_CLK_CLK_OUT_2, .present = true },
831 [tegra_clk_clk_out_3] = { .dt_id = TEGRA114_CLK_CLK_OUT_3, .present = true },
832 [tegra_clk_blink] = { .dt_id = TEGRA114_CLK_BLINK, .present = true },
833 [tegra_clk_xusb_host_src] = { .dt_id = TEGRA114_CLK_XUSB_HOST_SRC, .present = true },
834 [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA114_CLK_XUSB_FALCON_SRC, .present = true },
835 [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA114_CLK_XUSB_FS_SRC, .present = true },
836 [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA114_CLK_XUSB_SS_SRC, .present = true },
837 [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA114_CLK_XUSB_DEV_SRC, .present = true },
838 [tegra_clk_xusb_dev] = { .dt_id = TEGRA114_CLK_XUSB_DEV, .present = true },
839 [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA114_CLK_XUSB_HS_SRC, .present = true },
840 [tegra_clk_sclk] = { .dt_id = TEGRA114_CLK_SCLK, .present = true },
841 [tegra_clk_hclk] = { .dt_id = TEGRA114_CLK_HCLK, .present = true },
842 [tegra_clk_pclk] = { .dt_id = TEGRA114_CLK_PCLK, .present = true },
843 [tegra_clk_cclk_g] = { .dt_id = TEGRA114_CLK_CCLK_G, .present = true },
844 [tegra_clk_cclk_lp] = { .dt_id = TEGRA114_CLK_CCLK_LP, .present = true },
845 [tegra_clk_dfll_ref] = { .dt_id = TEGRA114_CLK_DFLL_REF, .present = true },
846 [tegra_clk_dfll_soc] = { .dt_id = TEGRA114_CLK_DFLL_SOC, .present = true },
847 [tegra_clk_audio0_mux] = { .dt_id = TEGRA114_CLK_AUDIO0_MUX, .present = true },
848 [tegra_clk_audio1_mux] = { .dt_id = TEGRA114_CLK_AUDIO1_MUX, .present = true },
849 [tegra_clk_audio2_mux] = { .dt_id = TEGRA114_CLK_AUDIO2_MUX, .present = true },
850 [tegra_clk_audio3_mux] = { .dt_id = TEGRA114_CLK_AUDIO3_MUX, .present = true },
851 [tegra_clk_audio4_mux] = { .dt_id = TEGRA114_CLK_AUDIO4_MUX, .present = true },
852 [tegra_clk_spdif_mux] = { .dt_id = TEGRA114_CLK_SPDIF_MUX, .present = true },
853 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_1_MUX, .present = true },
854 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_2_MUX, .present = true },
855 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_3_MUX, .present = true },
856 [tegra_clk_dsia_mux] = { .dt_id = TEGRA114_CLK_DSIA_MUX, .present = true },
857 [tegra_clk_dsib_mux] = { .dt_id = TEGRA114_CLK_DSIB_MUX, .present = true },
858};
859
860static struct tegra_devclk devclks[] __initdata = {
861 { .con_id = "clk_m", .dt_id = TEGRA114_CLK_CLK_M },
862 { .con_id = "pll_ref", .dt_id = TEGRA114_CLK_PLL_REF },
863 { .con_id = "clk_32k", .dt_id = TEGRA114_CLK_CLK_32K },
864 { .con_id = "clk_m_div2", .dt_id = TEGRA114_CLK_CLK_M_DIV2 },
865 { .con_id = "clk_m_div4", .dt_id = TEGRA114_CLK_CLK_M_DIV4 },
866 { .con_id = "pll_c", .dt_id = TEGRA114_CLK_PLL_C },
867 { .con_id = "pll_c_out1", .dt_id = TEGRA114_CLK_PLL_C_OUT1 },
868 { .con_id = "pll_c2", .dt_id = TEGRA114_CLK_PLL_C2 },
869 { .con_id = "pll_c3", .dt_id = TEGRA114_CLK_PLL_C3 },
870 { .con_id = "pll_p", .dt_id = TEGRA114_CLK_PLL_P },
871 { .con_id = "pll_p_out1", .dt_id = TEGRA114_CLK_PLL_P_OUT1 },
872 { .con_id = "pll_p_out2", .dt_id = TEGRA114_CLK_PLL_P_OUT2 },
873 { .con_id = "pll_p_out3", .dt_id = TEGRA114_CLK_PLL_P_OUT3 },
874 { .con_id = "pll_p_out4", .dt_id = TEGRA114_CLK_PLL_P_OUT4 },
875 { .con_id = "pll_m", .dt_id = TEGRA114_CLK_PLL_M },
876 { .con_id = "pll_m_out1", .dt_id = TEGRA114_CLK_PLL_M_OUT1 },
877 { .con_id = "pll_x", .dt_id = TEGRA114_CLK_PLL_X },
878 { .con_id = "pll_x_out0", .dt_id = TEGRA114_CLK_PLL_X_OUT0 },
879 { .con_id = "pll_u", .dt_id = TEGRA114_CLK_PLL_U },
880 { .con_id = "pll_u_480M", .dt_id = TEGRA114_CLK_PLL_U_480M },
881 { .con_id = "pll_u_60M", .dt_id = TEGRA114_CLK_PLL_U_60M },
882 { .con_id = "pll_u_48M", .dt_id = TEGRA114_CLK_PLL_U_48M },
883 { .con_id = "pll_u_12M", .dt_id = TEGRA114_CLK_PLL_U_12M },
884 { .con_id = "pll_d", .dt_id = TEGRA114_CLK_PLL_D },
885 { .con_id = "pll_d_out0", .dt_id = TEGRA114_CLK_PLL_D_OUT0 },
886 { .con_id = "pll_d2", .dt_id = TEGRA114_CLK_PLL_D2 },
887 { .con_id = "pll_d2_out0", .dt_id = TEGRA114_CLK_PLL_D2_OUT0 },
888 { .con_id = "pll_a", .dt_id = TEGRA114_CLK_PLL_A },
889 { .con_id = "pll_a_out0", .dt_id = TEGRA114_CLK_PLL_A_OUT0 },
890 { .con_id = "pll_re_vco", .dt_id = TEGRA114_CLK_PLL_RE_VCO },
891 { .con_id = "pll_re_out", .dt_id = TEGRA114_CLK_PLL_RE_OUT },
892 { .con_id = "pll_e_out0", .dt_id = TEGRA114_CLK_PLL_E_OUT0 },
893 { .con_id = "spdif_in_sync", .dt_id = TEGRA114_CLK_SPDIF_IN_SYNC },
894 { .con_id = "i2s0_sync", .dt_id = TEGRA114_CLK_I2S0_SYNC },
895 { .con_id = "i2s1_sync", .dt_id = TEGRA114_CLK_I2S1_SYNC },
896 { .con_id = "i2s2_sync", .dt_id = TEGRA114_CLK_I2S2_SYNC },
897 { .con_id = "i2s3_sync", .dt_id = TEGRA114_CLK_I2S3_SYNC },
898 { .con_id = "i2s4_sync", .dt_id = TEGRA114_CLK_I2S4_SYNC },
899 { .con_id = "vimclk_sync", .dt_id = TEGRA114_CLK_VIMCLK_SYNC },
900 { .con_id = "audio0", .dt_id = TEGRA114_CLK_AUDIO0 },
901 { .con_id = "audio1", .dt_id = TEGRA114_CLK_AUDIO1 },
902 { .con_id = "audio2", .dt_id = TEGRA114_CLK_AUDIO2 },
903 { .con_id = "audio3", .dt_id = TEGRA114_CLK_AUDIO3 },
904 { .con_id = "audio4", .dt_id = TEGRA114_CLK_AUDIO4 },
905 { .con_id = "spdif", .dt_id = TEGRA114_CLK_SPDIF },
906 { .con_id = "audio0_2x", .dt_id = TEGRA114_CLK_AUDIO0_2X },
907 { .con_id = "audio1_2x", .dt_id = TEGRA114_CLK_AUDIO1_2X },
908 { .con_id = "audio2_2x", .dt_id = TEGRA114_CLK_AUDIO2_2X },
909 { .con_id = "audio3_2x", .dt_id = TEGRA114_CLK_AUDIO3_2X },
910 { .con_id = "audio4_2x", .dt_id = TEGRA114_CLK_AUDIO4_2X },
911 { .con_id = "spdif_2x", .dt_id = TEGRA114_CLK_SPDIF_2X },
912 { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA114_CLK_EXTERN1 },
913 { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA114_CLK_EXTERN2 },
914 { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA114_CLK_EXTERN3 },
915 { .con_id = "blink", .dt_id = TEGRA114_CLK_BLINK },
916 { .con_id = "cclk_g", .dt_id = TEGRA114_CLK_CCLK_G },
917 { .con_id = "cclk_lp", .dt_id = TEGRA114_CLK_CCLK_LP },
918 { .con_id = "sclk", .dt_id = TEGRA114_CLK_SCLK },
919 { .con_id = "hclk", .dt_id = TEGRA114_CLK_HCLK },
920 { .con_id = "pclk", .dt_id = TEGRA114_CLK_PCLK },
921 { .con_id = "fuse", .dt_id = TEGRA114_CLK_FUSE },
922 { .dev_id = "rtc-tegra", .dt_id = TEGRA114_CLK_RTC },
923 { .dev_id = "timer", .dt_id = TEGRA114_CLK_TIMER },
924};
925
926static struct clk **clks;
1069 927
1070static unsigned long osc_freq; 928static unsigned long osc_freq;
1071static unsigned long pll_ref_freq; 929static unsigned long pll_ref_freq;
@@ -1086,16 +944,14 @@ static int __init tegra114_osc_clk_init(void __iomem *clk_base)
1086 /* clk_m */ 944 /* clk_m */
1087 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT, 945 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT,
1088 osc_freq); 946 osc_freq);
1089 clk_register_clkdev(clk, "clk_m", NULL); 947 clks[TEGRA114_CLK_CLK_M] = clk;
1090 clks[clk_m] = clk;
1091 948
1092 /* pll_ref */ 949 /* pll_ref */
1093 val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3; 950 val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3;
1094 pll_ref_div = 1 << val; 951 pll_ref_div = 1 << val;
1095 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m", 952 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
1096 CLK_SET_RATE_PARENT, 1, pll_ref_div); 953 CLK_SET_RATE_PARENT, 1, pll_ref_div);
1097 clk_register_clkdev(clk, "pll_ref", NULL); 954 clks[TEGRA114_CLK_PLL_REF] = clk;
1098 clks[pll_ref] = clk;
1099 955
1100 pll_ref_freq = osc_freq / pll_ref_div; 956 pll_ref_freq = osc_freq / pll_ref_div;
1101 957
@@ -1109,20 +965,17 @@ static void __init tegra114_fixed_clk_init(void __iomem *clk_base)
1109 /* clk_32k */ 965 /* clk_32k */
1110 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT, 966 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT,
1111 32768); 967 32768);
1112 clk_register_clkdev(clk, "clk_32k", NULL); 968 clks[TEGRA114_CLK_CLK_32K] = clk;
1113 clks[clk_32k] = clk;
1114 969
1115 /* clk_m_div2 */ 970 /* clk_m_div2 */
1116 clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m", 971 clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
1117 CLK_SET_RATE_PARENT, 1, 2); 972 CLK_SET_RATE_PARENT, 1, 2);
1118 clk_register_clkdev(clk, "clk_m_div2", NULL); 973 clks[TEGRA114_CLK_CLK_M_DIV2] = clk;
1119 clks[clk_m_div2] = clk;
1120 974
1121 /* clk_m_div4 */ 975 /* clk_m_div4 */
1122 clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m", 976 clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
1123 CLK_SET_RATE_PARENT, 1, 4); 977 CLK_SET_RATE_PARENT, 1, 4);
1124 clk_register_clkdev(clk, "clk_m_div4", NULL); 978 clks[TEGRA114_CLK_CLK_M_DIV4] = clk;
1125 clks[clk_m_div4] = clk;
1126 979
1127} 980}
1128 981
@@ -1208,63 +1061,6 @@ static __init void tegra114_utmi_param_configure(void __iomem *clk_base)
1208 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); 1061 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1209} 1062}
1210 1063
1211static void __init _clip_vco_min(struct tegra_clk_pll_params *pll_params)
1212{
1213 pll_params->vco_min =
1214 DIV_ROUND_UP(pll_params->vco_min, pll_ref_freq) * pll_ref_freq;
1215}
1216
1217static int __init _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
1218 void __iomem *clk_base)
1219{
1220 u32 val;
1221 u32 step_a, step_b;
1222
1223 switch (pll_ref_freq) {
1224 case 12000000:
1225 case 13000000:
1226 case 26000000:
1227 step_a = 0x2B;
1228 step_b = 0x0B;
1229 break;
1230 case 16800000:
1231 step_a = 0x1A;
1232 step_b = 0x09;
1233 break;
1234 case 19200000:
1235 step_a = 0x12;
1236 step_b = 0x08;
1237 break;
1238 default:
1239 pr_err("%s: Unexpected reference rate %lu\n",
1240 __func__, pll_ref_freq);
1241 WARN_ON(1);
1242 return -EINVAL;
1243 }
1244
1245 val = step_a << pll_params->stepa_shift;
1246 val |= step_b << pll_params->stepb_shift;
1247 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
1248
1249 return 0;
1250}
1251
1252static void __init _init_iddq(struct tegra_clk_pll_params *pll_params,
1253 void __iomem *clk_base)
1254{
1255 u32 val, val_iddq;
1256
1257 val = readl_relaxed(clk_base + pll_params->base_reg);
1258 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
1259
1260 if (val & BIT(30))
1261 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
1262 else {
1263 val_iddq |= BIT(pll_params->iddq_bit_idx);
1264 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
1265 }
1266}
1267
1268static void __init tegra114_pll_init(void __iomem *clk_base, 1064static void __init tegra114_pll_init(void __iomem *clk_base,
1269 void __iomem *pmc) 1065 void __iomem *pmc)
1270{ 1066{
@@ -1272,104 +1068,34 @@ static void __init tegra114_pll_init(void __iomem *clk_base,
1272 struct clk *clk; 1068 struct clk *clk;
1273 1069
1274 /* PLLC */ 1070 /* PLLC */
1275 _clip_vco_min(&pll_c_params); 1071 clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,
1276 if (_setup_dynamic_ramp(&pll_c_params, clk_base) >= 0) { 1072 pmc, 0, &pll_c_params, NULL);
1277 _init_iddq(&pll_c_params, clk_base); 1073 clks[TEGRA114_CLK_PLL_C] = clk;
1278 clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base, 1074
1279 pmc, 0, 0, &pll_c_params, TEGRA_PLL_USE_LOCK, 1075 /* PLLC_OUT1 */
1280 pll_c_freq_table, NULL); 1076 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
1281 clk_register_clkdev(clk, "pll_c", NULL); 1077 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1282 clks[pll_c] = clk; 1078 8, 8, 1, NULL);
1283 1079 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
1284 /* PLLC_OUT1 */ 1080 clk_base + PLLC_OUT, 1, 0,
1285 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", 1081 CLK_SET_RATE_PARENT, 0, NULL);
1286 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 1082 clks[TEGRA114_CLK_PLL_C_OUT1] = clk;
1287 8, 8, 1, NULL);
1288 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
1289 clk_base + PLLC_OUT, 1, 0,
1290 CLK_SET_RATE_PARENT, 0, NULL);
1291 clk_register_clkdev(clk, "pll_c_out1", NULL);
1292 clks[pll_c_out1] = clk;
1293 }
1294 1083
1295 /* PLLC2 */ 1084 /* PLLC2 */
1296 _clip_vco_min(&pll_c2_params); 1085 clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0,
1297 clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0, 0, 1086 &pll_c2_params, NULL);
1298 &pll_c2_params, TEGRA_PLL_USE_LOCK, 1087 clks[TEGRA114_CLK_PLL_C2] = clk;
1299 pll_cx_freq_table, NULL);
1300 clk_register_clkdev(clk, "pll_c2", NULL);
1301 clks[pll_c2] = clk;
1302 1088
1303 /* PLLC3 */ 1089 /* PLLC3 */
1304 _clip_vco_min(&pll_c3_params); 1090 clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0,
1305 clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0, 0, 1091 &pll_c3_params, NULL);
1306 &pll_c3_params, TEGRA_PLL_USE_LOCK, 1092 clks[TEGRA114_CLK_PLL_C3] = clk;
1307 pll_cx_freq_table, NULL);
1308 clk_register_clkdev(clk, "pll_c3", NULL);
1309 clks[pll_c3] = clk;
1310
1311 /* PLLP */
1312 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, pmc, 0,
1313 408000000, &pll_p_params,
1314 TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK,
1315 pll_p_freq_table, NULL);
1316 clk_register_clkdev(clk, "pll_p", NULL);
1317 clks[pll_p] = clk;
1318
1319 /* PLLP_OUT1 */
1320 clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p",
1321 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
1322 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, &pll_div_lock);
1323 clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div",
1324 clk_base + PLLP_OUTA, 1, 0,
1325 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
1326 &pll_div_lock);
1327 clk_register_clkdev(clk, "pll_p_out1", NULL);
1328 clks[pll_p_out1] = clk;
1329
1330 /* PLLP_OUT2 */
1331 clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p",
1332 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
1333 TEGRA_DIVIDER_ROUND_UP | TEGRA_DIVIDER_INT, 24,
1334 8, 1, &pll_div_lock);
1335 clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div",
1336 clk_base + PLLP_OUTA, 17, 16,
1337 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
1338 &pll_div_lock);
1339 clk_register_clkdev(clk, "pll_p_out2", NULL);
1340 clks[pll_p_out2] = clk;
1341
1342 /* PLLP_OUT3 */
1343 clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p",
1344 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED |
1345 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, &pll_div_lock);
1346 clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div",
1347 clk_base + PLLP_OUTB, 1, 0,
1348 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
1349 &pll_div_lock);
1350 clk_register_clkdev(clk, "pll_p_out3", NULL);
1351 clks[pll_p_out3] = clk;
1352
1353 /* PLLP_OUT4 */
1354 clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p",
1355 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED |
1356 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
1357 &pll_div_lock);
1358 clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div",
1359 clk_base + PLLP_OUTB, 17, 16,
1360 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
1361 &pll_div_lock);
1362 clk_register_clkdev(clk, "pll_p_out4", NULL);
1363 clks[pll_p_out4] = clk;
1364 1093
1365 /* PLLM */ 1094 /* PLLM */
1366 _clip_vco_min(&pll_m_params);
1367 clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc, 1095 clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
1368 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 0, 1096 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
1369 &pll_m_params, TEGRA_PLL_USE_LOCK, 1097 &pll_m_params, NULL);
1370 pll_m_freq_table, NULL); 1098 clks[TEGRA114_CLK_PLL_M] = clk;
1371 clk_register_clkdev(clk, "pll_m", NULL);
1372 clks[pll_m] = clk;
1373 1099
1374 /* PLLM_OUT1 */ 1100 /* PLLM_OUT1 */
1375 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", 1101 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
@@ -1378,41 +1104,20 @@ static void __init tegra114_pll_init(void __iomem *clk_base,
1378 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", 1104 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
1379 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | 1105 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
1380 CLK_SET_RATE_PARENT, 0, NULL); 1106 CLK_SET_RATE_PARENT, 0, NULL);
1381 clk_register_clkdev(clk, "pll_m_out1", NULL); 1107 clks[TEGRA114_CLK_PLL_M_OUT1] = clk;
1382 clks[pll_m_out1] = clk;
1383 1108
1384 /* PLLM_UD */ 1109 /* PLLM_UD */
1385 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m", 1110 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
1386 CLK_SET_RATE_PARENT, 1, 1); 1111 CLK_SET_RATE_PARENT, 1, 1);
1387 1112
1388 /* PLLX */
1389 _clip_vco_min(&pll_x_params);
1390 if (_setup_dynamic_ramp(&pll_x_params, clk_base) >= 0) {
1391 _init_iddq(&pll_x_params, clk_base);
1392 clk = tegra_clk_register_pllxc("pll_x", "pll_ref", clk_base,
1393 pmc, CLK_IGNORE_UNUSED, 0, &pll_x_params,
1394 TEGRA_PLL_USE_LOCK, pll_x_freq_table, NULL);
1395 clk_register_clkdev(clk, "pll_x", NULL);
1396 clks[pll_x] = clk;
1397 }
1398
1399 /* PLLX_OUT0 */
1400 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
1401 CLK_SET_RATE_PARENT, 1, 2);
1402 clk_register_clkdev(clk, "pll_x_out0", NULL);
1403 clks[pll_x_out0] = clk;
1404
1405 /* PLLU */ 1113 /* PLLU */
1406 val = readl(clk_base + pll_u_params.base_reg); 1114 val = readl(clk_base + pll_u_params.base_reg);
1407 val &= ~BIT(24); /* disable PLLU_OVERRIDE */ 1115 val &= ~BIT(24); /* disable PLLU_OVERRIDE */
1408 writel(val, clk_base + pll_u_params.base_reg); 1116 writel(val, clk_base + pll_u_params.base_reg);
1409 1117
1410 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0, 1118 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0,
1411 0, &pll_u_params, TEGRA_PLLU | 1119 &pll_u_params, &pll_u_lock);
1412 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 1120 clks[TEGRA114_CLK_PLL_U] = clk;
1413 TEGRA_PLL_USE_LOCK, pll_u_freq_table, &pll_u_lock);
1414 clk_register_clkdev(clk, "pll_u", NULL);
1415 clks[pll_u] = clk;
1416 1121
1417 tegra114_utmi_param_configure(clk_base); 1122 tegra114_utmi_param_configure(clk_base);
1418 1123
@@ -1420,731 +1125,97 @@ static void __init tegra114_pll_init(void __iomem *clk_base,
1420 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u", 1125 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u",
1421 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, 1126 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
1422 22, 0, &pll_u_lock); 1127 22, 0, &pll_u_lock);
1423 clk_register_clkdev(clk, "pll_u_480M", NULL); 1128 clks[TEGRA114_CLK_PLL_U_480M] = clk;
1424 clks[pll_u_480M] = clk;
1425 1129
1426 /* PLLU_60M */ 1130 /* PLLU_60M */
1427 clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u", 1131 clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u",
1428 CLK_SET_RATE_PARENT, 1, 8); 1132 CLK_SET_RATE_PARENT, 1, 8);
1429 clk_register_clkdev(clk, "pll_u_60M", NULL); 1133 clks[TEGRA114_CLK_PLL_U_60M] = clk;
1430 clks[pll_u_60M] = clk;
1431 1134
1432 /* PLLU_48M */ 1135 /* PLLU_48M */
1433 clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u", 1136 clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u",
1434 CLK_SET_RATE_PARENT, 1, 10); 1137 CLK_SET_RATE_PARENT, 1, 10);
1435 clk_register_clkdev(clk, "pll_u_48M", NULL); 1138 clks[TEGRA114_CLK_PLL_U_48M] = clk;
1436 clks[pll_u_48M] = clk;
1437 1139
1438 /* PLLU_12M */ 1140 /* PLLU_12M */
1439 clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u", 1141 clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u",
1440 CLK_SET_RATE_PARENT, 1, 40); 1142 CLK_SET_RATE_PARENT, 1, 40);
1441 clk_register_clkdev(clk, "pll_u_12M", NULL); 1143 clks[TEGRA114_CLK_PLL_U_12M] = clk;
1442 clks[pll_u_12M] = clk;
1443 1144
1444 /* PLLD */ 1145 /* PLLD */
1445 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0, 1146 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
1446 0, &pll_d_params, 1147 &pll_d_params, &pll_d_lock);
1447 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 1148 clks[TEGRA114_CLK_PLL_D] = clk;
1448 TEGRA_PLL_USE_LOCK, pll_d_freq_table, &pll_d_lock);
1449 clk_register_clkdev(clk, "pll_d", NULL);
1450 clks[pll_d] = clk;
1451 1149
1452 /* PLLD_OUT0 */ 1150 /* PLLD_OUT0 */
1453 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", 1151 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
1454 CLK_SET_RATE_PARENT, 1, 2); 1152 CLK_SET_RATE_PARENT, 1, 2);
1455 clk_register_clkdev(clk, "pll_d_out0", NULL); 1153 clks[TEGRA114_CLK_PLL_D_OUT0] = clk;
1456 clks[pll_d_out0] = clk;
1457 1154
1458 /* PLLD2 */ 1155 /* PLLD2 */
1459 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc, 0, 1156 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc, 0,
1460 0, &pll_d2_params, 1157 &pll_d2_params, &pll_d2_lock);
1461 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 1158 clks[TEGRA114_CLK_PLL_D2] = clk;
1462 TEGRA_PLL_USE_LOCK, pll_d_freq_table, &pll_d2_lock);
1463 clk_register_clkdev(clk, "pll_d2", NULL);
1464 clks[pll_d2] = clk;
1465 1159
1466 /* PLLD2_OUT0 */ 1160 /* PLLD2_OUT0 */
1467 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2", 1161 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
1468 CLK_SET_RATE_PARENT, 1, 2); 1162 CLK_SET_RATE_PARENT, 1, 2);
1469 clk_register_clkdev(clk, "pll_d2_out0", NULL); 1163 clks[TEGRA114_CLK_PLL_D2_OUT0] = clk;
1470 clks[pll_d2_out0] = clk;
1471
1472 /* PLLA */
1473 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, pmc, 0,
1474 0, &pll_a_params, TEGRA_PLL_HAS_CPCON |
1475 TEGRA_PLL_USE_LOCK, pll_a_freq_table, NULL);
1476 clk_register_clkdev(clk, "pll_a", NULL);
1477 clks[pll_a] = clk;
1478
1479 /* PLLA_OUT0 */
1480 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
1481 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1482 8, 8, 1, NULL);
1483 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
1484 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
1485 CLK_SET_RATE_PARENT, 0, NULL);
1486 clk_register_clkdev(clk, "pll_a_out0", NULL);
1487 clks[pll_a_out0] = clk;
1488 1164
1489 /* PLLRE */ 1165 /* PLLRE */
1490 _clip_vco_min(&pll_re_vco_params);
1491 clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc, 1166 clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,
1492 0, 0, &pll_re_vco_params, TEGRA_PLL_USE_LOCK, 1167 0, &pll_re_vco_params, &pll_re_lock, pll_ref_freq);
1493 NULL, &pll_re_lock, pll_ref_freq); 1168 clks[TEGRA114_CLK_PLL_RE_VCO] = clk;
1494 clk_register_clkdev(clk, "pll_re_vco", NULL);
1495 clks[pll_re_vco] = clk;
1496 1169
1497 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0, 1170 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
1498 clk_base + PLLRE_BASE, 16, 4, 0, 1171 clk_base + PLLRE_BASE, 16, 4, 0,
1499 pll_re_div_table, &pll_re_lock); 1172 pll_re_div_table, &pll_re_lock);
1500 clk_register_clkdev(clk, "pll_re_out", NULL); 1173 clks[TEGRA114_CLK_PLL_RE_OUT] = clk;
1501 clks[pll_re_out] = clk;
1502 1174
1503 /* PLLE */ 1175 /* PLLE */
1504 clk = tegra_clk_register_plle_tegra114("pll_e_out0", "pll_re_vco", 1176 clk = tegra_clk_register_plle_tegra114("pll_e_out0", "pll_ref",
1505 clk_base, 0, 100000000, &pll_e_params, 1177 clk_base, 0, &pll_e_params, NULL);
1506 pll_e_freq_table, NULL); 1178 clks[TEGRA114_CLK_PLL_E_OUT0] = clk;
1507 clk_register_clkdev(clk, "pll_e_out0", NULL);
1508 clks[pll_e_out0] = clk;
1509}
1510
1511static const char *mux_audio_sync_clk[] = { "spdif_in_sync", "i2s0_sync",
1512 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",
1513};
1514
1515static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
1516 "clk_m_div4", "extern1",
1517};
1518
1519static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
1520 "clk_m_div4", "extern2",
1521};
1522
1523static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
1524 "clk_m_div4", "extern3",
1525};
1526
1527static void __init tegra114_audio_clk_init(void __iomem *clk_base)
1528{
1529 struct clk *clk;
1530
1531 /* spdif_in_sync */
1532 clk = tegra_clk_register_sync_source("spdif_in_sync", 24000000,
1533 24000000);
1534 clk_register_clkdev(clk, "spdif_in_sync", NULL);
1535 clks[spdif_in_sync] = clk;
1536
1537 /* i2s0_sync */
1538 clk = tegra_clk_register_sync_source("i2s0_sync", 24000000, 24000000);
1539 clk_register_clkdev(clk, "i2s0_sync", NULL);
1540 clks[i2s0_sync] = clk;
1541
1542 /* i2s1_sync */
1543 clk = tegra_clk_register_sync_source("i2s1_sync", 24000000, 24000000);
1544 clk_register_clkdev(clk, "i2s1_sync", NULL);
1545 clks[i2s1_sync] = clk;
1546
1547 /* i2s2_sync */
1548 clk = tegra_clk_register_sync_source("i2s2_sync", 24000000, 24000000);
1549 clk_register_clkdev(clk, "i2s2_sync", NULL);
1550 clks[i2s2_sync] = clk;
1551
1552 /* i2s3_sync */
1553 clk = tegra_clk_register_sync_source("i2s3_sync", 24000000, 24000000);
1554 clk_register_clkdev(clk, "i2s3_sync", NULL);
1555 clks[i2s3_sync] = clk;
1556
1557 /* i2s4_sync */
1558 clk = tegra_clk_register_sync_source("i2s4_sync", 24000000, 24000000);
1559 clk_register_clkdev(clk, "i2s4_sync", NULL);
1560 clks[i2s4_sync] = clk;
1561
1562 /* vimclk_sync */
1563 clk = tegra_clk_register_sync_source("vimclk_sync", 24000000, 24000000);
1564 clk_register_clkdev(clk, "vimclk_sync", NULL);
1565 clks[vimclk_sync] = clk;
1566
1567 /* audio0 */
1568 clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk,
1569 ARRAY_SIZE(mux_audio_sync_clk),
1570 CLK_SET_RATE_NO_REPARENT,
1571 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0,
1572 NULL);
1573 clks[audio0_mux] = clk;
1574 clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0,
1575 clk_base + AUDIO_SYNC_CLK_I2S0, 4,
1576 CLK_GATE_SET_TO_DISABLE, NULL);
1577 clk_register_clkdev(clk, "audio0", NULL);
1578 clks[audio0] = clk;
1579
1580 /* audio1 */
1581 clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk,
1582 ARRAY_SIZE(mux_audio_sync_clk),
1583 CLK_SET_RATE_NO_REPARENT,
1584 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0,
1585 NULL);
1586 clks[audio1_mux] = clk;
1587 clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0,
1588 clk_base + AUDIO_SYNC_CLK_I2S1, 4,
1589 CLK_GATE_SET_TO_DISABLE, NULL);
1590 clk_register_clkdev(clk, "audio1", NULL);
1591 clks[audio1] = clk;
1592
1593 /* audio2 */
1594 clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk,
1595 ARRAY_SIZE(mux_audio_sync_clk),
1596 CLK_SET_RATE_NO_REPARENT,
1597 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0,
1598 NULL);
1599 clks[audio2_mux] = clk;
1600 clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0,
1601 clk_base + AUDIO_SYNC_CLK_I2S2, 4,
1602 CLK_GATE_SET_TO_DISABLE, NULL);
1603 clk_register_clkdev(clk, "audio2", NULL);
1604 clks[audio2] = clk;
1605
1606 /* audio3 */
1607 clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk,
1608 ARRAY_SIZE(mux_audio_sync_clk),
1609 CLK_SET_RATE_NO_REPARENT,
1610 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0,
1611 NULL);
1612 clks[audio3_mux] = clk;
1613 clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0,
1614 clk_base + AUDIO_SYNC_CLK_I2S3, 4,
1615 CLK_GATE_SET_TO_DISABLE, NULL);
1616 clk_register_clkdev(clk, "audio3", NULL);
1617 clks[audio3] = clk;
1618
1619 /* audio4 */
1620 clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk,
1621 ARRAY_SIZE(mux_audio_sync_clk),
1622 CLK_SET_RATE_NO_REPARENT,
1623 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0,
1624 NULL);
1625 clks[audio4_mux] = clk;
1626 clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0,
1627 clk_base + AUDIO_SYNC_CLK_I2S4, 4,
1628 CLK_GATE_SET_TO_DISABLE, NULL);
1629 clk_register_clkdev(clk, "audio4", NULL);
1630 clks[audio4] = clk;
1631
1632 /* spdif */
1633 clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk,
1634 ARRAY_SIZE(mux_audio_sync_clk),
1635 CLK_SET_RATE_NO_REPARENT,
1636 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0,
1637 NULL);
1638 clks[spdif_mux] = clk;
1639 clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0,
1640 clk_base + AUDIO_SYNC_CLK_SPDIF, 4,
1641 CLK_GATE_SET_TO_DISABLE, NULL);
1642 clk_register_clkdev(clk, "spdif", NULL);
1643 clks[spdif] = clk;
1644
1645 /* audio0_2x */
1646 clk = clk_register_fixed_factor(NULL, "audio0_doubler", "audio0",
1647 CLK_SET_RATE_PARENT, 2, 1);
1648 clk = tegra_clk_register_divider("audio0_div", "audio0_doubler",
1649 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 24, 1,
1650 0, &clk_doubler_lock);
1651 clk = tegra_clk_register_periph_gate("audio0_2x", "audio0_div",
1652 TEGRA_PERIPH_NO_RESET, clk_base,
1653 CLK_SET_RATE_PARENT, 113, &periph_v_regs,
1654 periph_clk_enb_refcnt);
1655 clk_register_clkdev(clk, "audio0_2x", NULL);
1656 clks[audio0_2x] = clk;
1657
1658 /* audio1_2x */
1659 clk = clk_register_fixed_factor(NULL, "audio1_doubler", "audio1",
1660 CLK_SET_RATE_PARENT, 2, 1);
1661 clk = tegra_clk_register_divider("audio1_div", "audio1_doubler",
1662 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 25, 1,
1663 0, &clk_doubler_lock);
1664 clk = tegra_clk_register_periph_gate("audio1_2x", "audio1_div",
1665 TEGRA_PERIPH_NO_RESET, clk_base,
1666 CLK_SET_RATE_PARENT, 114, &periph_v_regs,
1667 periph_clk_enb_refcnt);
1668 clk_register_clkdev(clk, "audio1_2x", NULL);
1669 clks[audio1_2x] = clk;
1670
1671 /* audio2_2x */
1672 clk = clk_register_fixed_factor(NULL, "audio2_doubler", "audio2",
1673 CLK_SET_RATE_PARENT, 2, 1);
1674 clk = tegra_clk_register_divider("audio2_div", "audio2_doubler",
1675 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 26, 1,
1676 0, &clk_doubler_lock);
1677 clk = tegra_clk_register_periph_gate("audio2_2x", "audio2_div",
1678 TEGRA_PERIPH_NO_RESET, clk_base,
1679 CLK_SET_RATE_PARENT, 115, &periph_v_regs,
1680 periph_clk_enb_refcnt);
1681 clk_register_clkdev(clk, "audio2_2x", NULL);
1682 clks[audio2_2x] = clk;
1683
1684 /* audio3_2x */
1685 clk = clk_register_fixed_factor(NULL, "audio3_doubler", "audio3",
1686 CLK_SET_RATE_PARENT, 2, 1);
1687 clk = tegra_clk_register_divider("audio3_div", "audio3_doubler",
1688 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 27, 1,
1689 0, &clk_doubler_lock);
1690 clk = tegra_clk_register_periph_gate("audio3_2x", "audio3_div",
1691 TEGRA_PERIPH_NO_RESET, clk_base,
1692 CLK_SET_RATE_PARENT, 116, &periph_v_regs,
1693 periph_clk_enb_refcnt);
1694 clk_register_clkdev(clk, "audio3_2x", NULL);
1695 clks[audio3_2x] = clk;
1696
1697 /* audio4_2x */
1698 clk = clk_register_fixed_factor(NULL, "audio4_doubler", "audio4",
1699 CLK_SET_RATE_PARENT, 2, 1);
1700 clk = tegra_clk_register_divider("audio4_div", "audio4_doubler",
1701 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 28, 1,
1702 0, &clk_doubler_lock);
1703 clk = tegra_clk_register_periph_gate("audio4_2x", "audio4_div",
1704 TEGRA_PERIPH_NO_RESET, clk_base,
1705 CLK_SET_RATE_PARENT, 117, &periph_v_regs,
1706 periph_clk_enb_refcnt);
1707 clk_register_clkdev(clk, "audio4_2x", NULL);
1708 clks[audio4_2x] = clk;
1709
1710 /* spdif_2x */
1711 clk = clk_register_fixed_factor(NULL, "spdif_doubler", "spdif",
1712 CLK_SET_RATE_PARENT, 2, 1);
1713 clk = tegra_clk_register_divider("spdif_div", "spdif_doubler",
1714 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 29, 1,
1715 0, &clk_doubler_lock);
1716 clk = tegra_clk_register_periph_gate("spdif_2x", "spdif_div",
1717 TEGRA_PERIPH_NO_RESET, clk_base,
1718 CLK_SET_RATE_PARENT, 118,
1719 &periph_v_regs, periph_clk_enb_refcnt);
1720 clk_register_clkdev(clk, "spdif_2x", NULL);
1721 clks[spdif_2x] = clk;
1722}
1723
1724static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
1725{
1726 struct clk *clk;
1727
1728 /* clk_out_1 */
1729 clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents,
1730 ARRAY_SIZE(clk_out1_parents),
1731 CLK_SET_RATE_NO_REPARENT,
1732 pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0,
1733 &clk_out_lock);
1734 clks[clk_out_1_mux] = clk;
1735 clk = clk_register_gate(NULL, "clk_out_1", "clk_out_1_mux", 0,
1736 pmc_base + PMC_CLK_OUT_CNTRL, 2, 0,
1737 &clk_out_lock);
1738 clk_register_clkdev(clk, "extern1", "clk_out_1");
1739 clks[clk_out_1] = clk;
1740
1741 /* clk_out_2 */
1742 clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,
1743 ARRAY_SIZE(clk_out2_parents),
1744 CLK_SET_RATE_NO_REPARENT,
1745 pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,
1746 &clk_out_lock);
1747 clks[clk_out_2_mux] = clk;
1748 clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0,
1749 pmc_base + PMC_CLK_OUT_CNTRL, 10, 0,
1750 &clk_out_lock);
1751 clk_register_clkdev(clk, "extern2", "clk_out_2");
1752 clks[clk_out_2] = clk;
1753
1754 /* clk_out_3 */
1755 clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,
1756 ARRAY_SIZE(clk_out3_parents),
1757 CLK_SET_RATE_NO_REPARENT,
1758 pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,
1759 &clk_out_lock);
1760 clks[clk_out_3_mux] = clk;
1761 clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0,
1762 pmc_base + PMC_CLK_OUT_CNTRL, 18, 0,
1763 &clk_out_lock);
1764 clk_register_clkdev(clk, "extern3", "clk_out_3");
1765 clks[clk_out_3] = clk;
1766
1767 /* blink */
1768 /* clear the blink timer register to directly output clk_32k */
1769 writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
1770 clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
1771 pmc_base + PMC_DPD_PADS_ORIDE,
1772 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
1773 clk = clk_register_gate(NULL, "blink", "blink_override", 0,
1774 pmc_base + PMC_CTRL,
1775 PMC_CTRL_BLINK_ENB, 0, NULL);
1776 clk_register_clkdev(clk, "blink", NULL);
1777 clks[blink] = clk;
1778
1779} 1179}
1780 1180
1781static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", 1181static __init void tegra114_periph_clk_init(void __iomem *clk_base,
1782 "pll_p", "pll_p_out2", "unused", 1182 void __iomem *pmc_base)
1783 "clk_32k", "pll_m_out1" };
1784
1785static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
1786 "pll_p", "pll_p_out4", "unused",
1787 "unused", "pll_x" };
1788
1789static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
1790 "pll_p", "pll_p_out4", "unused",
1791 "unused", "pll_x", "pll_x_out0" };
1792
1793static void __init tegra114_super_clk_init(void __iomem *clk_base)
1794{ 1183{
1795 struct clk *clk; 1184 struct clk *clk;
1185 u32 val;
1796 1186
1797 /* CCLKG */ 1187 /* xusb_hs_src */
1798 clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents, 1188 val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC);
1799 ARRAY_SIZE(cclk_g_parents), 1189 val |= BIT(25); /* always select PLLU_60M */
1800 CLK_SET_RATE_PARENT, 1190 writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC);
1801 clk_base + CCLKG_BURST_POLICY,
1802 0, 4, 0, 0, NULL);
1803 clk_register_clkdev(clk, "cclk_g", NULL);
1804 clks[cclk_g] = clk;
1805
1806 /* CCLKLP */
1807 clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents,
1808 ARRAY_SIZE(cclk_lp_parents),
1809 CLK_SET_RATE_PARENT,
1810 clk_base + CCLKLP_BURST_POLICY,
1811 0, 4, 8, 9, NULL);
1812 clk_register_clkdev(clk, "cclk_lp", NULL);
1813 clks[cclk_lp] = clk;
1814
1815 /* SCLK */
1816 clk = tegra_clk_register_super_mux("sclk", sclk_parents,
1817 ARRAY_SIZE(sclk_parents),
1818 CLK_SET_RATE_PARENT,
1819 clk_base + SCLK_BURST_POLICY,
1820 0, 4, 0, 0, NULL);
1821 clk_register_clkdev(clk, "sclk", NULL);
1822 clks[sclk] = clk;
1823
1824 /* HCLK */
1825 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
1826 clk_base + SYSTEM_CLK_RATE, 4, 2, 0,
1827 &sysrate_lock);
1828 clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT |
1829 CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE,
1830 7, CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
1831 clk_register_clkdev(clk, "hclk", NULL);
1832 clks[hclk] = clk;
1833
1834 /* PCLK */
1835 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
1836 clk_base + SYSTEM_CLK_RATE, 0, 2, 0,
1837 &sysrate_lock);
1838 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT |
1839 CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE,
1840 3, CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
1841 clk_register_clkdev(clk, "pclk", NULL);
1842 clks[pclk] = clk;
1843}
1844
1845static struct tegra_periph_init_data tegra_periph_clk_list[] = {
1846 TEGRA_INIT_DATA_MUX("i2s0", NULL, "tegra30-i2s.0", mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s0),
1847 TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra30-i2s.1", mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s1),
1848 TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra30-i2s.2", mux_pllaout0_audio2_2x_pllp_clkm, CLK_SOURCE_I2S2, 18, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s2),
1849 TEGRA_INIT_DATA_MUX("i2s3", NULL, "tegra30-i2s.3", mux_pllaout0_audio3_2x_pllp_clkm, CLK_SOURCE_I2S3, 101, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s3),
1850 TEGRA_INIT_DATA_MUX("i2s4", NULL, "tegra30-i2s.4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s4),
1851 TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra30-spdif", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_out),
1852 TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra30-spdif", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_in),
1853 TEGRA_INIT_DATA_MUX("pwm", NULL, "pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, &periph_l_regs, TEGRA_PERIPH_ON_APB, pwm),
1854 TEGRA_INIT_DATA_MUX("adx", NULL, "adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, &periph_w_regs, TEGRA_PERIPH_ON_APB, adx),
1855 TEGRA_INIT_DATA_MUX("amx", NULL, "amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, &periph_w_regs, TEGRA_PERIPH_ON_APB, amx),
1856 TEGRA_INIT_DATA_MUX("hda", "hda", "tegra30-hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, &periph_v_regs, TEGRA_PERIPH_ON_APB, hda),
1857 TEGRA_INIT_DATA_MUX("hda2codec_2x", "hda2codec", "tegra30-hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, &periph_v_regs, TEGRA_PERIPH_ON_APB, hda2codec_2x),
1858 TEGRA_INIT_DATA_MUX("sbc1", NULL, "tegra11-spi.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1),
1859 TEGRA_INIT_DATA_MUX("sbc2", NULL, "tegra11-spi.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC2, 44, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc2),
1860 TEGRA_INIT_DATA_MUX("sbc3", NULL, "tegra11-spi.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC3, 46, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc3),
1861 TEGRA_INIT_DATA_MUX("sbc4", NULL, "tegra11-spi.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC4, 68, &periph_u_regs, TEGRA_PERIPH_ON_APB, sbc4),
1862 TEGRA_INIT_DATA_MUX("sbc5", NULL, "tegra11-spi.4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC5, 104, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc5),
1863 TEGRA_INIT_DATA_MUX("sbc6", NULL, "tegra11-spi.5", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC6, 105, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc6),
1864 TEGRA_INIT_DATA_MUX8("ndflash", NULL, "tegra_nand", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed),
1865 TEGRA_INIT_DATA_MUX8("ndspeed", NULL, "tegra_nand_speed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed),
1866 TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, vfir),
1867 TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, &periph_l_regs, 0, sdmmc1),
1868 TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, &periph_l_regs, 0, sdmmc2),
1869 TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, &periph_u_regs, 0, sdmmc3),
1870 TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, &periph_l_regs, 0, sdmmc4),
1871 TEGRA_INIT_DATA_INT("vde", NULL, "vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, &periph_h_regs, 0, vde),
1872 TEGRA_INIT_DATA_MUX_FLAGS("csite", NULL, "csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, &periph_u_regs, TEGRA_PERIPH_ON_APB, csite, CLK_IGNORE_UNUSED),
1873 TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, &periph_u_regs, TEGRA_PERIPH_ON_APB, la),
1874 TEGRA_INIT_DATA_MUX("trace", NULL, "trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, &periph_u_regs, TEGRA_PERIPH_ON_APB, trace),
1875 TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, &periph_u_regs, TEGRA_PERIPH_ON_APB, owr),
1876 TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, &periph_h_regs, 0, nor),
1877 TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_MIPI, 50, &periph_h_regs, TEGRA_PERIPH_ON_APB, mipi),
1878 TEGRA_INIT_DATA_I2C("i2c1", "div-clk", "tegra11-i2c.0", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, &periph_l_regs, i2c1),
1879 TEGRA_INIT_DATA_I2C("i2c2", "div-clk", "tegra11-i2c.1", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, &periph_h_regs, i2c2),
1880 TEGRA_INIT_DATA_I2C("i2c3", "div-clk", "tegra11-i2c.2", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, &periph_u_regs, i2c3),
1881 TEGRA_INIT_DATA_I2C("i2c4", "div-clk", "tegra11-i2c.3", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, &periph_v_regs, i2c4),
1882 TEGRA_INIT_DATA_I2C("i2c5", "div-clk", "tegra11-i2c.4", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, &periph_h_regs, i2c5),
1883 TEGRA_INIT_DATA_UART("uarta", NULL, "tegra_uart.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, &periph_l_regs, uarta),
1884 TEGRA_INIT_DATA_UART("uartb", NULL, "tegra_uart.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, &periph_l_regs, uartb),
1885 TEGRA_INIT_DATA_UART("uartc", NULL, "tegra_uart.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, &periph_h_regs, uartc),
1886 TEGRA_INIT_DATA_UART("uartd", NULL, "tegra_uart.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, &periph_u_regs, uartd),
1887 TEGRA_INIT_DATA_INT("3d", NULL, "3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, &periph_l_regs, 0, gr_3d),
1888 TEGRA_INIT_DATA_INT("2d", NULL, "2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, &periph_l_regs, 0, gr_2d),
1889 TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, vi_sensor),
1890 TEGRA_INIT_DATA_INT8("vi", "vi", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, &periph_l_regs, 0, vi),
1891 TEGRA_INIT_DATA_INT8("epp", NULL, "epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, epp),
1892 TEGRA_INIT_DATA_INT8("msenc", NULL, "msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, &periph_u_regs, TEGRA_PERIPH_WAR_1005168, msenc),
1893 TEGRA_INIT_DATA_INT8("tsec", NULL, "tsec", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, &periph_u_regs, 0, tsec),
1894 TEGRA_INIT_DATA_INT8("host1x", NULL, "host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, &periph_l_regs, 0, host1x),
1895 TEGRA_INIT_DATA_MUX8("hdmi", NULL, "hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, &periph_h_regs, 0, hdmi),
1896 TEGRA_INIT_DATA_MUX("cilab", "cilab", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILAB, 144, &periph_w_regs, 0, cilab),
1897 TEGRA_INIT_DATA_MUX("cilcd", "cilcd", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILCD, 145, &periph_w_regs, 0, cilcd),
1898 TEGRA_INIT_DATA_MUX("cile", "cile", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILE, 146, &periph_w_regs, 0, cile),
1899 TEGRA_INIT_DATA_MUX("dsialp", "dsialp", "tegradc.0", mux_pllp_pllc_clkm, CLK_SOURCE_DSIALP, 147, &periph_w_regs, 0, dsialp),
1900 TEGRA_INIT_DATA_MUX("dsiblp", "dsiblp", "tegradc.1", mux_pllp_pllc_clkm, CLK_SOURCE_DSIBLP, 148, &periph_w_regs, 0, dsiblp),
1901 TEGRA_INIT_DATA_MUX("tsensor", NULL, "tegra-tsensor", mux_pllp_pllc_clkm_clk32, CLK_SOURCE_TSENSOR, 100, &periph_v_regs, TEGRA_PERIPH_ON_APB, tsensor),
1902 TEGRA_INIT_DATA_MUX("actmon", NULL, "actmon", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_ACTMON, 119, &periph_v_regs, 0, actmon),
1903 TEGRA_INIT_DATA_MUX8("extern1", NULL, "extern1", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, &periph_v_regs, 0, extern1),
1904 TEGRA_INIT_DATA_MUX8("extern2", NULL, "extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, &periph_v_regs, 0, extern2),
1905 TEGRA_INIT_DATA_MUX8("extern3", NULL, "extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, &periph_v_regs, 0, extern3),
1906 TEGRA_INIT_DATA_MUX("i2cslow", NULL, "i2cslow", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_I2CSLOW, 81, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2cslow),
1907 TEGRA_INIT_DATA_INT8("se", NULL, "se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, &periph_v_regs, TEGRA_PERIPH_ON_APB, se),
1908 TEGRA_INIT_DATA_INT_FLAGS("mselect", NULL, "mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, &periph_v_regs, 0, mselect, CLK_IGNORE_UNUSED),
1909 TEGRA_INIT_DATA_MUX("dfll_ref", "ref", "t114_dfll", mux_pllp_clkm, CLK_SOURCE_DFLL_REF, 155, &periph_w_regs, TEGRA_PERIPH_ON_APB, dfll_ref),
1910 TEGRA_INIT_DATA_MUX("dfll_soc", "soc", "t114_dfll", mux_pllp_clkm, CLK_SOURCE_DFLL_SOC, 155, &periph_w_regs, TEGRA_PERIPH_ON_APB, dfll_soc),
1911 TEGRA_INIT_DATA_MUX8("soc_therm", NULL, "soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, &periph_u_regs, TEGRA_PERIPH_ON_APB, soc_therm),
1912 TEGRA_INIT_DATA_XUSB("xusb_host_src", "host_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, &periph_w_regs, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, xusb_host_src),
1913 TEGRA_INIT_DATA_XUSB("xusb_falcon_src", "falcon_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, xusb_falcon_src),
1914 TEGRA_INIT_DATA_XUSB("xusb_fs_src", "fs_src", "tegra_xhci", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, xusb_fs_src),
1915 TEGRA_INIT_DATA_XUSB("xusb_ss_src", "ss_src", "tegra_xhci", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, xusb_ss_src),
1916 TEGRA_INIT_DATA_XUSB("xusb_dev_src", "dev_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, &periph_u_regs, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, xusb_dev_src),
1917 TEGRA_INIT_DATA_AUDIO("d_audio", "d_audio", "tegra30-ahub", CLK_SOURCE_D_AUDIO, 106, &periph_v_regs, TEGRA_PERIPH_ON_APB, d_audio),
1918 TEGRA_INIT_DATA_AUDIO("dam0", NULL, "tegra30-dam.0", CLK_SOURCE_DAM0, 108, &periph_v_regs, TEGRA_PERIPH_ON_APB, dam0),
1919 TEGRA_INIT_DATA_AUDIO("dam1", NULL, "tegra30-dam.1", CLK_SOURCE_DAM1, 109, &periph_v_regs, TEGRA_PERIPH_ON_APB, dam1),
1920 TEGRA_INIT_DATA_AUDIO("dam2", NULL, "tegra30-dam.2", CLK_SOURCE_DAM2, 110, &periph_v_regs, TEGRA_PERIPH_ON_APB, dam2),
1921};
1922
1923static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
1924 TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, &periph_l_regs, 0, disp1),
1925 TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, &periph_l_regs, 0, disp2),
1926};
1927 1191
1928static __init void tegra114_periph_clk_init(void __iomem *clk_base) 1192 clk = clk_register_fixed_factor(NULL, "xusb_hs_src", "pll_u_60M", 0,
1929{ 1193 1, 1);
1930 struct tegra_periph_init_data *data; 1194 clks[TEGRA114_CLK_XUSB_HS_SRC] = clk;
1931 struct clk *clk;
1932 int i;
1933 u32 val;
1934 1195
1935 /* apbdma */ 1196 /* dsia mux */
1936 clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base,
1937 0, 34, &periph_h_regs,
1938 periph_clk_enb_refcnt);
1939 clks[apbdma] = clk;
1940
1941 /* rtc */
1942 clk = tegra_clk_register_periph_gate("rtc", "clk_32k",
1943 TEGRA_PERIPH_ON_APB |
1944 TEGRA_PERIPH_NO_RESET, clk_base,
1945 0, 4, &periph_l_regs,
1946 periph_clk_enb_refcnt);
1947 clk_register_clkdev(clk, NULL, "rtc-tegra");
1948 clks[rtc] = clk;
1949
1950 /* kbc */
1951 clk = tegra_clk_register_periph_gate("kbc", "clk_32k",
1952 TEGRA_PERIPH_ON_APB |
1953 TEGRA_PERIPH_NO_RESET, clk_base,
1954 0, 36, &periph_h_regs,
1955 periph_clk_enb_refcnt);
1956 clks[kbc] = clk;
1957
1958 /* timer */
1959 clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base,
1960 0, 5, &periph_l_regs,
1961 periph_clk_enb_refcnt);
1962 clk_register_clkdev(clk, NULL, "timer");
1963 clks[timer] = clk;
1964
1965 /* kfuse */
1966 clk = tegra_clk_register_periph_gate("kfuse", "clk_m",
1967 TEGRA_PERIPH_ON_APB, clk_base, 0, 40,
1968 &periph_h_regs, periph_clk_enb_refcnt);
1969 clks[kfuse] = clk;
1970
1971 /* fuse */
1972 clk = tegra_clk_register_periph_gate("fuse", "clk_m",
1973 TEGRA_PERIPH_ON_APB, clk_base, 0, 39,
1974 &periph_h_regs, periph_clk_enb_refcnt);
1975 clks[fuse] = clk;
1976
1977 /* fuse_burn */
1978 clk = tegra_clk_register_periph_gate("fuse_burn", "clk_m",
1979 TEGRA_PERIPH_ON_APB, clk_base, 0, 39,
1980 &periph_h_regs, periph_clk_enb_refcnt);
1981 clks[fuse_burn] = clk;
1982
1983 /* apbif */
1984 clk = tegra_clk_register_periph_gate("apbif", "clk_m",
1985 TEGRA_PERIPH_ON_APB, clk_base, 0, 107,
1986 &periph_v_regs, periph_clk_enb_refcnt);
1987 clks[apbif] = clk;
1988
1989 /* hda2hdmi */
1990 clk = tegra_clk_register_periph_gate("hda2hdmi", "clk_m",
1991 TEGRA_PERIPH_ON_APB, clk_base, 0, 128,
1992 &periph_w_regs, periph_clk_enb_refcnt);
1993 clks[hda2hdmi] = clk;
1994
1995 /* vcp */
1996 clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, clk_base, 0,
1997 29, &periph_l_regs,
1998 periph_clk_enb_refcnt);
1999 clks[vcp] = clk;
2000
2001 /* bsea */
2002 clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, clk_base,
2003 0, 62, &periph_h_regs,
2004 periph_clk_enb_refcnt);
2005 clks[bsea] = clk;
2006
2007 /* bsev */
2008 clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, clk_base,
2009 0, 63, &periph_h_regs,
2010 periph_clk_enb_refcnt);
2011 clks[bsev] = clk;
2012
2013 /* mipi-cal */
2014 clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base,
2015 0, 56, &periph_h_regs,
2016 periph_clk_enb_refcnt);
2017 clks[mipi_cal] = clk;
2018
2019 /* usbd */
2020 clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base,
2021 0, 22, &periph_l_regs,
2022 periph_clk_enb_refcnt);
2023 clks[usbd] = clk;
2024
2025 /* usb2 */
2026 clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base,
2027 0, 58, &periph_h_regs,
2028 periph_clk_enb_refcnt);
2029 clks[usb2] = clk;
2030
2031 /* usb3 */
2032 clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base,
2033 0, 59, &periph_h_regs,
2034 periph_clk_enb_refcnt);
2035 clks[usb3] = clk;
2036
2037 /* csi */
2038 clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base,
2039 0, 52, &periph_h_regs,
2040 periph_clk_enb_refcnt);
2041 clks[csi] = clk;
2042
2043 /* isp */
2044 clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0,
2045 23, &periph_l_regs,
2046 periph_clk_enb_refcnt);
2047 clks[isp] = clk;
2048
2049 /* csus */
2050 clk = tegra_clk_register_periph_gate("csus", "clk_m",
2051 TEGRA_PERIPH_NO_RESET, clk_base, 0, 92,
2052 &periph_u_regs, periph_clk_enb_refcnt);
2053 clks[csus] = clk;
2054
2055 /* dds */
2056 clk = tegra_clk_register_periph_gate("dds", "clk_m",
2057 TEGRA_PERIPH_ON_APB, clk_base, 0, 150,
2058 &periph_w_regs, periph_clk_enb_refcnt);
2059 clks[dds] = clk;
2060
2061 /* dp2 */
2062 clk = tegra_clk_register_periph_gate("dp2", "clk_m",
2063 TEGRA_PERIPH_ON_APB, clk_base, 0, 152,
2064 &periph_w_regs, periph_clk_enb_refcnt);
2065 clks[dp2] = clk;
2066
2067 /* dtv */
2068 clk = tegra_clk_register_periph_gate("dtv", "clk_m",
2069 TEGRA_PERIPH_ON_APB, clk_base, 0, 79,
2070 &periph_u_regs, periph_clk_enb_refcnt);
2071 clks[dtv] = clk;
2072
2073 /* dsia */
2074 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0, 1197 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
2075 ARRAY_SIZE(mux_plld_out0_plld2_out0), 1198 ARRAY_SIZE(mux_plld_out0_plld2_out0),
2076 CLK_SET_RATE_NO_REPARENT, 1199 CLK_SET_RATE_NO_REPARENT,
2077 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock); 1200 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
2078 clks[dsia_mux] = clk; 1201 clks[TEGRA114_CLK_DSIA_MUX] = clk;
2079 clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base,
2080 0, 48, &periph_h_regs,
2081 periph_clk_enb_refcnt);
2082 clks[dsia] = clk;
2083 1202
2084 /* dsib */ 1203 /* dsib mux */
2085 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0, 1204 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0,
2086 ARRAY_SIZE(mux_plld_out0_plld2_out0), 1205 ARRAY_SIZE(mux_plld_out0_plld2_out0),
2087 CLK_SET_RATE_NO_REPARENT, 1206 CLK_SET_RATE_NO_REPARENT,
2088 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock); 1207 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
2089 clks[dsib_mux] = clk; 1208 clks[TEGRA114_CLK_DSIB_MUX] = clk;
2090 clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base,
2091 0, 82, &periph_u_regs,
2092 periph_clk_enb_refcnt);
2093 clks[dsib] = clk;
2094 1209
2095 /* xusb_hs_src */ 1210 /* emc mux */
2096 val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC);
2097 val |= BIT(25); /* always select PLLU_60M */
2098 writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC);
2099
2100 clk = clk_register_fixed_factor(NULL, "xusb_hs_src", "pll_u_60M", 0,
2101 1, 1);
2102 clks[xusb_hs_src] = clk;
2103
2104 /* xusb_host */
2105 clk = tegra_clk_register_periph_gate("xusb_host", "xusb_host_src", 0,
2106 clk_base, 0, 89, &periph_u_regs,
2107 periph_clk_enb_refcnt);
2108 clks[xusb_host] = clk;
2109
2110 /* xusb_ss */
2111 clk = tegra_clk_register_periph_gate("xusb_ss", "xusb_ss_src", 0,
2112 clk_base, 0, 156, &periph_w_regs,
2113 periph_clk_enb_refcnt);
2114 clks[xusb_host] = clk;
2115
2116 /* xusb_dev */
2117 clk = tegra_clk_register_periph_gate("xusb_dev", "xusb_dev_src", 0,
2118 clk_base, 0, 95, &periph_u_regs,
2119 periph_clk_enb_refcnt);
2120 clks[xusb_dev] = clk;
2121
2122 /* emc */
2123 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 1211 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
2124 ARRAY_SIZE(mux_pllmcp_clkm), 1212 ARRAY_SIZE(mux_pllmcp_clkm),
2125 CLK_SET_RATE_NO_REPARENT, 1213 CLK_SET_RATE_NO_REPARENT,
2126 clk_base + CLK_SOURCE_EMC, 1214 clk_base + CLK_SOURCE_EMC,
2127 29, 3, 0, NULL); 1215 29, 3, 0, NULL);
2128 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base,
2129 CLK_IGNORE_UNUSED, 57, &periph_h_regs,
2130 periph_clk_enb_refcnt);
2131 clks[emc] = clk;
2132
2133 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
2134 data = &tegra_periph_clk_list[i];
2135 clk = tegra_clk_register_periph(data->name, data->parent_names,
2136 data->num_parents, &data->periph,
2137 clk_base, data->offset, data->flags);
2138 clks[data->clk_id] = clk;
2139 }
2140 1216
2141 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) { 1217 tegra_periph_clk_init(clk_base, pmc_base, tegra114_clks,
2142 data = &tegra_periph_nodiv_clk_list[i]; 1218 &pll_p_params);
2143 clk = tegra_clk_register_periph_nodiv(data->name,
2144 data->parent_names, data->num_parents,
2145 &data->periph, clk_base, data->offset);
2146 clks[data->clk_id] = clk;
2147 }
2148} 1219}
2149 1220
2150/* Tegra114 CPU clock and reset control functions */ 1221/* Tegra114 CPU clock and reset control functions */
@@ -2207,28 +1278,37 @@ static const struct of_device_id pmc_match[] __initconst = {
2207 * breaks 1278 * breaks
2208 */ 1279 */
2209static struct tegra_clk_init_table init_table[] __initdata = { 1280static struct tegra_clk_init_table init_table[] __initdata = {
2210 {uarta, pll_p, 408000000, 0}, 1281 {TEGRA114_CLK_UARTA, TEGRA114_CLK_PLL_P, 408000000, 0},
2211 {uartb, pll_p, 408000000, 0}, 1282 {TEGRA114_CLK_UARTB, TEGRA114_CLK_PLL_P, 408000000, 0},
2212 {uartc, pll_p, 408000000, 0}, 1283 {TEGRA114_CLK_UARTC, TEGRA114_CLK_PLL_P, 408000000, 0},
2213 {uartd, pll_p, 408000000, 0}, 1284 {TEGRA114_CLK_UARTD, TEGRA114_CLK_PLL_P, 408000000, 0},
2214 {pll_a, clk_max, 564480000, 1}, 1285 {TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 1},
2215 {pll_a_out0, clk_max, 11289600, 1}, 1286 {TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 1},
2216 {extern1, pll_a_out0, 0, 1}, 1287 {TEGRA114_CLK_EXTERN1, TEGRA114_CLK_PLL_A_OUT0, 0, 1},
2217 {clk_out_1_mux, extern1, 0, 1}, 1288 {TEGRA114_CLK_CLK_OUT_1_MUX, TEGRA114_CLK_EXTERN1, 0, 1},
2218 {clk_out_1, clk_max, 0, 1}, 1289 {TEGRA114_CLK_CLK_OUT_1, TEGRA114_CLK_CLK_MAX, 0, 1},
2219 {i2s0, pll_a_out0, 11289600, 0}, 1290 {TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
2220 {i2s1, pll_a_out0, 11289600, 0}, 1291 {TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
2221 {i2s2, pll_a_out0, 11289600, 0}, 1292 {TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
2222 {i2s3, pll_a_out0, 11289600, 0}, 1293 {TEGRA114_CLK_I2S3, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
2223 {i2s4, pll_a_out0, 11289600, 0}, 1294 {TEGRA114_CLK_I2S4, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
2224 {dfll_soc, pll_p, 51000000, 1}, 1295 {TEGRA114_CLK_HOST1X, TEGRA114_CLK_PLL_P, 136000000, 0},
2225 {dfll_ref, pll_p, 51000000, 1}, 1296 {TEGRA114_CLK_DFLL_SOC, TEGRA114_CLK_PLL_P, 51000000, 1},
2226 {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */ 1297 {TEGRA114_CLK_DFLL_REF, TEGRA114_CLK_PLL_P, 51000000, 1},
1298 {TEGRA114_CLK_DISP1, TEGRA114_CLK_PLL_P, 0, 0},
1299 {TEGRA114_CLK_DISP2, TEGRA114_CLK_PLL_P, 0, 0},
1300 {TEGRA114_CLK_GR2D, TEGRA114_CLK_PLL_C2, 300000000, 0},
1301 {TEGRA114_CLK_GR3D, TEGRA114_CLK_PLL_C2, 300000000, 0},
1302 {TEGRA114_CLK_DSIALP, TEGRA114_CLK_PLL_P, 68000000, 0},
1303 {TEGRA114_CLK_DSIBLP, TEGRA114_CLK_PLL_P, 68000000, 0},
1304
1305 /* This MUST be the last entry. */
1306 {TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0},
2227}; 1307};
2228 1308
2229static void __init tegra114_clock_apply_init_table(void) 1309static void __init tegra114_clock_apply_init_table(void)
2230{ 1310{
2231 tegra_init_from_table(init_table, clks, clk_max); 1311 tegra_init_from_table(init_table, clks, TEGRA114_CLK_CLK_MAX);
2232} 1312}
2233 1313
2234 1314
@@ -2359,7 +1439,6 @@ EXPORT_SYMBOL(tegra114_clock_deassert_dfll_dvco_reset);
2359static void __init tegra114_clock_init(struct device_node *np) 1439static void __init tegra114_clock_init(struct device_node *np)
2360{ 1440{
2361 struct device_node *node; 1441 struct device_node *node;
2362 int i;
2363 1442
2364 clk_base = of_iomap(np, 0); 1443 clk_base = of_iomap(np, 0);
2365 if (!clk_base) { 1444 if (!clk_base) {
@@ -2381,29 +1460,23 @@ static void __init tegra114_clock_init(struct device_node *np)
2381 return; 1460 return;
2382 } 1461 }
2383 1462
1463 clks = tegra_clk_init(TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_PERIPH_BANKS);
1464 if (!clks)
1465 return;
1466
2384 if (tegra114_osc_clk_init(clk_base) < 0) 1467 if (tegra114_osc_clk_init(clk_base) < 0)
2385 return; 1468 return;
2386 1469
2387 tegra114_fixed_clk_init(clk_base); 1470 tegra114_fixed_clk_init(clk_base);
2388 tegra114_pll_init(clk_base, pmc_base); 1471 tegra114_pll_init(clk_base, pmc_base);
2389 tegra114_periph_clk_init(clk_base); 1472 tegra114_periph_clk_init(clk_base, pmc_base);
2390 tegra114_audio_clk_init(clk_base); 1473 tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks, &pll_a_params);
2391 tegra114_pmc_clk_init(pmc_base); 1474 tegra_pmc_clk_init(pmc_base, tegra114_clks);
2392 tegra114_super_clk_init(clk_base); 1475 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks,
2393 1476 &pll_x_params);
2394 for (i = 0; i < ARRAY_SIZE(clks); i++) { 1477
2395 if (IS_ERR(clks[i])) { 1478 tegra_add_of_provider(np);
2396 pr_err 1479 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
2397 ("Tegra114 clk %d: register failed with %ld\n",
2398 i, PTR_ERR(clks[i]));
2399 }
2400 if (!clks[i])
2401 clks[i] = ERR_PTR(-EINVAL);
2402 }
2403
2404 clk_data.clks = clks;
2405 clk_data.clk_num = ARRAY_SIZE(clks);
2406 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
2407 1480
2408 tegra_clk_apply_init_table = tegra114_clock_apply_init_table; 1481 tegra_clk_apply_init_table = tegra114_clock_apply_init_table;
2409 1482
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
new file mode 100644
index 000000000000..0ef4485e9b0a
--- /dev/null
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -0,0 +1,1424 @@
1/*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/clk-provider.h>
20#include <linux/clkdev.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/delay.h>
24#include <linux/export.h>
25#include <linux/clk/tegra.h>
26#include <dt-bindings/clock/tegra124-car.h>
27
28#include "clk.h"
29#include "clk-id.h"
30
31#define CLK_SOURCE_CSITE 0x1d4
32#define CLK_SOURCE_EMC 0x19c
33#define CLK_SOURCE_XUSB_SS_SRC 0x610
34
35#define PLLC_BASE 0x80
36#define PLLC_OUT 0x84
37#define PLLC_MISC2 0x88
38#define PLLC_MISC 0x8c
39#define PLLC2_BASE 0x4e8
40#define PLLC2_MISC 0x4ec
41#define PLLC3_BASE 0x4fc
42#define PLLC3_MISC 0x500
43#define PLLM_BASE 0x90
44#define PLLM_OUT 0x94
45#define PLLM_MISC 0x9c
46#define PLLP_BASE 0xa0
47#define PLLP_MISC 0xac
48#define PLLA_BASE 0xb0
49#define PLLA_MISC 0xbc
50#define PLLD_BASE 0xd0
51#define PLLD_MISC 0xdc
52#define PLLU_BASE 0xc0
53#define PLLU_MISC 0xcc
54#define PLLX_BASE 0xe0
55#define PLLX_MISC 0xe4
56#define PLLX_MISC2 0x514
57#define PLLX_MISC3 0x518
58#define PLLE_BASE 0xe8
59#define PLLE_MISC 0xec
60#define PLLD2_BASE 0x4b8
61#define PLLD2_MISC 0x4bc
62#define PLLE_AUX 0x48c
63#define PLLRE_BASE 0x4c4
64#define PLLRE_MISC 0x4c8
65#define PLLDP_BASE 0x590
66#define PLLDP_MISC 0x594
67#define PLLC4_BASE 0x5a4
68#define PLLC4_MISC 0x5a8
69
70#define PLLC_IDDQ_BIT 26
71#define PLLRE_IDDQ_BIT 16
72#define PLLSS_IDDQ_BIT 19
73
74#define PLL_BASE_LOCK BIT(27)
75#define PLLE_MISC_LOCK BIT(11)
76#define PLLRE_MISC_LOCK BIT(24)
77
78#define PLL_MISC_LOCK_ENABLE 18
79#define PLLC_MISC_LOCK_ENABLE 24
80#define PLLDU_MISC_LOCK_ENABLE 22
81#define PLLE_MISC_LOCK_ENABLE 9
82#define PLLRE_MISC_LOCK_ENABLE 30
83#define PLLSS_MISC_LOCK_ENABLE 30
84
85#define PLLXC_SW_MAX_P 6
86
87#define PMC_PLLM_WB0_OVERRIDE 0x1dc
88#define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
89
90#define UTMIP_PLL_CFG2 0x488
91#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
92#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
93#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
94#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
95#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
96
97#define UTMIP_PLL_CFG1 0x484
98#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
99#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
100#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
101#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
102#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
103#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
104#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
105
106#define UTMIPLL_HW_PWRDN_CFG0 0x52c
107#define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25)
108#define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
109#define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
110#define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
111#define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
112#define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
113#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
114#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
115
116/* Tegra CPU clock and reset control regs */
117#define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
118
119#ifdef CONFIG_PM_SLEEP
120static struct cpu_clk_suspend_context {
121 u32 clk_csite_src;
122} tegra124_cpu_clk_sctx;
123#endif
124
125static void __iomem *clk_base;
126static void __iomem *pmc_base;
127
128static unsigned long osc_freq;
129static unsigned long pll_ref_freq;
130
131static DEFINE_SPINLOCK(pll_d_lock);
132static DEFINE_SPINLOCK(pll_d2_lock);
133static DEFINE_SPINLOCK(pll_e_lock);
134static DEFINE_SPINLOCK(pll_re_lock);
135static DEFINE_SPINLOCK(pll_u_lock);
136
137/* possible OSC frequencies in Hz */
138static unsigned long tegra124_input_freq[] = {
139 [0] = 13000000,
140 [1] = 16800000,
141 [4] = 19200000,
142 [5] = 38400000,
143 [8] = 12000000,
144 [9] = 48000000,
145 [12] = 260000000,
146};
147
148static const char *mux_plld_out0_plld2_out0[] = {
149 "pll_d_out0", "pll_d2_out0",
150};
151#define mux_plld_out0_plld2_out0_idx NULL
152
153static const char *mux_pllmcp_clkm[] = {
154 "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_c2", "pll_c3",
155};
156#define mux_pllmcp_clkm_idx NULL
157
158static struct div_nmp pllxc_nmp = {
159 .divm_shift = 0,
160 .divm_width = 8,
161 .divn_shift = 8,
162 .divn_width = 8,
163 .divp_shift = 20,
164 .divp_width = 4,
165};
166
167static struct pdiv_map pllxc_p[] = {
168 { .pdiv = 1, .hw_val = 0 },
169 { .pdiv = 2, .hw_val = 1 },
170 { .pdiv = 3, .hw_val = 2 },
171 { .pdiv = 4, .hw_val = 3 },
172 { .pdiv = 5, .hw_val = 4 },
173 { .pdiv = 6, .hw_val = 5 },
174 { .pdiv = 8, .hw_val = 6 },
175 { .pdiv = 10, .hw_val = 7 },
176 { .pdiv = 12, .hw_val = 8 },
177 { .pdiv = 16, .hw_val = 9 },
178 { .pdiv = 12, .hw_val = 10 },
179 { .pdiv = 16, .hw_val = 11 },
180 { .pdiv = 20, .hw_val = 12 },
181 { .pdiv = 24, .hw_val = 13 },
182 { .pdiv = 32, .hw_val = 14 },
183 { .pdiv = 0, .hw_val = 0 },
184};
185
186static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
187 /* 1 GHz */
188 {12000000, 1000000000, 83, 0, 1}, /* actual: 996.0 MHz */
189 {13000000, 1000000000, 76, 0, 1}, /* actual: 988.0 MHz */
190 {16800000, 1000000000, 59, 0, 1}, /* actual: 991.2 MHz */
191 {19200000, 1000000000, 52, 0, 1}, /* actual: 998.4 MHz */
192 {26000000, 1000000000, 76, 1, 1}, /* actual: 988.0 MHz */
193 {0, 0, 0, 0, 0, 0},
194};
195
196static struct tegra_clk_pll_params pll_x_params = {
197 .input_min = 12000000,
198 .input_max = 800000000,
199 .cf_min = 12000000,
200 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
201 .vco_min = 700000000,
202 .vco_max = 3000000000UL,
203 .base_reg = PLLX_BASE,
204 .misc_reg = PLLX_MISC,
205 .lock_mask = PLL_BASE_LOCK,
206 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
207 .lock_delay = 300,
208 .iddq_reg = PLLX_MISC3,
209 .iddq_bit_idx = 3,
210 .max_p = 6,
211 .dyn_ramp_reg = PLLX_MISC2,
212 .stepa_shift = 16,
213 .stepb_shift = 24,
214 .pdiv_tohw = pllxc_p,
215 .div_nmp = &pllxc_nmp,
216 .freq_table = pll_x_freq_table,
217 .flags = TEGRA_PLL_USE_LOCK,
218};
219
220static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
221 { 12000000, 624000000, 104, 1, 2},
222 { 12000000, 600000000, 100, 1, 2},
223 { 13000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
224 { 16800000, 600000000, 71, 1, 2}, /* actual: 596.4 MHz */
225 { 19200000, 600000000, 62, 1, 2}, /* actual: 595.2 MHz */
226 { 26000000, 600000000, 92, 2, 2}, /* actual: 598.0 MHz */
227 { 0, 0, 0, 0, 0, 0 },
228};
229
230static struct tegra_clk_pll_params pll_c_params = {
231 .input_min = 12000000,
232 .input_max = 800000000,
233 .cf_min = 12000000,
234 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
235 .vco_min = 600000000,
236 .vco_max = 1400000000,
237 .base_reg = PLLC_BASE,
238 .misc_reg = PLLC_MISC,
239 .lock_mask = PLL_BASE_LOCK,
240 .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE,
241 .lock_delay = 300,
242 .iddq_reg = PLLC_MISC,
243 .iddq_bit_idx = PLLC_IDDQ_BIT,
244 .max_p = PLLXC_SW_MAX_P,
245 .dyn_ramp_reg = PLLC_MISC2,
246 .stepa_shift = 17,
247 .stepb_shift = 9,
248 .pdiv_tohw = pllxc_p,
249 .div_nmp = &pllxc_nmp,
250 .freq_table = pll_c_freq_table,
251 .flags = TEGRA_PLL_USE_LOCK,
252};
253
254static struct div_nmp pllcx_nmp = {
255 .divm_shift = 0,
256 .divm_width = 2,
257 .divn_shift = 8,
258 .divn_width = 8,
259 .divp_shift = 20,
260 .divp_width = 3,
261};
262
263static struct pdiv_map pllc_p[] = {
264 { .pdiv = 1, .hw_val = 0 },
265 { .pdiv = 2, .hw_val = 1 },
266 { .pdiv = 3, .hw_val = 2 },
267 { .pdiv = 4, .hw_val = 3 },
268 { .pdiv = 6, .hw_val = 4 },
269 { .pdiv = 8, .hw_val = 5 },
270 { .pdiv = 12, .hw_val = 6 },
271 { .pdiv = 16, .hw_val = 7 },
272 { .pdiv = 0, .hw_val = 0 },
273};
274
275static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
276 {12000000, 600000000, 100, 1, 2},
277 {13000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
278 {16800000, 600000000, 71, 1, 2}, /* actual: 596.4 MHz */
279 {19200000, 600000000, 62, 1, 2}, /* actual: 595.2 MHz */
280 {26000000, 600000000, 92, 2, 2}, /* actual: 598.0 MHz */
281 {0, 0, 0, 0, 0, 0},
282};
283
284static struct tegra_clk_pll_params pll_c2_params = {
285 .input_min = 12000000,
286 .input_max = 48000000,
287 .cf_min = 12000000,
288 .cf_max = 19200000,
289 .vco_min = 600000000,
290 .vco_max = 1200000000,
291 .base_reg = PLLC2_BASE,
292 .misc_reg = PLLC2_MISC,
293 .lock_mask = PLL_BASE_LOCK,
294 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
295 .lock_delay = 300,
296 .pdiv_tohw = pllc_p,
297 .div_nmp = &pllcx_nmp,
298 .max_p = 7,
299 .ext_misc_reg[0] = 0x4f0,
300 .ext_misc_reg[1] = 0x4f4,
301 .ext_misc_reg[2] = 0x4f8,
302 .freq_table = pll_cx_freq_table,
303 .flags = TEGRA_PLL_USE_LOCK,
304};
305
306static struct tegra_clk_pll_params pll_c3_params = {
307 .input_min = 12000000,
308 .input_max = 48000000,
309 .cf_min = 12000000,
310 .cf_max = 19200000,
311 .vco_min = 600000000,
312 .vco_max = 1200000000,
313 .base_reg = PLLC3_BASE,
314 .misc_reg = PLLC3_MISC,
315 .lock_mask = PLL_BASE_LOCK,
316 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
317 .lock_delay = 300,
318 .pdiv_tohw = pllc_p,
319 .div_nmp = &pllcx_nmp,
320 .max_p = 7,
321 .ext_misc_reg[0] = 0x504,
322 .ext_misc_reg[1] = 0x508,
323 .ext_misc_reg[2] = 0x50c,
324 .freq_table = pll_cx_freq_table,
325 .flags = TEGRA_PLL_USE_LOCK,
326};
327
328static struct div_nmp pllss_nmp = {
329 .divm_shift = 0,
330 .divm_width = 8,
331 .divn_shift = 8,
332 .divn_width = 8,
333 .divp_shift = 20,
334 .divp_width = 4,
335};
336
337static struct pdiv_map pll12g_ssd_esd_p[] = {
338 { .pdiv = 1, .hw_val = 0 },
339 { .pdiv = 2, .hw_val = 1 },
340 { .pdiv = 3, .hw_val = 2 },
341 { .pdiv = 4, .hw_val = 3 },
342 { .pdiv = 5, .hw_val = 4 },
343 { .pdiv = 6, .hw_val = 5 },
344 { .pdiv = 8, .hw_val = 6 },
345 { .pdiv = 10, .hw_val = 7 },
346 { .pdiv = 12, .hw_val = 8 },
347 { .pdiv = 16, .hw_val = 9 },
348 { .pdiv = 12, .hw_val = 10 },
349 { .pdiv = 16, .hw_val = 11 },
350 { .pdiv = 20, .hw_val = 12 },
351 { .pdiv = 24, .hw_val = 13 },
352 { .pdiv = 32, .hw_val = 14 },
353 { .pdiv = 0, .hw_val = 0 },
354};
355
356static struct tegra_clk_pll_freq_table pll_c4_freq_table[] = {
357 { 12000000, 600000000, 100, 1, 1},
358 { 13000000, 600000000, 92, 1, 1}, /* actual: 598.0 MHz */
359 { 16800000, 600000000, 71, 1, 1}, /* actual: 596.4 MHz */
360 { 19200000, 600000000, 62, 1, 1}, /* actual: 595.2 MHz */
361 { 26000000, 600000000, 92, 2, 1}, /* actual: 598.0 MHz */
362 { 0, 0, 0, 0, 0, 0 },
363};
364
365static struct tegra_clk_pll_params pll_c4_params = {
366 .input_min = 12000000,
367 .input_max = 1000000000,
368 .cf_min = 12000000,
369 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
370 .vco_min = 600000000,
371 .vco_max = 1200000000,
372 .base_reg = PLLC4_BASE,
373 .misc_reg = PLLC4_MISC,
374 .lock_mask = PLL_BASE_LOCK,
375 .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
376 .lock_delay = 300,
377 .iddq_reg = PLLC4_BASE,
378 .iddq_bit_idx = PLLSS_IDDQ_BIT,
379 .pdiv_tohw = pll12g_ssd_esd_p,
380 .div_nmp = &pllss_nmp,
381 .ext_misc_reg[0] = 0x5ac,
382 .ext_misc_reg[1] = 0x5b0,
383 .ext_misc_reg[2] = 0x5b4,
384 .freq_table = pll_c4_freq_table,
385};
386
387static struct pdiv_map pllm_p[] = {
388 { .pdiv = 1, .hw_val = 0 },
389 { .pdiv = 2, .hw_val = 1 },
390 { .pdiv = 0, .hw_val = 0 },
391};
392
393static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
394 {12000000, 800000000, 66, 1, 1}, /* actual: 792.0 MHz */
395 {13000000, 800000000, 61, 1, 1}, /* actual: 793.0 MHz */
396 {16800000, 800000000, 47, 1, 1}, /* actual: 789.6 MHz */
397 {19200000, 800000000, 41, 1, 1}, /* actual: 787.2 MHz */
398 {26000000, 800000000, 61, 2, 1}, /* actual: 793.0 MHz */
399 {0, 0, 0, 0, 0, 0},
400};
401
402static struct div_nmp pllm_nmp = {
403 .divm_shift = 0,
404 .divm_width = 8,
405 .override_divm_shift = 0,
406 .divn_shift = 8,
407 .divn_width = 8,
408 .override_divn_shift = 8,
409 .divp_shift = 20,
410 .divp_width = 1,
411 .override_divp_shift = 27,
412};
413
414static struct tegra_clk_pll_params pll_m_params = {
415 .input_min = 12000000,
416 .input_max = 500000000,
417 .cf_min = 12000000,
418 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
419 .vco_min = 400000000,
420 .vco_max = 1066000000,
421 .base_reg = PLLM_BASE,
422 .misc_reg = PLLM_MISC,
423 .lock_mask = PLL_BASE_LOCK,
424 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
425 .lock_delay = 300,
426 .max_p = 2,
427 .pdiv_tohw = pllm_p,
428 .div_nmp = &pllm_nmp,
429 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
430 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
431 .freq_table = pll_m_freq_table,
432 .flags = TEGRA_PLL_USE_LOCK,
433};
434
435static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
436 /* PLLE special case: use cpcon field to store cml divider value */
437 {336000000, 100000000, 100, 21, 16, 11},
438 {312000000, 100000000, 200, 26, 24, 13},
439 {13000000, 100000000, 200, 1, 26, 13},
440 {12000000, 100000000, 200, 1, 24, 13},
441 {0, 0, 0, 0, 0, 0},
442};
443
444static struct div_nmp plle_nmp = {
445 .divm_shift = 0,
446 .divm_width = 8,
447 .divn_shift = 8,
448 .divn_width = 8,
449 .divp_shift = 24,
450 .divp_width = 4,
451};
452
453static struct tegra_clk_pll_params pll_e_params = {
454 .input_min = 12000000,
455 .input_max = 1000000000,
456 .cf_min = 12000000,
457 .cf_max = 75000000,
458 .vco_min = 1600000000,
459 .vco_max = 2400000000U,
460 .base_reg = PLLE_BASE,
461 .misc_reg = PLLE_MISC,
462 .aux_reg = PLLE_AUX,
463 .lock_mask = PLLE_MISC_LOCK,
464 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
465 .lock_delay = 300,
466 .div_nmp = &plle_nmp,
467 .freq_table = pll_e_freq_table,
468 .flags = TEGRA_PLL_FIXED,
469 .fixed_rate = 100000000,
470};
471
472static const struct clk_div_table pll_re_div_table[] = {
473 { .val = 0, .div = 1 },
474 { .val = 1, .div = 2 },
475 { .val = 2, .div = 3 },
476 { .val = 3, .div = 4 },
477 { .val = 4, .div = 5 },
478 { .val = 5, .div = 6 },
479 { .val = 0, .div = 0 },
480};
481
482static struct div_nmp pllre_nmp = {
483 .divm_shift = 0,
484 .divm_width = 8,
485 .divn_shift = 8,
486 .divn_width = 8,
487 .divp_shift = 16,
488 .divp_width = 4,
489};
490
491static struct tegra_clk_pll_params pll_re_vco_params = {
492 .input_min = 12000000,
493 .input_max = 1000000000,
494 .cf_min = 12000000,
495 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
496 .vco_min = 300000000,
497 .vco_max = 600000000,
498 .base_reg = PLLRE_BASE,
499 .misc_reg = PLLRE_MISC,
500 .lock_mask = PLLRE_MISC_LOCK,
501 .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE,
502 .lock_delay = 300,
503 .iddq_reg = PLLRE_MISC,
504 .iddq_bit_idx = PLLRE_IDDQ_BIT,
505 .div_nmp = &pllre_nmp,
506 .flags = TEGRA_PLL_USE_LOCK,
507};
508
509static struct div_nmp pllp_nmp = {
510 .divm_shift = 0,
511 .divm_width = 5,
512 .divn_shift = 8,
513 .divn_width = 10,
514 .divp_shift = 20,
515 .divp_width = 3,
516};
517
518static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
519 {12000000, 216000000, 432, 12, 1, 8},
520 {13000000, 216000000, 432, 13, 1, 8},
521 {16800000, 216000000, 360, 14, 1, 8},
522 {19200000, 216000000, 360, 16, 1, 8},
523 {26000000, 216000000, 432, 26, 1, 8},
524 {0, 0, 0, 0, 0, 0},
525};
526
527static struct tegra_clk_pll_params pll_p_params = {
528 .input_min = 2000000,
529 .input_max = 31000000,
530 .cf_min = 1000000,
531 .cf_max = 6000000,
532 .vco_min = 200000000,
533 .vco_max = 700000000,
534 .base_reg = PLLP_BASE,
535 .misc_reg = PLLP_MISC,
536 .lock_mask = PLL_BASE_LOCK,
537 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
538 .lock_delay = 300,
539 .div_nmp = &pllp_nmp,
540 .freq_table = pll_p_freq_table,
541 .fixed_rate = 408000000,
542 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK,
543};
544
545static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
546 {9600000, 282240000, 147, 5, 0, 4},
547 {9600000, 368640000, 192, 5, 0, 4},
548 {9600000, 240000000, 200, 8, 0, 8},
549
550 {28800000, 282240000, 245, 25, 0, 8},
551 {28800000, 368640000, 320, 25, 0, 8},
552 {28800000, 240000000, 200, 24, 0, 8},
553 {0, 0, 0, 0, 0, 0},
554};
555
556static struct tegra_clk_pll_params pll_a_params = {
557 .input_min = 2000000,
558 .input_max = 31000000,
559 .cf_min = 1000000,
560 .cf_max = 6000000,
561 .vco_min = 200000000,
562 .vco_max = 700000000,
563 .base_reg = PLLA_BASE,
564 .misc_reg = PLLA_MISC,
565 .lock_mask = PLL_BASE_LOCK,
566 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
567 .lock_delay = 300,
568 .div_nmp = &pllp_nmp,
569 .freq_table = pll_a_freq_table,
570 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
571};
572
573static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
574 {12000000, 216000000, 864, 12, 4, 12},
575 {13000000, 216000000, 864, 13, 4, 12},
576 {16800000, 216000000, 720, 14, 4, 12},
577 {19200000, 216000000, 720, 16, 4, 12},
578 {26000000, 216000000, 864, 26, 4, 12},
579
580 {12000000, 594000000, 594, 12, 1, 12},
581 {13000000, 594000000, 594, 13, 1, 12},
582 {16800000, 594000000, 495, 14, 1, 12},
583 {19200000, 594000000, 495, 16, 1, 12},
584 {26000000, 594000000, 594, 26, 1, 12},
585
586 {12000000, 1000000000, 1000, 12, 1, 12},
587 {13000000, 1000000000, 1000, 13, 1, 12},
588 {19200000, 1000000000, 625, 12, 1, 12},
589 {26000000, 1000000000, 1000, 26, 1, 12},
590
591 {0, 0, 0, 0, 0, 0},
592};
593
594static struct tegra_clk_pll_params pll_d_params = {
595 .input_min = 2000000,
596 .input_max = 40000000,
597 .cf_min = 1000000,
598 .cf_max = 6000000,
599 .vco_min = 500000000,
600 .vco_max = 1000000000,
601 .base_reg = PLLD_BASE,
602 .misc_reg = PLLD_MISC,
603 .lock_mask = PLL_BASE_LOCK,
604 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
605 .lock_delay = 1000,
606 .div_nmp = &pllp_nmp,
607 .freq_table = pll_d_freq_table,
608 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
609 TEGRA_PLL_USE_LOCK,
610};
611
612static struct tegra_clk_pll_freq_table tegra124_pll_d2_freq_table[] = {
613 { 12000000, 148500000, 99, 1, 8},
614 { 12000000, 594000000, 99, 1, 1},
615 { 13000000, 594000000, 91, 1, 1}, /* actual: 591.5 MHz */
616 { 16800000, 594000000, 71, 1, 1}, /* actual: 596.4 MHz */
617 { 19200000, 594000000, 62, 1, 1}, /* actual: 595.2 MHz */
618 { 26000000, 594000000, 91, 2, 1}, /* actual: 591.5 MHz */
619 { 0, 0, 0, 0, 0, 0 },
620};
621
622static struct tegra_clk_pll_params tegra124_pll_d2_params = {
623 .input_min = 12000000,
624 .input_max = 1000000000,
625 .cf_min = 12000000,
626 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
627 .vco_min = 600000000,
628 .vco_max = 1200000000,
629 .base_reg = PLLD2_BASE,
630 .misc_reg = PLLD2_MISC,
631 .lock_mask = PLL_BASE_LOCK,
632 .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
633 .lock_delay = 300,
634 .iddq_reg = PLLD2_BASE,
635 .iddq_bit_idx = PLLSS_IDDQ_BIT,
636 .pdiv_tohw = pll12g_ssd_esd_p,
637 .div_nmp = &pllss_nmp,
638 .ext_misc_reg[0] = 0x570,
639 .ext_misc_reg[1] = 0x574,
640 .ext_misc_reg[2] = 0x578,
641 .max_p = 15,
642 .freq_table = tegra124_pll_d2_freq_table,
643};
644
645static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = {
646 { 12000000, 600000000, 100, 1, 1},
647 { 13000000, 600000000, 92, 1, 1}, /* actual: 598.0 MHz */
648 { 16800000, 600000000, 71, 1, 1}, /* actual: 596.4 MHz */
649 { 19200000, 600000000, 62, 1, 1}, /* actual: 595.2 MHz */
650 { 26000000, 600000000, 92, 2, 1}, /* actual: 598.0 MHz */
651 { 0, 0, 0, 0, 0, 0 },
652};
653
654static struct tegra_clk_pll_params pll_dp_params = {
655 .input_min = 12000000,
656 .input_max = 1000000000,
657 .cf_min = 12000000,
658 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
659 .vco_min = 600000000,
660 .vco_max = 1200000000,
661 .base_reg = PLLDP_BASE,
662 .misc_reg = PLLDP_MISC,
663 .lock_mask = PLL_BASE_LOCK,
664 .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
665 .lock_delay = 300,
666 .iddq_reg = PLLDP_BASE,
667 .iddq_bit_idx = PLLSS_IDDQ_BIT,
668 .pdiv_tohw = pll12g_ssd_esd_p,
669 .div_nmp = &pllss_nmp,
670 .ext_misc_reg[0] = 0x598,
671 .ext_misc_reg[1] = 0x59c,
672 .ext_misc_reg[2] = 0x5a0,
673 .max_p = 5,
674 .freq_table = pll_dp_freq_table,
675};
676
677static struct pdiv_map pllu_p[] = {
678 { .pdiv = 1, .hw_val = 1 },
679 { .pdiv = 2, .hw_val = 0 },
680 { .pdiv = 0, .hw_val = 0 },
681};
682
683static struct div_nmp pllu_nmp = {
684 .divm_shift = 0,
685 .divm_width = 5,
686 .divn_shift = 8,
687 .divn_width = 10,
688 .divp_shift = 20,
689 .divp_width = 1,
690};
691
692static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
693 {12000000, 480000000, 960, 12, 2, 12},
694 {13000000, 480000000, 960, 13, 2, 12},
695 {16800000, 480000000, 400, 7, 2, 5},
696 {19200000, 480000000, 200, 4, 2, 3},
697 {26000000, 480000000, 960, 26, 2, 12},
698 {0, 0, 0, 0, 0, 0},
699};
700
701static struct tegra_clk_pll_params pll_u_params = {
702 .input_min = 2000000,
703 .input_max = 40000000,
704 .cf_min = 1000000,
705 .cf_max = 6000000,
706 .vco_min = 480000000,
707 .vco_max = 960000000,
708 .base_reg = PLLU_BASE,
709 .misc_reg = PLLU_MISC,
710 .lock_mask = PLL_BASE_LOCK,
711 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
712 .lock_delay = 1000,
713 .pdiv_tohw = pllu_p,
714 .div_nmp = &pllu_nmp,
715 .freq_table = pll_u_freq_table,
716 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
717 TEGRA_PLL_USE_LOCK,
718};
719
720struct utmi_clk_param {
721 /* Oscillator Frequency in KHz */
722 u32 osc_frequency;
723 /* UTMIP PLL Enable Delay Count */
724 u8 enable_delay_count;
725 /* UTMIP PLL Stable count */
726 u8 stable_count;
727 /* UTMIP PLL Active delay count */
728 u8 active_delay_count;
729 /* UTMIP PLL Xtal frequency count */
730 u8 xtal_freq_count;
731};
732
733static const struct utmi_clk_param utmi_parameters[] = {
734 {.osc_frequency = 13000000, .enable_delay_count = 0x02,
735 .stable_count = 0x33, .active_delay_count = 0x05,
736 .xtal_freq_count = 0x7F},
737 {.osc_frequency = 19200000, .enable_delay_count = 0x03,
738 .stable_count = 0x4B, .active_delay_count = 0x06,
739 .xtal_freq_count = 0xBB},
740 {.osc_frequency = 12000000, .enable_delay_count = 0x02,
741 .stable_count = 0x2F, .active_delay_count = 0x04,
742 .xtal_freq_count = 0x76},
743 {.osc_frequency = 26000000, .enable_delay_count = 0x04,
744 .stable_count = 0x66, .active_delay_count = 0x09,
745 .xtal_freq_count = 0xFE},
746 {.osc_frequency = 16800000, .enable_delay_count = 0x03,
747 .stable_count = 0x41, .active_delay_count = 0x0A,
748 .xtal_freq_count = 0xA4},
749};
750
751static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
752 [tegra_clk_ispb] = { .dt_id = TEGRA124_CLK_ISPB, .present = true },
753 [tegra_clk_rtc] = { .dt_id = TEGRA124_CLK_RTC, .present = true },
754 [tegra_clk_timer] = { .dt_id = TEGRA124_CLK_TIMER, .present = true },
755 [tegra_clk_uarta] = { .dt_id = TEGRA124_CLK_UARTA, .present = true },
756 [tegra_clk_sdmmc2] = { .dt_id = TEGRA124_CLK_SDMMC2, .present = true },
757 [tegra_clk_i2s1] = { .dt_id = TEGRA124_CLK_I2S1, .present = true },
758 [tegra_clk_i2c1] = { .dt_id = TEGRA124_CLK_I2C1, .present = true },
759 [tegra_clk_ndflash] = { .dt_id = TEGRA124_CLK_NDFLASH, .present = true },
760 [tegra_clk_sdmmc1] = { .dt_id = TEGRA124_CLK_SDMMC1, .present = true },
761 [tegra_clk_sdmmc4] = { .dt_id = TEGRA124_CLK_SDMMC4, .present = true },
762 [tegra_clk_pwm] = { .dt_id = TEGRA124_CLK_PWM, .present = true },
763 [tegra_clk_i2s2] = { .dt_id = TEGRA124_CLK_I2S2, .present = true },
764 [tegra_clk_gr2d] = { .dt_id = TEGRA124_CLK_GR_2D, .present = true },
765 [tegra_clk_usbd] = { .dt_id = TEGRA124_CLK_USBD, .present = true },
766 [tegra_clk_isp_8] = { .dt_id = TEGRA124_CLK_ISP, .present = true },
767 [tegra_clk_gr3d] = { .dt_id = TEGRA124_CLK_GR_3D, .present = true },
768 [tegra_clk_disp2] = { .dt_id = TEGRA124_CLK_DISP2, .present = true },
769 [tegra_clk_disp1] = { .dt_id = TEGRA124_CLK_DISP1, .present = true },
770 [tegra_clk_host1x] = { .dt_id = TEGRA124_CLK_HOST1X, .present = true },
771 [tegra_clk_vcp] = { .dt_id = TEGRA124_CLK_VCP, .present = true },
772 [tegra_clk_i2s0] = { .dt_id = TEGRA124_CLK_I2S0, .present = true },
773 [tegra_clk_apbdma] = { .dt_id = TEGRA124_CLK_APBDMA, .present = true },
774 [tegra_clk_kbc] = { .dt_id = TEGRA124_CLK_KBC, .present = true },
775 [tegra_clk_kfuse] = { .dt_id = TEGRA124_CLK_KFUSE, .present = true },
776 [tegra_clk_sbc1] = { .dt_id = TEGRA124_CLK_SBC1, .present = true },
777 [tegra_clk_nor] = { .dt_id = TEGRA124_CLK_NOR, .present = true },
778 [tegra_clk_sbc2] = { .dt_id = TEGRA124_CLK_SBC2, .present = true },
779 [tegra_clk_sbc3] = { .dt_id = TEGRA124_CLK_SBC3, .present = true },
780 [tegra_clk_i2c5] = { .dt_id = TEGRA124_CLK_I2C5, .present = true },
781 [tegra_clk_dsia] = { .dt_id = TEGRA124_CLK_DSIA, .present = true },
782 [tegra_clk_mipi] = { .dt_id = TEGRA124_CLK_MIPI, .present = true },
783 [tegra_clk_hdmi] = { .dt_id = TEGRA124_CLK_HDMI, .present = true },
784 [tegra_clk_csi] = { .dt_id = TEGRA124_CLK_CSI, .present = true },
785 [tegra_clk_i2c2] = { .dt_id = TEGRA124_CLK_I2C2, .present = true },
786 [tegra_clk_uartc] = { .dt_id = TEGRA124_CLK_UARTC, .present = true },
787 [tegra_clk_mipi_cal] = { .dt_id = TEGRA124_CLK_MIPI_CAL, .present = true },
788 [tegra_clk_emc] = { .dt_id = TEGRA124_CLK_EMC, .present = true },
789 [tegra_clk_usb2] = { .dt_id = TEGRA124_CLK_USB2, .present = true },
790 [tegra_clk_usb3] = { .dt_id = TEGRA124_CLK_USB3, .present = true },
791 [tegra_clk_vde_8] = { .dt_id = TEGRA124_CLK_VDE, .present = true },
792 [tegra_clk_bsea] = { .dt_id = TEGRA124_CLK_BSEA, .present = true },
793 [tegra_clk_bsev] = { .dt_id = TEGRA124_CLK_BSEV, .present = true },
794 [tegra_clk_uartd] = { .dt_id = TEGRA124_CLK_UARTD, .present = true },
795 [tegra_clk_i2c3] = { .dt_id = TEGRA124_CLK_I2C3, .present = true },
796 [tegra_clk_sbc4] = { .dt_id = TEGRA124_CLK_SBC4, .present = true },
797 [tegra_clk_sdmmc3] = { .dt_id = TEGRA124_CLK_SDMMC3, .present = true },
798 [tegra_clk_pcie] = { .dt_id = TEGRA124_CLK_PCIE, .present = true },
799 [tegra_clk_owr] = { .dt_id = TEGRA124_CLK_OWR, .present = true },
800 [tegra_clk_afi] = { .dt_id = TEGRA124_CLK_AFI, .present = true },
801 [tegra_clk_csite] = { .dt_id = TEGRA124_CLK_CSITE, .present = true },
802 [tegra_clk_la] = { .dt_id = TEGRA124_CLK_LA, .present = true },
803 [tegra_clk_trace] = { .dt_id = TEGRA124_CLK_TRACE, .present = true },
804 [tegra_clk_soc_therm] = { .dt_id = TEGRA124_CLK_SOC_THERM, .present = true },
805 [tegra_clk_dtv] = { .dt_id = TEGRA124_CLK_DTV, .present = true },
806 [tegra_clk_ndspeed] = { .dt_id = TEGRA124_CLK_NDSPEED, .present = true },
807 [tegra_clk_i2cslow] = { .dt_id = TEGRA124_CLK_I2CSLOW, .present = true },
808 [tegra_clk_dsib] = { .dt_id = TEGRA124_CLK_DSIB, .present = true },
809 [tegra_clk_tsec] = { .dt_id = TEGRA124_CLK_TSEC, .present = true },
810 [tegra_clk_xusb_host] = { .dt_id = TEGRA124_CLK_XUSB_HOST, .present = true },
811 [tegra_clk_msenc] = { .dt_id = TEGRA124_CLK_MSENC, .present = true },
812 [tegra_clk_csus] = { .dt_id = TEGRA124_CLK_CSUS, .present = true },
813 [tegra_clk_mselect] = { .dt_id = TEGRA124_CLK_MSELECT, .present = true },
814 [tegra_clk_tsensor] = { .dt_id = TEGRA124_CLK_TSENSOR, .present = true },
815 [tegra_clk_i2s3] = { .dt_id = TEGRA124_CLK_I2S3, .present = true },
816 [tegra_clk_i2s4] = { .dt_id = TEGRA124_CLK_I2S4, .present = true },
817 [tegra_clk_i2c4] = { .dt_id = TEGRA124_CLK_I2C4, .present = true },
818 [tegra_clk_sbc5] = { .dt_id = TEGRA124_CLK_SBC5, .present = true },
819 [tegra_clk_sbc6] = { .dt_id = TEGRA124_CLK_SBC6, .present = true },
820 [tegra_clk_d_audio] = { .dt_id = TEGRA124_CLK_D_AUDIO, .present = true },
821 [tegra_clk_apbif] = { .dt_id = TEGRA124_CLK_APBIF, .present = true },
822 [tegra_clk_dam0] = { .dt_id = TEGRA124_CLK_DAM0, .present = true },
823 [tegra_clk_dam1] = { .dt_id = TEGRA124_CLK_DAM1, .present = true },
824 [tegra_clk_dam2] = { .dt_id = TEGRA124_CLK_DAM2, .present = true },
825 [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA124_CLK_HDA2CODEC_2X, .present = true },
826 [tegra_clk_audio0_2x] = { .dt_id = TEGRA124_CLK_AUDIO0_2X, .present = true },
827 [tegra_clk_audio1_2x] = { .dt_id = TEGRA124_CLK_AUDIO1_2X, .present = true },
828 [tegra_clk_audio2_2x] = { .dt_id = TEGRA124_CLK_AUDIO2_2X, .present = true },
829 [tegra_clk_audio3_2x] = { .dt_id = TEGRA124_CLK_AUDIO3_2X, .present = true },
830 [tegra_clk_audio4_2x] = { .dt_id = TEGRA124_CLK_AUDIO4_2X, .present = true },
831 [tegra_clk_spdif_2x] = { .dt_id = TEGRA124_CLK_SPDIF_2X, .present = true },
832 [tegra_clk_actmon] = { .dt_id = TEGRA124_CLK_ACTMON, .present = true },
833 [tegra_clk_extern1] = { .dt_id = TEGRA124_CLK_EXTERN1, .present = true },
834 [tegra_clk_extern2] = { .dt_id = TEGRA124_CLK_EXTERN2, .present = true },
835 [tegra_clk_extern3] = { .dt_id = TEGRA124_CLK_EXTERN3, .present = true },
836 [tegra_clk_sata_oob] = { .dt_id = TEGRA124_CLK_SATA_OOB, .present = true },
837 [tegra_clk_sata] = { .dt_id = TEGRA124_CLK_SATA, .present = true },
838 [tegra_clk_hda] = { .dt_id = TEGRA124_CLK_HDA, .present = true },
839 [tegra_clk_se] = { .dt_id = TEGRA124_CLK_SE, .present = true },
840 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA124_CLK_HDA2HDMI, .present = true },
841 [tegra_clk_sata_cold] = { .dt_id = TEGRA124_CLK_SATA_COLD, .present = true },
842 [tegra_clk_cilab] = { .dt_id = TEGRA124_CLK_CILAB, .present = true },
843 [tegra_clk_cilcd] = { .dt_id = TEGRA124_CLK_CILCD, .present = true },
844 [tegra_clk_cile] = { .dt_id = TEGRA124_CLK_CILE, .present = true },
845 [tegra_clk_dsialp] = { .dt_id = TEGRA124_CLK_DSIALP, .present = true },
846 [tegra_clk_dsiblp] = { .dt_id = TEGRA124_CLK_DSIBLP, .present = true },
847 [tegra_clk_entropy] = { .dt_id = TEGRA124_CLK_ENTROPY, .present = true },
848 [tegra_clk_dds] = { .dt_id = TEGRA124_CLK_DDS, .present = true },
849 [tegra_clk_dp2] = { .dt_id = TEGRA124_CLK_DP2, .present = true },
850 [tegra_clk_amx] = { .dt_id = TEGRA124_CLK_AMX, .present = true },
851 [tegra_clk_adx] = { .dt_id = TEGRA124_CLK_ADX, .present = true },
852 [tegra_clk_xusb_ss] = { .dt_id = TEGRA124_CLK_XUSB_SS, .present = true },
853 [tegra_clk_i2c6] = { .dt_id = TEGRA124_CLK_I2C6, .present = true },
854 [tegra_clk_vim2_clk] = { .dt_id = TEGRA124_CLK_VIM2_CLK, .present = true },
855 [tegra_clk_hdmi_audio] = { .dt_id = TEGRA124_CLK_HDMI_AUDIO, .present = true },
856 [tegra_clk_clk72Mhz] = { .dt_id = TEGRA124_CLK_CLK72MHZ, .present = true },
857 [tegra_clk_vic03] = { .dt_id = TEGRA124_CLK_VIC03, .present = true },
858 [tegra_clk_adx1] = { .dt_id = TEGRA124_CLK_ADX1, .present = true },
859 [tegra_clk_dpaux] = { .dt_id = TEGRA124_CLK_DPAUX, .present = true },
860 [tegra_clk_sor0] = { .dt_id = TEGRA124_CLK_SOR0, .present = true },
861 [tegra_clk_sor0_lvds] = { .dt_id = TEGRA124_CLK_SOR0_LVDS, .present = true },
862 [tegra_clk_gpu] = { .dt_id = TEGRA124_CLK_GPU, .present = true },
863 [tegra_clk_amx1] = { .dt_id = TEGRA124_CLK_AMX1, .present = true },
864 [tegra_clk_uartb] = { .dt_id = TEGRA124_CLK_UARTB, .present = true },
865 [tegra_clk_vfir] = { .dt_id = TEGRA124_CLK_VFIR, .present = true },
866 [tegra_clk_spdif_in] = { .dt_id = TEGRA124_CLK_SPDIF_IN, .present = true },
867 [tegra_clk_spdif_out] = { .dt_id = TEGRA124_CLK_SPDIF_OUT, .present = true },
868 [tegra_clk_vi_9] = { .dt_id = TEGRA124_CLK_VI, .present = true },
869 [tegra_clk_vi_sensor] = { .dt_id = TEGRA124_CLK_VI_SENSOR, .present = true },
870 [tegra_clk_fuse] = { .dt_id = TEGRA124_CLK_FUSE, .present = true },
871 [tegra_clk_fuse_burn] = { .dt_id = TEGRA124_CLK_FUSE_BURN, .present = true },
872 [tegra_clk_clk_32k] = { .dt_id = TEGRA124_CLK_CLK_32K, .present = true },
873 [tegra_clk_clk_m] = { .dt_id = TEGRA124_CLK_CLK_M, .present = true },
874 [tegra_clk_clk_m_div2] = { .dt_id = TEGRA124_CLK_CLK_M_DIV2, .present = true },
875 [tegra_clk_clk_m_div4] = { .dt_id = TEGRA124_CLK_CLK_M_DIV4, .present = true },
876 [tegra_clk_pll_ref] = { .dt_id = TEGRA124_CLK_PLL_REF, .present = true },
877 [tegra_clk_pll_c] = { .dt_id = TEGRA124_CLK_PLL_C, .present = true },
878 [tegra_clk_pll_c_out1] = { .dt_id = TEGRA124_CLK_PLL_C_OUT1, .present = true },
879 [tegra_clk_pll_c2] = { .dt_id = TEGRA124_CLK_PLL_C2, .present = true },
880 [tegra_clk_pll_c3] = { .dt_id = TEGRA124_CLK_PLL_C3, .present = true },
881 [tegra_clk_pll_m] = { .dt_id = TEGRA124_CLK_PLL_M, .present = true },
882 [tegra_clk_pll_m_out1] = { .dt_id = TEGRA124_CLK_PLL_M_OUT1, .present = true },
883 [tegra_clk_pll_p] = { .dt_id = TEGRA124_CLK_PLL_P, .present = true },
884 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA124_CLK_PLL_P_OUT1, .present = true },
885 [tegra_clk_pll_p_out2] = { .dt_id = TEGRA124_CLK_PLL_P_OUT2, .present = true },
886 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA124_CLK_PLL_P_OUT3, .present = true },
887 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA124_CLK_PLL_P_OUT4, .present = true },
888 [tegra_clk_pll_a] = { .dt_id = TEGRA124_CLK_PLL_A, .present = true },
889 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA124_CLK_PLL_A_OUT0, .present = true },
890 [tegra_clk_pll_d] = { .dt_id = TEGRA124_CLK_PLL_D, .present = true },
891 [tegra_clk_pll_d_out0] = { .dt_id = TEGRA124_CLK_PLL_D_OUT0, .present = true },
892 [tegra_clk_pll_d2] = { .dt_id = TEGRA124_CLK_PLL_D2, .present = true },
893 [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA124_CLK_PLL_D2_OUT0, .present = true },
894 [tegra_clk_pll_u] = { .dt_id = TEGRA124_CLK_PLL_U, .present = true },
895 [tegra_clk_pll_u_480m] = { .dt_id = TEGRA124_CLK_PLL_U_480M, .present = true },
896 [tegra_clk_pll_u_60m] = { .dt_id = TEGRA124_CLK_PLL_U_60M, .present = true },
897 [tegra_clk_pll_u_48m] = { .dt_id = TEGRA124_CLK_PLL_U_48M, .present = true },
898 [tegra_clk_pll_u_12m] = { .dt_id = TEGRA124_CLK_PLL_U_12M, .present = true },
899 [tegra_clk_pll_x] = { .dt_id = TEGRA124_CLK_PLL_X, .present = true },
900 [tegra_clk_pll_x_out0] = { .dt_id = TEGRA124_CLK_PLL_X_OUT0, .present = true },
901 [tegra_clk_pll_re_vco] = { .dt_id = TEGRA124_CLK_PLL_RE_VCO, .present = true },
902 [tegra_clk_pll_re_out] = { .dt_id = TEGRA124_CLK_PLL_RE_OUT, .present = true },
903 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA124_CLK_SPDIF_IN_SYNC, .present = true },
904 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA124_CLK_I2S0_SYNC, .present = true },
905 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA124_CLK_I2S1_SYNC, .present = true },
906 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA124_CLK_I2S2_SYNC, .present = true },
907 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA124_CLK_I2S3_SYNC, .present = true },
908 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA124_CLK_I2S4_SYNC, .present = true },
909 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA124_CLK_VIMCLK_SYNC, .present = true },
910 [tegra_clk_audio0] = { .dt_id = TEGRA124_CLK_AUDIO0, .present = true },
911 [tegra_clk_audio1] = { .dt_id = TEGRA124_CLK_AUDIO1, .present = true },
912 [tegra_clk_audio2] = { .dt_id = TEGRA124_CLK_AUDIO2, .present = true },
913 [tegra_clk_audio3] = { .dt_id = TEGRA124_CLK_AUDIO3, .present = true },
914 [tegra_clk_audio4] = { .dt_id = TEGRA124_CLK_AUDIO4, .present = true },
915 [tegra_clk_spdif] = { .dt_id = TEGRA124_CLK_SPDIF, .present = true },
916 [tegra_clk_clk_out_1] = { .dt_id = TEGRA124_CLK_CLK_OUT_1, .present = true },
917 [tegra_clk_clk_out_2] = { .dt_id = TEGRA124_CLK_CLK_OUT_2, .present = true },
918 [tegra_clk_clk_out_3] = { .dt_id = TEGRA124_CLK_CLK_OUT_3, .present = true },
919 [tegra_clk_blink] = { .dt_id = TEGRA124_CLK_BLINK, .present = true },
920 [tegra_clk_xusb_host_src] = { .dt_id = TEGRA124_CLK_XUSB_HOST_SRC, .present = true },
921 [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA124_CLK_XUSB_FALCON_SRC, .present = true },
922 [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA124_CLK_XUSB_FS_SRC, .present = true },
923 [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA124_CLK_XUSB_SS_SRC, .present = true },
924 [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA124_CLK_XUSB_DEV_SRC, .present = true },
925 [tegra_clk_xusb_dev] = { .dt_id = TEGRA124_CLK_XUSB_DEV, .present = true },
926 [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA124_CLK_XUSB_HS_SRC, .present = true },
927 [tegra_clk_sclk] = { .dt_id = TEGRA124_CLK_SCLK, .present = true },
928 [tegra_clk_hclk] = { .dt_id = TEGRA124_CLK_HCLK, .present = true },
929 [tegra_clk_pclk] = { .dt_id = TEGRA124_CLK_PCLK, .present = true },
930 [tegra_clk_cclk_g] = { .dt_id = TEGRA124_CLK_CCLK_G, .present = true },
931 [tegra_clk_cclk_lp] = { .dt_id = TEGRA124_CLK_CCLK_LP, .present = true },
932 [tegra_clk_dfll_ref] = { .dt_id = TEGRA124_CLK_DFLL_REF, .present = true },
933 [tegra_clk_dfll_soc] = { .dt_id = TEGRA124_CLK_DFLL_SOC, .present = true },
934 [tegra_clk_vi_sensor2] = { .dt_id = TEGRA124_CLK_VI_SENSOR2, .present = true },
935 [tegra_clk_pll_p_out5] = { .dt_id = TEGRA124_CLK_PLL_P_OUT5, .present = true },
936 [tegra_clk_pll_c4] = { .dt_id = TEGRA124_CLK_PLL_C4, .present = true },
937 [tegra_clk_pll_dp] = { .dt_id = TEGRA124_CLK_PLL_DP, .present = true },
938 [tegra_clk_audio0_mux] = { .dt_id = TEGRA124_CLK_AUDIO0_MUX, .present = true },
939 [tegra_clk_audio1_mux] = { .dt_id = TEGRA124_CLK_AUDIO1_MUX, .present = true },
940 [tegra_clk_audio2_mux] = { .dt_id = TEGRA124_CLK_AUDIO2_MUX, .present = true },
941 [tegra_clk_audio3_mux] = { .dt_id = TEGRA124_CLK_AUDIO3_MUX, .present = true },
942 [tegra_clk_audio4_mux] = { .dt_id = TEGRA124_CLK_AUDIO4_MUX, .present = true },
943 [tegra_clk_spdif_mux] = { .dt_id = TEGRA124_CLK_SPDIF_MUX, .present = true },
944 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_1_MUX, .present = true },
945 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_2_MUX, .present = true },
946 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_3_MUX, .present = true },
947 [tegra_clk_dsia_mux] = { .dt_id = TEGRA124_CLK_DSIA_MUX, .present = true },
948 [tegra_clk_dsib_mux] = { .dt_id = TEGRA124_CLK_DSIB_MUX, .present = true },
949 [tegra_clk_uarte] = { .dt_id = TEGRA124_CLK_UARTE, .present = true },
950};
951
952static struct tegra_devclk devclks[] __initdata = {
953 { .con_id = "clk_m", .dt_id = TEGRA124_CLK_CLK_M },
954 { .con_id = "pll_ref", .dt_id = TEGRA124_CLK_PLL_REF },
955 { .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K },
956 { .con_id = "clk_m_div2", .dt_id = TEGRA124_CLK_CLK_M_DIV2 },
957 { .con_id = "clk_m_div4", .dt_id = TEGRA124_CLK_CLK_M_DIV4 },
958 { .con_id = "pll_c", .dt_id = TEGRA124_CLK_PLL_C },
959 { .con_id = "pll_c_out1", .dt_id = TEGRA124_CLK_PLL_C_OUT1 },
960 { .con_id = "pll_c2", .dt_id = TEGRA124_CLK_PLL_C2 },
961 { .con_id = "pll_c3", .dt_id = TEGRA124_CLK_PLL_C3 },
962 { .con_id = "pll_p", .dt_id = TEGRA124_CLK_PLL_P },
963 { .con_id = "pll_p_out1", .dt_id = TEGRA124_CLK_PLL_P_OUT1 },
964 { .con_id = "pll_p_out2", .dt_id = TEGRA124_CLK_PLL_P_OUT2 },
965 { .con_id = "pll_p_out3", .dt_id = TEGRA124_CLK_PLL_P_OUT3 },
966 { .con_id = "pll_p_out4", .dt_id = TEGRA124_CLK_PLL_P_OUT4 },
967 { .con_id = "pll_m", .dt_id = TEGRA124_CLK_PLL_M },
968 { .con_id = "pll_m_out1", .dt_id = TEGRA124_CLK_PLL_M_OUT1 },
969 { .con_id = "pll_x", .dt_id = TEGRA124_CLK_PLL_X },
970 { .con_id = "pll_x_out0", .dt_id = TEGRA124_CLK_PLL_X_OUT0 },
971 { .con_id = "pll_u", .dt_id = TEGRA124_CLK_PLL_U },
972 { .con_id = "pll_u_480M", .dt_id = TEGRA124_CLK_PLL_U_480M },
973 { .con_id = "pll_u_60M", .dt_id = TEGRA124_CLK_PLL_U_60M },
974 { .con_id = "pll_u_48M", .dt_id = TEGRA124_CLK_PLL_U_48M },
975 { .con_id = "pll_u_12M", .dt_id = TEGRA124_CLK_PLL_U_12M },
976 { .con_id = "pll_d", .dt_id = TEGRA124_CLK_PLL_D },
977 { .con_id = "pll_d_out0", .dt_id = TEGRA124_CLK_PLL_D_OUT0 },
978 { .con_id = "pll_d2", .dt_id = TEGRA124_CLK_PLL_D2 },
979 { .con_id = "pll_d2_out0", .dt_id = TEGRA124_CLK_PLL_D2_OUT0 },
980 { .con_id = "pll_a", .dt_id = TEGRA124_CLK_PLL_A },
981 { .con_id = "pll_a_out0", .dt_id = TEGRA124_CLK_PLL_A_OUT0 },
982 { .con_id = "pll_re_vco", .dt_id = TEGRA124_CLK_PLL_RE_VCO },
983 { .con_id = "pll_re_out", .dt_id = TEGRA124_CLK_PLL_RE_OUT },
984 { .con_id = "spdif_in_sync", .dt_id = TEGRA124_CLK_SPDIF_IN_SYNC },
985 { .con_id = "i2s0_sync", .dt_id = TEGRA124_CLK_I2S0_SYNC },
986 { .con_id = "i2s1_sync", .dt_id = TEGRA124_CLK_I2S1_SYNC },
987 { .con_id = "i2s2_sync", .dt_id = TEGRA124_CLK_I2S2_SYNC },
988 { .con_id = "i2s3_sync", .dt_id = TEGRA124_CLK_I2S3_SYNC },
989 { .con_id = "i2s4_sync", .dt_id = TEGRA124_CLK_I2S4_SYNC },
990 { .con_id = "vimclk_sync", .dt_id = TEGRA124_CLK_VIMCLK_SYNC },
991 { .con_id = "audio0", .dt_id = TEGRA124_CLK_AUDIO0 },
992 { .con_id = "audio1", .dt_id = TEGRA124_CLK_AUDIO1 },
993 { .con_id = "audio2", .dt_id = TEGRA124_CLK_AUDIO2 },
994 { .con_id = "audio3", .dt_id = TEGRA124_CLK_AUDIO3 },
995 { .con_id = "audio4", .dt_id = TEGRA124_CLK_AUDIO4 },
996 { .con_id = "spdif", .dt_id = TEGRA124_CLK_SPDIF },
997 { .con_id = "audio0_2x", .dt_id = TEGRA124_CLK_AUDIO0_2X },
998 { .con_id = "audio1_2x", .dt_id = TEGRA124_CLK_AUDIO1_2X },
999 { .con_id = "audio2_2x", .dt_id = TEGRA124_CLK_AUDIO2_2X },
1000 { .con_id = "audio3_2x", .dt_id = TEGRA124_CLK_AUDIO3_2X },
1001 { .con_id = "audio4_2x", .dt_id = TEGRA124_CLK_AUDIO4_2X },
1002 { .con_id = "spdif_2x", .dt_id = TEGRA124_CLK_SPDIF_2X },
1003 { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA124_CLK_EXTERN1 },
1004 { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA124_CLK_EXTERN2 },
1005 { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA124_CLK_EXTERN3 },
1006 { .con_id = "blink", .dt_id = TEGRA124_CLK_BLINK },
1007 { .con_id = "cclk_g", .dt_id = TEGRA124_CLK_CCLK_G },
1008 { .con_id = "cclk_lp", .dt_id = TEGRA124_CLK_CCLK_LP },
1009 { .con_id = "sclk", .dt_id = TEGRA124_CLK_SCLK },
1010 { .con_id = "hclk", .dt_id = TEGRA124_CLK_HCLK },
1011 { .con_id = "pclk", .dt_id = TEGRA124_CLK_PCLK },
1012 { .con_id = "fuse", .dt_id = TEGRA124_CLK_FUSE },
1013 { .dev_id = "rtc-tegra", .dt_id = TEGRA124_CLK_RTC },
1014 { .dev_id = "timer", .dt_id = TEGRA124_CLK_TIMER },
1015};
1016
1017static struct clk **clks;
1018
1019static void tegra124_utmi_param_configure(void __iomem *clk_base)
1020{
1021 u32 reg;
1022 int i;
1023
1024 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1025 if (osc_freq == utmi_parameters[i].osc_frequency)
1026 break;
1027 }
1028
1029 if (i >= ARRAY_SIZE(utmi_parameters)) {
1030 pr_err("%s: Unexpected oscillator freq %lu\n", __func__,
1031 osc_freq);
1032 return;
1033 }
1034
1035 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
1036
1037 /* Program UTMIP PLL stable and active counts */
1038 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
1039 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1040 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count);
1041
1042 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1043
1044 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].
1045 active_delay_count);
1046
1047 /* Remove power downs from UTMIP PLL control bits */
1048 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1049 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1050 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1051
1052 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
1053
1054 /* Program UTMIP PLL delay and oscillator frequency counts */
1055 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1056 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1057
1058 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].
1059 enable_delay_count);
1060
1061 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1062 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i].
1063 xtal_freq_count);
1064
1065 /* Remove power downs from UTMIP PLL control bits */
1066 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1067 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1068 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1069 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1070 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
1071
1072 /* Setup HW control of UTMIPLL */
1073 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1074 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1075 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1076 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
1077 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1078
1079 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1080 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1081 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1082 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
1083
1084 udelay(1);
1085
1086 /* Setup SW override of UTMIPLL assuming USB2.0
1087 ports are assigned to USB2 */
1088 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1089 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
1090 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1091 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1092
1093 udelay(1);
1094
1095 /* Enable HW control UTMIPLL */
1096 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1097 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1098 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1099}
1100
1101static __init void tegra124_periph_clk_init(void __iomem *clk_base,
1102 void __iomem *pmc_base)
1103{
1104 struct clk *clk;
1105 u32 val;
1106
1107 /* xusb_hs_src */
1108 val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC);
1109 val |= BIT(25); /* always select PLLU_60M */
1110 writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC);
1111
1112 clk = clk_register_fixed_factor(NULL, "xusb_hs_src", "pll_u_60M", 0,
1113 1, 1);
1114 clks[TEGRA124_CLK_XUSB_HS_SRC] = clk;
1115
1116 /* dsia mux */
1117 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
1118 ARRAY_SIZE(mux_plld_out0_plld2_out0), 0,
1119 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
1120 clks[TEGRA124_CLK_DSIA_MUX] = clk;
1121
1122 /* dsib mux */
1123 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0,
1124 ARRAY_SIZE(mux_plld_out0_plld2_out0), 0,
1125 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
1126 clks[TEGRA124_CLK_DSIB_MUX] = clk;
1127
1128 /* emc mux */
1129 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
1130 ARRAY_SIZE(mux_pllmcp_clkm), 0,
1131 clk_base + CLK_SOURCE_EMC,
1132 29, 3, 0, NULL);
1133
1134 /* cml0 */
1135 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
1136 0, 0, &pll_e_lock);
1137 clk_register_clkdev(clk, "cml0", NULL);
1138 clks[TEGRA124_CLK_CML0] = clk;
1139
1140 /* cml1 */
1141 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
1142 1, 0, &pll_e_lock);
1143 clk_register_clkdev(clk, "cml1", NULL);
1144 clks[TEGRA124_CLK_CML1] = clk;
1145
1146 tegra_periph_clk_init(clk_base, pmc_base, tegra124_clks, &pll_p_params);
1147}
1148
1149static void __init tegra124_pll_init(void __iomem *clk_base,
1150 void __iomem *pmc)
1151{
1152 u32 val;
1153 struct clk *clk;
1154
1155 /* PLLC */
1156 clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,
1157 pmc, 0, &pll_c_params, NULL);
1158 clk_register_clkdev(clk, "pll_c", NULL);
1159 clks[TEGRA124_CLK_PLL_C] = clk;
1160
1161 /* PLLC_OUT1 */
1162 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
1163 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1164 8, 8, 1, NULL);
1165 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
1166 clk_base + PLLC_OUT, 1, 0,
1167 CLK_SET_RATE_PARENT, 0, NULL);
1168 clk_register_clkdev(clk, "pll_c_out1", NULL);
1169 clks[TEGRA124_CLK_PLL_C_OUT1] = clk;
1170
1171 /* PLLC2 */
1172 clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0,
1173 &pll_c2_params, NULL);
1174 clk_register_clkdev(clk, "pll_c2", NULL);
1175 clks[TEGRA124_CLK_PLL_C2] = clk;
1176
1177 /* PLLC3 */
1178 clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0,
1179 &pll_c3_params, NULL);
1180 clk_register_clkdev(clk, "pll_c3", NULL);
1181 clks[TEGRA124_CLK_PLL_C3] = clk;
1182
1183 /* PLLM */
1184 clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
1185 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
1186 &pll_m_params, NULL);
1187 clk_register_clkdev(clk, "pll_m", NULL);
1188 clks[TEGRA124_CLK_PLL_M] = clk;
1189
1190 /* PLLM_OUT1 */
1191 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
1192 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1193 8, 8, 1, NULL);
1194 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
1195 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
1196 CLK_SET_RATE_PARENT, 0, NULL);
1197 clk_register_clkdev(clk, "pll_m_out1", NULL);
1198 clks[TEGRA124_CLK_PLL_M_OUT1] = clk;
1199
1200 /* PLLM_UD */
1201 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
1202 CLK_SET_RATE_PARENT, 1, 1);
1203
1204 /* PLLU */
1205 val = readl(clk_base + pll_u_params.base_reg);
1206 val &= ~BIT(24); /* disable PLLU_OVERRIDE */
1207 writel(val, clk_base + pll_u_params.base_reg);
1208
1209 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0,
1210 &pll_u_params, &pll_u_lock);
1211 clk_register_clkdev(clk, "pll_u", NULL);
1212 clks[TEGRA124_CLK_PLL_U] = clk;
1213
1214 tegra124_utmi_param_configure(clk_base);
1215
1216 /* PLLU_480M */
1217 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u",
1218 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
1219 22, 0, &pll_u_lock);
1220 clk_register_clkdev(clk, "pll_u_480M", NULL);
1221 clks[TEGRA124_CLK_PLL_U_480M] = clk;
1222
1223 /* PLLU_60M */
1224 clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u",
1225 CLK_SET_RATE_PARENT, 1, 8);
1226 clk_register_clkdev(clk, "pll_u_60M", NULL);
1227 clks[TEGRA124_CLK_PLL_U_60M] = clk;
1228
1229 /* PLLU_48M */
1230 clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u",
1231 CLK_SET_RATE_PARENT, 1, 10);
1232 clk_register_clkdev(clk, "pll_u_48M", NULL);
1233 clks[TEGRA124_CLK_PLL_U_48M] = clk;
1234
1235 /* PLLU_12M */
1236 clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u",
1237 CLK_SET_RATE_PARENT, 1, 40);
1238 clk_register_clkdev(clk, "pll_u_12M", NULL);
1239 clks[TEGRA124_CLK_PLL_U_12M] = clk;
1240
1241 /* PLLD */
1242 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
1243 &pll_d_params, &pll_d_lock);
1244 clk_register_clkdev(clk, "pll_d", NULL);
1245 clks[TEGRA124_CLK_PLL_D] = clk;
1246
1247 /* PLLD_OUT0 */
1248 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
1249 CLK_SET_RATE_PARENT, 1, 2);
1250 clk_register_clkdev(clk, "pll_d_out0", NULL);
1251 clks[TEGRA124_CLK_PLL_D_OUT0] = clk;
1252
1253 /* PLLRE */
1254 clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,
1255 0, &pll_re_vco_params, &pll_re_lock, pll_ref_freq);
1256 clk_register_clkdev(clk, "pll_re_vco", NULL);
1257 clks[TEGRA124_CLK_PLL_RE_VCO] = clk;
1258
1259 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
1260 clk_base + PLLRE_BASE, 16, 4, 0,
1261 pll_re_div_table, &pll_re_lock);
1262 clk_register_clkdev(clk, "pll_re_out", NULL);
1263 clks[TEGRA124_CLK_PLL_RE_OUT] = clk;
1264
1265 /* PLLE */
1266 clk = tegra_clk_register_plle_tegra114("pll_e", "pll_ref",
1267 clk_base, 0, &pll_e_params, NULL);
1268 clk_register_clkdev(clk, "pll_e", NULL);
1269 clks[TEGRA124_CLK_PLL_E] = clk;
1270
1271 /* PLLC4 */
1272 clk = tegra_clk_register_pllss("pll_c4", "pll_ref", clk_base, 0,
1273 &pll_c4_params, NULL);
1274 clk_register_clkdev(clk, "pll_c4", NULL);
1275 clks[TEGRA124_CLK_PLL_C4] = clk;
1276
1277 /* PLLDP */
1278 clk = tegra_clk_register_pllss("pll_dp", "pll_ref", clk_base, 0,
1279 &pll_dp_params, NULL);
1280 clk_register_clkdev(clk, "pll_dp", NULL);
1281 clks[TEGRA124_CLK_PLL_DP] = clk;
1282
1283 /* PLLD2 */
1284 clk = tegra_clk_register_pllss("pll_d2", "pll_ref", clk_base, 0,
1285 &tegra124_pll_d2_params, NULL);
1286 clk_register_clkdev(clk, "pll_d2", NULL);
1287 clks[TEGRA124_CLK_PLL_D2] = clk;
1288
1289 /* PLLD2_OUT0 ?? */
1290 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
1291 CLK_SET_RATE_PARENT, 1, 2);
1292 clk_register_clkdev(clk, "pll_d2_out0", NULL);
1293 clks[TEGRA124_CLK_PLL_D2_OUT0] = clk;
1294
1295}
1296
1297/* Tegra124 CPU clock and reset control functions */
1298static void tegra124_wait_cpu_in_reset(u32 cpu)
1299{
1300 unsigned int reg;
1301
1302 do {
1303 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1304 cpu_relax();
1305 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
1306}
1307
1308static void tegra124_disable_cpu_clock(u32 cpu)
1309{
1310 /* flow controller would take care in the power sequence. */
1311}
1312
1313#ifdef CONFIG_PM_SLEEP
1314static void tegra124_cpu_clock_suspend(void)
1315{
1316 /* switch coresite to clk_m, save off original source */
1317 tegra124_cpu_clk_sctx.clk_csite_src =
1318 readl(clk_base + CLK_SOURCE_CSITE);
1319 writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
1320}
1321
1322static void tegra124_cpu_clock_resume(void)
1323{
1324 writel(tegra124_cpu_clk_sctx.clk_csite_src,
1325 clk_base + CLK_SOURCE_CSITE);
1326}
1327#endif
1328
1329static struct tegra_cpu_car_ops tegra124_cpu_car_ops = {
1330 .wait_for_reset = tegra124_wait_cpu_in_reset,
1331 .disable_clock = tegra124_disable_cpu_clock,
1332#ifdef CONFIG_PM_SLEEP
1333 .suspend = tegra124_cpu_clock_suspend,
1334 .resume = tegra124_cpu_clock_resume,
1335#endif
1336};
1337
1338static const struct of_device_id pmc_match[] __initconst = {
1339 { .compatible = "nvidia,tegra124-pmc" },
1340 {},
1341};
1342
1343static struct tegra_clk_init_table init_table[] __initdata = {
1344 {TEGRA124_CLK_UARTA, TEGRA124_CLK_PLL_P, 408000000, 0},
1345 {TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 408000000, 0},
1346 {TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 408000000, 0},
1347 {TEGRA124_CLK_UARTD, TEGRA124_CLK_PLL_P, 408000000, 0},
1348 {TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 564480000, 1},
1349 {TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 1},
1350 {TEGRA124_CLK_EXTERN1, TEGRA124_CLK_PLL_A_OUT0, 0, 1},
1351 {TEGRA124_CLK_CLK_OUT_1_MUX, TEGRA124_CLK_EXTERN1, 0, 1},
1352 {TEGRA124_CLK_CLK_OUT_1, TEGRA124_CLK_CLK_MAX, 0, 1},
1353 {TEGRA124_CLK_I2S0, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
1354 {TEGRA124_CLK_I2S1, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
1355 {TEGRA124_CLK_I2S2, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
1356 {TEGRA124_CLK_I2S3, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
1357 {TEGRA124_CLK_I2S4, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
1358 {TEGRA124_CLK_VDE, TEGRA124_CLK_PLL_P, 0, 0},
1359 {TEGRA124_CLK_HOST1X, TEGRA124_CLK_PLL_P, 136000000, 1},
1360 {TEGRA124_CLK_SCLK, TEGRA124_CLK_PLL_P_OUT2, 102000000, 1},
1361 {TEGRA124_CLK_DFLL_SOC, TEGRA124_CLK_PLL_P, 51000000, 1},
1362 {TEGRA124_CLK_DFLL_REF, TEGRA124_CLK_PLL_P, 51000000, 1},
1363 {TEGRA124_CLK_PLL_C, TEGRA124_CLK_CLK_MAX, 768000000, 0},
1364 {TEGRA124_CLK_PLL_C_OUT1, TEGRA124_CLK_CLK_MAX, 100000000, 0},
1365 {TEGRA124_CLK_SBC4, TEGRA124_CLK_PLL_P, 12000000, 1},
1366 {TEGRA124_CLK_TSEC, TEGRA124_CLK_PLL_C3, 0, 0},
1367 {TEGRA124_CLK_MSENC, TEGRA124_CLK_PLL_C3, 0, 0},
1368 /* This MUST be the last entry. */
1369 {TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
1370};
1371
1372static void __init tegra124_clock_apply_init_table(void)
1373{
1374 tegra_init_from_table(init_table, clks, TEGRA124_CLK_CLK_MAX);
1375}
1376
1377static void __init tegra124_clock_init(struct device_node *np)
1378{
1379 struct device_node *node;
1380
1381 clk_base = of_iomap(np, 0);
1382 if (!clk_base) {
1383 pr_err("ioremap tegra124 CAR failed\n");
1384 return;
1385 }
1386
1387 node = of_find_matching_node(NULL, pmc_match);
1388 if (!node) {
1389 pr_err("Failed to find pmc node\n");
1390 WARN_ON(1);
1391 return;
1392 }
1393
1394 pmc_base = of_iomap(node, 0);
1395 if (!pmc_base) {
1396 pr_err("Can't map pmc registers\n");
1397 WARN_ON(1);
1398 return;
1399 }
1400
1401 clks = tegra_clk_init(TEGRA124_CLK_CLK_MAX, 6);
1402 if (!clks)
1403 return;
1404
1405 if (tegra_osc_clk_init(clk_base, tegra124_clks, tegra124_input_freq,
1406 ARRAY_SIZE(tegra124_input_freq), &osc_freq, &pll_ref_freq) < 0)
1407 return;
1408
1409 tegra_fixed_clk_init(tegra124_clks);
1410 tegra124_pll_init(clk_base, pmc_base);
1411 tegra124_periph_clk_init(clk_base, pmc_base);
1412 tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks, &pll_a_params);
1413 tegra_pmc_clk_init(pmc_base, tegra124_clks);
1414
1415 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra124_clks,
1416 &pll_x_params);
1417 tegra_add_of_provider(np);
1418 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1419
1420 tegra_clk_apply_init_table = tegra124_clock_apply_init_table;
1421
1422 tegra_cpu_car_ops = &tegra124_cpu_car_ops;
1423}
1424CLK_OF_DECLARE(tegra124, "nvidia,tegra124-car", tegra124_clock_init);
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 056f649d0d89..b3b7204acfe7 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -22,30 +22,10 @@
22#include <linux/of_address.h> 22#include <linux/of_address.h>
23#include <linux/clk/tegra.h> 23#include <linux/clk/tegra.h>
24#include <linux/delay.h> 24#include <linux/delay.h>
25#include <dt-bindings/clock/tegra20-car.h>
25 26
26#include "clk.h" 27#include "clk.h"
27 28#include "clk-id.h"
28#define RST_DEVICES_L 0x004
29#define RST_DEVICES_H 0x008
30#define RST_DEVICES_U 0x00c
31#define RST_DEVICES_SET_L 0x300
32#define RST_DEVICES_CLR_L 0x304
33#define RST_DEVICES_SET_H 0x308
34#define RST_DEVICES_CLR_H 0x30c
35#define RST_DEVICES_SET_U 0x310
36#define RST_DEVICES_CLR_U 0x314
37#define RST_DEVICES_NUM 3
38
39#define CLK_OUT_ENB_L 0x010
40#define CLK_OUT_ENB_H 0x014
41#define CLK_OUT_ENB_U 0x018
42#define CLK_OUT_ENB_SET_L 0x320
43#define CLK_OUT_ENB_CLR_L 0x324
44#define CLK_OUT_ENB_SET_H 0x328
45#define CLK_OUT_ENB_CLR_H 0x32c
46#define CLK_OUT_ENB_SET_U 0x330
47#define CLK_OUT_ENB_CLR_U 0x334
48#define CLK_OUT_ENB_NUM 3
49 29
50#define OSC_CTRL 0x50 30#define OSC_CTRL 0x50
51#define OSC_CTRL_OSC_FREQ_MASK (3<<30) 31#define OSC_CTRL_OSC_FREQ_MASK (3<<30)
@@ -67,6 +47,8 @@
67#define OSC_FREQ_DET_BUSY (1<<31) 47#define OSC_FREQ_DET_BUSY (1<<31)
68#define OSC_FREQ_DET_CNT_MASK 0xFFFF 48#define OSC_FREQ_DET_CNT_MASK 0xFFFF
69 49
50#define TEGRA20_CLK_PERIPH_BANKS 3
51
70#define PLLS_BASE 0xf0 52#define PLLS_BASE 0xf0
71#define PLLS_MISC 0xf4 53#define PLLS_MISC 0xf4
72#define PLLC_BASE 0x80 54#define PLLC_BASE 0x80
@@ -114,34 +96,15 @@
114 96
115#define CLK_SOURCE_I2S1 0x100 97#define CLK_SOURCE_I2S1 0x100
116#define CLK_SOURCE_I2S2 0x104 98#define CLK_SOURCE_I2S2 0x104
117#define CLK_SOURCE_SPDIF_OUT 0x108
118#define CLK_SOURCE_SPDIF_IN 0x10c
119#define CLK_SOURCE_PWM 0x110 99#define CLK_SOURCE_PWM 0x110
120#define CLK_SOURCE_SPI 0x114 100#define CLK_SOURCE_SPI 0x114
121#define CLK_SOURCE_SBC1 0x134
122#define CLK_SOURCE_SBC2 0x118
123#define CLK_SOURCE_SBC3 0x11c
124#define CLK_SOURCE_SBC4 0x1b4
125#define CLK_SOURCE_XIO 0x120 101#define CLK_SOURCE_XIO 0x120
126#define CLK_SOURCE_TWC 0x12c 102#define CLK_SOURCE_TWC 0x12c
127#define CLK_SOURCE_IDE 0x144 103#define CLK_SOURCE_IDE 0x144
128#define CLK_SOURCE_NDFLASH 0x160
129#define CLK_SOURCE_VFIR 0x168
130#define CLK_SOURCE_SDMMC1 0x150
131#define CLK_SOURCE_SDMMC2 0x154
132#define CLK_SOURCE_SDMMC3 0x1bc
133#define CLK_SOURCE_SDMMC4 0x164
134#define CLK_SOURCE_CVE 0x140
135#define CLK_SOURCE_TVO 0x188
136#define CLK_SOURCE_TVDAC 0x194
137#define CLK_SOURCE_HDMI 0x18c 104#define CLK_SOURCE_HDMI 0x18c
138#define CLK_SOURCE_DISP1 0x138 105#define CLK_SOURCE_DISP1 0x138
139#define CLK_SOURCE_DISP2 0x13c 106#define CLK_SOURCE_DISP2 0x13c
140#define CLK_SOURCE_CSITE 0x1d4 107#define CLK_SOURCE_CSITE 0x1d4
141#define CLK_SOURCE_LA 0x1f8
142#define CLK_SOURCE_OWR 0x1cc
143#define CLK_SOURCE_NOR 0x1d0
144#define CLK_SOURCE_MIPI 0x174
145#define CLK_SOURCE_I2C1 0x124 108#define CLK_SOURCE_I2C1 0x124
146#define CLK_SOURCE_I2C2 0x198 109#define CLK_SOURCE_I2C2 0x198
147#define CLK_SOURCE_I2C3 0x1b8 110#define CLK_SOURCE_I2C3 0x1b8
@@ -151,24 +114,10 @@
151#define CLK_SOURCE_UARTC 0x1a0 114#define CLK_SOURCE_UARTC 0x1a0
152#define CLK_SOURCE_UARTD 0x1c0 115#define CLK_SOURCE_UARTD 0x1c0
153#define CLK_SOURCE_UARTE 0x1c4 116#define CLK_SOURCE_UARTE 0x1c4
154#define CLK_SOURCE_3D 0x158
155#define CLK_SOURCE_2D 0x15c
156#define CLK_SOURCE_MPE 0x170
157#define CLK_SOURCE_EPP 0x16c
158#define CLK_SOURCE_HOST1X 0x180
159#define CLK_SOURCE_VDE 0x1c8
160#define CLK_SOURCE_VI 0x148
161#define CLK_SOURCE_VI_SENSOR 0x1a8
162#define CLK_SOURCE_EMC 0x19c 117#define CLK_SOURCE_EMC 0x19c
163 118
164#define AUDIO_SYNC_CLK 0x38 119#define AUDIO_SYNC_CLK 0x38
165 120
166#define PMC_CTRL 0x0
167#define PMC_CTRL_BLINK_ENB 7
168#define PMC_DPD_PADS_ORIDE 0x1c
169#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
170#define PMC_BLINK_TIMER 0x40
171
172/* Tegra CPU clock and reset control regs */ 121/* Tegra CPU clock and reset control regs */
173#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c 122#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
174#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340 123#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
@@ -188,64 +137,32 @@ static struct cpu_clk_suspend_context {
188} tegra20_cpu_clk_sctx; 137} tegra20_cpu_clk_sctx;
189#endif 138#endif
190 139
191static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
192
193static void __iomem *clk_base; 140static void __iomem *clk_base;
194static void __iomem *pmc_base; 141static void __iomem *pmc_base;
195 142
196static DEFINE_SPINLOCK(pll_div_lock); 143#define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \
197static DEFINE_SPINLOCK(sysrate_lock); 144 _clk_num, _gate_flags, _clk_id) \
198 145 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
199#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \
200 _clk_num, _regs, _gate_flags, _clk_id) \
201 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
202 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \ 146 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
203 _regs, _clk_num, periph_clk_enb_refcnt, \ 147 _clk_num, \
204 _gate_flags, _clk_id) 148 _gate_flags, _clk_id)
205 149
206#define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \ 150#define TEGRA_INIT_DATA_DIV16(_name, _parents, _offset, \
207 _clk_num, _regs, _gate_flags, _clk_id) \ 151 _clk_num, _gate_flags, _clk_id) \
208 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 152 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
209 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs, \ 153 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, \
210 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 154 _clk_num, _gate_flags, \
211 _clk_id)
212
213#define TEGRA_INIT_DATA_DIV16(_name, _con_id, _dev_id, _parents, _offset, \
214 _clk_num, _regs, _gate_flags, _clk_id) \
215 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
216 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, _regs, \
217 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
218 _clk_id) 155 _clk_id)
219 156
220#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \ 157#define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \
221 _mux_shift, _mux_width, _clk_num, _regs, \ 158 _mux_shift, _mux_width, _clk_num, \
222 _gate_flags, _clk_id) \ 159 _gate_flags, _clk_id) \
223 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 160 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
224 _mux_shift, _mux_width, 0, 0, 0, 0, 0, _regs, \ 161 _mux_shift, _mux_width, 0, 0, 0, 0, 0, \
225 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 162 _clk_num, _gate_flags, \
226 _clk_id) 163 _clk_id)
227 164
228/* IDs assigned here must be in sync with DT bindings definition 165static struct clk **clks;
229 * for Tegra20 clocks .
230 */
231enum tegra20_clk {
232 cpu, ac97 = 3, rtc, timer, uarta, gpio = 8, sdmmc2, i2s1 = 11, i2c1,
233 ndflash, sdmmc1, sdmmc4, twc, pwm, i2s2, epp, gr2d = 21, usbd, isp,
234 gr3d, ide, disp2, disp1, host1x, vcp, cache2 = 31, mem, ahbdma, apbdma,
235 kbc = 36, stat_mon, pmc, fuse, kfuse, sbc1, nor, spi, sbc2, xio, sbc3,
236 dvc, dsi, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2,
237 usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
238 pex, owr, afi, csite, pcie_xclk, avpucq = 75, la, irama = 84, iramb,
239 iramc, iramd, cram2, audio_2x, clk_d, csus = 92, cdev2, cdev1,
240 uartb = 96, vfir, spdif_in, spdif_out, vi, vi_sensor, tvo, cve,
241 osc, clk_32k, clk_m, sclk, cclk, hclk, pclk, blink, pll_a, pll_a_out0,
242 pll_c, pll_c_out1, pll_d, pll_d_out0, pll_e, pll_m, pll_m_out1,
243 pll_p, pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_s, pll_u,
244 pll_x, cop, audio, pll_ref, twd, clk_max,
245};
246
247static struct clk *clks[clk_max];
248static struct clk_onecell_data clk_data;
249 166
250static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 167static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
251 { 12000000, 600000000, 600, 12, 0, 8 }, 168 { 12000000, 600000000, 600, 12, 0, 8 },
@@ -383,6 +300,8 @@ static struct tegra_clk_pll_params pll_c_params = {
383 .lock_mask = PLL_BASE_LOCK, 300 .lock_mask = PLL_BASE_LOCK,
384 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 301 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
385 .lock_delay = 300, 302 .lock_delay = 300,
303 .freq_table = pll_c_freq_table,
304 .flags = TEGRA_PLL_HAS_CPCON,
386}; 305};
387 306
388static struct tegra_clk_pll_params pll_m_params = { 307static struct tegra_clk_pll_params pll_m_params = {
@@ -397,6 +316,8 @@ static struct tegra_clk_pll_params pll_m_params = {
397 .lock_mask = PLL_BASE_LOCK, 316 .lock_mask = PLL_BASE_LOCK,
398 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 317 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
399 .lock_delay = 300, 318 .lock_delay = 300,
319 .freq_table = pll_m_freq_table,
320 .flags = TEGRA_PLL_HAS_CPCON,
400}; 321};
401 322
402static struct tegra_clk_pll_params pll_p_params = { 323static struct tegra_clk_pll_params pll_p_params = {
@@ -411,6 +332,9 @@ static struct tegra_clk_pll_params pll_p_params = {
411 .lock_mask = PLL_BASE_LOCK, 332 .lock_mask = PLL_BASE_LOCK,
412 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 333 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
413 .lock_delay = 300, 334 .lock_delay = 300,
335 .freq_table = pll_p_freq_table,
336 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON,
337 .fixed_rate = 216000000,
414}; 338};
415 339
416static struct tegra_clk_pll_params pll_a_params = { 340static struct tegra_clk_pll_params pll_a_params = {
@@ -425,6 +349,8 @@ static struct tegra_clk_pll_params pll_a_params = {
425 .lock_mask = PLL_BASE_LOCK, 349 .lock_mask = PLL_BASE_LOCK,
426 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 350 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
427 .lock_delay = 300, 351 .lock_delay = 300,
352 .freq_table = pll_a_freq_table,
353 .flags = TEGRA_PLL_HAS_CPCON,
428}; 354};
429 355
430static struct tegra_clk_pll_params pll_d_params = { 356static struct tegra_clk_pll_params pll_d_params = {
@@ -439,6 +365,8 @@ static struct tegra_clk_pll_params pll_d_params = {
439 .lock_mask = PLL_BASE_LOCK, 365 .lock_mask = PLL_BASE_LOCK,
440 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 366 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
441 .lock_delay = 1000, 367 .lock_delay = 1000,
368 .freq_table = pll_d_freq_table,
369 .flags = TEGRA_PLL_HAS_CPCON,
442}; 370};
443 371
444static struct pdiv_map pllu_p[] = { 372static struct pdiv_map pllu_p[] = {
@@ -460,6 +388,8 @@ static struct tegra_clk_pll_params pll_u_params = {
460 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 388 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
461 .lock_delay = 1000, 389 .lock_delay = 1000,
462 .pdiv_tohw = pllu_p, 390 .pdiv_tohw = pllu_p,
391 .freq_table = pll_u_freq_table,
392 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON,
463}; 393};
464 394
465static struct tegra_clk_pll_params pll_x_params = { 395static struct tegra_clk_pll_params pll_x_params = {
@@ -474,6 +404,8 @@ static struct tegra_clk_pll_params pll_x_params = {
474 .lock_mask = PLL_BASE_LOCK, 404 .lock_mask = PLL_BASE_LOCK,
475 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 405 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
476 .lock_delay = 300, 406 .lock_delay = 300,
407 .freq_table = pll_x_freq_table,
408 .flags = TEGRA_PLL_HAS_CPCON,
477}; 409};
478 410
479static struct tegra_clk_pll_params pll_e_params = { 411static struct tegra_clk_pll_params pll_e_params = {
@@ -488,34 +420,161 @@ static struct tegra_clk_pll_params pll_e_params = {
488 .lock_mask = PLLE_MISC_LOCK, 420 .lock_mask = PLLE_MISC_LOCK,
489 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 421 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
490 .lock_delay = 0, 422 .lock_delay = 0,
423 .freq_table = pll_e_freq_table,
424 .flags = TEGRA_PLL_FIXED,
425 .fixed_rate = 100000000,
491}; 426};
492 427
493/* Peripheral clock registers */ 428static struct tegra_devclk devclks[] __initdata = {
494static struct tegra_clk_periph_regs periph_l_regs = { 429 { .con_id = "pll_c", .dt_id = TEGRA20_CLK_PLL_C },
495 .enb_reg = CLK_OUT_ENB_L, 430 { .con_id = "pll_c_out1", .dt_id = TEGRA20_CLK_PLL_C_OUT1 },
496 .enb_set_reg = CLK_OUT_ENB_SET_L, 431 { .con_id = "pll_p", .dt_id = TEGRA20_CLK_PLL_P },
497 .enb_clr_reg = CLK_OUT_ENB_CLR_L, 432 { .con_id = "pll_p_out1", .dt_id = TEGRA20_CLK_PLL_P_OUT1 },
498 .rst_reg = RST_DEVICES_L, 433 { .con_id = "pll_p_out2", .dt_id = TEGRA20_CLK_PLL_P_OUT2 },
499 .rst_set_reg = RST_DEVICES_SET_L, 434 { .con_id = "pll_p_out3", .dt_id = TEGRA20_CLK_PLL_P_OUT3 },
500 .rst_clr_reg = RST_DEVICES_CLR_L, 435 { .con_id = "pll_p_out4", .dt_id = TEGRA20_CLK_PLL_P_OUT4 },
436 { .con_id = "pll_m", .dt_id = TEGRA20_CLK_PLL_M },
437 { .con_id = "pll_m_out1", .dt_id = TEGRA20_CLK_PLL_M_OUT1 },
438 { .con_id = "pll_x", .dt_id = TEGRA20_CLK_PLL_X },
439 { .con_id = "pll_u", .dt_id = TEGRA20_CLK_PLL_U },
440 { .con_id = "pll_d", .dt_id = TEGRA20_CLK_PLL_D },
441 { .con_id = "pll_d_out0", .dt_id = TEGRA20_CLK_PLL_D_OUT0 },
442 { .con_id = "pll_a", .dt_id = TEGRA20_CLK_PLL_A },
443 { .con_id = "pll_a_out0", .dt_id = TEGRA20_CLK_PLL_A_OUT0 },
444 { .con_id = "pll_e", .dt_id = TEGRA20_CLK_PLL_E },
445 { .con_id = "cclk", .dt_id = TEGRA20_CLK_CCLK },
446 { .con_id = "sclk", .dt_id = TEGRA20_CLK_SCLK },
447 { .con_id = "hclk", .dt_id = TEGRA20_CLK_HCLK },
448 { .con_id = "pclk", .dt_id = TEGRA20_CLK_PCLK },
449 { .con_id = "fuse", .dt_id = TEGRA20_CLK_FUSE },
450 { .con_id = "twd", .dt_id = TEGRA20_CLK_TWD },
451 { .con_id = "audio", .dt_id = TEGRA20_CLK_AUDIO },
452 { .con_id = "audio_2x", .dt_id = TEGRA20_CLK_AUDIO_2X },
453 { .dev_id = "tegra20-ac97", .dt_id = TEGRA20_CLK_AC97 },
454 { .dev_id = "tegra-apbdma", .dt_id = TEGRA20_CLK_APBDMA },
455 { .dev_id = "rtc-tegra", .dt_id = TEGRA20_CLK_RTC },
456 { .dev_id = "timer", .dt_id = TEGRA20_CLK_TIMER },
457 { .dev_id = "tegra-kbc", .dt_id = TEGRA20_CLK_KBC },
458 { .con_id = "csus", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_CSUS },
459 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_VCP },
460 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_BSEA },
461 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA20_CLK_BSEV },
462 { .con_id = "emc", .dt_id = TEGRA20_CLK_EMC },
463 { .dev_id = "fsl-tegra-udc", .dt_id = TEGRA20_CLK_USBD },
464 { .dev_id = "tegra-ehci.1", .dt_id = TEGRA20_CLK_USB2 },
465 { .dev_id = "tegra-ehci.2", .dt_id = TEGRA20_CLK_USB3 },
466 { .dev_id = "dsi", .dt_id = TEGRA20_CLK_DSI },
467 { .con_id = "csi", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_CSI },
468 { .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_ISP },
469 { .con_id = "pex", .dt_id = TEGRA20_CLK_PEX },
470 { .con_id = "afi", .dt_id = TEGRA20_CLK_AFI },
471 { .con_id = "pcie_xclk", .dt_id = TEGRA20_CLK_PCIE_XCLK },
472 { .con_id = "cdev1", .dt_id = TEGRA20_CLK_CDEV1 },
473 { .con_id = "cdev2", .dt_id = TEGRA20_CLK_CDEV2 },
474 { .con_id = "clk_32k", .dt_id = TEGRA20_CLK_CLK_32K },
475 { .con_id = "blink", .dt_id = TEGRA20_CLK_BLINK },
476 { .con_id = "clk_m", .dt_id = TEGRA20_CLK_CLK_M },
477 { .con_id = "pll_ref", .dt_id = TEGRA20_CLK_PLL_REF },
478 { .dev_id = "tegra20-i2s.0", .dt_id = TEGRA20_CLK_I2S1 },
479 { .dev_id = "tegra20-i2s.1", .dt_id = TEGRA20_CLK_I2S2 },
480 { .con_id = "spdif_out", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_OUT },
481 { .con_id = "spdif_in", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_IN },
482 { .dev_id = "spi_tegra.0", .dt_id = TEGRA20_CLK_SBC1 },
483 { .dev_id = "spi_tegra.1", .dt_id = TEGRA20_CLK_SBC2 },
484 { .dev_id = "spi_tegra.2", .dt_id = TEGRA20_CLK_SBC3 },
485 { .dev_id = "spi_tegra.3", .dt_id = TEGRA20_CLK_SBC4 },
486 { .dev_id = "spi", .dt_id = TEGRA20_CLK_SPI },
487 { .dev_id = "xio", .dt_id = TEGRA20_CLK_XIO },
488 { .dev_id = "twc", .dt_id = TEGRA20_CLK_TWC },
489 { .dev_id = "ide", .dt_id = TEGRA20_CLK_IDE },
490 { .dev_id = "tegra_nand", .dt_id = TEGRA20_CLK_NDFLASH },
491 { .dev_id = "vfir", .dt_id = TEGRA20_CLK_VFIR },
492 { .dev_id = "csite", .dt_id = TEGRA20_CLK_CSITE },
493 { .dev_id = "la", .dt_id = TEGRA20_CLK_LA },
494 { .dev_id = "tegra_w1", .dt_id = TEGRA20_CLK_OWR },
495 { .dev_id = "mipi", .dt_id = TEGRA20_CLK_MIPI },
496 { .dev_id = "vde", .dt_id = TEGRA20_CLK_VDE },
497 { .con_id = "vi", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_VI },
498 { .dev_id = "epp", .dt_id = TEGRA20_CLK_EPP },
499 { .dev_id = "mpe", .dt_id = TEGRA20_CLK_MPE },
500 { .dev_id = "host1x", .dt_id = TEGRA20_CLK_HOST1X },
501 { .dev_id = "3d", .dt_id = TEGRA20_CLK_GR3D },
502 { .dev_id = "2d", .dt_id = TEGRA20_CLK_GR2D },
503 { .dev_id = "tegra-nor", .dt_id = TEGRA20_CLK_NOR },
504 { .dev_id = "sdhci-tegra.0", .dt_id = TEGRA20_CLK_SDMMC1 },
505 { .dev_id = "sdhci-tegra.1", .dt_id = TEGRA20_CLK_SDMMC2 },
506 { .dev_id = "sdhci-tegra.2", .dt_id = TEGRA20_CLK_SDMMC3 },
507 { .dev_id = "sdhci-tegra.3", .dt_id = TEGRA20_CLK_SDMMC4 },
508 { .dev_id = "cve", .dt_id = TEGRA20_CLK_CVE },
509 { .dev_id = "tvo", .dt_id = TEGRA20_CLK_TVO },
510 { .dev_id = "tvdac", .dt_id = TEGRA20_CLK_TVDAC },
511 { .con_id = "vi_sensor", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_VI_SENSOR },
512 { .dev_id = "hdmi", .dt_id = TEGRA20_CLK_HDMI },
513 { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA20_CLK_I2C1 },
514 { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA20_CLK_I2C2 },
515 { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA20_CLK_I2C3 },
516 { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA20_CLK_DVC },
517 { .dev_id = "tegra-pwm", .dt_id = TEGRA20_CLK_PWM },
518 { .dev_id = "tegra_uart.0", .dt_id = TEGRA20_CLK_UARTA },
519 { .dev_id = "tegra_uart.1", .dt_id = TEGRA20_CLK_UARTB },
520 { .dev_id = "tegra_uart.2", .dt_id = TEGRA20_CLK_UARTC },
521 { .dev_id = "tegra_uart.3", .dt_id = TEGRA20_CLK_UARTD },
522 { .dev_id = "tegra_uart.4", .dt_id = TEGRA20_CLK_UARTE },
523 { .dev_id = "tegradc.0", .dt_id = TEGRA20_CLK_DISP1 },
524 { .dev_id = "tegradc.1", .dt_id = TEGRA20_CLK_DISP2 },
501}; 525};
502 526
503static struct tegra_clk_periph_regs periph_h_regs = { 527static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = {
504 .enb_reg = CLK_OUT_ENB_H, 528 [tegra_clk_spdif_out] = { .dt_id = TEGRA20_CLK_SPDIF_OUT, .present = true },
505 .enb_set_reg = CLK_OUT_ENB_SET_H, 529 [tegra_clk_spdif_in] = { .dt_id = TEGRA20_CLK_SPDIF_IN, .present = true },
506 .enb_clr_reg = CLK_OUT_ENB_CLR_H, 530 [tegra_clk_sdmmc1] = { .dt_id = TEGRA20_CLK_SDMMC1, .present = true },
507 .rst_reg = RST_DEVICES_H, 531 [tegra_clk_sdmmc2] = { .dt_id = TEGRA20_CLK_SDMMC2, .present = true },
508 .rst_set_reg = RST_DEVICES_SET_H, 532 [tegra_clk_sdmmc3] = { .dt_id = TEGRA20_CLK_SDMMC3, .present = true },
509 .rst_clr_reg = RST_DEVICES_CLR_H, 533 [tegra_clk_sdmmc4] = { .dt_id = TEGRA20_CLK_SDMMC4, .present = true },
510}; 534 [tegra_clk_la] = { .dt_id = TEGRA20_CLK_LA, .present = true },
511 535 [tegra_clk_csite] = { .dt_id = TEGRA20_CLK_CSITE, .present = true },
512static struct tegra_clk_periph_regs periph_u_regs = { 536 [tegra_clk_vfir] = { .dt_id = TEGRA20_CLK_VFIR, .present = true },
513 .enb_reg = CLK_OUT_ENB_U, 537 [tegra_clk_mipi] = { .dt_id = TEGRA20_CLK_MIPI, .present = true },
514 .enb_set_reg = CLK_OUT_ENB_SET_U, 538 [tegra_clk_nor] = { .dt_id = TEGRA20_CLK_NOR, .present = true },
515 .enb_clr_reg = CLK_OUT_ENB_CLR_U, 539 [tegra_clk_rtc] = { .dt_id = TEGRA20_CLK_RTC, .present = true },
516 .rst_reg = RST_DEVICES_U, 540 [tegra_clk_timer] = { .dt_id = TEGRA20_CLK_TIMER, .present = true },
517 .rst_set_reg = RST_DEVICES_SET_U, 541 [tegra_clk_kbc] = { .dt_id = TEGRA20_CLK_KBC, .present = true },
518 .rst_clr_reg = RST_DEVICES_CLR_U, 542 [tegra_clk_csus] = { .dt_id = TEGRA20_CLK_CSUS, .present = true },
543 [tegra_clk_vcp] = { .dt_id = TEGRA20_CLK_VCP, .present = true },
544 [tegra_clk_bsea] = { .dt_id = TEGRA20_CLK_BSEA, .present = true },
545 [tegra_clk_bsev] = { .dt_id = TEGRA20_CLK_BSEV, .present = true },
546 [tegra_clk_usbd] = { .dt_id = TEGRA20_CLK_USBD, .present = true },
547 [tegra_clk_usb2] = { .dt_id = TEGRA20_CLK_USB2, .present = true },
548 [tegra_clk_usb3] = { .dt_id = TEGRA20_CLK_USB3, .present = true },
549 [tegra_clk_csi] = { .dt_id = TEGRA20_CLK_CSI, .present = true },
550 [tegra_clk_isp] = { .dt_id = TEGRA20_CLK_ISP, .present = true },
551 [tegra_clk_clk_32k] = { .dt_id = TEGRA20_CLK_CLK_32K, .present = true },
552 [tegra_clk_blink] = { .dt_id = TEGRA20_CLK_BLINK, .present = true },
553 [tegra_clk_hclk] = { .dt_id = TEGRA20_CLK_HCLK, .present = true },
554 [tegra_clk_pclk] = { .dt_id = TEGRA20_CLK_PCLK, .present = true },
555 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA20_CLK_PLL_P_OUT1, .present = true },
556 [tegra_clk_pll_p_out2] = { .dt_id = TEGRA20_CLK_PLL_P_OUT2, .present = true },
557 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA20_CLK_PLL_P_OUT3, .present = true },
558 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA20_CLK_PLL_P_OUT4, .present = true },
559 [tegra_clk_pll_p] = { .dt_id = TEGRA20_CLK_PLL_P, .present = true },
560 [tegra_clk_owr] = { .dt_id = TEGRA20_CLK_OWR, .present = true },
561 [tegra_clk_sbc1] = { .dt_id = TEGRA20_CLK_SBC1, .present = true },
562 [tegra_clk_sbc2] = { .dt_id = TEGRA20_CLK_SBC2, .present = true },
563 [tegra_clk_sbc3] = { .dt_id = TEGRA20_CLK_SBC3, .present = true },
564 [tegra_clk_sbc4] = { .dt_id = TEGRA20_CLK_SBC4, .present = true },
565 [tegra_clk_vde] = { .dt_id = TEGRA20_CLK_VDE, .present = true },
566 [tegra_clk_vi] = { .dt_id = TEGRA20_CLK_VI, .present = true },
567 [tegra_clk_epp] = { .dt_id = TEGRA20_CLK_EPP, .present = true },
568 [tegra_clk_mpe] = { .dt_id = TEGRA20_CLK_MPE, .present = true },
569 [tegra_clk_host1x] = { .dt_id = TEGRA20_CLK_HOST1X, .present = true },
570 [tegra_clk_gr2d] = { .dt_id = TEGRA20_CLK_GR2D, .present = true },
571 [tegra_clk_gr3d] = { .dt_id = TEGRA20_CLK_GR3D, .present = true },
572 [tegra_clk_ndflash] = { .dt_id = TEGRA20_CLK_NDFLASH, .present = true },
573 [tegra_clk_cve] = { .dt_id = TEGRA20_CLK_CVE, .present = true },
574 [tegra_clk_tvo] = { .dt_id = TEGRA20_CLK_TVO, .present = true },
575 [tegra_clk_tvdac] = { .dt_id = TEGRA20_CLK_TVDAC, .present = true },
576 [tegra_clk_vi_sensor] = { .dt_id = TEGRA20_CLK_VI_SENSOR, .present = true },
577 [tegra_clk_afi] = { .dt_id = TEGRA20_CLK_AFI, .present = true },
519}; 578};
520 579
521static unsigned long tegra20_clk_measure_input_freq(void) 580static unsigned long tegra20_clk_measure_input_freq(void)
@@ -577,10 +636,8 @@ static void tegra20_pll_init(void)
577 636
578 /* PLLC */ 637 /* PLLC */
579 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0, 638 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0,
580 0, &pll_c_params, TEGRA_PLL_HAS_CPCON, 639 &pll_c_params, NULL);
581 pll_c_freq_table, NULL); 640 clks[TEGRA20_CLK_PLL_C] = clk;
582 clk_register_clkdev(clk, "pll_c", NULL);
583 clks[pll_c] = clk;
584 641
585 /* PLLC_OUT1 */ 642 /* PLLC_OUT1 */
586 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", 643 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
@@ -589,71 +646,13 @@ static void tegra20_pll_init(void)
589 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", 646 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
590 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, 647 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,
591 0, NULL); 648 0, NULL);
592 clk_register_clkdev(clk, "pll_c_out1", NULL); 649 clks[TEGRA20_CLK_PLL_C_OUT1] = clk;
593 clks[pll_c_out1] = clk;
594
595 /* PLLP */
596 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, NULL, 0,
597 216000000, &pll_p_params, TEGRA_PLL_FIXED |
598 TEGRA_PLL_HAS_CPCON, pll_p_freq_table, NULL);
599 clk_register_clkdev(clk, "pll_p", NULL);
600 clks[pll_p] = clk;
601
602 /* PLLP_OUT1 */
603 clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p",
604 clk_base + PLLP_OUTA, 0,
605 TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP,
606 8, 8, 1, &pll_div_lock);
607 clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div",
608 clk_base + PLLP_OUTA, 1, 0,
609 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
610 &pll_div_lock);
611 clk_register_clkdev(clk, "pll_p_out1", NULL);
612 clks[pll_p_out1] = clk;
613
614 /* PLLP_OUT2 */
615 clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p",
616 clk_base + PLLP_OUTA, 0,
617 TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP,
618 24, 8, 1, &pll_div_lock);
619 clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div",
620 clk_base + PLLP_OUTA, 17, 16,
621 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
622 &pll_div_lock);
623 clk_register_clkdev(clk, "pll_p_out2", NULL);
624 clks[pll_p_out2] = clk;
625
626 /* PLLP_OUT3 */
627 clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p",
628 clk_base + PLLP_OUTB, 0,
629 TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP,
630 8, 8, 1, &pll_div_lock);
631 clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div",
632 clk_base + PLLP_OUTB, 1, 0,
633 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
634 &pll_div_lock);
635 clk_register_clkdev(clk, "pll_p_out3", NULL);
636 clks[pll_p_out3] = clk;
637
638 /* PLLP_OUT4 */
639 clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p",
640 clk_base + PLLP_OUTB, 0,
641 TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP,
642 24, 8, 1, &pll_div_lock);
643 clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div",
644 clk_base + PLLP_OUTB, 17, 16,
645 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
646 &pll_div_lock);
647 clk_register_clkdev(clk, "pll_p_out4", NULL);
648 clks[pll_p_out4] = clk;
649 650
650 /* PLLM */ 651 /* PLLM */
651 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL, 652 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL,
652 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 0, 653 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
653 &pll_m_params, TEGRA_PLL_HAS_CPCON, 654 &pll_m_params, NULL);
654 pll_m_freq_table, NULL); 655 clks[TEGRA20_CLK_PLL_M] = clk;
655 clk_register_clkdev(clk, "pll_m", NULL);
656 clks[pll_m] = clk;
657 656
658 /* PLLM_OUT1 */ 657 /* PLLM_OUT1 */
659 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", 658 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
@@ -662,42 +661,32 @@ static void tegra20_pll_init(void)
662 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", 661 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
663 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | 662 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
664 CLK_SET_RATE_PARENT, 0, NULL); 663 CLK_SET_RATE_PARENT, 0, NULL);
665 clk_register_clkdev(clk, "pll_m_out1", NULL); 664 clks[TEGRA20_CLK_PLL_M_OUT1] = clk;
666 clks[pll_m_out1] = clk;
667 665
668 /* PLLX */ 666 /* PLLX */
669 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0, 667 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0,
670 0, &pll_x_params, TEGRA_PLL_HAS_CPCON, 668 &pll_x_params, NULL);
671 pll_x_freq_table, NULL); 669 clks[TEGRA20_CLK_PLL_X] = clk;
672 clk_register_clkdev(clk, "pll_x", NULL);
673 clks[pll_x] = clk;
674 670
675 /* PLLU */ 671 /* PLLU */
676 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0, 672 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0,
677 0, &pll_u_params, TEGRA_PLLU | TEGRA_PLL_HAS_CPCON, 673 &pll_u_params, NULL);
678 pll_u_freq_table, NULL); 674 clks[TEGRA20_CLK_PLL_U] = clk;
679 clk_register_clkdev(clk, "pll_u", NULL);
680 clks[pll_u] = clk;
681 675
682 /* PLLD */ 676 /* PLLD */
683 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, NULL, 0, 677 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, NULL, 0,
684 0, &pll_d_params, TEGRA_PLL_HAS_CPCON, 678 &pll_d_params, NULL);
685 pll_d_freq_table, NULL); 679 clks[TEGRA20_CLK_PLL_D] = clk;
686 clk_register_clkdev(clk, "pll_d", NULL);
687 clks[pll_d] = clk;
688 680
689 /* PLLD_OUT0 */ 681 /* PLLD_OUT0 */
690 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", 682 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
691 CLK_SET_RATE_PARENT, 1, 2); 683 CLK_SET_RATE_PARENT, 1, 2);
692 clk_register_clkdev(clk, "pll_d_out0", NULL); 684 clks[TEGRA20_CLK_PLL_D_OUT0] = clk;
693 clks[pll_d_out0] = clk;
694 685
695 /* PLLA */ 686 /* PLLA */
696 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, NULL, 0, 687 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, NULL, 0,
697 0, &pll_a_params, TEGRA_PLL_HAS_CPCON, 688 &pll_a_params, NULL);
698 pll_a_freq_table, NULL); 689 clks[TEGRA20_CLK_PLL_A] = clk;
699 clk_register_clkdev(clk, "pll_a", NULL);
700 clks[pll_a] = clk;
701 690
702 /* PLLA_OUT0 */ 691 /* PLLA_OUT0 */
703 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a", 692 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
@@ -706,15 +695,12 @@ static void tegra20_pll_init(void)
706 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div", 695 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
707 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | 696 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
708 CLK_SET_RATE_PARENT, 0, NULL); 697 CLK_SET_RATE_PARENT, 0, NULL);
709 clk_register_clkdev(clk, "pll_a_out0", NULL); 698 clks[TEGRA20_CLK_PLL_A_OUT0] = clk;
710 clks[pll_a_out0] = clk;
711 699
712 /* PLLE */ 700 /* PLLE */
713 clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base, 701 clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base,
714 0, 100000000, &pll_e_params, 702 0, &pll_e_params, NULL);
715 0, pll_e_freq_table, NULL); 703 clks[TEGRA20_CLK_PLL_E] = clk;
716 clk_register_clkdev(clk, "pll_e", NULL);
717 clks[pll_e] = clk;
718} 704}
719 705
720static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 706static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
@@ -732,40 +718,17 @@ static void tegra20_super_clk_init(void)
732 clk = tegra_clk_register_super_mux("cclk", cclk_parents, 718 clk = tegra_clk_register_super_mux("cclk", cclk_parents,
733 ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT, 719 ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT,
734 clk_base + CCLK_BURST_POLICY, 0, 4, 0, 0, NULL); 720 clk_base + CCLK_BURST_POLICY, 0, 4, 0, 0, NULL);
735 clk_register_clkdev(clk, "cclk", NULL); 721 clks[TEGRA20_CLK_CCLK] = clk;
736 clks[cclk] = clk;
737 722
738 /* SCLK */ 723 /* SCLK */
739 clk = tegra_clk_register_super_mux("sclk", sclk_parents, 724 clk = tegra_clk_register_super_mux("sclk", sclk_parents,
740 ARRAY_SIZE(sclk_parents), CLK_SET_RATE_PARENT, 725 ARRAY_SIZE(sclk_parents), CLK_SET_RATE_PARENT,
741 clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL); 726 clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL);
742 clk_register_clkdev(clk, "sclk", NULL); 727 clks[TEGRA20_CLK_SCLK] = clk;
743 clks[sclk] = clk;
744
745 /* HCLK */
746 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
747 clk_base + CLK_SYSTEM_RATE, 4, 2, 0,
748 &sysrate_lock);
749 clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT,
750 clk_base + CLK_SYSTEM_RATE, 7,
751 CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
752 clk_register_clkdev(clk, "hclk", NULL);
753 clks[hclk] = clk;
754
755 /* PCLK */
756 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
757 clk_base + CLK_SYSTEM_RATE, 0, 2, 0,
758 &sysrate_lock);
759 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT,
760 clk_base + CLK_SYSTEM_RATE, 3,
761 CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
762 clk_register_clkdev(clk, "pclk", NULL);
763 clks[pclk] = clk;
764 728
765 /* twd */ 729 /* twd */
766 clk = clk_register_fixed_factor(NULL, "twd", "cclk", 0, 1, 4); 730 clk = clk_register_fixed_factor(NULL, "twd", "cclk", 0, 1, 4);
767 clk_register_clkdev(clk, "twd", NULL); 731 clks[TEGRA20_CLK_TWD] = clk;
768 clks[twd] = clk;
769} 732}
770 733
771static const char *audio_parents[] = {"spdif_in", "i2s1", "i2s2", "unused", 734static const char *audio_parents[] = {"spdif_in", "i2s1", "i2s2", "unused",
@@ -784,18 +747,16 @@ static void __init tegra20_audio_clk_init(void)
784 clk = clk_register_gate(NULL, "audio", "audio_mux", 0, 747 clk = clk_register_gate(NULL, "audio", "audio_mux", 0,
785 clk_base + AUDIO_SYNC_CLK, 4, 748 clk_base + AUDIO_SYNC_CLK, 4,
786 CLK_GATE_SET_TO_DISABLE, NULL); 749 CLK_GATE_SET_TO_DISABLE, NULL);
787 clk_register_clkdev(clk, "audio", NULL); 750 clks[TEGRA20_CLK_AUDIO] = clk;
788 clks[audio] = clk;
789 751
790 /* audio_2x */ 752 /* audio_2x */
791 clk = clk_register_fixed_factor(NULL, "audio_doubler", "audio", 753 clk = clk_register_fixed_factor(NULL, "audio_doubler", "audio",
792 CLK_SET_RATE_PARENT, 2, 1); 754 CLK_SET_RATE_PARENT, 2, 1);
793 clk = tegra_clk_register_periph_gate("audio_2x", "audio_doubler", 755 clk = tegra_clk_register_periph_gate("audio_2x", "audio_doubler",
794 TEGRA_PERIPH_NO_RESET, clk_base, 756 TEGRA_PERIPH_NO_RESET, clk_base,
795 CLK_SET_RATE_PARENT, 89, &periph_u_regs, 757 CLK_SET_RATE_PARENT, 89,
796 periph_clk_enb_refcnt); 758 periph_clk_enb_refcnt);
797 clk_register_clkdev(clk, "audio_2x", NULL); 759 clks[TEGRA20_CLK_AUDIO_2X] = clk;
798 clks[audio_2x] = clk;
799 760
800} 761}
801 762
@@ -803,68 +764,36 @@ static const char *i2s1_parents[] = {"pll_a_out0", "audio_2x", "pll_p",
803 "clk_m"}; 764 "clk_m"};
804static const char *i2s2_parents[] = {"pll_a_out0", "audio_2x", "pll_p", 765static const char *i2s2_parents[] = {"pll_a_out0", "audio_2x", "pll_p",
805 "clk_m"}; 766 "clk_m"};
806static const char *spdif_out_parents[] = {"pll_a_out0", "audio_2x", "pll_p",
807 "clk_m"};
808static const char *spdif_in_parents[] = {"pll_p", "pll_c", "pll_m"};
809static const char *pwm_parents[] = {"pll_p", "pll_c", "audio", "clk_m", 767static const char *pwm_parents[] = {"pll_p", "pll_c", "audio", "clk_m",
810 "clk_32k"}; 768 "clk_32k"};
811static const char *mux_pllpcm_clkm[] = {"pll_p", "pll_c", "pll_m", "clk_m"}; 769static const char *mux_pllpcm_clkm[] = {"pll_p", "pll_c", "pll_m", "clk_m"};
812static const char *mux_pllmcpa[] = {"pll_m", "pll_c", "pll_c", "pll_a"};
813static const char *mux_pllpdc_clkm[] = {"pll_p", "pll_d_out0", "pll_c", 770static const char *mux_pllpdc_clkm[] = {"pll_p", "pll_d_out0", "pll_c",
814 "clk_m"}; 771 "clk_m"};
815static const char *mux_pllmcp_clkm[] = {"pll_m", "pll_c", "pll_p", "clk_m"}; 772static const char *mux_pllmcp_clkm[] = {"pll_m", "pll_c", "pll_p", "clk_m"};
816 773
817static struct tegra_periph_init_data tegra_periph_clk_list[] = { 774static struct tegra_periph_init_data tegra_periph_clk_list[] = {
818 TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra20-i2s.0", i2s1_parents, CLK_SOURCE_I2S1, 11, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s1), 775 TEGRA_INIT_DATA_MUX("i2s1", i2s1_parents, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2S1),
819 TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra20-i2s.1", i2s2_parents, CLK_SOURCE_I2S2, 18, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s2), 776 TEGRA_INIT_DATA_MUX("i2s2", i2s2_parents, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2S2),
820 TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra20-spdif", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_out), 777 TEGRA_INIT_DATA_MUX("spi", mux_pllpcm_clkm, CLK_SOURCE_SPI, 43, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_SPI),
821 TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra20-spdif", spdif_in_parents, CLK_SOURCE_SPDIF_IN, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_in), 778 TEGRA_INIT_DATA_MUX("xio", mux_pllpcm_clkm, CLK_SOURCE_XIO, 45, 0, TEGRA20_CLK_XIO),
822 TEGRA_INIT_DATA_MUX("sbc1", NULL, "spi_tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1), 779 TEGRA_INIT_DATA_MUX("twc", mux_pllpcm_clkm, CLK_SOURCE_TWC, 16, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_TWC),
823 TEGRA_INIT_DATA_MUX("sbc2", NULL, "spi_tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SBC2, 44, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc2), 780 TEGRA_INIT_DATA_MUX("ide", mux_pllpcm_clkm, CLK_SOURCE_XIO, 25, 0, TEGRA20_CLK_IDE),
824 TEGRA_INIT_DATA_MUX("sbc3", NULL, "spi_tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SBC3, 46, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc3), 781 TEGRA_INIT_DATA_DIV16("dvc", mux_pllpcm_clkm, CLK_SOURCE_DVC, 47, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_DVC),
825 TEGRA_INIT_DATA_MUX("sbc4", NULL, "spi_tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SBC4, 68, &periph_u_regs, TEGRA_PERIPH_ON_APB, sbc4), 782 TEGRA_INIT_DATA_DIV16("i2c1", mux_pllpcm_clkm, CLK_SOURCE_I2C1, 12, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C1),
826 TEGRA_INIT_DATA_MUX("spi", NULL, "spi", mux_pllpcm_clkm, CLK_SOURCE_SPI, 43, &periph_h_regs, TEGRA_PERIPH_ON_APB, spi), 783 TEGRA_INIT_DATA_DIV16("i2c2", mux_pllpcm_clkm, CLK_SOURCE_I2C2, 54, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C2),
827 TEGRA_INIT_DATA_MUX("xio", NULL, "xio", mux_pllpcm_clkm, CLK_SOURCE_XIO, 45, &periph_h_regs, 0, xio), 784 TEGRA_INIT_DATA_DIV16("i2c3", mux_pllpcm_clkm, CLK_SOURCE_I2C3, 67, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C3),
828 TEGRA_INIT_DATA_MUX("twc", NULL, "twc", mux_pllpcm_clkm, CLK_SOURCE_TWC, 16, &periph_l_regs, TEGRA_PERIPH_ON_APB, twc), 785 TEGRA_INIT_DATA_MUX("hdmi", mux_pllpdc_clkm, CLK_SOURCE_HDMI, 51, 0, TEGRA20_CLK_HDMI),
829 TEGRA_INIT_DATA_MUX("ide", NULL, "ide", mux_pllpcm_clkm, CLK_SOURCE_XIO, 25, &periph_l_regs, 0, ide), 786 TEGRA_INIT_DATA("pwm", NULL, NULL, pwm_parents, CLK_SOURCE_PWM, 28, 3, 0, 0, 8, 1, 0, 17, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_PWM),
830 TEGRA_INIT_DATA_MUX("ndflash", NULL, "tegra_nand", mux_pllpcm_clkm, CLK_SOURCE_NDFLASH, 13, &periph_l_regs, 0, ndflash),
831 TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllpcm_clkm, CLK_SOURCE_VFIR, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, vfir),
832 TEGRA_INIT_DATA_MUX("csite", NULL, "csite", mux_pllpcm_clkm, CLK_SOURCE_CSITE, 73, &periph_u_regs, 0, csite),
833 TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllpcm_clkm, CLK_SOURCE_LA, 76, &periph_u_regs, 0, la),
834 TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllpcm_clkm, CLK_SOURCE_OWR, 71, &periph_u_regs, TEGRA_PERIPH_ON_APB, owr),
835 TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllpcm_clkm, CLK_SOURCE_MIPI, 50, &periph_h_regs, TEGRA_PERIPH_ON_APB, mipi),
836 TEGRA_INIT_DATA_MUX("vde", NULL, "vde", mux_pllpcm_clkm, CLK_SOURCE_VDE, 61, &periph_h_regs, 0, vde),
837 TEGRA_INIT_DATA_MUX("vi", "vi", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI, 20, &periph_l_regs, 0, vi),
838 TEGRA_INIT_DATA_MUX("epp", NULL, "epp", mux_pllmcpa, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, epp),
839 TEGRA_INIT_DATA_MUX("mpe", NULL, "mpe", mux_pllmcpa, CLK_SOURCE_MPE, 60, &periph_h_regs, 0, mpe),
840 TEGRA_INIT_DATA_MUX("host1x", NULL, "host1x", mux_pllmcpa, CLK_SOURCE_HOST1X, 28, &periph_l_regs, 0, host1x),
841 TEGRA_INIT_DATA_MUX("3d", NULL, "3d", mux_pllmcpa, CLK_SOURCE_3D, 24, &periph_l_regs, TEGRA_PERIPH_MANUAL_RESET, gr3d),
842 TEGRA_INIT_DATA_MUX("2d", NULL, "2d", mux_pllmcpa, CLK_SOURCE_2D, 21, &periph_l_regs, 0, gr2d),
843 TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllpcm_clkm, CLK_SOURCE_NOR, 42, &periph_h_regs, 0, nor),
844 TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SDMMC1, 14, &periph_l_regs, 0, sdmmc1),
845 TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SDMMC2, 9, &periph_l_regs, 0, sdmmc2),
846 TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SDMMC3, 69, &periph_u_regs, 0, sdmmc3),
847 TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SDMMC4, 15, &periph_l_regs, 0, sdmmc4),
848 TEGRA_INIT_DATA_MUX("cve", NULL, "cve", mux_pllpdc_clkm, CLK_SOURCE_CVE, 49, &periph_h_regs, 0, cve),
849 TEGRA_INIT_DATA_MUX("tvo", NULL, "tvo", mux_pllpdc_clkm, CLK_SOURCE_TVO, 49, &periph_h_regs, 0, tvo),
850 TEGRA_INIT_DATA_MUX("tvdac", NULL, "tvdac", mux_pllpdc_clkm, CLK_SOURCE_TVDAC, 53, &periph_h_regs, 0, tvdac),
851 TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, vi_sensor),
852 TEGRA_INIT_DATA_DIV16("i2c1", "div-clk", "tegra-i2c.0", mux_pllpcm_clkm, CLK_SOURCE_I2C1, 12, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2c1),
853 TEGRA_INIT_DATA_DIV16("i2c2", "div-clk", "tegra-i2c.1", mux_pllpcm_clkm, CLK_SOURCE_I2C2, 54, &periph_h_regs, TEGRA_PERIPH_ON_APB, i2c2),
854 TEGRA_INIT_DATA_DIV16("i2c3", "div-clk", "tegra-i2c.2", mux_pllpcm_clkm, CLK_SOURCE_I2C3, 67, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2c3),
855 TEGRA_INIT_DATA_DIV16("dvc", "div-clk", "tegra-i2c.3", mux_pllpcm_clkm, CLK_SOURCE_DVC, 47, &periph_h_regs, TEGRA_PERIPH_ON_APB, dvc),
856 TEGRA_INIT_DATA_MUX("hdmi", NULL, "hdmi", mux_pllpdc_clkm, CLK_SOURCE_HDMI, 51, &periph_h_regs, 0, hdmi),
857 TEGRA_INIT_DATA("pwm", NULL, "tegra-pwm", pwm_parents, CLK_SOURCE_PWM, 28, 3, 0, 0, 8, 1, 0, &periph_l_regs, 17, periph_clk_enb_refcnt, TEGRA_PERIPH_ON_APB, pwm),
858}; 787};
859 788
860static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { 789static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
861 TEGRA_INIT_DATA_NODIV("uarta", NULL, "tegra_uart.0", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 30, 2, 6, &periph_l_regs, TEGRA_PERIPH_ON_APB, uarta), 790 TEGRA_INIT_DATA_NODIV("uarta", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 30, 2, 6, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTA),
862 TEGRA_INIT_DATA_NODIV("uartb", NULL, "tegra_uart.1", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 30, 2, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, uartb), 791 TEGRA_INIT_DATA_NODIV("uartb", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 30, 2, 7, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTB),
863 TEGRA_INIT_DATA_NODIV("uartc", NULL, "tegra_uart.2", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 30, 2, 55, &periph_h_regs, TEGRA_PERIPH_ON_APB, uartc), 792 TEGRA_INIT_DATA_NODIV("uartc", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 30, 2, 55, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTC),
864 TEGRA_INIT_DATA_NODIV("uartd", NULL, "tegra_uart.3", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 30, 2, 65, &periph_u_regs, TEGRA_PERIPH_ON_APB, uartd), 793 TEGRA_INIT_DATA_NODIV("uartd", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 30, 2, 65, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTD),
865 TEGRA_INIT_DATA_NODIV("uarte", NULL, "tegra_uart.4", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 30, 2, 66, &periph_u_regs, TEGRA_PERIPH_ON_APB, uarte), 794 TEGRA_INIT_DATA_NODIV("uarte", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 30, 2, 66, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTE),
866 TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllpdc_clkm, CLK_SOURCE_DISP1, 30, 2, 27, &periph_l_regs, 0, disp1), 795 TEGRA_INIT_DATA_NODIV("disp1", mux_pllpdc_clkm, CLK_SOURCE_DISP1, 30, 2, 27, 0, TEGRA20_CLK_DISP1),
867 TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllpdc_clkm, CLK_SOURCE_DISP2, 30, 2, 26, &periph_l_regs, 0, disp2), 796 TEGRA_INIT_DATA_NODIV("disp2", mux_pllpdc_clkm, CLK_SOURCE_DISP2, 30, 2, 26, 0, TEGRA20_CLK_DISP2),
868}; 797};
869 798
870static void __init tegra20_periph_clk_init(void) 799static void __init tegra20_periph_clk_init(void)
@@ -876,69 +805,13 @@ static void __init tegra20_periph_clk_init(void)
876 /* ac97 */ 805 /* ac97 */
877 clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0", 806 clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0",
878 TEGRA_PERIPH_ON_APB, 807 TEGRA_PERIPH_ON_APB,
879 clk_base, 0, 3, &periph_l_regs, 808 clk_base, 0, 3, periph_clk_enb_refcnt);
880 periph_clk_enb_refcnt); 809 clks[TEGRA20_CLK_AC97] = clk;
881 clk_register_clkdev(clk, NULL, "tegra20-ac97");
882 clks[ac97] = clk;
883 810
884 /* apbdma */ 811 /* apbdma */
885 clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base, 812 clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base,
886 0, 34, &periph_h_regs, 813 0, 34, periph_clk_enb_refcnt);
887 periph_clk_enb_refcnt); 814 clks[TEGRA20_CLK_APBDMA] = clk;
888 clk_register_clkdev(clk, NULL, "tegra-apbdma");
889 clks[apbdma] = clk;
890
891 /* rtc */
892 clk = tegra_clk_register_periph_gate("rtc", "clk_32k",
893 TEGRA_PERIPH_NO_RESET,
894 clk_base, 0, 4, &periph_l_regs,
895 periph_clk_enb_refcnt);
896 clk_register_clkdev(clk, NULL, "rtc-tegra");
897 clks[rtc] = clk;
898
899 /* timer */
900 clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base,
901 0, 5, &periph_l_regs,
902 periph_clk_enb_refcnt);
903 clk_register_clkdev(clk, NULL, "timer");
904 clks[timer] = clk;
905
906 /* kbc */
907 clk = tegra_clk_register_periph_gate("kbc", "clk_32k",
908 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB,
909 clk_base, 0, 36, &periph_h_regs,
910 periph_clk_enb_refcnt);
911 clk_register_clkdev(clk, NULL, "tegra-kbc");
912 clks[kbc] = clk;
913
914 /* csus */
915 clk = tegra_clk_register_periph_gate("csus", "clk_m",
916 TEGRA_PERIPH_NO_RESET,
917 clk_base, 0, 92, &periph_u_regs,
918 periph_clk_enb_refcnt);
919 clk_register_clkdev(clk, "csus", "tengra_camera");
920 clks[csus] = clk;
921
922 /* vcp */
923 clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0,
924 clk_base, 0, 29, &periph_l_regs,
925 periph_clk_enb_refcnt);
926 clk_register_clkdev(clk, "vcp", "tegra-avp");
927 clks[vcp] = clk;
928
929 /* bsea */
930 clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0,
931 clk_base, 0, 62, &periph_h_regs,
932 periph_clk_enb_refcnt);
933 clk_register_clkdev(clk, "bsea", "tegra-avp");
934 clks[bsea] = clk;
935
936 /* bsev */
937 clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0,
938 clk_base, 0, 63, &periph_h_regs,
939 periph_clk_enb_refcnt);
940 clk_register_clkdev(clk, "bsev", "tegra-aes");
941 clks[bsev] = clk;
942 815
943 /* emc */ 816 /* emc */
944 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 817 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
@@ -947,130 +820,57 @@ static void __init tegra20_periph_clk_init(void)
947 clk_base + CLK_SOURCE_EMC, 820 clk_base + CLK_SOURCE_EMC,
948 30, 2, 0, NULL); 821 30, 2, 0, NULL);
949 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0, 822 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
950 57, &periph_h_regs, periph_clk_enb_refcnt); 823 57, periph_clk_enb_refcnt);
951 clk_register_clkdev(clk, "emc", NULL); 824 clks[TEGRA20_CLK_EMC] = clk;
952 clks[emc] = clk;
953
954 /* usbd */
955 clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base, 0,
956 22, &periph_l_regs, periph_clk_enb_refcnt);
957 clk_register_clkdev(clk, NULL, "fsl-tegra-udc");
958 clks[usbd] = clk;
959
960 /* usb2 */
961 clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base, 0,
962 58, &periph_h_regs, periph_clk_enb_refcnt);
963 clk_register_clkdev(clk, NULL, "tegra-ehci.1");
964 clks[usb2] = clk;
965
966 /* usb3 */
967 clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base, 0,
968 59, &periph_h_regs, periph_clk_enb_refcnt);
969 clk_register_clkdev(clk, NULL, "tegra-ehci.2");
970 clks[usb3] = clk;
971 825
972 /* dsi */ 826 /* dsi */
973 clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0, 827 clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0,
974 48, &periph_h_regs, periph_clk_enb_refcnt); 828 48, periph_clk_enb_refcnt);
975 clk_register_clkdev(clk, NULL, "dsi"); 829 clk_register_clkdev(clk, NULL, "dsi");
976 clks[dsi] = clk; 830 clks[TEGRA20_CLK_DSI] = clk;
977
978 /* csi */
979 clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base,
980 0, 52, &periph_h_regs,
981 periph_clk_enb_refcnt);
982 clk_register_clkdev(clk, "csi", "tegra_camera");
983 clks[csi] = clk;
984
985 /* isp */
986 clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0, 23,
987 &periph_l_regs, periph_clk_enb_refcnt);
988 clk_register_clkdev(clk, "isp", "tegra_camera");
989 clks[isp] = clk;
990 831
991 /* pex */ 832 /* pex */
992 clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70, 833 clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70,
993 &periph_u_regs, periph_clk_enb_refcnt); 834 periph_clk_enb_refcnt);
994 clk_register_clkdev(clk, "pex", NULL); 835 clks[TEGRA20_CLK_PEX] = clk;
995 clks[pex] = clk;
996
997 /* afi */
998 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72,
999 &periph_u_regs, periph_clk_enb_refcnt);
1000 clk_register_clkdev(clk, "afi", NULL);
1001 clks[afi] = clk;
1002 836
1003 /* pcie_xclk */ 837 /* pcie_xclk */
1004 clk = tegra_clk_register_periph_gate("pcie_xclk", "clk_m", 0, clk_base, 838 clk = tegra_clk_register_periph_gate("pcie_xclk", "clk_m", 0, clk_base,
1005 0, 74, &periph_u_regs, 839 0, 74, periph_clk_enb_refcnt);
1006 periph_clk_enb_refcnt); 840 clks[TEGRA20_CLK_PCIE_XCLK] = clk;
1007 clk_register_clkdev(clk, "pcie_xclk", NULL);
1008 clks[pcie_xclk] = clk;
1009 841
1010 /* cdev1 */ 842 /* cdev1 */
1011 clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, CLK_IS_ROOT, 843 clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, CLK_IS_ROOT,
1012 26000000); 844 26000000);
1013 clk = tegra_clk_register_periph_gate("cdev1", "cdev1_fixed", 0, 845 clk = tegra_clk_register_periph_gate("cdev1", "cdev1_fixed", 0,
1014 clk_base, 0, 94, &periph_u_regs, 846 clk_base, 0, 94, periph_clk_enb_refcnt);
1015 periph_clk_enb_refcnt); 847 clks[TEGRA20_CLK_CDEV1] = clk;
1016 clk_register_clkdev(clk, "cdev1", NULL);
1017 clks[cdev1] = clk;
1018 848
1019 /* cdev2 */ 849 /* cdev2 */
1020 clk = clk_register_fixed_rate(NULL, "cdev2_fixed", NULL, CLK_IS_ROOT, 850 clk = clk_register_fixed_rate(NULL, "cdev2_fixed", NULL, CLK_IS_ROOT,
1021 26000000); 851 26000000);
1022 clk = tegra_clk_register_periph_gate("cdev2", "cdev2_fixed", 0, 852 clk = tegra_clk_register_periph_gate("cdev2", "cdev2_fixed", 0,
1023 clk_base, 0, 93, &periph_u_regs, 853 clk_base, 0, 93, periph_clk_enb_refcnt);
1024 periph_clk_enb_refcnt); 854 clks[TEGRA20_CLK_CDEV2] = clk;
1025 clk_register_clkdev(clk, "cdev2", NULL);
1026 clks[cdev2] = clk;
1027 855
1028 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { 856 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
1029 data = &tegra_periph_clk_list[i]; 857 data = &tegra_periph_clk_list[i];
1030 clk = tegra_clk_register_periph(data->name, data->parent_names, 858 clk = tegra_clk_register_periph(data->name, data->p.parent_names,
1031 data->num_parents, &data->periph, 859 data->num_parents, &data->periph,
1032 clk_base, data->offset, data->flags); 860 clk_base, data->offset, data->flags);
1033 clk_register_clkdev(clk, data->con_id, data->dev_id);
1034 clks[data->clk_id] = clk; 861 clks[data->clk_id] = clk;
1035 } 862 }
1036 863
1037 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) { 864 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
1038 data = &tegra_periph_nodiv_clk_list[i]; 865 data = &tegra_periph_nodiv_clk_list[i];
1039 clk = tegra_clk_register_periph_nodiv(data->name, 866 clk = tegra_clk_register_periph_nodiv(data->name,
1040 data->parent_names, 867 data->p.parent_names,
1041 data->num_parents, &data->periph, 868 data->num_parents, &data->periph,
1042 clk_base, data->offset); 869 clk_base, data->offset);
1043 clk_register_clkdev(clk, data->con_id, data->dev_id);
1044 clks[data->clk_id] = clk; 870 clks[data->clk_id] = clk;
1045 } 871 }
1046}
1047
1048 872
1049static void __init tegra20_fixed_clk_init(void) 873 tegra_periph_clk_init(clk_base, pmc_base, tegra20_clks, &pll_p_params);
1050{
1051 struct clk *clk;
1052
1053 /* clk_32k */
1054 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT,
1055 32768);
1056 clk_register_clkdev(clk, "clk_32k", NULL);
1057 clks[clk_32k] = clk;
1058}
1059
1060static void __init tegra20_pmc_clk_init(void)
1061{
1062 struct clk *clk;
1063
1064 /* blink */
1065 writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
1066 clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
1067 pmc_base + PMC_DPD_PADS_ORIDE,
1068 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
1069 clk = clk_register_gate(NULL, "blink", "blink_override", 0,
1070 pmc_base + PMC_CTRL,
1071 PMC_CTRL_BLINK_ENB, 0, NULL);
1072 clk_register_clkdev(clk, "blink", NULL);
1073 clks[blink] = clk;
1074} 874}
1075 875
1076static void __init tegra20_osc_clk_init(void) 876static void __init tegra20_osc_clk_init(void)
@@ -1084,15 +884,13 @@ static void __init tegra20_osc_clk_init(void)
1084 /* clk_m */ 884 /* clk_m */
1085 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT | 885 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT |
1086 CLK_IGNORE_UNUSED, input_freq); 886 CLK_IGNORE_UNUSED, input_freq);
1087 clk_register_clkdev(clk, "clk_m", NULL); 887 clks[TEGRA20_CLK_CLK_M] = clk;
1088 clks[clk_m] = clk;
1089 888
1090 /* pll_ref */ 889 /* pll_ref */
1091 pll_ref_div = tegra20_get_pll_ref_div(); 890 pll_ref_div = tegra20_get_pll_ref_div();
1092 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m", 891 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
1093 CLK_SET_RATE_PARENT, 1, pll_ref_div); 892 CLK_SET_RATE_PARENT, 1, pll_ref_div);
1094 clk_register_clkdev(clk, "pll_ref", NULL); 893 clks[TEGRA20_CLK_PLL_REF] = clk;
1095 clks[pll_ref] = clk;
1096} 894}
1097 895
1098/* Tegra20 CPU clock and reset control functions */ 896/* Tegra20 CPU clock and reset control functions */
@@ -1226,49 +1024,49 @@ static struct tegra_cpu_car_ops tegra20_cpu_car_ops = {
1226}; 1024};
1227 1025
1228static struct tegra_clk_init_table init_table[] __initdata = { 1026static struct tegra_clk_init_table init_table[] __initdata = {
1229 {pll_p, clk_max, 216000000, 1}, 1027 {TEGRA20_CLK_PLL_P, TEGRA20_CLK_CLK_MAX, 216000000, 1},
1230 {pll_p_out1, clk_max, 28800000, 1}, 1028 {TEGRA20_CLK_PLL_P_OUT1, TEGRA20_CLK_CLK_MAX, 28800000, 1},
1231 {pll_p_out2, clk_max, 48000000, 1}, 1029 {TEGRA20_CLK_PLL_P_OUT2, TEGRA20_CLK_CLK_MAX, 48000000, 1},
1232 {pll_p_out3, clk_max, 72000000, 1}, 1030 {TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1},
1233 {pll_p_out4, clk_max, 24000000, 1}, 1031 {TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1},
1234 {pll_c, clk_max, 600000000, 1}, 1032 {TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 1},
1235 {pll_c_out1, clk_max, 120000000, 1}, 1033 {TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 120000000, 1},
1236 {sclk, pll_c_out1, 0, 1}, 1034 {TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 0, 1},
1237 {hclk, clk_max, 0, 1}, 1035 {TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 0, 1},
1238 {pclk, clk_max, 60000000, 1}, 1036 {TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 1},
1239 {csite, clk_max, 0, 1}, 1037 {TEGRA20_CLK_CSITE, TEGRA20_CLK_CLK_MAX, 0, 1},
1240 {emc, clk_max, 0, 1}, 1038 {TEGRA20_CLK_EMC, TEGRA20_CLK_CLK_MAX, 0, 1},
1241 {cclk, clk_max, 0, 1}, 1039 {TEGRA20_CLK_CCLK, TEGRA20_CLK_CLK_MAX, 0, 1},
1242 {uarta, pll_p, 0, 0}, 1040 {TEGRA20_CLK_UARTA, TEGRA20_CLK_PLL_P, 0, 0},
1243 {uartb, pll_p, 0, 0}, 1041 {TEGRA20_CLK_UARTB, TEGRA20_CLK_PLL_P, 0, 0},
1244 {uartc, pll_p, 0, 0}, 1042 {TEGRA20_CLK_UARTC, TEGRA20_CLK_PLL_P, 0, 0},
1245 {uartd, pll_p, 0, 0}, 1043 {TEGRA20_CLK_UARTD, TEGRA20_CLK_PLL_P, 0, 0},
1246 {uarte, pll_p, 0, 0}, 1044 {TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P, 0, 0},
1247 {pll_a, clk_max, 56448000, 1}, 1045 {TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 1},
1248 {pll_a_out0, clk_max, 11289600, 1}, 1046 {TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 1},
1249 {cdev1, clk_max, 0, 1}, 1047 {TEGRA20_CLK_CDEV1, TEGRA20_CLK_CLK_MAX, 0, 1},
1250 {blink, clk_max, 32768, 1}, 1048 {TEGRA20_CLK_BLINK, TEGRA20_CLK_CLK_MAX, 32768, 1},
1251 {i2s1, pll_a_out0, 11289600, 0}, 1049 {TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0},
1252 {i2s2, pll_a_out0, 11289600, 0}, 1050 {TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0},
1253 {sdmmc1, pll_p, 48000000, 0}, 1051 {TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0},
1254 {sdmmc3, pll_p, 48000000, 0}, 1052 {TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0},
1255 {sdmmc4, pll_p, 48000000, 0}, 1053 {TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0},
1256 {spi, pll_p, 20000000, 0}, 1054 {TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0},
1257 {sbc1, pll_p, 100000000, 0}, 1055 {TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0},
1258 {sbc2, pll_p, 100000000, 0}, 1056 {TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0},
1259 {sbc3, pll_p, 100000000, 0}, 1057 {TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0},
1260 {sbc4, pll_p, 100000000, 0}, 1058 {TEGRA20_CLK_SBC4, TEGRA20_CLK_PLL_P, 100000000, 0},
1261 {host1x, pll_c, 150000000, 0}, 1059 {TEGRA20_CLK_HOST1X, TEGRA20_CLK_PLL_C, 150000000, 0},
1262 {disp1, pll_p, 600000000, 0}, 1060 {TEGRA20_CLK_DISP1, TEGRA20_CLK_PLL_P, 600000000, 0},
1263 {disp2, pll_p, 600000000, 0}, 1061 {TEGRA20_CLK_DISP2, TEGRA20_CLK_PLL_P, 600000000, 0},
1264 {gr2d, pll_c, 300000000, 0}, 1062 {TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0},
1265 {gr3d, pll_c, 300000000, 0}, 1063 {TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0},
1266 {clk_max, clk_max, 0, 0}, /* This MUST be the last entry */ 1064 {TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0}, /* This MUST be the last entry */
1267}; 1065};
1268 1066
1269static void __init tegra20_clock_apply_init_table(void) 1067static void __init tegra20_clock_apply_init_table(void)
1270{ 1068{
1271 tegra_init_from_table(init_table, clks, clk_max); 1069 tegra_init_from_table(init_table, clks, TEGRA20_CLK_CLK_MAX);
1272} 1070}
1273 1071
1274/* 1072/*
@@ -1277,11 +1075,11 @@ static void __init tegra20_clock_apply_init_table(void)
1277 * table under two names. 1075 * table under two names.
1278 */ 1076 */
1279static struct tegra_clk_duplicate tegra_clk_duplicates[] = { 1077static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
1280 TEGRA_CLK_DUPLICATE(usbd, "utmip-pad", NULL), 1078 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "utmip-pad", NULL),
1281 TEGRA_CLK_DUPLICATE(usbd, "tegra-ehci.0", NULL), 1079 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-ehci.0", NULL),
1282 TEGRA_CLK_DUPLICATE(usbd, "tegra-otg", NULL), 1080 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-otg", NULL),
1283 TEGRA_CLK_DUPLICATE(cclk, NULL, "cpu"), 1081 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CCLK, NULL, "cpu"),
1284 TEGRA_CLK_DUPLICATE(clk_max, NULL, NULL), /* Must be the last entry */ 1082 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CLK_MAX, NULL, NULL), /* Must be the last entry */
1285}; 1083};
1286 1084
1287static const struct of_device_id pmc_match[] __initconst = { 1085static const struct of_device_id pmc_match[] __initconst = {
@@ -1291,7 +1089,6 @@ static const struct of_device_id pmc_match[] __initconst = {
1291 1089
1292static void __init tegra20_clock_init(struct device_node *np) 1090static void __init tegra20_clock_init(struct device_node *np)
1293{ 1091{
1294 int i;
1295 struct device_node *node; 1092 struct device_node *node;
1296 1093
1297 clk_base = of_iomap(np, 0); 1094 clk_base = of_iomap(np, 0);
@@ -1312,30 +1109,23 @@ static void __init tegra20_clock_init(struct device_node *np)
1312 BUG(); 1109 BUG();
1313 } 1110 }
1314 1111
1112 clks = tegra_clk_init(TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_PERIPH_BANKS);
1113 if (!clks)
1114 return;
1115
1315 tegra20_osc_clk_init(); 1116 tegra20_osc_clk_init();
1316 tegra20_pmc_clk_init(); 1117 tegra_fixed_clk_init(tegra20_clks);
1317 tegra20_fixed_clk_init();
1318 tegra20_pll_init(); 1118 tegra20_pll_init();
1319 tegra20_super_clk_init(); 1119 tegra20_super_clk_init();
1120 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra20_clks, NULL);
1320 tegra20_periph_clk_init(); 1121 tegra20_periph_clk_init();
1321 tegra20_audio_clk_init(); 1122 tegra20_audio_clk_init();
1123 tegra_pmc_clk_init(pmc_base, tegra20_clks);
1322 1124
1125 tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA20_CLK_CLK_MAX);
1323 1126
1324 for (i = 0; i < ARRAY_SIZE(clks); i++) { 1127 tegra_add_of_provider(np);
1325 if (IS_ERR(clks[i])) { 1128 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1326 pr_err("Tegra20 clk %d: register failed with %ld\n",
1327 i, PTR_ERR(clks[i]));
1328 BUG();
1329 }
1330 if (!clks[i])
1331 clks[i] = ERR_PTR(-EINVAL);
1332 }
1333
1334 tegra_init_dup_clks(tegra_clk_duplicates, clks, clk_max);
1335
1336 clk_data.clks = clks;
1337 clk_data.clk_num = ARRAY_SIZE(clks);
1338 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
1339 1129
1340 tegra_clk_apply_init_table = tegra20_clock_apply_init_table; 1130 tegra_clk_apply_init_table = tegra20_clock_apply_init_table;
1341 1131
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index dbe7c8003c5c..dcb6843b3a89 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -23,42 +23,9 @@
23#include <linux/of_address.h> 23#include <linux/of_address.h>
24#include <linux/clk/tegra.h> 24#include <linux/clk/tegra.h>
25#include <linux/tegra-powergate.h> 25#include <linux/tegra-powergate.h>
26 26#include <dt-bindings/clock/tegra30-car.h>
27#include "clk.h" 27#include "clk.h"
28 28#include "clk-id.h"
29#define RST_DEVICES_L 0x004
30#define RST_DEVICES_H 0x008
31#define RST_DEVICES_U 0x00c
32#define RST_DEVICES_V 0x358
33#define RST_DEVICES_W 0x35c
34#define RST_DEVICES_SET_L 0x300
35#define RST_DEVICES_CLR_L 0x304
36#define RST_DEVICES_SET_H 0x308
37#define RST_DEVICES_CLR_H 0x30c
38#define RST_DEVICES_SET_U 0x310
39#define RST_DEVICES_CLR_U 0x314
40#define RST_DEVICES_SET_V 0x430
41#define RST_DEVICES_CLR_V 0x434
42#define RST_DEVICES_SET_W 0x438
43#define RST_DEVICES_CLR_W 0x43c
44#define RST_DEVICES_NUM 5
45
46#define CLK_OUT_ENB_L 0x010
47#define CLK_OUT_ENB_H 0x014
48#define CLK_OUT_ENB_U 0x018
49#define CLK_OUT_ENB_V 0x360
50#define CLK_OUT_ENB_W 0x364
51#define CLK_OUT_ENB_SET_L 0x320
52#define CLK_OUT_ENB_CLR_L 0x324
53#define CLK_OUT_ENB_SET_H 0x328
54#define CLK_OUT_ENB_CLR_H 0x32c
55#define CLK_OUT_ENB_SET_U 0x330
56#define CLK_OUT_ENB_CLR_U 0x334
57#define CLK_OUT_ENB_SET_V 0x440
58#define CLK_OUT_ENB_CLR_V 0x444
59#define CLK_OUT_ENB_SET_W 0x448
60#define CLK_OUT_ENB_CLR_W 0x44c
61#define CLK_OUT_ENB_NUM 5
62 29
63#define OSC_CTRL 0x50 30#define OSC_CTRL 0x50
64#define OSC_CTRL_OSC_FREQ_MASK (0xF<<28) 31#define OSC_CTRL_OSC_FREQ_MASK (0xF<<28)
@@ -92,6 +59,8 @@
92 59
93#define SYSTEM_CLK_RATE 0x030 60#define SYSTEM_CLK_RATE 0x030
94 61
62#define TEGRA30_CLK_PERIPH_BANKS 5
63
95#define PLLC_BASE 0x80 64#define PLLC_BASE 0x80
96#define PLLC_MISC 0x8c 65#define PLLC_MISC 0x8c
97#define PLLM_BASE 0x90 66#define PLLM_BASE 0x90
@@ -132,88 +101,21 @@
132#define AUDIO_SYNC_CLK_I2S4 0x4b0 101#define AUDIO_SYNC_CLK_I2S4 0x4b0
133#define AUDIO_SYNC_CLK_SPDIF 0x4b4 102#define AUDIO_SYNC_CLK_SPDIF 0x4b4
134 103
135#define PMC_CLK_OUT_CNTRL 0x1a8
136
137#define CLK_SOURCE_I2S0 0x1d8
138#define CLK_SOURCE_I2S1 0x100
139#define CLK_SOURCE_I2S2 0x104
140#define CLK_SOURCE_I2S3 0x3bc
141#define CLK_SOURCE_I2S4 0x3c0
142#define CLK_SOURCE_SPDIF_OUT 0x108 104#define CLK_SOURCE_SPDIF_OUT 0x108
143#define CLK_SOURCE_SPDIF_IN 0x10c
144#define CLK_SOURCE_PWM 0x110 105#define CLK_SOURCE_PWM 0x110
145#define CLK_SOURCE_D_AUDIO 0x3d0 106#define CLK_SOURCE_D_AUDIO 0x3d0
146#define CLK_SOURCE_DAM0 0x3d8 107#define CLK_SOURCE_DAM0 0x3d8
147#define CLK_SOURCE_DAM1 0x3dc 108#define CLK_SOURCE_DAM1 0x3dc
148#define CLK_SOURCE_DAM2 0x3e0 109#define CLK_SOURCE_DAM2 0x3e0
149#define CLK_SOURCE_HDA 0x428
150#define CLK_SOURCE_HDA2CODEC_2X 0x3e4
151#define CLK_SOURCE_SBC1 0x134
152#define CLK_SOURCE_SBC2 0x118
153#define CLK_SOURCE_SBC3 0x11c
154#define CLK_SOURCE_SBC4 0x1b4
155#define CLK_SOURCE_SBC5 0x3c8
156#define CLK_SOURCE_SBC6 0x3cc
157#define CLK_SOURCE_SATA_OOB 0x420
158#define CLK_SOURCE_SATA 0x424
159#define CLK_SOURCE_NDFLASH 0x160
160#define CLK_SOURCE_NDSPEED 0x3f8
161#define CLK_SOURCE_VFIR 0x168
162#define CLK_SOURCE_SDMMC1 0x150
163#define CLK_SOURCE_SDMMC2 0x154
164#define CLK_SOURCE_SDMMC3 0x1bc
165#define CLK_SOURCE_SDMMC4 0x164
166#define CLK_SOURCE_VDE 0x1c8
167#define CLK_SOURCE_CSITE 0x1d4
168#define CLK_SOURCE_LA 0x1f8
169#define CLK_SOURCE_OWR 0x1cc
170#define CLK_SOURCE_NOR 0x1d0
171#define CLK_SOURCE_MIPI 0x174
172#define CLK_SOURCE_I2C1 0x124
173#define CLK_SOURCE_I2C2 0x198
174#define CLK_SOURCE_I2C3 0x1b8
175#define CLK_SOURCE_I2C4 0x3c4
176#define CLK_SOURCE_I2C5 0x128
177#define CLK_SOURCE_UARTA 0x178
178#define CLK_SOURCE_UARTB 0x17c
179#define CLK_SOURCE_UARTC 0x1a0
180#define CLK_SOURCE_UARTD 0x1c0
181#define CLK_SOURCE_UARTE 0x1c4
182#define CLK_SOURCE_VI 0x148
183#define CLK_SOURCE_VI_SENSOR 0x1a8
184#define CLK_SOURCE_3D 0x158
185#define CLK_SOURCE_3D2 0x3b0 110#define CLK_SOURCE_3D2 0x3b0
186#define CLK_SOURCE_2D 0x15c 111#define CLK_SOURCE_2D 0x15c
187#define CLK_SOURCE_EPP 0x16c
188#define CLK_SOURCE_MPE 0x170
189#define CLK_SOURCE_HOST1X 0x180
190#define CLK_SOURCE_CVE 0x140
191#define CLK_SOURCE_TVO 0x188
192#define CLK_SOURCE_DTV 0x1dc
193#define CLK_SOURCE_HDMI 0x18c 112#define CLK_SOURCE_HDMI 0x18c
194#define CLK_SOURCE_TVDAC 0x194
195#define CLK_SOURCE_DISP1 0x138
196#define CLK_SOURCE_DISP2 0x13c
197#define CLK_SOURCE_DSIB 0xd0 113#define CLK_SOURCE_DSIB 0xd0
198#define CLK_SOURCE_TSENSOR 0x3b8
199#define CLK_SOURCE_ACTMON 0x3e8
200#define CLK_SOURCE_EXTERN1 0x3ec
201#define CLK_SOURCE_EXTERN2 0x3f0
202#define CLK_SOURCE_EXTERN3 0x3f4
203#define CLK_SOURCE_I2CSLOW 0x3fc
204#define CLK_SOURCE_SE 0x42c 114#define CLK_SOURCE_SE 0x42c
205#define CLK_SOURCE_MSELECT 0x3b4
206#define CLK_SOURCE_EMC 0x19c 115#define CLK_SOURCE_EMC 0x19c
207 116
208#define AUDIO_SYNC_DOUBLER 0x49c 117#define AUDIO_SYNC_DOUBLER 0x49c
209 118
210#define PMC_CTRL 0
211#define PMC_CTRL_BLINK_ENB 7
212
213#define PMC_DPD_PADS_ORIDE 0x1c
214#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
215#define PMC_BLINK_TIMER 0x40
216
217#define UTMIP_PLL_CFG2 0x488 119#define UTMIP_PLL_CFG2 0x488
218#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6) 120#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
219#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) 121#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
@@ -266,89 +168,41 @@ static struct cpu_clk_suspend_context {
266} tegra30_cpu_clk_sctx; 168} tegra30_cpu_clk_sctx;
267#endif 169#endif
268 170
269static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
270
271static void __iomem *clk_base; 171static void __iomem *clk_base;
272static void __iomem *pmc_base; 172static void __iomem *pmc_base;
273static unsigned long input_freq; 173static unsigned long input_freq;
274 174
275static DEFINE_SPINLOCK(clk_doubler_lock);
276static DEFINE_SPINLOCK(clk_out_lock);
277static DEFINE_SPINLOCK(pll_div_lock);
278static DEFINE_SPINLOCK(cml_lock); 175static DEFINE_SPINLOCK(cml_lock);
279static DEFINE_SPINLOCK(pll_d_lock); 176static DEFINE_SPINLOCK(pll_d_lock);
280static DEFINE_SPINLOCK(sysrate_lock);
281
282#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \
283 _clk_num, _regs, _gate_flags, _clk_id) \
284 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
285 30, 2, 0, 0, 8, 1, 0, _regs, _clk_num, \
286 periph_clk_enb_refcnt, _gate_flags, _clk_id)
287
288#define TEGRA_INIT_DATA_DIV16(_name, _con_id, _dev_id, _parents, _offset, \
289 _clk_num, _regs, _gate_flags, _clk_id) \
290 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
291 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, \
292 _regs, _clk_num, periph_clk_enb_refcnt, \
293 _gate_flags, _clk_id)
294
295#define TEGRA_INIT_DATA_MUX8(_name, _con_id, _dev_id, _parents, _offset, \
296 _clk_num, _regs, _gate_flags, _clk_id) \
297 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
298 29, 3, 0, 0, 8, 1, 0, _regs, _clk_num, \
299 periph_clk_enb_refcnt, _gate_flags, _clk_id)
300
301#define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \
302 _clk_num, _regs, _gate_flags, _clk_id) \
303 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
304 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs, \
305 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
306 _clk_id)
307 177
308#define TEGRA_INIT_DATA_UART(_name, _con_id, _dev_id, _parents, _offset,\ 178#define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \
309 _clk_num, _regs, _clk_id) \ 179 _clk_num, _gate_flags, _clk_id) \
310 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 180 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
311 30, 2, 0, 0, 16, 1, TEGRA_DIVIDER_UART, _regs, \ 181 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
312 _clk_num, periph_clk_enb_refcnt, 0, _clk_id) 182 _clk_num, _gate_flags, _clk_id)
183
184#define TEGRA_INIT_DATA_MUX8(_name, _parents, _offset, \
185 _clk_num, _gate_flags, _clk_id) \
186 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
187 29, 3, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
188 _clk_num, _gate_flags, _clk_id)
189
190#define TEGRA_INIT_DATA_INT(_name, _parents, _offset, \
191 _clk_num, _gate_flags, _clk_id) \
192 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
193 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT | \
194 TEGRA_DIVIDER_ROUND_UP, _clk_num, \
195 _gate_flags, _clk_id)
313 196
314#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \ 197#define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \
315 _mux_shift, _mux_width, _clk_num, _regs, \ 198 _mux_shift, _mux_width, _clk_num, \
316 _gate_flags, _clk_id) \ 199 _gate_flags, _clk_id) \
317 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 200 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
318 _mux_shift, _mux_width, 0, 0, 0, 0, 0, _regs, \ 201 _mux_shift, _mux_width, 0, 0, 0, 0, 0,\
319 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 202 _clk_num, _gate_flags, \
320 _clk_id) 203 _clk_id)
321 204
322/* 205static struct clk **clks;
323 * IDs assigned here must be in sync with DT bindings definition
324 * for Tegra30 clocks.
325 */
326enum tegra30_clk {
327 cpu, rtc = 4, timer, uarta, gpio = 8, sdmmc2, i2s1 = 11, i2c1, ndflash,
328 sdmmc1, sdmmc4, pwm = 17, i2s2, epp, gr2d = 21, usbd, isp, gr3d,
329 disp2 = 26, disp1, host1x, vcp, i2s0, cop_cache, mc, ahbdma, apbdma,
330 kbc = 36, statmon, pmc, kfuse = 40, sbc1, nor, sbc2 = 44, sbc3 = 46,
331 i2c5, dsia, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2,
332 usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
333 pcie, owr, afi, csite, pciex, avpucq, la, dtv = 79, ndspeed, i2cslow,
334 dsib, irama = 84, iramb, iramc, iramd, cram2, audio_2x = 90, csus = 92,
335 cdev2, cdev1, cpu_g = 96, cpu_lp, gr3d2, mselect, tsensor, i2s3, i2s4,
336 i2c4, sbc5, sbc6, d_audio, apbif, dam0, dam1, dam2, hda2codec_2x,
337 atomics, audio0_2x, audio1_2x, audio2_2x, audio3_2x, audio4_2x,
338 spdif_2x, actmon, extern1, extern2, extern3, sata_oob, sata, hda,
339 se = 127, hda2hdmi, sata_cold, uartb = 160, vfir, spdif_in, spdif_out,
340 vi, vi_sensor, fuse, fuse_burn, cve, tvo, clk_32k, clk_m, clk_m_div2,
341 clk_m_div4, pll_ref, pll_c, pll_c_out1, pll_m, pll_m_out1, pll_p,
342 pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_a, pll_a_out0,
343 pll_d, pll_d_out0, pll_d2, pll_d2_out0, pll_u, pll_x, pll_x_out0, pll_e,
344 spdif_in_sync, i2s0_sync, i2s1_sync, i2s2_sync, i2s3_sync, i2s4_sync,
345 vimclk_sync, audio0, audio1, audio2, audio3, audio4, spdif, clk_out_1,
346 clk_out_2, clk_out_3, sclk, blink, cclk_g, cclk_lp, twd, cml0, cml1,
347 hclk, pclk, clk_out_1_mux = 300, clk_max
348};
349
350static struct clk *clks[clk_max];
351static struct clk_onecell_data clk_data;
352 206
353/* 207/*
354 * Structure defining the fields for USB UTMI clocks Parameters. 208 * Structure defining the fields for USB UTMI clocks Parameters.
@@ -564,6 +418,8 @@ static struct tegra_clk_pll_params pll_c_params = {
564 .lock_mask = PLL_BASE_LOCK, 418 .lock_mask = PLL_BASE_LOCK,
565 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 419 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
566 .lock_delay = 300, 420 .lock_delay = 300,
421 .freq_table = pll_c_freq_table,
422 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
567}; 423};
568 424
569static struct div_nmp pllm_nmp = { 425static struct div_nmp pllm_nmp = {
@@ -593,6 +449,9 @@ static struct tegra_clk_pll_params pll_m_params = {
593 .div_nmp = &pllm_nmp, 449 .div_nmp = &pllm_nmp,
594 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE, 450 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
595 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE, 451 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE,
452 .freq_table = pll_m_freq_table,
453 .flags = TEGRA_PLLM | TEGRA_PLL_HAS_CPCON |
454 TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK,
596}; 455};
597 456
598static struct tegra_clk_pll_params pll_p_params = { 457static struct tegra_clk_pll_params pll_p_params = {
@@ -607,6 +466,9 @@ static struct tegra_clk_pll_params pll_p_params = {
607 .lock_mask = PLL_BASE_LOCK, 466 .lock_mask = PLL_BASE_LOCK,
608 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 467 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
609 .lock_delay = 300, 468 .lock_delay = 300,
469 .freq_table = pll_p_freq_table,
470 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
471 .fixed_rate = 408000000,
610}; 472};
611 473
612static struct tegra_clk_pll_params pll_a_params = { 474static struct tegra_clk_pll_params pll_a_params = {
@@ -621,6 +483,8 @@ static struct tegra_clk_pll_params pll_a_params = {
621 .lock_mask = PLL_BASE_LOCK, 483 .lock_mask = PLL_BASE_LOCK,
622 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 484 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
623 .lock_delay = 300, 485 .lock_delay = 300,
486 .freq_table = pll_a_freq_table,
487 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
624}; 488};
625 489
626static struct tegra_clk_pll_params pll_d_params = { 490static struct tegra_clk_pll_params pll_d_params = {
@@ -635,6 +499,10 @@ static struct tegra_clk_pll_params pll_d_params = {
635 .lock_mask = PLL_BASE_LOCK, 499 .lock_mask = PLL_BASE_LOCK,
636 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 500 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
637 .lock_delay = 1000, 501 .lock_delay = 1000,
502 .freq_table = pll_d_freq_table,
503 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
504 TEGRA_PLL_USE_LOCK,
505
638}; 506};
639 507
640static struct tegra_clk_pll_params pll_d2_params = { 508static struct tegra_clk_pll_params pll_d2_params = {
@@ -649,6 +517,9 @@ static struct tegra_clk_pll_params pll_d2_params = {
649 .lock_mask = PLL_BASE_LOCK, 517 .lock_mask = PLL_BASE_LOCK,
650 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 518 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
651 .lock_delay = 1000, 519 .lock_delay = 1000,
520 .freq_table = pll_d_freq_table,
521 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
522 TEGRA_PLL_USE_LOCK,
652}; 523};
653 524
654static struct tegra_clk_pll_params pll_u_params = { 525static struct tegra_clk_pll_params pll_u_params = {
@@ -664,6 +535,8 @@ static struct tegra_clk_pll_params pll_u_params = {
664 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 535 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
665 .lock_delay = 1000, 536 .lock_delay = 1000,
666 .pdiv_tohw = pllu_p, 537 .pdiv_tohw = pllu_p,
538 .freq_table = pll_u_freq_table,
539 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON,
667}; 540};
668 541
669static struct tegra_clk_pll_params pll_x_params = { 542static struct tegra_clk_pll_params pll_x_params = {
@@ -678,6 +551,9 @@ static struct tegra_clk_pll_params pll_x_params = {
678 .lock_mask = PLL_BASE_LOCK, 551 .lock_mask = PLL_BASE_LOCK,
679 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 552 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
680 .lock_delay = 300, 553 .lock_delay = 300,
554 .freq_table = pll_x_freq_table,
555 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_DCCON |
556 TEGRA_PLL_USE_LOCK,
681}; 557};
682 558
683static struct tegra_clk_pll_params pll_e_params = { 559static struct tegra_clk_pll_params pll_e_params = {
@@ -692,116 +568,300 @@ static struct tegra_clk_pll_params pll_e_params = {
692 .lock_mask = PLLE_MISC_LOCK, 568 .lock_mask = PLLE_MISC_LOCK,
693 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 569 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
694 .lock_delay = 300, 570 .lock_delay = 300,
571 .freq_table = pll_e_freq_table,
572 .flags = TEGRA_PLLE_CONFIGURE | TEGRA_PLL_FIXED,
573 .fixed_rate = 100000000,
695}; 574};
696 575
697/* Peripheral clock registers */ 576static unsigned long tegra30_input_freq[] = {
698static struct tegra_clk_periph_regs periph_l_regs = { 577 [0] = 13000000,
699 .enb_reg = CLK_OUT_ENB_L, 578 [1] = 16800000,
700 .enb_set_reg = CLK_OUT_ENB_SET_L, 579 [4] = 19200000,
701 .enb_clr_reg = CLK_OUT_ENB_CLR_L, 580 [5] = 38400000,
702 .rst_reg = RST_DEVICES_L, 581 [8] = 12000000,
703 .rst_set_reg = RST_DEVICES_SET_L, 582 [9] = 48000000,
704 .rst_clr_reg = RST_DEVICES_CLR_L, 583 [12] = 260000000,
705}; 584};
706 585
707static struct tegra_clk_periph_regs periph_h_regs = { 586static struct tegra_devclk devclks[] __initdata = {
708 .enb_reg = CLK_OUT_ENB_H, 587 { .con_id = "pll_c", .dt_id = TEGRA30_CLK_PLL_C },
709 .enb_set_reg = CLK_OUT_ENB_SET_H, 588 { .con_id = "pll_c_out1", .dt_id = TEGRA30_CLK_PLL_C_OUT1 },
710 .enb_clr_reg = CLK_OUT_ENB_CLR_H, 589 { .con_id = "pll_p", .dt_id = TEGRA30_CLK_PLL_P },
711 .rst_reg = RST_DEVICES_H, 590 { .con_id = "pll_p_out1", .dt_id = TEGRA30_CLK_PLL_P_OUT1 },
712 .rst_set_reg = RST_DEVICES_SET_H, 591 { .con_id = "pll_p_out2", .dt_id = TEGRA30_CLK_PLL_P_OUT2 },
713 .rst_clr_reg = RST_DEVICES_CLR_H, 592 { .con_id = "pll_p_out3", .dt_id = TEGRA30_CLK_PLL_P_OUT3 },
593 { .con_id = "pll_p_out4", .dt_id = TEGRA30_CLK_PLL_P_OUT4 },
594 { .con_id = "pll_m", .dt_id = TEGRA30_CLK_PLL_M },
595 { .con_id = "pll_m_out1", .dt_id = TEGRA30_CLK_PLL_M_OUT1 },
596 { .con_id = "pll_x", .dt_id = TEGRA30_CLK_PLL_X },
597 { .con_id = "pll_x_out0", .dt_id = TEGRA30_CLK_PLL_X_OUT0 },
598 { .con_id = "pll_u", .dt_id = TEGRA30_CLK_PLL_U },
599 { .con_id = "pll_d", .dt_id = TEGRA30_CLK_PLL_D },
600 { .con_id = "pll_d_out0", .dt_id = TEGRA30_CLK_PLL_D_OUT0 },
601 { .con_id = "pll_d2", .dt_id = TEGRA30_CLK_PLL_D2 },
602 { .con_id = "pll_d2_out0", .dt_id = TEGRA30_CLK_PLL_D2_OUT0 },
603 { .con_id = "pll_a", .dt_id = TEGRA30_CLK_PLL_A },
604 { .con_id = "pll_a_out0", .dt_id = TEGRA30_CLK_PLL_A_OUT0 },
605 { .con_id = "pll_e", .dt_id = TEGRA30_CLK_PLL_E },
606 { .con_id = "spdif_in_sync", .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC },
607 { .con_id = "i2s0_sync", .dt_id = TEGRA30_CLK_I2S0_SYNC },
608 { .con_id = "i2s1_sync", .dt_id = TEGRA30_CLK_I2S1_SYNC },
609 { .con_id = "i2s2_sync", .dt_id = TEGRA30_CLK_I2S2_SYNC },
610 { .con_id = "i2s3_sync", .dt_id = TEGRA30_CLK_I2S3_SYNC },
611 { .con_id = "i2s4_sync", .dt_id = TEGRA30_CLK_I2S4_SYNC },
612 { .con_id = "vimclk_sync", .dt_id = TEGRA30_CLK_VIMCLK_SYNC },
613 { .con_id = "audio0", .dt_id = TEGRA30_CLK_AUDIO0 },
614 { .con_id = "audio1", .dt_id = TEGRA30_CLK_AUDIO1 },
615 { .con_id = "audio2", .dt_id = TEGRA30_CLK_AUDIO2 },
616 { .con_id = "audio3", .dt_id = TEGRA30_CLK_AUDIO3 },
617 { .con_id = "audio4", .dt_id = TEGRA30_CLK_AUDIO4 },
618 { .con_id = "spdif", .dt_id = TEGRA30_CLK_SPDIF },
619 { .con_id = "audio0_2x", .dt_id = TEGRA30_CLK_AUDIO0_2X },
620 { .con_id = "audio1_2x", .dt_id = TEGRA30_CLK_AUDIO1_2X },
621 { .con_id = "audio2_2x", .dt_id = TEGRA30_CLK_AUDIO2_2X },
622 { .con_id = "audio3_2x", .dt_id = TEGRA30_CLK_AUDIO3_2X },
623 { .con_id = "audio4_2x", .dt_id = TEGRA30_CLK_AUDIO4_2X },
624 { .con_id = "spdif_2x", .dt_id = TEGRA30_CLK_SPDIF_2X },
625 { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA30_CLK_EXTERN1 },
626 { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA30_CLK_EXTERN2 },
627 { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA30_CLK_EXTERN3 },
628 { .con_id = "blink", .dt_id = TEGRA30_CLK_BLINK },
629 { .con_id = "cclk_g", .dt_id = TEGRA30_CLK_CCLK_G },
630 { .con_id = "cclk_lp", .dt_id = TEGRA30_CLK_CCLK_LP },
631 { .con_id = "sclk", .dt_id = TEGRA30_CLK_SCLK },
632 { .con_id = "hclk", .dt_id = TEGRA30_CLK_HCLK },
633 { .con_id = "pclk", .dt_id = TEGRA30_CLK_PCLK },
634 { .con_id = "twd", .dt_id = TEGRA30_CLK_TWD },
635 { .con_id = "emc", .dt_id = TEGRA30_CLK_EMC },
636 { .con_id = "clk_32k", .dt_id = TEGRA30_CLK_CLK_32K },
637 { .con_id = "clk_m_div2", .dt_id = TEGRA30_CLK_CLK_M_DIV2 },
638 { .con_id = "clk_m_div4", .dt_id = TEGRA30_CLK_CLK_M_DIV4 },
639 { .con_id = "cml0", .dt_id = TEGRA30_CLK_CML0 },
640 { .con_id = "cml1", .dt_id = TEGRA30_CLK_CML1 },
641 { .con_id = "clk_m", .dt_id = TEGRA30_CLK_CLK_M },
642 { .con_id = "pll_ref", .dt_id = TEGRA30_CLK_PLL_REF },
643 { .con_id = "csus", .dev_id = "tengra_camera", .dt_id = TEGRA30_CLK_CSUS },
644 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_VCP },
645 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_BSEA },
646 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA30_CLK_BSEV },
647 { .con_id = "dsia", .dev_id = "tegradc.0", .dt_id = TEGRA30_CLK_DSIA },
648 { .con_id = "csi", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_CSI },
649 { .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_ISP },
650 { .con_id = "pcie", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIE },
651 { .con_id = "afi", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_AFI },
652 { .con_id = "pciex", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIEX },
653 { .con_id = "fuse", .dt_id = TEGRA30_CLK_FUSE },
654 { .con_id = "fuse_burn", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE_BURN },
655 { .con_id = "apbif", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_APBIF },
656 { .con_id = "hda2hdmi", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2HDMI },
657 { .dev_id = "tegra-apbdma", .dt_id = TEGRA30_CLK_APBDMA },
658 { .dev_id = "rtc-tegra", .dt_id = TEGRA30_CLK_RTC },
659 { .dev_id = "timer", .dt_id = TEGRA30_CLK_TIMER },
660 { .dev_id = "tegra-kbc", .dt_id = TEGRA30_CLK_KBC },
661 { .dev_id = "fsl-tegra-udc", .dt_id = TEGRA30_CLK_USBD },
662 { .dev_id = "tegra-ehci.1", .dt_id = TEGRA30_CLK_USB2 },
663 { .dev_id = "tegra-ehci.2", .dt_id = TEGRA30_CLK_USB2 },
664 { .dev_id = "kfuse-tegra", .dt_id = TEGRA30_CLK_KFUSE },
665 { .dev_id = "tegra_sata_cold", .dt_id = TEGRA30_CLK_SATA_COLD },
666 { .dev_id = "dtv", .dt_id = TEGRA30_CLK_DTV },
667 { .dev_id = "tegra30-i2s.0", .dt_id = TEGRA30_CLK_I2S0 },
668 { .dev_id = "tegra30-i2s.1", .dt_id = TEGRA30_CLK_I2S1 },
669 { .dev_id = "tegra30-i2s.2", .dt_id = TEGRA30_CLK_I2S2 },
670 { .dev_id = "tegra30-i2s.3", .dt_id = TEGRA30_CLK_I2S3 },
671 { .dev_id = "tegra30-i2s.4", .dt_id = TEGRA30_CLK_I2S4 },
672 { .con_id = "spdif_out", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_OUT },
673 { .con_id = "spdif_in", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_IN },
674 { .con_id = "d_audio", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_D_AUDIO },
675 { .dev_id = "tegra30-dam.0", .dt_id = TEGRA30_CLK_DAM0 },
676 { .dev_id = "tegra30-dam.1", .dt_id = TEGRA30_CLK_DAM1 },
677 { .dev_id = "tegra30-dam.2", .dt_id = TEGRA30_CLK_DAM2 },
678 { .con_id = "hda", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA },
679 { .con_id = "hda2codec", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2CODEC_2X },
680 { .dev_id = "spi_tegra.0", .dt_id = TEGRA30_CLK_SBC1 },
681 { .dev_id = "spi_tegra.1", .dt_id = TEGRA30_CLK_SBC2 },
682 { .dev_id = "spi_tegra.2", .dt_id = TEGRA30_CLK_SBC3 },
683 { .dev_id = "spi_tegra.3", .dt_id = TEGRA30_CLK_SBC4 },
684 { .dev_id = "spi_tegra.4", .dt_id = TEGRA30_CLK_SBC5 },
685 { .dev_id = "spi_tegra.5", .dt_id = TEGRA30_CLK_SBC6 },
686 { .dev_id = "tegra_sata_oob", .dt_id = TEGRA30_CLK_SATA_OOB },
687 { .dev_id = "tegra_sata", .dt_id = TEGRA30_CLK_SATA },
688 { .dev_id = "tegra_nand", .dt_id = TEGRA30_CLK_NDFLASH },
689 { .dev_id = "tegra_nand_speed", .dt_id = TEGRA30_CLK_NDSPEED },
690 { .dev_id = "vfir", .dt_id = TEGRA30_CLK_VFIR },
691 { .dev_id = "csite", .dt_id = TEGRA30_CLK_CSITE },
692 { .dev_id = "la", .dt_id = TEGRA30_CLK_LA },
693 { .dev_id = "tegra_w1", .dt_id = TEGRA30_CLK_OWR },
694 { .dev_id = "mipi", .dt_id = TEGRA30_CLK_MIPI },
695 { .dev_id = "tegra-tsensor", .dt_id = TEGRA30_CLK_TSENSOR },
696 { .dev_id = "i2cslow", .dt_id = TEGRA30_CLK_I2CSLOW },
697 { .dev_id = "vde", .dt_id = TEGRA30_CLK_VDE },
698 { .con_id = "vi", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_VI },
699 { .dev_id = "epp", .dt_id = TEGRA30_CLK_EPP },
700 { .dev_id = "mpe", .dt_id = TEGRA30_CLK_MPE },
701 { .dev_id = "host1x", .dt_id = TEGRA30_CLK_HOST1X },
702 { .dev_id = "3d", .dt_id = TEGRA30_CLK_GR3D },
703 { .dev_id = "3d2", .dt_id = TEGRA30_CLK_GR3D2 },
704 { .dev_id = "2d", .dt_id = TEGRA30_CLK_GR2D },
705 { .dev_id = "se", .dt_id = TEGRA30_CLK_SE },
706 { .dev_id = "mselect", .dt_id = TEGRA30_CLK_MSELECT },
707 { .dev_id = "tegra-nor", .dt_id = TEGRA30_CLK_NOR },
708 { .dev_id = "sdhci-tegra.0", .dt_id = TEGRA30_CLK_SDMMC1 },
709 { .dev_id = "sdhci-tegra.1", .dt_id = TEGRA30_CLK_SDMMC2 },
710 { .dev_id = "sdhci-tegra.2", .dt_id = TEGRA30_CLK_SDMMC3 },
711 { .dev_id = "sdhci-tegra.3", .dt_id = TEGRA30_CLK_SDMMC4 },
712 { .dev_id = "cve", .dt_id = TEGRA30_CLK_CVE },
713 { .dev_id = "tvo", .dt_id = TEGRA30_CLK_TVO },
714 { .dev_id = "tvdac", .dt_id = TEGRA30_CLK_TVDAC },
715 { .dev_id = "actmon", .dt_id = TEGRA30_CLK_ACTMON },
716 { .con_id = "vi_sensor", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_VI_SENSOR },
717 { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA30_CLK_I2C1 },
718 { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA30_CLK_I2C2 },
719 { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA30_CLK_I2C3 },
720 { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA30_CLK_I2C4 },
721 { .con_id = "div-clk", .dev_id = "tegra-i2c.4", .dt_id = TEGRA30_CLK_I2C5 },
722 { .dev_id = "tegra_uart.0", .dt_id = TEGRA30_CLK_UARTA },
723 { .dev_id = "tegra_uart.1", .dt_id = TEGRA30_CLK_UARTB },
724 { .dev_id = "tegra_uart.2", .dt_id = TEGRA30_CLK_UARTC },
725 { .dev_id = "tegra_uart.3", .dt_id = TEGRA30_CLK_UARTD },
726 { .dev_id = "tegra_uart.4", .dt_id = TEGRA30_CLK_UARTE },
727 { .dev_id = "hdmi", .dt_id = TEGRA30_CLK_HDMI },
728 { .dev_id = "extern1", .dt_id = TEGRA30_CLK_EXTERN1 },
729 { .dev_id = "extern2", .dt_id = TEGRA30_CLK_EXTERN2 },
730 { .dev_id = "extern3", .dt_id = TEGRA30_CLK_EXTERN3 },
731 { .dev_id = "pwm", .dt_id = TEGRA30_CLK_PWM },
732 { .dev_id = "tegradc.0", .dt_id = TEGRA30_CLK_DISP1 },
733 { .dev_id = "tegradc.1", .dt_id = TEGRA30_CLK_DISP2 },
734 { .dev_id = "tegradc.1", .dt_id = TEGRA30_CLK_DSIB },
714}; 735};
715 736
716static struct tegra_clk_periph_regs periph_u_regs = { 737static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
717 .enb_reg = CLK_OUT_ENB_U, 738 [tegra_clk_clk_32k] = { .dt_id = TEGRA30_CLK_CLK_32K, .present = true },
718 .enb_set_reg = CLK_OUT_ENB_SET_U, 739 [tegra_clk_clk_m] = { .dt_id = TEGRA30_CLK_CLK_M, .present = true },
719 .enb_clr_reg = CLK_OUT_ENB_CLR_U, 740 [tegra_clk_clk_m_div2] = { .dt_id = TEGRA30_CLK_CLK_M_DIV2, .present = true },
720 .rst_reg = RST_DEVICES_U, 741 [tegra_clk_clk_m_div4] = { .dt_id = TEGRA30_CLK_CLK_M_DIV4, .present = true },
721 .rst_set_reg = RST_DEVICES_SET_U, 742 [tegra_clk_pll_ref] = { .dt_id = TEGRA30_CLK_PLL_REF, .present = true },
722 .rst_clr_reg = RST_DEVICES_CLR_U, 743 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC, .present = true },
723}; 744 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA30_CLK_I2S0_SYNC, .present = true },
745 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA30_CLK_I2S1_SYNC, .present = true },
746 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA30_CLK_I2S2_SYNC, .present = true },
747 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA30_CLK_I2S3_SYNC, .present = true },
748 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA30_CLK_I2S4_SYNC, .present = true },
749 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA30_CLK_VIMCLK_SYNC, .present = true },
750 [tegra_clk_audio0] = { .dt_id = TEGRA30_CLK_AUDIO0, .present = true },
751 [tegra_clk_audio1] = { .dt_id = TEGRA30_CLK_AUDIO1, .present = true },
752 [tegra_clk_audio2] = { .dt_id = TEGRA30_CLK_AUDIO2, .present = true },
753 [tegra_clk_audio3] = { .dt_id = TEGRA30_CLK_AUDIO3, .present = true },
754 [tegra_clk_audio4] = { .dt_id = TEGRA30_CLK_AUDIO4, .present = true },
755 [tegra_clk_spdif] = { .dt_id = TEGRA30_CLK_SPDIF, .present = true },
756 [tegra_clk_audio0_mux] = { .dt_id = TEGRA30_CLK_AUDIO0_MUX, .present = true },
757 [tegra_clk_audio1_mux] = { .dt_id = TEGRA30_CLK_AUDIO1_MUX, .present = true },
758 [tegra_clk_audio2_mux] = { .dt_id = TEGRA30_CLK_AUDIO2_MUX, .present = true },
759 [tegra_clk_audio3_mux] = { .dt_id = TEGRA30_CLK_AUDIO3_MUX, .present = true },
760 [tegra_clk_audio4_mux] = { .dt_id = TEGRA30_CLK_AUDIO4_MUX, .present = true },
761 [tegra_clk_spdif_mux] = { .dt_id = TEGRA30_CLK_SPDIF_MUX, .present = true },
762 [tegra_clk_audio0_2x] = { .dt_id = TEGRA30_CLK_AUDIO0_2X, .present = true },
763 [tegra_clk_audio1_2x] = { .dt_id = TEGRA30_CLK_AUDIO1_2X, .present = true },
764 [tegra_clk_audio2_2x] = { .dt_id = TEGRA30_CLK_AUDIO2_2X, .present = true },
765 [tegra_clk_audio3_2x] = { .dt_id = TEGRA30_CLK_AUDIO3_2X, .present = true },
766 [tegra_clk_audio4_2x] = { .dt_id = TEGRA30_CLK_AUDIO4_2X, .present = true },
767 [tegra_clk_spdif_2x] = { .dt_id = TEGRA30_CLK_SPDIF_2X, .present = true },
768 [tegra_clk_clk_out_1] = { .dt_id = TEGRA30_CLK_CLK_OUT_1, .present = true },
769 [tegra_clk_clk_out_2] = { .dt_id = TEGRA30_CLK_CLK_OUT_2, .present = true },
770 [tegra_clk_clk_out_3] = { .dt_id = TEGRA30_CLK_CLK_OUT_3, .present = true },
771 [tegra_clk_blink] = { .dt_id = TEGRA30_CLK_BLINK, .present = true },
772 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_1_MUX, .present = true },
773 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_2_MUX, .present = true },
774 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_3_MUX, .present = true },
775 [tegra_clk_hclk] = { .dt_id = TEGRA30_CLK_HCLK, .present = true },
776 [tegra_clk_pclk] = { .dt_id = TEGRA30_CLK_PCLK, .present = true },
777 [tegra_clk_i2s0] = { .dt_id = TEGRA30_CLK_I2S0, .present = true },
778 [tegra_clk_i2s1] = { .dt_id = TEGRA30_CLK_I2S1, .present = true },
779 [tegra_clk_i2s2] = { .dt_id = TEGRA30_CLK_I2S2, .present = true },
780 [tegra_clk_i2s3] = { .dt_id = TEGRA30_CLK_I2S3, .present = true },
781 [tegra_clk_i2s4] = { .dt_id = TEGRA30_CLK_I2S4, .present = true },
782 [tegra_clk_spdif_in] = { .dt_id = TEGRA30_CLK_SPDIF_IN, .present = true },
783 [tegra_clk_hda] = { .dt_id = TEGRA30_CLK_HDA, .present = true },
784 [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA30_CLK_HDA2CODEC_2X, .present = true },
785 [tegra_clk_sbc1] = { .dt_id = TEGRA30_CLK_SBC1, .present = true },
786 [tegra_clk_sbc2] = { .dt_id = TEGRA30_CLK_SBC2, .present = true },
787 [tegra_clk_sbc3] = { .dt_id = TEGRA30_CLK_SBC3, .present = true },
788 [tegra_clk_sbc4] = { .dt_id = TEGRA30_CLK_SBC4, .present = true },
789 [tegra_clk_sbc5] = { .dt_id = TEGRA30_CLK_SBC5, .present = true },
790 [tegra_clk_sbc6] = { .dt_id = TEGRA30_CLK_SBC6, .present = true },
791 [tegra_clk_ndflash] = { .dt_id = TEGRA30_CLK_NDFLASH, .present = true },
792 [tegra_clk_ndspeed] = { .dt_id = TEGRA30_CLK_NDSPEED, .present = true },
793 [tegra_clk_vfir] = { .dt_id = TEGRA30_CLK_VFIR, .present = true },
794 [tegra_clk_la] = { .dt_id = TEGRA30_CLK_LA, .present = true },
795 [tegra_clk_csite] = { .dt_id = TEGRA30_CLK_CSITE, .present = true },
796 [tegra_clk_owr] = { .dt_id = TEGRA30_CLK_OWR, .present = true },
797 [tegra_clk_mipi] = { .dt_id = TEGRA30_CLK_MIPI, .present = true },
798 [tegra_clk_tsensor] = { .dt_id = TEGRA30_CLK_TSENSOR, .present = true },
799 [tegra_clk_i2cslow] = { .dt_id = TEGRA30_CLK_I2CSLOW, .present = true },
800 [tegra_clk_vde] = { .dt_id = TEGRA30_CLK_VDE, .present = true },
801 [tegra_clk_vi] = { .dt_id = TEGRA30_CLK_VI, .present = true },
802 [tegra_clk_epp] = { .dt_id = TEGRA30_CLK_EPP, .present = true },
803 [tegra_clk_mpe] = { .dt_id = TEGRA30_CLK_MPE, .present = true },
804 [tegra_clk_host1x] = { .dt_id = TEGRA30_CLK_HOST1X, .present = true },
805 [tegra_clk_gr2d] = { .dt_id = TEGRA30_CLK_GR2D, .present = true },
806 [tegra_clk_gr3d] = { .dt_id = TEGRA30_CLK_GR3D, .present = true },
807 [tegra_clk_mselect] = { .dt_id = TEGRA30_CLK_MSELECT, .present = true },
808 [tegra_clk_nor] = { .dt_id = TEGRA30_CLK_NOR, .present = true },
809 [tegra_clk_sdmmc1] = { .dt_id = TEGRA30_CLK_SDMMC1, .present = true },
810 [tegra_clk_sdmmc2] = { .dt_id = TEGRA30_CLK_SDMMC2, .present = true },
811 [tegra_clk_sdmmc3] = { .dt_id = TEGRA30_CLK_SDMMC3, .present = true },
812 [tegra_clk_sdmmc4] = { .dt_id = TEGRA30_CLK_SDMMC4, .present = true },
813 [tegra_clk_cve] = { .dt_id = TEGRA30_CLK_CVE, .present = true },
814 [tegra_clk_tvo] = { .dt_id = TEGRA30_CLK_TVO, .present = true },
815 [tegra_clk_tvdac] = { .dt_id = TEGRA30_CLK_TVDAC, .present = true },
816 [tegra_clk_actmon] = { .dt_id = TEGRA30_CLK_ACTMON, .present = true },
817 [tegra_clk_vi_sensor] = { .dt_id = TEGRA30_CLK_VI_SENSOR, .present = true },
818 [tegra_clk_i2c1] = { .dt_id = TEGRA30_CLK_I2C1, .present = true },
819 [tegra_clk_i2c2] = { .dt_id = TEGRA30_CLK_I2C2, .present = true },
820 [tegra_clk_i2c3] = { .dt_id = TEGRA30_CLK_I2C3, .present = true },
821 [tegra_clk_i2c4] = { .dt_id = TEGRA30_CLK_I2C4, .present = true },
822 [tegra_clk_i2c5] = { .dt_id = TEGRA30_CLK_I2C5, .present = true },
823 [tegra_clk_uarta] = { .dt_id = TEGRA30_CLK_UARTA, .present = true },
824 [tegra_clk_uartb] = { .dt_id = TEGRA30_CLK_UARTB, .present = true },
825 [tegra_clk_uartc] = { .dt_id = TEGRA30_CLK_UARTC, .present = true },
826 [tegra_clk_uartd] = { .dt_id = TEGRA30_CLK_UARTD, .present = true },
827 [tegra_clk_uarte] = { .dt_id = TEGRA30_CLK_UARTE, .present = true },
828 [tegra_clk_extern1] = { .dt_id = TEGRA30_CLK_EXTERN1, .present = true },
829 [tegra_clk_extern2] = { .dt_id = TEGRA30_CLK_EXTERN2, .present = true },
830 [tegra_clk_extern3] = { .dt_id = TEGRA30_CLK_EXTERN3, .present = true },
831 [tegra_clk_disp1] = { .dt_id = TEGRA30_CLK_DISP1, .present = true },
832 [tegra_clk_disp2] = { .dt_id = TEGRA30_CLK_DISP2, .present = true },
833 [tegra_clk_apbdma] = { .dt_id = TEGRA30_CLK_APBDMA, .present = true },
834 [tegra_clk_rtc] = { .dt_id = TEGRA30_CLK_RTC, .present = true },
835 [tegra_clk_timer] = { .dt_id = TEGRA30_CLK_TIMER, .present = true },
836 [tegra_clk_kbc] = { .dt_id = TEGRA30_CLK_KBC, .present = true },
837 [tegra_clk_csus] = { .dt_id = TEGRA30_CLK_CSUS, .present = true },
838 [tegra_clk_vcp] = { .dt_id = TEGRA30_CLK_VCP, .present = true },
839 [tegra_clk_bsea] = { .dt_id = TEGRA30_CLK_BSEA, .present = true },
840 [tegra_clk_bsev] = { .dt_id = TEGRA30_CLK_BSEV, .present = true },
841 [tegra_clk_usbd] = { .dt_id = TEGRA30_CLK_USBD, .present = true },
842 [tegra_clk_usb2] = { .dt_id = TEGRA30_CLK_USB2, .present = true },
843 [tegra_clk_usb3] = { .dt_id = TEGRA30_CLK_USB3, .present = true },
844 [tegra_clk_csi] = { .dt_id = TEGRA30_CLK_CSI, .present = true },
845 [tegra_clk_isp] = { .dt_id = TEGRA30_CLK_ISP, .present = true },
846 [tegra_clk_kfuse] = { .dt_id = TEGRA30_CLK_KFUSE, .present = true },
847 [tegra_clk_fuse] = { .dt_id = TEGRA30_CLK_FUSE, .present = true },
848 [tegra_clk_fuse_burn] = { .dt_id = TEGRA30_CLK_FUSE_BURN, .present = true },
849 [tegra_clk_apbif] = { .dt_id = TEGRA30_CLK_APBIF, .present = true },
850 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA30_CLK_HDA2HDMI, .present = true },
851 [tegra_clk_sata_cold] = { .dt_id = TEGRA30_CLK_SATA_COLD, .present = true },
852 [tegra_clk_sata_oob] = { .dt_id = TEGRA30_CLK_SATA_OOB, .present = true },
853 [tegra_clk_sata] = { .dt_id = TEGRA30_CLK_SATA, .present = true },
854 [tegra_clk_dtv] = { .dt_id = TEGRA30_CLK_DTV, .present = true },
855 [tegra_clk_pll_p] = { .dt_id = TEGRA30_CLK_PLL_P, .present = true },
856 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA30_CLK_PLL_P_OUT1, .present = true },
857 [tegra_clk_pll_p_out2] = { .dt_id = TEGRA30_CLK_PLL_P_OUT2, .present = true },
858 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA30_CLK_PLL_P_OUT3, .present = true },
859 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA30_CLK_PLL_P_OUT4, .present = true },
860 [tegra_clk_pll_a] = { .dt_id = TEGRA30_CLK_PLL_A, .present = true },
861 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA30_CLK_PLL_A_OUT0, .present = true },
724 862
725static struct tegra_clk_periph_regs periph_v_regs = {
726 .enb_reg = CLK_OUT_ENB_V,
727 .enb_set_reg = CLK_OUT_ENB_SET_V,
728 .enb_clr_reg = CLK_OUT_ENB_CLR_V,
729 .rst_reg = RST_DEVICES_V,
730 .rst_set_reg = RST_DEVICES_SET_V,
731 .rst_clr_reg = RST_DEVICES_CLR_V,
732}; 863};
733 864
734static struct tegra_clk_periph_regs periph_w_regs = {
735 .enb_reg = CLK_OUT_ENB_W,
736 .enb_set_reg = CLK_OUT_ENB_SET_W,
737 .enb_clr_reg = CLK_OUT_ENB_CLR_W,
738 .rst_reg = RST_DEVICES_W,
739 .rst_set_reg = RST_DEVICES_SET_W,
740 .rst_clr_reg = RST_DEVICES_CLR_W,
741};
742
743static void tegra30_clk_measure_input_freq(void)
744{
745 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL);
746 u32 auto_clk_control = osc_ctrl & OSC_CTRL_OSC_FREQ_MASK;
747 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
748
749 switch (auto_clk_control) {
750 case OSC_CTRL_OSC_FREQ_12MHZ:
751 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
752 input_freq = 12000000;
753 break;
754 case OSC_CTRL_OSC_FREQ_13MHZ:
755 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
756 input_freq = 13000000;
757 break;
758 case OSC_CTRL_OSC_FREQ_19_2MHZ:
759 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
760 input_freq = 19200000;
761 break;
762 case OSC_CTRL_OSC_FREQ_26MHZ:
763 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
764 input_freq = 26000000;
765 break;
766 case OSC_CTRL_OSC_FREQ_16_8MHZ:
767 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
768 input_freq = 16800000;
769 break;
770 case OSC_CTRL_OSC_FREQ_38_4MHZ:
771 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_2);
772 input_freq = 38400000;
773 break;
774 case OSC_CTRL_OSC_FREQ_48MHZ:
775 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4);
776 input_freq = 48000000;
777 break;
778 default:
779 pr_err("Unexpected auto clock control value %d",
780 auto_clk_control);
781 BUG();
782 return;
783 }
784}
785
786static unsigned int tegra30_get_pll_ref_div(void)
787{
788 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) &
789 OSC_CTRL_PLL_REF_DIV_MASK;
790
791 switch (pll_ref_div) {
792 case OSC_CTRL_PLL_REF_DIV_1:
793 return 1;
794 case OSC_CTRL_PLL_REF_DIV_2:
795 return 2;
796 case OSC_CTRL_PLL_REF_DIV_4:
797 return 4;
798 default:
799 pr_err("Invalid pll ref divider %d", pll_ref_div);
800 BUG();
801 }
802 return 0;
803}
804
805static void tegra30_utmi_param_configure(void) 865static void tegra30_utmi_param_configure(void)
806{ 866{
807 u32 reg; 867 u32 reg;
@@ -863,11 +923,8 @@ static void __init tegra30_pll_init(void)
863 923
864 /* PLLC */ 924 /* PLLC */
865 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0, 925 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0,
866 0, &pll_c_params, 926 &pll_c_params, NULL);
867 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK, 927 clks[TEGRA30_CLK_PLL_C] = clk;
868 pll_c_freq_table, NULL);
869 clk_register_clkdev(clk, "pll_c", NULL);
870 clks[pll_c] = clk;
871 928
872 /* PLLC_OUT1 */ 929 /* PLLC_OUT1 */
873 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", 930 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
@@ -876,73 +933,13 @@ static void __init tegra30_pll_init(void)
876 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", 933 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
877 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, 934 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,
878 0, NULL); 935 0, NULL);
879 clk_register_clkdev(clk, "pll_c_out1", NULL); 936 clks[TEGRA30_CLK_PLL_C_OUT1] = clk;
880 clks[pll_c_out1] = clk;
881
882 /* PLLP */
883 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, pmc_base, 0,
884 408000000, &pll_p_params,
885 TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON |
886 TEGRA_PLL_USE_LOCK, pll_p_freq_table, NULL);
887 clk_register_clkdev(clk, "pll_p", NULL);
888 clks[pll_p] = clk;
889
890 /* PLLP_OUT1 */
891 clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p",
892 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
893 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1,
894 &pll_div_lock);
895 clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div",
896 clk_base + PLLP_OUTA, 1, 0,
897 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
898 &pll_div_lock);
899 clk_register_clkdev(clk, "pll_p_out1", NULL);
900 clks[pll_p_out1] = clk;
901
902 /* PLLP_OUT2 */
903 clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p",
904 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
905 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
906 &pll_div_lock);
907 clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div",
908 clk_base + PLLP_OUTA, 17, 16,
909 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
910 &pll_div_lock);
911 clk_register_clkdev(clk, "pll_p_out2", NULL);
912 clks[pll_p_out2] = clk;
913
914 /* PLLP_OUT3 */
915 clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p",
916 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED |
917 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1,
918 &pll_div_lock);
919 clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div",
920 clk_base + PLLP_OUTB, 1, 0,
921 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
922 &pll_div_lock);
923 clk_register_clkdev(clk, "pll_p_out3", NULL);
924 clks[pll_p_out3] = clk;
925
926 /* PLLP_OUT4 */
927 clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p",
928 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED |
929 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
930 &pll_div_lock);
931 clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div",
932 clk_base + PLLP_OUTB, 17, 16,
933 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
934 &pll_div_lock);
935 clk_register_clkdev(clk, "pll_p_out4", NULL);
936 clks[pll_p_out4] = clk;
937 937
938 /* PLLM */ 938 /* PLLM */
939 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base, 939 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base,
940 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 0, 940 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
941 &pll_m_params, TEGRA_PLLM | TEGRA_PLL_HAS_CPCON | 941 &pll_m_params, NULL);
942 TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK, 942 clks[TEGRA30_CLK_PLL_M] = clk;
943 pll_m_freq_table, NULL);
944 clk_register_clkdev(clk, "pll_m", NULL);
945 clks[pll_m] = clk;
946 943
947 /* PLLM_OUT1 */ 944 /* PLLM_OUT1 */
948 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", 945 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
@@ -951,78 +948,44 @@ static void __init tegra30_pll_init(void)
951 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", 948 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
952 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | 949 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
953 CLK_SET_RATE_PARENT, 0, NULL); 950 CLK_SET_RATE_PARENT, 0, NULL);
954 clk_register_clkdev(clk, "pll_m_out1", NULL); 951 clks[TEGRA30_CLK_PLL_M_OUT1] = clk;
955 clks[pll_m_out1] = clk;
956 952
957 /* PLLX */ 953 /* PLLX */
958 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0, 954 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0,
959 0, &pll_x_params, TEGRA_PLL_HAS_CPCON | 955 &pll_x_params, NULL);
960 TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK, 956 clks[TEGRA30_CLK_PLL_X] = clk;
961 pll_x_freq_table, NULL);
962 clk_register_clkdev(clk, "pll_x", NULL);
963 clks[pll_x] = clk;
964 957
965 /* PLLX_OUT0 */ 958 /* PLLX_OUT0 */
966 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x", 959 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
967 CLK_SET_RATE_PARENT, 1, 2); 960 CLK_SET_RATE_PARENT, 1, 2);
968 clk_register_clkdev(clk, "pll_x_out0", NULL); 961 clks[TEGRA30_CLK_PLL_X_OUT0] = clk;
969 clks[pll_x_out0] = clk;
970 962
971 /* PLLU */ 963 /* PLLU */
972 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc_base, 0, 964 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc_base, 0,
973 0, &pll_u_params, TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | 965 &pll_u_params, NULL);
974 TEGRA_PLL_SET_LFCON, 966 clks[TEGRA30_CLK_PLL_U] = clk;
975 pll_u_freq_table,
976 NULL);
977 clk_register_clkdev(clk, "pll_u", NULL);
978 clks[pll_u] = clk;
979 967
980 tegra30_utmi_param_configure(); 968 tegra30_utmi_param_configure();
981 969
982 /* PLLD */ 970 /* PLLD */
983 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0, 971 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0,
984 0, &pll_d_params, TEGRA_PLL_HAS_CPCON | 972 &pll_d_params, &pll_d_lock);
985 TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK, 973 clks[TEGRA30_CLK_PLL_D] = clk;
986 pll_d_freq_table, &pll_d_lock);
987 clk_register_clkdev(clk, "pll_d", NULL);
988 clks[pll_d] = clk;
989 974
990 /* PLLD_OUT0 */ 975 /* PLLD_OUT0 */
991 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", 976 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
992 CLK_SET_RATE_PARENT, 1, 2); 977 CLK_SET_RATE_PARENT, 1, 2);
993 clk_register_clkdev(clk, "pll_d_out0", NULL); 978 clks[TEGRA30_CLK_PLL_D_OUT0] = clk;
994 clks[pll_d_out0] = clk;
995 979
996 /* PLLD2 */ 980 /* PLLD2 */
997 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0, 981 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0,
998 0, &pll_d2_params, TEGRA_PLL_HAS_CPCON | 982 &pll_d2_params, NULL);
999 TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK, 983 clks[TEGRA30_CLK_PLL_D2] = clk;
1000 pll_d_freq_table, NULL);
1001 clk_register_clkdev(clk, "pll_d2", NULL);
1002 clks[pll_d2] = clk;
1003 984
1004 /* PLLD2_OUT0 */ 985 /* PLLD2_OUT0 */
1005 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2", 986 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
1006 CLK_SET_RATE_PARENT, 1, 2); 987 CLK_SET_RATE_PARENT, 1, 2);
1007 clk_register_clkdev(clk, "pll_d2_out0", NULL); 988 clks[TEGRA30_CLK_PLL_D2_OUT0] = clk;
1008 clks[pll_d2_out0] = clk;
1009
1010 /* PLLA */
1011 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, pmc_base,
1012 0, 0, &pll_a_params, TEGRA_PLL_HAS_CPCON |
1013 TEGRA_PLL_USE_LOCK, pll_a_freq_table, NULL);
1014 clk_register_clkdev(clk, "pll_a", NULL);
1015 clks[pll_a] = clk;
1016
1017 /* PLLA_OUT0 */
1018 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
1019 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1020 8, 8, 1, NULL);
1021 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
1022 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
1023 CLK_SET_RATE_PARENT, 0, NULL);
1024 clk_register_clkdev(clk, "pll_a_out0", NULL);
1025 clks[pll_a_out0] = clk;
1026 989
1027 /* PLLE */ 990 /* PLLE */
1028 clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents, 991 clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents,
@@ -1030,258 +993,8 @@ static void __init tegra30_pll_init(void)
1030 CLK_SET_RATE_NO_REPARENT, 993 CLK_SET_RATE_NO_REPARENT,
1031 clk_base + PLLE_AUX, 2, 1, 0, NULL); 994 clk_base + PLLE_AUX, 2, 1, 0, NULL);
1032 clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base, 995 clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base,
1033 CLK_GET_RATE_NOCACHE, 100000000, &pll_e_params, 996 CLK_GET_RATE_NOCACHE, &pll_e_params, NULL);
1034 TEGRA_PLLE_CONFIGURE, pll_e_freq_table, NULL); 997 clks[TEGRA30_CLK_PLL_E] = clk;
1035 clk_register_clkdev(clk, "pll_e", NULL);
1036 clks[pll_e] = clk;
1037}
1038
1039static const char *mux_audio_sync_clk[] = { "spdif_in_sync", "i2s0_sync",
1040 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",};
1041static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
1042 "clk_m_div4", "extern1", };
1043static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
1044 "clk_m_div4", "extern2", };
1045static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
1046 "clk_m_div4", "extern3", };
1047
1048static void __init tegra30_audio_clk_init(void)
1049{
1050 struct clk *clk;
1051
1052 /* spdif_in_sync */
1053 clk = tegra_clk_register_sync_source("spdif_in_sync", 24000000,
1054 24000000);
1055 clk_register_clkdev(clk, "spdif_in_sync", NULL);
1056 clks[spdif_in_sync] = clk;
1057
1058 /* i2s0_sync */
1059 clk = tegra_clk_register_sync_source("i2s0_sync", 24000000, 24000000);
1060 clk_register_clkdev(clk, "i2s0_sync", NULL);
1061 clks[i2s0_sync] = clk;
1062
1063 /* i2s1_sync */
1064 clk = tegra_clk_register_sync_source("i2s1_sync", 24000000, 24000000);
1065 clk_register_clkdev(clk, "i2s1_sync", NULL);
1066 clks[i2s1_sync] = clk;
1067
1068 /* i2s2_sync */
1069 clk = tegra_clk_register_sync_source("i2s2_sync", 24000000, 24000000);
1070 clk_register_clkdev(clk, "i2s2_sync", NULL);
1071 clks[i2s2_sync] = clk;
1072
1073 /* i2s3_sync */
1074 clk = tegra_clk_register_sync_source("i2s3_sync", 24000000, 24000000);
1075 clk_register_clkdev(clk, "i2s3_sync", NULL);
1076 clks[i2s3_sync] = clk;
1077
1078 /* i2s4_sync */
1079 clk = tegra_clk_register_sync_source("i2s4_sync", 24000000, 24000000);
1080 clk_register_clkdev(clk, "i2s4_sync", NULL);
1081 clks[i2s4_sync] = clk;
1082
1083 /* vimclk_sync */
1084 clk = tegra_clk_register_sync_source("vimclk_sync", 24000000, 24000000);
1085 clk_register_clkdev(clk, "vimclk_sync", NULL);
1086 clks[vimclk_sync] = clk;
1087
1088 /* audio0 */
1089 clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk,
1090 ARRAY_SIZE(mux_audio_sync_clk),
1091 CLK_SET_RATE_NO_REPARENT,
1092 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0, NULL);
1093 clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0,
1094 clk_base + AUDIO_SYNC_CLK_I2S0, 4,
1095 CLK_GATE_SET_TO_DISABLE, NULL);
1096 clk_register_clkdev(clk, "audio0", NULL);
1097 clks[audio0] = clk;
1098
1099 /* audio1 */
1100 clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk,
1101 ARRAY_SIZE(mux_audio_sync_clk),
1102 CLK_SET_RATE_NO_REPARENT,
1103 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0, NULL);
1104 clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0,
1105 clk_base + AUDIO_SYNC_CLK_I2S1, 4,
1106 CLK_GATE_SET_TO_DISABLE, NULL);
1107 clk_register_clkdev(clk, "audio1", NULL);
1108 clks[audio1] = clk;
1109
1110 /* audio2 */
1111 clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk,
1112 ARRAY_SIZE(mux_audio_sync_clk),
1113 CLK_SET_RATE_NO_REPARENT,
1114 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0, NULL);
1115 clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0,
1116 clk_base + AUDIO_SYNC_CLK_I2S2, 4,
1117 CLK_GATE_SET_TO_DISABLE, NULL);
1118 clk_register_clkdev(clk, "audio2", NULL);
1119 clks[audio2] = clk;
1120
1121 /* audio3 */
1122 clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk,
1123 ARRAY_SIZE(mux_audio_sync_clk),
1124 CLK_SET_RATE_NO_REPARENT,
1125 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0, NULL);
1126 clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0,
1127 clk_base + AUDIO_SYNC_CLK_I2S3, 4,
1128 CLK_GATE_SET_TO_DISABLE, NULL);
1129 clk_register_clkdev(clk, "audio3", NULL);
1130 clks[audio3] = clk;
1131
1132 /* audio4 */
1133 clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk,
1134 ARRAY_SIZE(mux_audio_sync_clk),
1135 CLK_SET_RATE_NO_REPARENT,
1136 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0, NULL);
1137 clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0,
1138 clk_base + AUDIO_SYNC_CLK_I2S4, 4,
1139 CLK_GATE_SET_TO_DISABLE, NULL);
1140 clk_register_clkdev(clk, "audio4", NULL);
1141 clks[audio4] = clk;
1142
1143 /* spdif */
1144 clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk,
1145 ARRAY_SIZE(mux_audio_sync_clk),
1146 CLK_SET_RATE_NO_REPARENT,
1147 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0, NULL);
1148 clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0,
1149 clk_base + AUDIO_SYNC_CLK_SPDIF, 4,
1150 CLK_GATE_SET_TO_DISABLE, NULL);
1151 clk_register_clkdev(clk, "spdif", NULL);
1152 clks[spdif] = clk;
1153
1154 /* audio0_2x */
1155 clk = clk_register_fixed_factor(NULL, "audio0_doubler", "audio0",
1156 CLK_SET_RATE_PARENT, 2, 1);
1157 clk = tegra_clk_register_divider("audio0_div", "audio0_doubler",
1158 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 24, 1, 0,
1159 &clk_doubler_lock);
1160 clk = tegra_clk_register_periph_gate("audio0_2x", "audio0_div",
1161 TEGRA_PERIPH_NO_RESET, clk_base,
1162 CLK_SET_RATE_PARENT, 113, &periph_v_regs,
1163 periph_clk_enb_refcnt);
1164 clk_register_clkdev(clk, "audio0_2x", NULL);
1165 clks[audio0_2x] = clk;
1166
1167 /* audio1_2x */
1168 clk = clk_register_fixed_factor(NULL, "audio1_doubler", "audio1",
1169 CLK_SET_RATE_PARENT, 2, 1);
1170 clk = tegra_clk_register_divider("audio1_div", "audio1_doubler",
1171 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 25, 1, 0,
1172 &clk_doubler_lock);
1173 clk = tegra_clk_register_periph_gate("audio1_2x", "audio1_div",
1174 TEGRA_PERIPH_NO_RESET, clk_base,
1175 CLK_SET_RATE_PARENT, 114, &periph_v_regs,
1176 periph_clk_enb_refcnt);
1177 clk_register_clkdev(clk, "audio1_2x", NULL);
1178 clks[audio1_2x] = clk;
1179
1180 /* audio2_2x */
1181 clk = clk_register_fixed_factor(NULL, "audio2_doubler", "audio2",
1182 CLK_SET_RATE_PARENT, 2, 1);
1183 clk = tegra_clk_register_divider("audio2_div", "audio2_doubler",
1184 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 26, 1, 0,
1185 &clk_doubler_lock);
1186 clk = tegra_clk_register_periph_gate("audio2_2x", "audio2_div",
1187 TEGRA_PERIPH_NO_RESET, clk_base,
1188 CLK_SET_RATE_PARENT, 115, &periph_v_regs,
1189 periph_clk_enb_refcnt);
1190 clk_register_clkdev(clk, "audio2_2x", NULL);
1191 clks[audio2_2x] = clk;
1192
1193 /* audio3_2x */
1194 clk = clk_register_fixed_factor(NULL, "audio3_doubler", "audio3",
1195 CLK_SET_RATE_PARENT, 2, 1);
1196 clk = tegra_clk_register_divider("audio3_div", "audio3_doubler",
1197 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 27, 1, 0,
1198 &clk_doubler_lock);
1199 clk = tegra_clk_register_periph_gate("audio3_2x", "audio3_div",
1200 TEGRA_PERIPH_NO_RESET, clk_base,
1201 CLK_SET_RATE_PARENT, 116, &periph_v_regs,
1202 periph_clk_enb_refcnt);
1203 clk_register_clkdev(clk, "audio3_2x", NULL);
1204 clks[audio3_2x] = clk;
1205
1206 /* audio4_2x */
1207 clk = clk_register_fixed_factor(NULL, "audio4_doubler", "audio4",
1208 CLK_SET_RATE_PARENT, 2, 1);
1209 clk = tegra_clk_register_divider("audio4_div", "audio4_doubler",
1210 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 28, 1, 0,
1211 &clk_doubler_lock);
1212 clk = tegra_clk_register_periph_gate("audio4_2x", "audio4_div",
1213 TEGRA_PERIPH_NO_RESET, clk_base,
1214 CLK_SET_RATE_PARENT, 117, &periph_v_regs,
1215 periph_clk_enb_refcnt);
1216 clk_register_clkdev(clk, "audio4_2x", NULL);
1217 clks[audio4_2x] = clk;
1218
1219 /* spdif_2x */
1220 clk = clk_register_fixed_factor(NULL, "spdif_doubler", "spdif",
1221 CLK_SET_RATE_PARENT, 2, 1);
1222 clk = tegra_clk_register_divider("spdif_div", "spdif_doubler",
1223 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 29, 1, 0,
1224 &clk_doubler_lock);
1225 clk = tegra_clk_register_periph_gate("spdif_2x", "spdif_div",
1226 TEGRA_PERIPH_NO_RESET, clk_base,
1227 CLK_SET_RATE_PARENT, 118, &periph_v_regs,
1228 periph_clk_enb_refcnt);
1229 clk_register_clkdev(clk, "spdif_2x", NULL);
1230 clks[spdif_2x] = clk;
1231}
1232
1233static void __init tegra30_pmc_clk_init(void)
1234{
1235 struct clk *clk;
1236
1237 /* clk_out_1 */
1238 clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents,
1239 ARRAY_SIZE(clk_out1_parents),
1240 CLK_SET_RATE_NO_REPARENT,
1241 pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0,
1242 &clk_out_lock);
1243 clks[clk_out_1_mux] = clk;
1244 clk = clk_register_gate(NULL, "clk_out_1", "clk_out_1_mux", 0,
1245 pmc_base + PMC_CLK_OUT_CNTRL, 2, 0,
1246 &clk_out_lock);
1247 clk_register_clkdev(clk, "extern1", "clk_out_1");
1248 clks[clk_out_1] = clk;
1249
1250 /* clk_out_2 */
1251 clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,
1252 ARRAY_SIZE(clk_out2_parents),
1253 CLK_SET_RATE_NO_REPARENT,
1254 pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,
1255 &clk_out_lock);
1256 clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0,
1257 pmc_base + PMC_CLK_OUT_CNTRL, 10, 0,
1258 &clk_out_lock);
1259 clk_register_clkdev(clk, "extern2", "clk_out_2");
1260 clks[clk_out_2] = clk;
1261
1262 /* clk_out_3 */
1263 clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,
1264 ARRAY_SIZE(clk_out3_parents),
1265 CLK_SET_RATE_NO_REPARENT,
1266 pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,
1267 &clk_out_lock);
1268 clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0,
1269 pmc_base + PMC_CLK_OUT_CNTRL, 18, 0,
1270 &clk_out_lock);
1271 clk_register_clkdev(clk, "extern3", "clk_out_3");
1272 clks[clk_out_3] = clk;
1273
1274 /* blink */
1275 writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
1276 clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
1277 pmc_base + PMC_DPD_PADS_ORIDE,
1278 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
1279 clk = clk_register_gate(NULL, "blink", "blink_override", 0,
1280 pmc_base + PMC_CTRL,
1281 PMC_CTRL_BLINK_ENB, 0, NULL);
1282 clk_register_clkdev(clk, "blink", NULL);
1283 clks[blink] = clk;
1284
1285} 998}
1286 999
1287static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 1000static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
@@ -1332,8 +1045,7 @@ static void __init tegra30_super_clk_init(void)
1332 CLK_SET_RATE_PARENT, 1045 CLK_SET_RATE_PARENT,
1333 clk_base + CCLKG_BURST_POLICY, 1046 clk_base + CCLKG_BURST_POLICY,
1334 0, 4, 0, 0, NULL); 1047 0, 4, 0, 0, NULL);
1335 clk_register_clkdev(clk, "cclk_g", NULL); 1048 clks[TEGRA30_CLK_CCLK_G] = clk;
1336 clks[cclk_g] = clk;
1337 1049
1338 /* 1050 /*
1339 * Clock input to cclk_lp divided from pll_p using 1051 * Clock input to cclk_lp divided from pll_p using
@@ -1369,8 +1081,7 @@ static void __init tegra30_super_clk_init(void)
1369 clk_base + CCLKLP_BURST_POLICY, 1081 clk_base + CCLKLP_BURST_POLICY,
1370 TEGRA_DIVIDER_2, 4, 8, 9, 1082 TEGRA_DIVIDER_2, 4, 8, 9,
1371 NULL); 1083 NULL);
1372 clk_register_clkdev(clk, "cclk_lp", NULL); 1084 clks[TEGRA30_CLK_CCLK_LP] = clk;
1373 clks[cclk_lp] = clk;
1374 1085
1375 /* SCLK */ 1086 /* SCLK */
1376 clk = tegra_clk_register_super_mux("sclk", sclk_parents, 1087 clk = tegra_clk_register_super_mux("sclk", sclk_parents,
@@ -1378,142 +1089,44 @@ static void __init tegra30_super_clk_init(void)
1378 CLK_SET_RATE_PARENT, 1089 CLK_SET_RATE_PARENT,
1379 clk_base + SCLK_BURST_POLICY, 1090 clk_base + SCLK_BURST_POLICY,
1380 0, 4, 0, 0, NULL); 1091 0, 4, 0, 0, NULL);
1381 clk_register_clkdev(clk, "sclk", NULL); 1092 clks[TEGRA30_CLK_SCLK] = clk;
1382 clks[sclk] = clk;
1383
1384 /* HCLK */
1385 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
1386 clk_base + SYSTEM_CLK_RATE, 4, 2, 0,
1387 &sysrate_lock);
1388 clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT,
1389 clk_base + SYSTEM_CLK_RATE, 7,
1390 CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
1391 clk_register_clkdev(clk, "hclk", NULL);
1392 clks[hclk] = clk;
1393
1394 /* PCLK */
1395 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
1396 clk_base + SYSTEM_CLK_RATE, 0, 2, 0,
1397 &sysrate_lock);
1398 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT,
1399 clk_base + SYSTEM_CLK_RATE, 3,
1400 CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
1401 clk_register_clkdev(clk, "pclk", NULL);
1402 clks[pclk] = clk;
1403 1093
1404 /* twd */ 1094 /* twd */
1405 clk = clk_register_fixed_factor(NULL, "twd", "cclk_g", 1095 clk = clk_register_fixed_factor(NULL, "twd", "cclk_g",
1406 CLK_SET_RATE_PARENT, 1, 2); 1096 CLK_SET_RATE_PARENT, 1, 2);
1407 clk_register_clkdev(clk, "twd", NULL); 1097 clks[TEGRA30_CLK_TWD] = clk;
1408 clks[twd] = clk; 1098
1099 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra30_clks, NULL);
1409} 1100}
1410 1101
1411static const char *mux_pllacp_clkm[] = { "pll_a_out0", "unused", "pll_p", 1102static const char *mux_pllacp_clkm[] = { "pll_a_out0", "unused", "pll_p",
1412 "clk_m" }; 1103 "clk_m" };
1413static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" }; 1104static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" };
1414static const char *mux_pllmcp_clkm[] = { "pll_m", "pll_c", "pll_p", "clk_m" }; 1105static const char *mux_pllmcp_clkm[] = { "pll_m", "pll_c", "pll_p", "clk_m" };
1415static const char *i2s0_parents[] = { "pll_a_out0", "audio0_2x", "pll_p",
1416 "clk_m" };
1417static const char *i2s1_parents[] = { "pll_a_out0", "audio1_2x", "pll_p",
1418 "clk_m" };
1419static const char *i2s2_parents[] = { "pll_a_out0", "audio2_2x", "pll_p",
1420 "clk_m" };
1421static const char *i2s3_parents[] = { "pll_a_out0", "audio3_2x", "pll_p",
1422 "clk_m" };
1423static const char *i2s4_parents[] = { "pll_a_out0", "audio4_2x", "pll_p",
1424 "clk_m" };
1425static const char *spdif_out_parents[] = { "pll_a_out0", "spdif_2x", "pll_p", 1106static const char *spdif_out_parents[] = { "pll_a_out0", "spdif_2x", "pll_p",
1426 "clk_m" }; 1107 "clk_m" };
1427static const char *spdif_in_parents[] = { "pll_p", "pll_c", "pll_m" };
1428static const char *mux_pllpc_clk32k_clkm[] = { "pll_p", "pll_c", "clk_32k",
1429 "clk_m" };
1430static const char *mux_pllpc_clkm_clk32k[] = { "pll_p", "pll_c", "clk_m",
1431 "clk_32k" };
1432static const char *mux_pllmcpa[] = { "pll_m", "pll_c", "pll_p", "pll_a_out0" }; 1108static const char *mux_pllmcpa[] = { "pll_m", "pll_c", "pll_p", "pll_a_out0" };
1433static const char *mux_pllpdc_clkm[] = { "pll_p", "pll_d_out0", "pll_c",
1434 "clk_m" };
1435static const char *mux_pllp_clkm[] = { "pll_p", "unused", "unused", "clk_m" };
1436static const char *mux_pllpmdacd2_clkm[] = { "pll_p", "pll_m", "pll_d_out0", 1109static const char *mux_pllpmdacd2_clkm[] = { "pll_p", "pll_m", "pll_d_out0",
1437 "pll_a_out0", "pll_c", 1110 "pll_a_out0", "pll_c",
1438 "pll_d2_out0", "clk_m" }; 1111 "pll_d2_out0", "clk_m" };
1439static const char *mux_plla_clk32k_pllp_clkm_plle[] = { "pll_a_out0",
1440 "clk_32k", "pll_p",
1441 "clk_m", "pll_e" };
1442static const char *mux_plld_out0_plld2_out0[] = { "pll_d_out0", 1112static const char *mux_plld_out0_plld2_out0[] = { "pll_d_out0",
1443 "pll_d2_out0" }; 1113 "pll_d2_out0" };
1114static const char *pwm_parents[] = { "pll_p", "pll_c", "clk_32k", "clk_m" };
1444 1115
1445static struct tegra_periph_init_data tegra_periph_clk_list[] = { 1116static struct tegra_periph_init_data tegra_periph_clk_list[] = {
1446 TEGRA_INIT_DATA_MUX("i2s0", NULL, "tegra30-i2s.0", i2s0_parents, CLK_SOURCE_I2S0, 30, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s0), 1117 TEGRA_INIT_DATA_MUX("spdif_out", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, TEGRA30_CLK_SPDIF_OUT),
1447 TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra30-i2s.1", i2s1_parents, CLK_SOURCE_I2S1, 11, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s1), 1118 TEGRA_INIT_DATA_MUX("d_audio", mux_pllacp_clkm, CLK_SOURCE_D_AUDIO, 106, 0, TEGRA30_CLK_D_AUDIO),
1448 TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra30-i2s.2", i2s2_parents, CLK_SOURCE_I2S2, 18, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s2), 1119 TEGRA_INIT_DATA_MUX("dam0", mux_pllacp_clkm, CLK_SOURCE_DAM0, 108, 0, TEGRA30_CLK_DAM0),
1449 TEGRA_INIT_DATA_MUX("i2s3", NULL, "tegra30-i2s.3", i2s3_parents, CLK_SOURCE_I2S3, 101, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s3), 1120 TEGRA_INIT_DATA_MUX("dam1", mux_pllacp_clkm, CLK_SOURCE_DAM1, 109, 0, TEGRA30_CLK_DAM1),
1450 TEGRA_INIT_DATA_MUX("i2s4", NULL, "tegra30-i2s.4", i2s4_parents, CLK_SOURCE_I2S4, 102, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s4), 1121 TEGRA_INIT_DATA_MUX("dam2", mux_pllacp_clkm, CLK_SOURCE_DAM2, 110, 0, TEGRA30_CLK_DAM2),
1451 TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra30-spdif", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_out), 1122 TEGRA_INIT_DATA_INT("3d2", mux_pllmcpa, CLK_SOURCE_3D2, 98, TEGRA_PERIPH_MANUAL_RESET, TEGRA30_CLK_GR3D2),
1452 TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra30-spdif", spdif_in_parents, CLK_SOURCE_SPDIF_IN, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_in), 1123 TEGRA_INIT_DATA_INT("se", mux_pllpcm_clkm, CLK_SOURCE_SE, 127, 0, TEGRA30_CLK_SE),
1453 TEGRA_INIT_DATA_MUX("d_audio", "d_audio", "tegra30-ahub", mux_pllacp_clkm, CLK_SOURCE_D_AUDIO, 106, &periph_v_regs, 0, d_audio), 1124 TEGRA_INIT_DATA_MUX8("hdmi", mux_pllpmdacd2_clkm, CLK_SOURCE_HDMI, 51, 0, TEGRA30_CLK_HDMI),
1454 TEGRA_INIT_DATA_MUX("dam0", NULL, "tegra30-dam.0", mux_pllacp_clkm, CLK_SOURCE_DAM0, 108, &periph_v_regs, 0, dam0), 1125 TEGRA_INIT_DATA("pwm", NULL, NULL, pwm_parents, CLK_SOURCE_PWM, 28, 2, 0, 0, 8, 1, 0, 17, TEGRA_PERIPH_ON_APB, TEGRA30_CLK_PWM),
1455 TEGRA_INIT_DATA_MUX("dam1", NULL, "tegra30-dam.1", mux_pllacp_clkm, CLK_SOURCE_DAM1, 109, &periph_v_regs, 0, dam1),
1456 TEGRA_INIT_DATA_MUX("dam2", NULL, "tegra30-dam.2", mux_pllacp_clkm, CLK_SOURCE_DAM2, 110, &periph_v_regs, 0, dam2),
1457 TEGRA_INIT_DATA_MUX("hda", "hda", "tegra30-hda", mux_pllpcm_clkm, CLK_SOURCE_HDA, 125, &periph_v_regs, 0, hda),
1458 TEGRA_INIT_DATA_MUX("hda2codec_2x", "hda2codec", "tegra30-hda", mux_pllpcm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, &periph_v_regs, 0, hda2codec_2x),
1459 TEGRA_INIT_DATA_MUX("sbc1", NULL, "spi_tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1),
1460 TEGRA_INIT_DATA_MUX("sbc2", NULL, "spi_tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SBC2, 44, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc2),
1461 TEGRA_INIT_DATA_MUX("sbc3", NULL, "spi_tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SBC3, 46, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc3),
1462 TEGRA_INIT_DATA_MUX("sbc4", NULL, "spi_tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SBC4, 68, &periph_u_regs, TEGRA_PERIPH_ON_APB, sbc4),
1463 TEGRA_INIT_DATA_MUX("sbc5", NULL, "spi_tegra.4", mux_pllpcm_clkm, CLK_SOURCE_SBC5, 104, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc5),
1464 TEGRA_INIT_DATA_MUX("sbc6", NULL, "spi_tegra.5", mux_pllpcm_clkm, CLK_SOURCE_SBC6, 105, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc6),
1465 TEGRA_INIT_DATA_MUX("sata_oob", NULL, "tegra_sata_oob", mux_pllpcm_clkm, CLK_SOURCE_SATA_OOB, 123, &periph_v_regs, TEGRA_PERIPH_ON_APB, sata_oob),
1466 TEGRA_INIT_DATA_MUX("sata", NULL, "tegra_sata", mux_pllpcm_clkm, CLK_SOURCE_SATA, 124, &periph_v_regs, TEGRA_PERIPH_ON_APB, sata),
1467 TEGRA_INIT_DATA_MUX("ndflash", NULL, "tegra_nand", mux_pllpcm_clkm, CLK_SOURCE_NDFLASH, 13, &periph_l_regs, TEGRA_PERIPH_ON_APB, ndflash),
1468 TEGRA_INIT_DATA_MUX("ndspeed", NULL, "tegra_nand_speed", mux_pllpcm_clkm, CLK_SOURCE_NDSPEED, 80, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed),
1469 TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllpcm_clkm, CLK_SOURCE_VFIR, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, vfir),
1470 TEGRA_INIT_DATA_MUX("csite", NULL, "csite", mux_pllpcm_clkm, CLK_SOURCE_CSITE, 73, &periph_u_regs, TEGRA_PERIPH_ON_APB, csite),
1471 TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllpcm_clkm, CLK_SOURCE_LA, 76, &periph_u_regs, TEGRA_PERIPH_ON_APB, la),
1472 TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllpcm_clkm, CLK_SOURCE_OWR, 71, &periph_u_regs, TEGRA_PERIPH_ON_APB, owr),
1473 TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllpcm_clkm, CLK_SOURCE_MIPI, 50, &periph_h_regs, TEGRA_PERIPH_ON_APB, mipi),
1474 TEGRA_INIT_DATA_MUX("tsensor", NULL, "tegra-tsensor", mux_pllpc_clkm_clk32k, CLK_SOURCE_TSENSOR, 100, &periph_v_regs, TEGRA_PERIPH_ON_APB, tsensor),
1475 TEGRA_INIT_DATA_MUX("i2cslow", NULL, "i2cslow", mux_pllpc_clk32k_clkm, CLK_SOURCE_I2CSLOW, 81, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2cslow),
1476 TEGRA_INIT_DATA_INT("vde", NULL, "vde", mux_pllpcm_clkm, CLK_SOURCE_VDE, 61, &periph_h_regs, 0, vde),
1477 TEGRA_INIT_DATA_INT("vi", "vi", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI, 20, &periph_l_regs, 0, vi),
1478 TEGRA_INIT_DATA_INT("epp", NULL, "epp", mux_pllmcpa, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, epp),
1479 TEGRA_INIT_DATA_INT("mpe", NULL, "mpe", mux_pllmcpa, CLK_SOURCE_MPE, 60, &periph_h_regs, 0, mpe),
1480 TEGRA_INIT_DATA_INT("host1x", NULL, "host1x", mux_pllmcpa, CLK_SOURCE_HOST1X, 28, &periph_l_regs, 0, host1x),
1481 TEGRA_INIT_DATA_INT("3d", NULL, "3d", mux_pllmcpa, CLK_SOURCE_3D, 24, &periph_l_regs, TEGRA_PERIPH_MANUAL_RESET, gr3d),
1482 TEGRA_INIT_DATA_INT("3d2", NULL, "3d2", mux_pllmcpa, CLK_SOURCE_3D2, 98, &periph_v_regs, TEGRA_PERIPH_MANUAL_RESET, gr3d2),
1483 TEGRA_INIT_DATA_INT("2d", NULL, "2d", mux_pllmcpa, CLK_SOURCE_2D, 21, &periph_l_regs, 0, gr2d),
1484 TEGRA_INIT_DATA_INT("se", NULL, "se", mux_pllpcm_clkm, CLK_SOURCE_SE, 127, &periph_v_regs, 0, se),
1485 TEGRA_INIT_DATA_MUX("mselect", NULL, "mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, &periph_v_regs, 0, mselect),
1486 TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllpcm_clkm, CLK_SOURCE_NOR, 42, &periph_h_regs, 0, nor),
1487 TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SDMMC1, 14, &periph_l_regs, 0, sdmmc1),
1488 TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SDMMC2, 9, &periph_l_regs, 0, sdmmc2),
1489 TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SDMMC3, 69, &periph_u_regs, 0, sdmmc3),
1490 TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SDMMC4, 15, &periph_l_regs, 0, sdmmc4),
1491 TEGRA_INIT_DATA_MUX("cve", NULL, "cve", mux_pllpdc_clkm, CLK_SOURCE_CVE, 49, &periph_h_regs, 0, cve),
1492 TEGRA_INIT_DATA_MUX("tvo", NULL, "tvo", mux_pllpdc_clkm, CLK_SOURCE_TVO, 49, &periph_h_regs, 0, tvo),
1493 TEGRA_INIT_DATA_MUX("tvdac", NULL, "tvdac", mux_pllpdc_clkm, CLK_SOURCE_TVDAC, 53, &periph_h_regs, 0, tvdac),
1494 TEGRA_INIT_DATA_MUX("actmon", NULL, "actmon", mux_pllpc_clk32k_clkm, CLK_SOURCE_ACTMON, 119, &periph_v_regs, 0, actmon),
1495 TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, vi_sensor),
1496 TEGRA_INIT_DATA_DIV16("i2c1", "div-clk", "tegra-i2c.0", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2c1),
1497 TEGRA_INIT_DATA_DIV16("i2c2", "div-clk", "tegra-i2c.1", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, &periph_h_regs, TEGRA_PERIPH_ON_APB, i2c2),
1498 TEGRA_INIT_DATA_DIV16("i2c3", "div-clk", "tegra-i2c.2", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2c3),
1499 TEGRA_INIT_DATA_DIV16("i2c4", "div-clk", "tegra-i2c.3", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2c4),
1500 TEGRA_INIT_DATA_DIV16("i2c5", "div-clk", "tegra-i2c.4", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, &periph_h_regs, TEGRA_PERIPH_ON_APB, i2c5),
1501 TEGRA_INIT_DATA_UART("uarta", NULL, "tegra_uart.0", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 6, &periph_l_regs, uarta),
1502 TEGRA_INIT_DATA_UART("uartb", NULL, "tegra_uart.1", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 7, &periph_l_regs, uartb),
1503 TEGRA_INIT_DATA_UART("uartc", NULL, "tegra_uart.2", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 55, &periph_h_regs, uartc),
1504 TEGRA_INIT_DATA_UART("uartd", NULL, "tegra_uart.3", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 65, &periph_u_regs, uartd),
1505 TEGRA_INIT_DATA_UART("uarte", NULL, "tegra_uart.4", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 66, &periph_u_regs, uarte),
1506 TEGRA_INIT_DATA_MUX8("hdmi", NULL, "hdmi", mux_pllpmdacd2_clkm, CLK_SOURCE_HDMI, 51, &periph_h_regs, 0, hdmi),
1507 TEGRA_INIT_DATA_MUX8("extern1", NULL, "extern1", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, &periph_v_regs, 0, extern1),
1508 TEGRA_INIT_DATA_MUX8("extern2", NULL, "extern2", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, &periph_v_regs, 0, extern2),
1509 TEGRA_INIT_DATA_MUX8("extern3", NULL, "extern3", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, &periph_v_regs, 0, extern3),
1510 TEGRA_INIT_DATA("pwm", NULL, "pwm", mux_pllpc_clk32k_clkm, CLK_SOURCE_PWM, 28, 2, 0, 0, 8, 1, 0, &periph_l_regs, 17, periph_clk_enb_refcnt, 0, pwm),
1511}; 1126};
1512 1127
1513static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { 1128static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
1514 TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllpmdacd2_clkm, CLK_SOURCE_DISP1, 29, 3, 27, &periph_l_regs, 0, disp1), 1129 TEGRA_INIT_DATA_NODIV("dsib", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB, 25, 1, 82, 0, TEGRA30_CLK_DSIB),
1515 TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllpmdacd2_clkm, CLK_SOURCE_DISP2, 29, 3, 26, &periph_l_regs, 0, disp2),
1516 TEGRA_INIT_DATA_NODIV("dsib", NULL, "tegradc.1", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB, 25, 1, 82, &periph_u_regs, 0, dsib),
1517}; 1130};
1518 1131
1519static void __init tegra30_periph_clk_init(void) 1132static void __init tegra30_periph_clk_init(void)
@@ -1522,170 +1135,25 @@ static void __init tegra30_periph_clk_init(void)
1522 struct clk *clk; 1135 struct clk *clk;
1523 int i; 1136 int i;
1524 1137
1525 /* apbdma */
1526 clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base, 0, 34,
1527 &periph_h_regs, periph_clk_enb_refcnt);
1528 clk_register_clkdev(clk, NULL, "tegra-apbdma");
1529 clks[apbdma] = clk;
1530
1531 /* rtc */
1532 clk = tegra_clk_register_periph_gate("rtc", "clk_32k",
1533 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB,
1534 clk_base, 0, 4, &periph_l_regs,
1535 periph_clk_enb_refcnt);
1536 clk_register_clkdev(clk, NULL, "rtc-tegra");
1537 clks[rtc] = clk;
1538
1539 /* timer */
1540 clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base, 0,
1541 5, &periph_l_regs, periph_clk_enb_refcnt);
1542 clk_register_clkdev(clk, NULL, "timer");
1543 clks[timer] = clk;
1544
1545 /* kbc */
1546 clk = tegra_clk_register_periph_gate("kbc", "clk_32k",
1547 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB,
1548 clk_base, 0, 36, &periph_h_regs,
1549 periph_clk_enb_refcnt);
1550 clk_register_clkdev(clk, NULL, "tegra-kbc");
1551 clks[kbc] = clk;
1552
1553 /* csus */
1554 clk = tegra_clk_register_periph_gate("csus", "clk_m",
1555 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB,
1556 clk_base, 0, 92, &periph_u_regs,
1557 periph_clk_enb_refcnt);
1558 clk_register_clkdev(clk, "csus", "tengra_camera");
1559 clks[csus] = clk;
1560
1561 /* vcp */
1562 clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, clk_base, 0, 29,
1563 &periph_l_regs, periph_clk_enb_refcnt);
1564 clk_register_clkdev(clk, "vcp", "tegra-avp");
1565 clks[vcp] = clk;
1566
1567 /* bsea */
1568 clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, clk_base, 0,
1569 62, &periph_h_regs, periph_clk_enb_refcnt);
1570 clk_register_clkdev(clk, "bsea", "tegra-avp");
1571 clks[bsea] = clk;
1572
1573 /* bsev */
1574 clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, clk_base, 0,
1575 63, &periph_h_regs, periph_clk_enb_refcnt);
1576 clk_register_clkdev(clk, "bsev", "tegra-aes");
1577 clks[bsev] = clk;
1578
1579 /* usbd */
1580 clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base, 0,
1581 22, &periph_l_regs, periph_clk_enb_refcnt);
1582 clk_register_clkdev(clk, NULL, "fsl-tegra-udc");
1583 clks[usbd] = clk;
1584
1585 /* usb2 */
1586 clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base, 0,
1587 58, &periph_h_regs, periph_clk_enb_refcnt);
1588 clk_register_clkdev(clk, NULL, "tegra-ehci.1");
1589 clks[usb2] = clk;
1590
1591 /* usb3 */
1592 clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base, 0,
1593 59, &periph_h_regs, periph_clk_enb_refcnt);
1594 clk_register_clkdev(clk, NULL, "tegra-ehci.2");
1595 clks[usb3] = clk;
1596
1597 /* dsia */ 1138 /* dsia */
1598 clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base, 1139 clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base,
1599 0, 48, &periph_h_regs, 1140 0, 48, periph_clk_enb_refcnt);
1600 periph_clk_enb_refcnt); 1141 clks[TEGRA30_CLK_DSIA] = clk;
1601 clk_register_clkdev(clk, "dsia", "tegradc.0");
1602 clks[dsia] = clk;
1603
1604 /* csi */
1605 clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base,
1606 0, 52, &periph_h_regs,
1607 periph_clk_enb_refcnt);
1608 clk_register_clkdev(clk, "csi", "tegra_camera");
1609 clks[csi] = clk;
1610
1611 /* isp */
1612 clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0, 23,
1613 &periph_l_regs, periph_clk_enb_refcnt);
1614 clk_register_clkdev(clk, "isp", "tegra_camera");
1615 clks[isp] = clk;
1616 1142
1617 /* pcie */ 1143 /* pcie */
1618 clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0, 1144 clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0,
1619 70, &periph_u_regs, periph_clk_enb_refcnt); 1145 70, periph_clk_enb_refcnt);
1620 clk_register_clkdev(clk, "pcie", "tegra-pcie"); 1146 clks[TEGRA30_CLK_PCIE] = clk;
1621 clks[pcie] = clk;
1622 1147
1623 /* afi */ 1148 /* afi */
1624 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72, 1149 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72,
1625 &periph_u_regs, periph_clk_enb_refcnt); 1150 periph_clk_enb_refcnt);
1626 clk_register_clkdev(clk, "afi", "tegra-pcie"); 1151 clks[TEGRA30_CLK_AFI] = clk;
1627 clks[afi] = clk;
1628 1152
1629 /* pciex */ 1153 /* pciex */
1630 clk = tegra_clk_register_periph_gate("pciex", "pll_e", 0, clk_base, 0, 1154 clk = tegra_clk_register_periph_gate("pciex", "pll_e", 0, clk_base, 0,
1631 74, &periph_u_regs, periph_clk_enb_refcnt); 1155 74, periph_clk_enb_refcnt);
1632 clk_register_clkdev(clk, "pciex", "tegra-pcie"); 1156 clks[TEGRA30_CLK_PCIEX] = clk;
1633 clks[pciex] = clk;
1634
1635 /* kfuse */
1636 clk = tegra_clk_register_periph_gate("kfuse", "clk_m",
1637 TEGRA_PERIPH_ON_APB,
1638 clk_base, 0, 40, &periph_h_regs,
1639 periph_clk_enb_refcnt);
1640 clk_register_clkdev(clk, NULL, "kfuse-tegra");
1641 clks[kfuse] = clk;
1642
1643 /* fuse */
1644 clk = tegra_clk_register_periph_gate("fuse", "clk_m",
1645 TEGRA_PERIPH_ON_APB,
1646 clk_base, 0, 39, &periph_h_regs,
1647 periph_clk_enb_refcnt);
1648 clk_register_clkdev(clk, "fuse", "fuse-tegra");
1649 clks[fuse] = clk;
1650
1651 /* fuse_burn */
1652 clk = tegra_clk_register_periph_gate("fuse_burn", "clk_m",
1653 TEGRA_PERIPH_ON_APB,
1654 clk_base, 0, 39, &periph_h_regs,
1655 periph_clk_enb_refcnt);
1656 clk_register_clkdev(clk, "fuse_burn", "fuse-tegra");
1657 clks[fuse_burn] = clk;
1658
1659 /* apbif */
1660 clk = tegra_clk_register_periph_gate("apbif", "clk_m", 0,
1661 clk_base, 0, 107, &periph_v_regs,
1662 periph_clk_enb_refcnt);
1663 clk_register_clkdev(clk, "apbif", "tegra30-ahub");
1664 clks[apbif] = clk;
1665
1666 /* hda2hdmi */
1667 clk = tegra_clk_register_periph_gate("hda2hdmi", "clk_m",
1668 TEGRA_PERIPH_ON_APB,
1669 clk_base, 0, 128, &periph_w_regs,
1670 periph_clk_enb_refcnt);
1671 clk_register_clkdev(clk, "hda2hdmi", "tegra30-hda");
1672 clks[hda2hdmi] = clk;
1673
1674 /* sata_cold */
1675 clk = tegra_clk_register_periph_gate("sata_cold", "clk_m",
1676 TEGRA_PERIPH_ON_APB,
1677 clk_base, 0, 129, &periph_w_regs,
1678 periph_clk_enb_refcnt);
1679 clk_register_clkdev(clk, NULL, "tegra_sata_cold");
1680 clks[sata_cold] = clk;
1681
1682 /* dtv */
1683 clk = tegra_clk_register_periph_gate("dtv", "clk_m",
1684 TEGRA_PERIPH_ON_APB,
1685 clk_base, 0, 79, &periph_u_regs,
1686 periph_clk_enb_refcnt);
1687 clk_register_clkdev(clk, NULL, "dtv");
1688 clks[dtv] = clk;
1689 1157
1690 /* emc */ 1158 /* emc */
1691 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 1159 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
@@ -1694,84 +1162,37 @@ static void __init tegra30_periph_clk_init(void)
1694 clk_base + CLK_SOURCE_EMC, 1162 clk_base + CLK_SOURCE_EMC,
1695 30, 2, 0, NULL); 1163 30, 2, 0, NULL);
1696 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0, 1164 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
1697 57, &periph_h_regs, periph_clk_enb_refcnt); 1165 57, periph_clk_enb_refcnt);
1698 clk_register_clkdev(clk, "emc", NULL); 1166 clks[TEGRA30_CLK_EMC] = clk;
1699 clks[emc] = clk; 1167
1168 /* cml0 */
1169 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
1170 0, 0, &cml_lock);
1171 clks[TEGRA30_CLK_CML0] = clk;
1172
1173 /* cml1 */
1174 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
1175 1, 0, &cml_lock);
1176 clks[TEGRA30_CLK_CML1] = clk;
1700 1177
1701 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { 1178 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
1702 data = &tegra_periph_clk_list[i]; 1179 data = &tegra_periph_clk_list[i];
1703 clk = tegra_clk_register_periph(data->name, data->parent_names, 1180 clk = tegra_clk_register_periph(data->name, data->p.parent_names,
1704 data->num_parents, &data->periph, 1181 data->num_parents, &data->periph,
1705 clk_base, data->offset, data->flags); 1182 clk_base, data->offset, data->flags);
1706 clk_register_clkdev(clk, data->con_id, data->dev_id);
1707 clks[data->clk_id] = clk; 1183 clks[data->clk_id] = clk;
1708 } 1184 }
1709 1185
1710 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) { 1186 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
1711 data = &tegra_periph_nodiv_clk_list[i]; 1187 data = &tegra_periph_nodiv_clk_list[i];
1712 clk = tegra_clk_register_periph_nodiv(data->name, 1188 clk = tegra_clk_register_periph_nodiv(data->name,
1713 data->parent_names, 1189 data->p.parent_names,
1714 data->num_parents, &data->periph, 1190 data->num_parents, &data->periph,
1715 clk_base, data->offset); 1191 clk_base, data->offset);
1716 clk_register_clkdev(clk, data->con_id, data->dev_id);
1717 clks[data->clk_id] = clk; 1192 clks[data->clk_id] = clk;
1718 } 1193 }
1719}
1720
1721static void __init tegra30_fixed_clk_init(void)
1722{
1723 struct clk *clk;
1724
1725 /* clk_32k */
1726 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT,
1727 32768);
1728 clk_register_clkdev(clk, "clk_32k", NULL);
1729 clks[clk_32k] = clk;
1730
1731 /* clk_m_div2 */
1732 clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
1733 CLK_SET_RATE_PARENT, 1, 2);
1734 clk_register_clkdev(clk, "clk_m_div2", NULL);
1735 clks[clk_m_div2] = clk;
1736
1737 /* clk_m_div4 */
1738 clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
1739 CLK_SET_RATE_PARENT, 1, 4);
1740 clk_register_clkdev(clk, "clk_m_div4", NULL);
1741 clks[clk_m_div4] = clk;
1742
1743 /* cml0 */
1744 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
1745 0, 0, &cml_lock);
1746 clk_register_clkdev(clk, "cml0", NULL);
1747 clks[cml0] = clk;
1748 1194
1749 /* cml1 */ 1195 tegra_periph_clk_init(clk_base, pmc_base, tegra30_clks, &pll_p_params);
1750 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
1751 1, 0, &cml_lock);
1752 clk_register_clkdev(clk, "cml1", NULL);
1753 clks[cml1] = clk;
1754}
1755
1756static void __init tegra30_osc_clk_init(void)
1757{
1758 struct clk *clk;
1759 unsigned int pll_ref_div;
1760
1761 tegra30_clk_measure_input_freq();
1762
1763 /* clk_m */
1764 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT,
1765 input_freq);
1766 clk_register_clkdev(clk, "clk_m", NULL);
1767 clks[clk_m] = clk;
1768
1769 /* pll_ref */
1770 pll_ref_div = tegra30_get_pll_ref_div();
1771 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
1772 CLK_SET_RATE_PARENT, 1, pll_ref_div);
1773 clk_register_clkdev(clk, "pll_ref", NULL);
1774 clks[pll_ref] = clk;
1775} 1196}
1776 1197
1777/* Tegra30 CPU clock and reset control functions */ 1198/* Tegra30 CPU clock and reset control functions */
@@ -1913,48 +1334,49 @@ static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
1913}; 1334};
1914 1335
1915static struct tegra_clk_init_table init_table[] __initdata = { 1336static struct tegra_clk_init_table init_table[] __initdata = {
1916 {uarta, pll_p, 408000000, 0}, 1337 {TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P, 408000000, 0},
1917 {uartb, pll_p, 408000000, 0}, 1338 {TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P, 408000000, 0},
1918 {uartc, pll_p, 408000000, 0}, 1339 {TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0},
1919 {uartd, pll_p, 408000000, 0}, 1340 {TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 0},
1920 {uarte, pll_p, 408000000, 0}, 1341 {TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0},
1921 {pll_a, clk_max, 564480000, 1}, 1342 {TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 1},
1922 {pll_a_out0, clk_max, 11289600, 1}, 1343 {TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 1},
1923 {extern1, pll_a_out0, 0, 1}, 1344 {TEGRA30_CLK_EXTERN1, TEGRA30_CLK_PLL_A_OUT0, 0, 1},
1924 {clk_out_1_mux, extern1, 0, 0}, 1345 {TEGRA30_CLK_CLK_OUT_1_MUX, TEGRA30_CLK_EXTERN1, 0, 0},
1925 {clk_out_1, clk_max, 0, 1}, 1346 {TEGRA30_CLK_CLK_OUT_1, TEGRA30_CLK_CLK_MAX, 0, 1},
1926 {blink, clk_max, 0, 1}, 1347 {TEGRA30_CLK_BLINK, TEGRA30_CLK_CLK_MAX, 0, 1},
1927 {i2s0, pll_a_out0, 11289600, 0}, 1348 {TEGRA30_CLK_I2S0, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
1928 {i2s1, pll_a_out0, 11289600, 0}, 1349 {TEGRA30_CLK_I2S1, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
1929 {i2s2, pll_a_out0, 11289600, 0}, 1350 {TEGRA30_CLK_I2S2, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
1930 {i2s3, pll_a_out0, 11289600, 0}, 1351 {TEGRA30_CLK_I2S3, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
1931 {i2s4, pll_a_out0, 11289600, 0}, 1352 {TEGRA30_CLK_I2S4, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
1932 {sdmmc1, pll_p, 48000000, 0}, 1353 {TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0},
1933 {sdmmc2, pll_p, 48000000, 0}, 1354 {TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0},
1934 {sdmmc3, pll_p, 48000000, 0}, 1355 {TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0},
1935 {pll_m, clk_max, 0, 1}, 1356 {TEGRA30_CLK_PLL_M, TEGRA30_CLK_CLK_MAX, 0, 1},
1936 {pclk, clk_max, 0, 1}, 1357 {TEGRA30_CLK_PCLK, TEGRA30_CLK_CLK_MAX, 0, 1},
1937 {csite, clk_max, 0, 1}, 1358 {TEGRA30_CLK_CSITE, TEGRA30_CLK_CLK_MAX, 0, 1},
1938 {emc, clk_max, 0, 1}, 1359 {TEGRA30_CLK_EMC, TEGRA30_CLK_CLK_MAX, 0, 1},
1939 {mselect, clk_max, 0, 1}, 1360 {TEGRA30_CLK_MSELECT, TEGRA30_CLK_CLK_MAX, 0, 1},
1940 {sbc1, pll_p, 100000000, 0}, 1361 {TEGRA30_CLK_SBC1, TEGRA30_CLK_PLL_P, 100000000, 0},
1941 {sbc2, pll_p, 100000000, 0}, 1362 {TEGRA30_CLK_SBC2, TEGRA30_CLK_PLL_P, 100000000, 0},
1942 {sbc3, pll_p, 100000000, 0}, 1363 {TEGRA30_CLK_SBC3, TEGRA30_CLK_PLL_P, 100000000, 0},
1943 {sbc4, pll_p, 100000000, 0}, 1364 {TEGRA30_CLK_SBC4, TEGRA30_CLK_PLL_P, 100000000, 0},
1944 {sbc5, pll_p, 100000000, 0}, 1365 {TEGRA30_CLK_SBC5, TEGRA30_CLK_PLL_P, 100000000, 0},
1945 {sbc6, pll_p, 100000000, 0}, 1366 {TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0},
1946 {host1x, pll_c, 150000000, 0}, 1367 {TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 150000000, 0},
1947 {disp1, pll_p, 600000000, 0}, 1368 {TEGRA30_CLK_DISP1, TEGRA30_CLK_PLL_P, 600000000, 0},
1948 {disp2, pll_p, 600000000, 0}, 1369 {TEGRA30_CLK_DISP2, TEGRA30_CLK_PLL_P, 600000000, 0},
1949 {twd, clk_max, 0, 1}, 1370 {TEGRA30_CLK_TWD, TEGRA30_CLK_CLK_MAX, 0, 1},
1950 {gr2d, pll_c, 300000000, 0}, 1371 {TEGRA30_CLK_GR2D, TEGRA30_CLK_PLL_C, 300000000, 0},
1951 {gr3d, pll_c, 300000000, 0}, 1372 {TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0},
1952 {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */ 1373 {TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0},
1374 {TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0}, /* This MUST be the last entry. */
1953}; 1375};
1954 1376
1955static void __init tegra30_clock_apply_init_table(void) 1377static void __init tegra30_clock_apply_init_table(void)
1956{ 1378{
1957 tegra_init_from_table(init_table, clks, clk_max); 1379 tegra_init_from_table(init_table, clks, TEGRA30_CLK_CLK_MAX);
1958} 1380}
1959 1381
1960/* 1382/*
@@ -1963,19 +1385,19 @@ static void __init tegra30_clock_apply_init_table(void)
1963 * table under two names. 1385 * table under two names.
1964 */ 1386 */
1965static struct tegra_clk_duplicate tegra_clk_duplicates[] = { 1387static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
1966 TEGRA_CLK_DUPLICATE(usbd, "utmip-pad", NULL), 1388 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "utmip-pad", NULL),
1967 TEGRA_CLK_DUPLICATE(usbd, "tegra-ehci.0", NULL), 1389 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "tegra-ehci.0", NULL),
1968 TEGRA_CLK_DUPLICATE(usbd, "tegra-otg", NULL), 1390 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "tegra-otg", NULL),
1969 TEGRA_CLK_DUPLICATE(bsev, "tegra-avp", "bsev"), 1391 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEV, "tegra-avp", "bsev"),
1970 TEGRA_CLK_DUPLICATE(bsev, "nvavp", "bsev"), 1392 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEV, "nvavp", "bsev"),
1971 TEGRA_CLK_DUPLICATE(vde, "tegra-aes", "vde"), 1393 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VDE, "tegra-aes", "vde"),
1972 TEGRA_CLK_DUPLICATE(bsea, "tegra-aes", "bsea"), 1394 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "tegra-aes", "bsea"),
1973 TEGRA_CLK_DUPLICATE(bsea, "nvavp", "bsea"), 1395 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "nvavp", "bsea"),
1974 TEGRA_CLK_DUPLICATE(cml1, "tegra_sata_cml", NULL), 1396 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML1, "tegra_sata_cml", NULL),
1975 TEGRA_CLK_DUPLICATE(cml0, "tegra_pcie", "cml"), 1397 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML0, "tegra_pcie", "cml"),
1976 TEGRA_CLK_DUPLICATE(pciex, "tegra_pcie", "pciex"), 1398 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_PCIEX, "tegra_pcie", "pciex"),
1977 TEGRA_CLK_DUPLICATE(vcp, "nvavp", "vcp"), 1399 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VCP, "nvavp", "vcp"),
1978 TEGRA_CLK_DUPLICATE(clk_max, NULL, NULL), /* MUST be the last entry */ 1400 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CLK_MAX, NULL, NULL), /* MUST be the last entry */
1979}; 1401};
1980 1402
1981static const struct of_device_id pmc_match[] __initconst = { 1403static const struct of_device_id pmc_match[] __initconst = {
@@ -1986,7 +1408,6 @@ static const struct of_device_id pmc_match[] __initconst = {
1986static void __init tegra30_clock_init(struct device_node *np) 1408static void __init tegra30_clock_init(struct device_node *np)
1987{ 1409{
1988 struct device_node *node; 1410 struct device_node *node;
1989 int i;
1990 1411
1991 clk_base = of_iomap(np, 0); 1412 clk_base = of_iomap(np, 0);
1992 if (!clk_base) { 1413 if (!clk_base) {
@@ -2006,29 +1427,26 @@ static void __init tegra30_clock_init(struct device_node *np)
2006 BUG(); 1427 BUG();
2007 } 1428 }
2008 1429
2009 tegra30_osc_clk_init(); 1430 clks = tegra_clk_init(TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_PERIPH_BANKS);
2010 tegra30_fixed_clk_init(); 1431 if (!clks)
1432 return;
1433
1434 if (tegra_osc_clk_init(clk_base, tegra30_clks, tegra30_input_freq,
1435 ARRAY_SIZE(tegra30_input_freq), &input_freq, NULL) < 0)
1436 return;
1437
1438
1439 tegra_fixed_clk_init(tegra30_clks);
2011 tegra30_pll_init(); 1440 tegra30_pll_init();
2012 tegra30_super_clk_init(); 1441 tegra30_super_clk_init();
2013 tegra30_periph_clk_init(); 1442 tegra30_periph_clk_init();
2014 tegra30_audio_clk_init(); 1443 tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks, &pll_a_params);
2015 tegra30_pmc_clk_init(); 1444 tegra_pmc_clk_init(pmc_base, tegra30_clks);
2016
2017 for (i = 0; i < ARRAY_SIZE(clks); i++) {
2018 if (IS_ERR(clks[i])) {
2019 pr_err("Tegra30 clk %d: register failed with %ld\n",
2020 i, PTR_ERR(clks[i]));
2021 BUG();
2022 }
2023 if (!clks[i])
2024 clks[i] = ERR_PTR(-EINVAL);
2025 }
2026 1445
2027 tegra_init_dup_clks(tegra_clk_duplicates, clks, clk_max); 1446 tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX);
2028 1447
2029 clk_data.clks = clks; 1448 tegra_add_of_provider(np);
2030 clk_data.clk_num = ARRAY_SIZE(clks); 1449 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
2031 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
2032 1450
2033 tegra_clk_apply_init_table = tegra30_clock_apply_init_table; 1451 tegra_clk_apply_init_table = tegra30_clock_apply_init_table;
2034 1452
diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
index 86581ac1fd69..a12a5f5107ec 100644
--- a/drivers/clk/tegra/clk.c
+++ b/drivers/clk/tegra/clk.c
@@ -21,10 +21,139 @@
21 21
22#include "clk.h" 22#include "clk.h"
23 23
24#define CLK_OUT_ENB_L 0x010
25#define CLK_OUT_ENB_H 0x014
26#define CLK_OUT_ENB_U 0x018
27#define CLK_OUT_ENB_V 0x360
28#define CLK_OUT_ENB_W 0x364
29#define CLK_OUT_ENB_X 0x280
30#define CLK_OUT_ENB_SET_L 0x320
31#define CLK_OUT_ENB_CLR_L 0x324
32#define CLK_OUT_ENB_SET_H 0x328
33#define CLK_OUT_ENB_CLR_H 0x32c
34#define CLK_OUT_ENB_SET_U 0x330
35#define CLK_OUT_ENB_CLR_U 0x334
36#define CLK_OUT_ENB_SET_V 0x440
37#define CLK_OUT_ENB_CLR_V 0x444
38#define CLK_OUT_ENB_SET_W 0x448
39#define CLK_OUT_ENB_CLR_W 0x44c
40#define CLK_OUT_ENB_SET_X 0x284
41#define CLK_OUT_ENB_CLR_X 0x288
42
43#define RST_DEVICES_L 0x004
44#define RST_DEVICES_H 0x008
45#define RST_DEVICES_U 0x00C
46#define RST_DFLL_DVCO 0x2F4
47#define RST_DEVICES_V 0x358
48#define RST_DEVICES_W 0x35C
49#define RST_DEVICES_X 0x28C
50#define RST_DEVICES_SET_L 0x300
51#define RST_DEVICES_CLR_L 0x304
52#define RST_DEVICES_SET_H 0x308
53#define RST_DEVICES_CLR_H 0x30c
54#define RST_DEVICES_SET_U 0x310
55#define RST_DEVICES_CLR_U 0x314
56#define RST_DEVICES_SET_V 0x430
57#define RST_DEVICES_CLR_V 0x434
58#define RST_DEVICES_SET_W 0x438
59#define RST_DEVICES_CLR_W 0x43c
60#define RST_DEVICES_SET_X 0x290
61#define RST_DEVICES_CLR_X 0x294
62
24/* Global data of Tegra CPU CAR ops */ 63/* Global data of Tegra CPU CAR ops */
25static struct tegra_cpu_car_ops dummy_car_ops; 64static struct tegra_cpu_car_ops dummy_car_ops;
26struct tegra_cpu_car_ops *tegra_cpu_car_ops = &dummy_car_ops; 65struct tegra_cpu_car_ops *tegra_cpu_car_ops = &dummy_car_ops;
27 66
67int *periph_clk_enb_refcnt;
68static int periph_banks;
69static struct clk **clks;
70static int clk_num;
71static struct clk_onecell_data clk_data;
72
73static struct tegra_clk_periph_regs periph_regs[] = {
74 [0] = {
75 .enb_reg = CLK_OUT_ENB_L,
76 .enb_set_reg = CLK_OUT_ENB_SET_L,
77 .enb_clr_reg = CLK_OUT_ENB_CLR_L,
78 .rst_reg = RST_DEVICES_L,
79 .rst_set_reg = RST_DEVICES_SET_L,
80 .rst_clr_reg = RST_DEVICES_CLR_L,
81 },
82 [1] = {
83 .enb_reg = CLK_OUT_ENB_H,
84 .enb_set_reg = CLK_OUT_ENB_SET_H,
85 .enb_clr_reg = CLK_OUT_ENB_CLR_H,
86 .rst_reg = RST_DEVICES_H,
87 .rst_set_reg = RST_DEVICES_SET_H,
88 .rst_clr_reg = RST_DEVICES_CLR_H,
89 },
90 [2] = {
91 .enb_reg = CLK_OUT_ENB_U,
92 .enb_set_reg = CLK_OUT_ENB_SET_U,
93 .enb_clr_reg = CLK_OUT_ENB_CLR_U,
94 .rst_reg = RST_DEVICES_U,
95 .rst_set_reg = RST_DEVICES_SET_U,
96 .rst_clr_reg = RST_DEVICES_CLR_U,
97 },
98 [3] = {
99 .enb_reg = CLK_OUT_ENB_V,
100 .enb_set_reg = CLK_OUT_ENB_SET_V,
101 .enb_clr_reg = CLK_OUT_ENB_CLR_V,
102 .rst_reg = RST_DEVICES_V,
103 .rst_set_reg = RST_DEVICES_SET_V,
104 .rst_clr_reg = RST_DEVICES_CLR_V,
105 },
106 [4] = {
107 .enb_reg = CLK_OUT_ENB_W,
108 .enb_set_reg = CLK_OUT_ENB_SET_W,
109 .enb_clr_reg = CLK_OUT_ENB_CLR_W,
110 .rst_reg = RST_DEVICES_W,
111 .rst_set_reg = RST_DEVICES_SET_W,
112 .rst_clr_reg = RST_DEVICES_CLR_W,
113 },
114 [5] = {
115 .enb_reg = CLK_OUT_ENB_X,
116 .enb_set_reg = CLK_OUT_ENB_SET_X,
117 .enb_clr_reg = CLK_OUT_ENB_CLR_X,
118 .rst_reg = RST_DEVICES_X,
119 .rst_set_reg = RST_DEVICES_SET_X,
120 .rst_clr_reg = RST_DEVICES_CLR_X,
121 },
122};
123
124struct tegra_clk_periph_regs *get_reg_bank(int clkid)
125{
126 int reg_bank = clkid / 32;
127
128 if (reg_bank < periph_banks)
129 return &periph_regs[reg_bank];
130 else {
131 WARN_ON(1);
132 return NULL;
133 }
134}
135
136struct clk ** __init tegra_clk_init(int num, int banks)
137{
138 if (WARN_ON(banks > ARRAY_SIZE(periph_regs)))
139 return NULL;
140
141 periph_clk_enb_refcnt = kzalloc(32 * banks *
142 sizeof(*periph_clk_enb_refcnt), GFP_KERNEL);
143 if (!periph_clk_enb_refcnt)
144 return NULL;
145
146 periph_banks = banks;
147
148 clks = kzalloc(num * sizeof(struct clk *), GFP_KERNEL);
149 if (!clks)
150 kfree(periph_clk_enb_refcnt);
151
152 clk_num = num;
153
154 return clks;
155}
156
28void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list, 157void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
29 struct clk *clks[], int clk_max) 158 struct clk *clks[], int clk_max)
30{ 159{
@@ -74,6 +203,43 @@ void __init tegra_init_from_table(struct tegra_clk_init_table *tbl,
74 } 203 }
75} 204}
76 205
206void __init tegra_add_of_provider(struct device_node *np)
207{
208 int i;
209
210 for (i = 0; i < clk_num; i++) {
211 if (IS_ERR(clks[i])) {
212 pr_err
213 ("Tegra clk %d: register failed with %ld\n",
214 i, PTR_ERR(clks[i]));
215 }
216 if (!clks[i])
217 clks[i] = ERR_PTR(-EINVAL);
218 }
219
220 clk_data.clks = clks;
221 clk_data.clk_num = clk_num;
222 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
223}
224
225void __init tegra_register_devclks(struct tegra_devclk *dev_clks, int num)
226{
227 int i;
228
229 for (i = 0; i < num; i++, dev_clks++)
230 clk_register_clkdev(clks[dev_clks->dt_id], dev_clks->con_id,
231 dev_clks->dev_id);
232}
233
234struct clk ** __init tegra_lookup_dt_id(int clk_id,
235 struct tegra_clk *tegra_clk)
236{
237 if (tegra_clk[clk_id].present)
238 return &clks[tegra_clk[clk_id].dt_id];
239 else
240 return NULL;
241}
242
77tegra_clk_apply_init_table_func tegra_clk_apply_init_table; 243tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
78 244
79void __init tegra_clocks_apply_init_table(void) 245void __init tegra_clocks_apply_init_table(void)
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 07cfacd91686..40fb011233c0 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -37,6 +37,8 @@ struct tegra_clk_sync_source {
37 container_of(_hw, struct tegra_clk_sync_source, hw) 37 container_of(_hw, struct tegra_clk_sync_source, hw)
38 38
39extern const struct clk_ops tegra_clk_sync_source_ops; 39extern const struct clk_ops tegra_clk_sync_source_ops;
40extern int *periph_clk_enb_refcnt;
41
40struct clk *tegra_clk_register_sync_source(const char *name, 42struct clk *tegra_clk_register_sync_source(const char *name,
41 unsigned long fixed_rate, unsigned long max_rate); 43 unsigned long fixed_rate, unsigned long max_rate);
42 44
@@ -188,12 +190,15 @@ struct tegra_clk_pll_params {
188 u32 ext_misc_reg[3]; 190 u32 ext_misc_reg[3];
189 u32 pmc_divnm_reg; 191 u32 pmc_divnm_reg;
190 u32 pmc_divp_reg; 192 u32 pmc_divp_reg;
193 u32 flags;
191 int stepa_shift; 194 int stepa_shift;
192 int stepb_shift; 195 int stepb_shift;
193 int lock_delay; 196 int lock_delay;
194 int max_p; 197 int max_p;
195 struct pdiv_map *pdiv_tohw; 198 struct pdiv_map *pdiv_tohw;
196 struct div_nmp *div_nmp; 199 struct div_nmp *div_nmp;
200 struct tegra_clk_pll_freq_table *freq_table;
201 unsigned long fixed_rate;
197}; 202};
198 203
199/** 204/**
@@ -233,10 +238,7 @@ struct tegra_clk_pll {
233 struct clk_hw hw; 238 struct clk_hw hw;
234 void __iomem *clk_base; 239 void __iomem *clk_base;
235 void __iomem *pmc; 240 void __iomem *pmc;
236 u32 flags;
237 unsigned long fixed_rate;
238 spinlock_t *lock; 241 spinlock_t *lock;
239 struct tegra_clk_pll_freq_table *freq_table;
240 struct tegra_clk_pll_params *params; 242 struct tegra_clk_pll_params *params;
241}; 243};
242 244
@@ -258,56 +260,49 @@ extern const struct clk_ops tegra_clk_pll_ops;
258extern const struct clk_ops tegra_clk_plle_ops; 260extern const struct clk_ops tegra_clk_plle_ops;
259struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, 261struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
260 void __iomem *clk_base, void __iomem *pmc, 262 void __iomem *clk_base, void __iomem *pmc,
261 unsigned long flags, unsigned long fixed_rate, 263 unsigned long flags, struct tegra_clk_pll_params *pll_params,
262 struct tegra_clk_pll_params *pll_params, u32 pll_flags, 264 spinlock_t *lock);
263 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock);
264 265
265struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, 266struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
266 void __iomem *clk_base, void __iomem *pmc, 267 void __iomem *clk_base, void __iomem *pmc,
267 unsigned long flags, unsigned long fixed_rate, 268 unsigned long flags, struct tegra_clk_pll_params *pll_params,
268 struct tegra_clk_pll_params *pll_params, u32 pll_flags, 269 spinlock_t *lock);
269 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock);
270 270
271struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, 271struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
272 void __iomem *clk_base, void __iomem *pmc, 272 void __iomem *clk_base, void __iomem *pmc,
273 unsigned long flags, unsigned long fixed_rate, 273 unsigned long flags,
274 struct tegra_clk_pll_params *pll_params, 274 struct tegra_clk_pll_params *pll_params,
275 u32 pll_flags,
276 struct tegra_clk_pll_freq_table *freq_table,
277 spinlock_t *lock); 275 spinlock_t *lock);
278 276
279struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, 277struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
280 void __iomem *clk_base, void __iomem *pmc, 278 void __iomem *clk_base, void __iomem *pmc,
281 unsigned long flags, unsigned long fixed_rate, 279 unsigned long flags,
282 struct tegra_clk_pll_params *pll_params, 280 struct tegra_clk_pll_params *pll_params,
283 u32 pll_flags,
284 struct tegra_clk_pll_freq_table *freq_table,
285 spinlock_t *lock); 281 spinlock_t *lock);
286 282
287struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, 283struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
288 void __iomem *clk_base, void __iomem *pmc, 284 void __iomem *clk_base, void __iomem *pmc,
289 unsigned long flags, unsigned long fixed_rate, 285 unsigned long flags,
290 struct tegra_clk_pll_params *pll_params, 286 struct tegra_clk_pll_params *pll_params,
291 u32 pll_flags,
292 struct tegra_clk_pll_freq_table *freq_table,
293 spinlock_t *lock); 287 spinlock_t *lock);
294 288
295struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, 289struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
296 void __iomem *clk_base, void __iomem *pmc, 290 void __iomem *clk_base, void __iomem *pmc,
297 unsigned long flags, unsigned long fixed_rate, 291 unsigned long flags,
298 struct tegra_clk_pll_params *pll_params, 292 struct tegra_clk_pll_params *pll_params,
299 u32 pll_flags,
300 struct tegra_clk_pll_freq_table *freq_table,
301 spinlock_t *lock, unsigned long parent_rate); 293 spinlock_t *lock, unsigned long parent_rate);
302 294
303struct clk *tegra_clk_register_plle_tegra114(const char *name, 295struct clk *tegra_clk_register_plle_tegra114(const char *name,
304 const char *parent_name, 296 const char *parent_name,
305 void __iomem *clk_base, unsigned long flags, 297 void __iomem *clk_base, unsigned long flags,
306 unsigned long fixed_rate,
307 struct tegra_clk_pll_params *pll_params, 298 struct tegra_clk_pll_params *pll_params,
308 struct tegra_clk_pll_freq_table *freq_table,
309 spinlock_t *lock); 299 spinlock_t *lock);
310 300
301struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
302 void __iomem *clk_base, unsigned long flags,
303 struct tegra_clk_pll_params *pll_params,
304 spinlock_t *lock);
305
311/** 306/**
312 * struct tegra_clk_pll_out - PLL divider down clock 307 * struct tegra_clk_pll_out - PLL divider down clock
313 * 308 *
@@ -395,13 +390,14 @@ struct tegra_clk_periph_gate {
395#define TEGRA_PERIPH_MANUAL_RESET BIT(1) 390#define TEGRA_PERIPH_MANUAL_RESET BIT(1)
396#define TEGRA_PERIPH_ON_APB BIT(2) 391#define TEGRA_PERIPH_ON_APB BIT(2)
397#define TEGRA_PERIPH_WAR_1005168 BIT(3) 392#define TEGRA_PERIPH_WAR_1005168 BIT(3)
393#define TEGRA_PERIPH_NO_DIV BIT(4)
394#define TEGRA_PERIPH_NO_GATE BIT(5)
398 395
399void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert); 396void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert);
400extern const struct clk_ops tegra_clk_periph_gate_ops; 397extern const struct clk_ops tegra_clk_periph_gate_ops;
401struct clk *tegra_clk_register_periph_gate(const char *name, 398struct clk *tegra_clk_register_periph_gate(const char *name,
402 const char *parent_name, u8 gate_flags, void __iomem *clk_base, 399 const char *parent_name, u8 gate_flags, void __iomem *clk_base,
403 unsigned long flags, int clk_num, 400 unsigned long flags, int clk_num, int *enable_refcnt);
404 struct tegra_clk_periph_regs *pregs, int *enable_refcnt);
405 401
406/** 402/**
407 * struct clk-periph - peripheral clock 403 * struct clk-periph - peripheral clock
@@ -443,26 +439,26 @@ struct clk *tegra_clk_register_periph_nodiv(const char *name,
443 439
444#define TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, _mux_flags, \ 440#define TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, _mux_flags, \
445 _div_shift, _div_width, _div_frac_width, \ 441 _div_shift, _div_width, _div_frac_width, \
446 _div_flags, _clk_num, _enb_refcnt, _regs, \ 442 _div_flags, _clk_num,\
447 _gate_flags, _table) \ 443 _gate_flags, _table, _lock) \
448 { \ 444 { \
449 .mux = { \ 445 .mux = { \
450 .flags = _mux_flags, \ 446 .flags = _mux_flags, \
451 .shift = _mux_shift, \ 447 .shift = _mux_shift, \
452 .mask = _mux_mask, \ 448 .mask = _mux_mask, \
453 .table = _table, \ 449 .table = _table, \
450 .lock = _lock, \
454 }, \ 451 }, \
455 .divider = { \ 452 .divider = { \
456 .flags = _div_flags, \ 453 .flags = _div_flags, \
457 .shift = _div_shift, \ 454 .shift = _div_shift, \
458 .width = _div_width, \ 455 .width = _div_width, \
459 .frac_width = _div_frac_width, \ 456 .frac_width = _div_frac_width, \
457 .lock = _lock, \
460 }, \ 458 }, \
461 .gate = { \ 459 .gate = { \
462 .flags = _gate_flags, \ 460 .flags = _gate_flags, \
463 .clk_num = _clk_num, \ 461 .clk_num = _clk_num, \
464 .enable_refcnt = _enb_refcnt, \
465 .regs = _regs, \
466 }, \ 462 }, \
467 .mux_ops = &clk_mux_ops, \ 463 .mux_ops = &clk_mux_ops, \
468 .div_ops = &tegra_clk_frac_div_ops, \ 464 .div_ops = &tegra_clk_frac_div_ops, \
@@ -472,7 +468,10 @@ struct clk *tegra_clk_register_periph_nodiv(const char *name,
472struct tegra_periph_init_data { 468struct tegra_periph_init_data {
473 const char *name; 469 const char *name;
474 int clk_id; 470 int clk_id;
475 const char **parent_names; 471 union {
472 const char **parent_names;
473 const char *parent_name;
474 } p;
476 int num_parents; 475 int num_parents;
477 struct tegra_clk_periph periph; 476 struct tegra_clk_periph periph;
478 u32 offset; 477 u32 offset;
@@ -483,20 +482,19 @@ struct tegra_periph_init_data {
483 482
484#define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\ 483#define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\
485 _mux_shift, _mux_mask, _mux_flags, _div_shift, \ 484 _mux_shift, _mux_mask, _mux_flags, _div_shift, \
486 _div_width, _div_frac_width, _div_flags, _regs, \ 485 _div_width, _div_frac_width, _div_flags, \
487 _clk_num, _enb_refcnt, _gate_flags, _clk_id, _table,\ 486 _clk_num, _gate_flags, _clk_id, _table, \
488 _flags) \ 487 _flags, _lock) \
489 { \ 488 { \
490 .name = _name, \ 489 .name = _name, \
491 .clk_id = _clk_id, \ 490 .clk_id = _clk_id, \
492 .parent_names = _parent_names, \ 491 .p.parent_names = _parent_names, \
493 .num_parents = ARRAY_SIZE(_parent_names), \ 492 .num_parents = ARRAY_SIZE(_parent_names), \
494 .periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, \ 493 .periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, \
495 _mux_flags, _div_shift, \ 494 _mux_flags, _div_shift, \
496 _div_width, _div_frac_width, \ 495 _div_width, _div_frac_width, \
497 _div_flags, _clk_num, \ 496 _div_flags, _clk_num, \
498 _enb_refcnt, _regs, \ 497 _gate_flags, _table, _lock), \
499 _gate_flags, _table), \
500 .offset = _offset, \ 498 .offset = _offset, \
501 .con_id = _con_id, \ 499 .con_id = _con_id, \
502 .dev_id = _dev_id, \ 500 .dev_id = _dev_id, \
@@ -505,13 +503,13 @@ struct tegra_periph_init_data {
505 503
506#define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\ 504#define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\
507 _mux_shift, _mux_width, _mux_flags, _div_shift, \ 505 _mux_shift, _mux_width, _mux_flags, _div_shift, \
508 _div_width, _div_frac_width, _div_flags, _regs, \ 506 _div_width, _div_frac_width, _div_flags, \
509 _clk_num, _enb_refcnt, _gate_flags, _clk_id) \ 507 _clk_num, _gate_flags, _clk_id) \
510 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\ 508 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\
511 _mux_shift, BIT(_mux_width) - 1, _mux_flags, \ 509 _mux_shift, BIT(_mux_width) - 1, _mux_flags, \
512 _div_shift, _div_width, _div_frac_width, _div_flags, \ 510 _div_shift, _div_width, _div_frac_width, _div_flags, \
513 _regs, _clk_num, _enb_refcnt, _gate_flags, _clk_id,\ 511 _clk_num, _gate_flags, _clk_id,\
514 NULL, 0) 512 NULL, 0, NULL)
515 513
516/** 514/**
517 * struct clk_super_mux - super clock 515 * struct clk_super_mux - super clock
@@ -581,12 +579,49 @@ struct tegra_clk_duplicate {
581 }, \ 579 }, \
582 } 580 }
583 581
582struct tegra_clk {
583 int dt_id;
584 bool present;
585};
586
587struct tegra_devclk {
588 int dt_id;
589 char *dev_id;
590 char *con_id;
591};
592
584void tegra_init_from_table(struct tegra_clk_init_table *tbl, 593void tegra_init_from_table(struct tegra_clk_init_table *tbl,
585 struct clk *clks[], int clk_max); 594 struct clk *clks[], int clk_max);
586 595
587void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list, 596void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
588 struct clk *clks[], int clk_max); 597 struct clk *clks[], int clk_max);
589 598
599struct tegra_clk_periph_regs *get_reg_bank(int clkid);
600struct clk **tegra_clk_init(int num, int periph_banks);
601
602struct clk **tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk);
603
604void tegra_add_of_provider(struct device_node *np);
605void tegra_register_devclks(struct tegra_devclk *dev_clks, int num);
606
607void tegra_audio_clk_init(void __iomem *clk_base,
608 void __iomem *pmc_base, struct tegra_clk *tegra_clks,
609 struct tegra_clk_pll_params *pll_params);
610
611void tegra_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base,
612 struct tegra_clk *tegra_clks,
613 struct tegra_clk_pll_params *pll_params);
614
615void tegra_pmc_clk_init(void __iomem *pmc_base, struct tegra_clk *tegra_clks);
616void tegra_fixed_clk_init(struct tegra_clk *tegra_clks);
617int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *tegra_clks,
618 unsigned long *input_freqs, int num,
619 unsigned long *osc_freq,
620 unsigned long *pll_ref_freq);
621void tegra_super_clk_gen4_init(void __iomem *clk_base,
622 void __iomem *pmc_base, struct tegra_clk *tegra_clks,
623 struct tegra_clk_pll_params *pll_params);
624
590void tegra114_clock_tune_cpu_trimmers_high(void); 625void tegra114_clock_tune_cpu_trimmers_high(void);
591void tegra114_clock_tune_cpu_trimmers_low(void); 626void tegra114_clock_tune_cpu_trimmers_low(void);
592void tegra114_clock_tune_cpu_trimmers_init(void); 627void tegra114_clock_tune_cpu_trimmers_init(void);
diff --git a/drivers/clk/ux500/clk-prcmu.c b/drivers/clk/ux500/clk-prcmu.c
index 293a28854417..e2d63bc47436 100644
--- a/drivers/clk/ux500/clk-prcmu.c
+++ b/drivers/clk/ux500/clk-prcmu.c
@@ -36,7 +36,7 @@ static int clk_prcmu_prepare(struct clk_hw *hw)
36 if (!ret) 36 if (!ret)
37 clk->is_prepared = 1; 37 clk->is_prepared = 1;
38 38
39 return ret;; 39 return ret;
40} 40}
41 41
42static void clk_prcmu_unprepare(struct clk_hw *hw) 42static void clk_prcmu_unprepare(struct clk_hw *hw)
diff --git a/drivers/clk/versatile/clk-sp810.c b/drivers/clk/versatile/clk-sp810.c
index bf9b15a585e1..c6e86a9a2aa3 100644
--- a/drivers/clk/versatile/clk-sp810.c
+++ b/drivers/clk/versatile/clk-sp810.c
@@ -123,7 +123,7 @@ static const struct clk_ops clk_sp810_timerclken_ops = {
123 .set_parent = clk_sp810_timerclken_set_parent, 123 .set_parent = clk_sp810_timerclken_set_parent,
124}; 124};
125 125
126struct clk *clk_sp810_timerclken_of_get(struct of_phandle_args *clkspec, 126static struct clk *clk_sp810_timerclken_of_get(struct of_phandle_args *clkspec,
127 void *data) 127 void *data)
128{ 128{
129 struct clk_sp810 *sp810 = data; 129 struct clk_sp810 *sp810 = data;
diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c
index 10772aa72e4e..09dd0173ea0a 100644
--- a/drivers/clk/zynq/clkc.c
+++ b/drivers/clk/zynq/clkc.c
@@ -102,9 +102,10 @@ static const char *swdt_ext_clk_input_names[] __initdata = {"swdt_ext_clk"};
102 102
103static void __init zynq_clk_register_fclk(enum zynq_clk fclk, 103static void __init zynq_clk_register_fclk(enum zynq_clk fclk,
104 const char *clk_name, void __iomem *fclk_ctrl_reg, 104 const char *clk_name, void __iomem *fclk_ctrl_reg,
105 const char **parents) 105 const char **parents, int enable)
106{ 106{
107 struct clk *clk; 107 struct clk *clk;
108 u32 enable_reg;
108 char *mux_name; 109 char *mux_name;
109 char *div0_name; 110 char *div0_name;
110 char *div1_name; 111 char *div1_name;
@@ -147,6 +148,12 @@ static void __init zynq_clk_register_fclk(enum zynq_clk fclk,
147 clks[fclk] = clk_register_gate(NULL, clk_name, 148 clks[fclk] = clk_register_gate(NULL, clk_name,
148 div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg, 149 div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg,
149 0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock); 150 0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock);
151 enable_reg = readl(fclk_gate_reg) & 1;
152 if (enable && !enable_reg) {
153 if (clk_prepare_enable(clks[fclk]))
154 pr_warn("%s: FCLK%u enable failed\n", __func__,
155 fclk - fclk0);
156 }
150 kfree(mux_name); 157 kfree(mux_name);
151 kfree(div0_name); 158 kfree(div0_name);
152 kfree(div1_name); 159 kfree(div1_name);
@@ -213,6 +220,7 @@ static void __init zynq_clk_setup(struct device_node *np)
213 int ret; 220 int ret;
214 struct clk *clk; 221 struct clk *clk;
215 char *clk_name; 222 char *clk_name;
223 unsigned int fclk_enable = 0;
216 const char *clk_output_name[clk_max]; 224 const char *clk_output_name[clk_max];
217 const char *cpu_parents[4]; 225 const char *cpu_parents[4];
218 const char *periph_parents[4]; 226 const char *periph_parents[4];
@@ -238,6 +246,8 @@ static void __init zynq_clk_setup(struct device_node *np)
238 periph_parents[2] = clk_output_name[armpll]; 246 periph_parents[2] = clk_output_name[armpll];
239 periph_parents[3] = clk_output_name[ddrpll]; 247 periph_parents[3] = clk_output_name[ddrpll];
240 248
249 of_property_read_u32(np, "fclk-enable", &fclk_enable);
250
241 /* ps_clk */ 251 /* ps_clk */
242 ret = of_property_read_u32(np, "ps-clk-frequency", &tmp); 252 ret = of_property_read_u32(np, "ps-clk-frequency", &tmp);
243 if (ret) { 253 if (ret) {
@@ -340,10 +350,12 @@ static void __init zynq_clk_setup(struct device_node *np)
340 clk_prepare_enable(clks[dci]); 350 clk_prepare_enable(clks[dci]);
341 351
342 /* Peripheral clocks */ 352 /* Peripheral clocks */
343 for (i = fclk0; i <= fclk3; i++) 353 for (i = fclk0; i <= fclk3; i++) {
354 int enable = !!(fclk_enable & BIT(i - fclk0));
344 zynq_clk_register_fclk(i, clk_output_name[i], 355 zynq_clk_register_fclk(i, clk_output_name[i],
345 SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0), 356 SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0),
346 periph_parents); 357 periph_parents, enable);
358 }
347 359
348 zynq_clk_register_periph_clk(lqspi, 0, clk_output_name[lqspi], NULL, 360 zynq_clk_register_periph_clk(lqspi, 0, clk_output_name[lqspi], NULL,
349 SLCR_LQSPI_CLK_CTRL, periph_parents, 0); 361 SLCR_LQSPI_CLK_CTRL, periph_parents, 0);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-01 10:43:59 -0500